WO2013015362A1 - Élément de cellule solaire et module de cellules solaires - Google Patents

Élément de cellule solaire et module de cellules solaires Download PDF

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Publication number
WO2013015362A1
WO2013015362A1 PCT/JP2012/068977 JP2012068977W WO2013015362A1 WO 2013015362 A1 WO2013015362 A1 WO 2013015362A1 JP 2012068977 W JP2012068977 W JP 2012068977W WO 2013015362 A1 WO2013015362 A1 WO 2013015362A1
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Prior art keywords
layer
solar cell
semiconductor substrate
electrode
cell element
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PCT/JP2012/068977
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English (en)
Japanese (ja)
Inventor
順平 佐藤
京田　豪
陽平 小柏
佑介 名合
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京セラ株式会社
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Application filed by 京セラ株式会社 filed Critical 京セラ株式会社
Priority to JP2013525752A priority Critical patent/JP5726308B2/ja
Priority to CN201280037684.1A priority patent/CN103718305B/zh
Publication of WO2013015362A1 publication Critical patent/WO2013015362A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
    • H01L31/02245—Electrode arrangements specially adapted for back-contact solar cells for metallisation wrap-through [MWT] type solar cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells

Definitions

  • the present invention relates to a solar cell element and a solar cell module.
  • Such a solar cell element has a semiconductor substrate having a plurality of through holes, a first electrode, and a second electrode.
  • the first electrode is provided over a part of the light receiving surface, the through hole, and the back surface of the semiconductor substrate.
  • the second electrode has a polarity different from that of the first electrode.
  • the second electrode is provided at a portion where the first electrode is not disposed on the back surface of the semiconductor substrate.
  • the back contact type solar cell element two electrodes (first electrode and second electrode) having different polarities are arranged on the back surface of the semiconductor substrate. Thereby, the defect by leakage may arise in the solar cell element.
  • One object of the present invention is to provide a solar cell element and a solar cell module with reduced leakage.
  • a solar cell element is located on a first conductive type semiconductor substrate having a first surface and a second surface on the back side of the first surface, and the first surface.
  • a second conductivity type semiconductor having a second layer located on the second surface, passing through the first layer and the semiconductor substrate or via the side surface of the semiconductor substrate and continuing to the first layer With layers.
  • the solar cell element is electrically connected to the main electrode portion through the main electrode portion located on the first layer and the semiconductor substrate or via a side surface of the semiconductor substrate.
  • a first electrode having a first output extraction portion located on the second layer; and a second electrode located on a portion of the second surface where the second layer is not located.
  • the sheet resistance of the second layer is larger than the sheet resistance of the first layer.
  • a solar cell module according to an embodiment of the present invention includes the solar cell element.
  • the output characteristics can be improved.
  • a solar cell element 10 As shown in FIGS. 1 to 4, a solar cell element 10 according to an embodiment of the present invention includes a one-conductivity type semiconductor substrate 1, a reverse conductivity type layer 2 having a conductivity type different from that of the semiconductor substrate 1, and a through hole. 3, the 1st electrode 4, the 2nd electrode 5, the semiconductor part 6, and the antireflection layer 7 are provided.
  • the semiconductor substrate 1 has a first surface 1F (upper surface side in FIG. 3) and a second surface 1S (lower surface side in FIG. 3) on the back side of the first surface 1F.
  • the first surface 1F is a light receiving surface.
  • the first surface 1F may be referred to as a light receiving surface of the semiconductor substrate 1
  • the second surface 1S may be referred to as a back surface of the semiconductor substrate 1.
  • a crystalline silicon substrate such as a single crystal silicon substrate or a polycrystalline silicon substrate having a predetermined dopant element (conductivity control impurity) and having one conductivity type (for example, p-type) is used. . That is, the semiconductor substrate 1 has the first conductivity type.
  • the thickness of the semiconductor substrate 1 can be, for example, 250 ⁇ m or less, and further 150 ⁇ m or less.
  • the shape of the semiconductor substrate 1 is not particularly limited. The shape of the semiconductor substrate 1 may be a square shape, for example.
  • the semiconductor substrate 1 for example, a crystalline silicon substrate having a p-type conductivity may be used.
  • the semiconductor substrate 1 is p-type, for example, boron or gallium may be used as the dopant element.
  • a texture structure (uneven structure) 1a having a large number of fine protrusions 1b is formed on the first surface 1F of the semiconductor substrate 1, as shown in FIG. 3, a texture structure (uneven structure) 1a having a large number of fine protrusions 1b is formed. Thereby, reflection of incident light on the first surface 1F can be reduced and more sunlight can be absorbed into the semiconductor substrate 1.
  • the texture structure 1a is not an essential component in the present embodiment, and may be formed as necessary.
  • the semiconductor substrate 1 is provided with a plurality of through holes 3 penetrating from the first surface 1F to the second surface 1S.
  • the through hole 3 has a third layer 2c formed on the inner surface thereof.
  • a conduction portion 4 b of the first electrode 4 described later is formed inside the through hole 3.
  • the through-holes 3 are formed at a predetermined pitch in a diameter range of 50 ⁇ m or more and 300 ⁇ m or less.
  • the through holes 3 may have different diameters of the openings in the first surface 1F and the second surface 1S.
  • the through-hole 3 may have a shape whose diameter decreases from the first surface 1F side toward the second surface 1S side.
  • the reverse conductivity type layer 2 is a layer having a conductivity type opposite to that of the semiconductor substrate 1. That is, the reverse conductivity type layer 2 corresponds to a semiconductor layer having the second conductivity type.
  • the reverse conductivity type layer 2 is formed on the inner surface of the first layer 2a formed on the first surface 1F of the semiconductor substrate 1, the second layer 2b formed on the second surface 1S of the semiconductor substrate 1, and the through hole 3.
  • the formed third layer 2c is included.
  • the first layer 2a is formed so as to be continuous with the second layer 2b via the third layer 2c.
  • the reverse conductivity type layer 2 has an n-type conductivity type.
  • the first layer 2a is formed as an n + type having a sheet resistance of about 40 to 100 ⁇ / ⁇ , for example. By setting the value of the sheet resistance within this range, increase in surface recombination and increase in surface resistance on the first surface 1F can be reduced.
  • the first layer 2a is formed on the first surface 1F of the semiconductor substrate 1 with a thickness of about 0.2 ⁇ m to 2 ⁇ m, for example.
  • the second layer 2b is formed on the second surface 1S of the semiconductor substrate 1 in the formation region of the first electrode 4 and its peripheral portion.
  • the second layer 2b has a higher sheet resistance than the first layer 2a.
  • the sheet resistance of the second layer 2b may be, for example, 100 to 600 ⁇ / ⁇ .
  • the third layer 2 c is formed on the inner surface of the through hole 3.
  • the third layer 2c only needs to have a sheet resistance equivalent to that of the first layer 2a.
  • the third layer 2c may have a sheet resistance lower than that of the first layer 2a. Thereby, the increase in surface resistance is further reduced.
  • a pn junction is formed between the region of one conductivity type in the semiconductor substrate 1 and the opposite conductivity type layer 2.
  • the semiconductor part 6 is provided in order to form an internal electric field inside the solar cell element 10. That is, the semiconductor part 6 is a layer provided for the purpose of obtaining the BSF effect (Back Surface Field Effect). This makes it difficult for carrier recombination to occur near the second surface 1S of the semiconductor substrate 1. As a result, a decrease in power generation efficiency is reduced.
  • BSF effect Back Surface Field Effect
  • the semiconductor portion 6 is formed on substantially the entire surface of the second surface 1S of the semiconductor substrate 1 other than the region where the second layer 2b is formed. For example, as shown in FIG. 3A, the semiconductor unit 6 is formed so as not to contact the second layer 2b on the second surface 1S.
  • the formation pattern of the semiconductor portion 6 varies depending on the formation pattern of the first electrode 4.
  • the semiconductor unit 6 has the same conductivity type as that of the semiconductor substrate 1. In other words, if the semiconductor substrate 1 is p-type as the first conductivity type, the semiconductor portion 6 is also the first conductivity type (p-type). And the density
  • a dopant element such as boron or aluminum in the second surface 1S, for example.
  • the concentration of the dopant element contained in the semiconductor portion 6 may be about 1 ⁇ 10 18 to 5 ⁇ 10 21 atoms / cm 3 .
  • the semiconductor portion 6 has a p + type conductivity type containing a higher concentration of dopant than the p type conductivity type of the semiconductor substrate 1. Thereby, a favorable ohmic contact is formed between the current collector 5b described later.
  • the semiconductor unit 6 may be formed in 70% or more of the entire region of the second surface 1S. Thereby, the BSF effect increases. As a result, the output characteristics of the solar cell element 10 are improved.
  • the semiconductor unit 6 is not an essential component in the present embodiment, and may be formed as necessary.
  • the antireflection layer 7 is formed on the first surface 1F side of the semiconductor substrate 1.
  • the antireflection layer 7 is formed on the first layer 2a.
  • the antireflection layer 7 has a role of reducing the reflection of incident light on the surface (first surface 1F) of the semiconductor substrate 1.
  • the antireflection layer 7 can be formed of silicon nitride or an oxide material.
  • the thickness of the antireflection layer 7 is set to a value that realizes a condition of low reflection with respect to incident light. For example, when a silicon substrate is used as the semiconductor substrate 1, the antireflection layer 7 may be formed to a thickness of about 500 to 1200 mm with a material having a refractive index of about 1.8 to 2.3.
  • the antireflection layer 7 is not an essential component in the present embodiment, and may be provided as necessary.
  • the first electrode 4 has a plurality of main electrode portions 4a, a plurality of conduction portions 4b, and a plurality of first output extraction portions 4c.
  • the main electrode portion 4 a is formed on the first surface 1 ⁇ / b> F of the semiconductor substrate 1.
  • the conduction part 4 b is electrically connected to the main electrode part 4 a and is provided in the through hole 3.
  • the first output extraction portion 4c is formed on the second surface 1S and connected to the conduction portion 4b. That is, the main electrode portion 4 a is electrically connected to the first output extraction portion 4 c via the conduction portion 4 b that penetrates the semiconductor substrate 1.
  • the main electrode portion 4a has a function of collecting carriers generated on the first surface 1F side.
  • the conduction part 4b has a function of guiding the carriers collected by the main electrode part 4a to the first output extraction part 4c provided on the second surface 1S side.
  • the 1st output extraction part 4c has a function as a wiring connection part connected with the wiring which electrically connects adjacent solar cell elements 10 mutually.
  • the conductive portion 4 b is provided corresponding to the through hole 3 formed in the semiconductor substrate 1. As shown in FIGS. 3A and 3B, the conductive portion 4b is provided so as to be led out from the first surface 1F side of the semiconductor substrate 1 to the second surface 1S side. In FIG. 1, the formation position of the conduction part 4 b illustrated in a black circle shape corresponds to the formation position of the through hole 3.
  • the plurality of conductive portions 4b are arranged in a predetermined direction.
  • the plurality of conducting portions 4 b are arranged in a plurality of rows (three rows in FIG. 1) in a direction parallel to the reference side BS of the first surface 1 F of the semiconductor substrate 1.
  • the reference side BS is a side that is parallel to the arrangement direction of the solar cell elements 10 when the solar cell module 20 is formed by arranging a plurality of solar cell elements 10.
  • parallel should not be strictly understood as in mathematical definition.
  • the conducting portions 4b are provided so as to be arranged in a plurality of (three in FIG. 1) straight lines. And the some conduction
  • the main electrode portion 4a connects the conductive portions 4b belonging to different columns on the first surface 1F of the semiconductor substrate 1.
  • the main electrode portion 4a is linear.
  • the linear main electrode portion 4 a is disposed so as to extend along a direction orthogonal to the arrangement direction of the conductive portions 4 b, that is, a direction orthogonal to the reference side BS. .
  • the main electrode part 4a arranged in this way connects the three conducting parts 4b located on a straight line orthogonal to the reference side BS.
  • the width of the main electrode portion 4a can be 50 to 200 ⁇ m, and the interval between the main electrode portions 4a can be about 1 to 3 mm.
  • the number of conductive portions 4b arranged in the direction along the reference side BS is the same as the number of main electrode portions 4a. Therefore, increase of the resistance loss of the electrode part in a light-receiving surface is reduced, ensuring the light-receiving area in the 1st surface 1F.
  • the first electrode 4 may be disposed so as to cover the through-hole 3 as shown in FIG. At this time, the first electrode 4 may be provided with a circular pad electrode portion 4 e having a diameter larger than the diameter of the through hole 3.
  • the main electrode portion 4a and the conducting portion 4b can be easily connected even if the formation position of the main electrode portion 4a is slightly shifted from a desired position in the manufacturing process. Thereby, the reliability of the solar cell element 10 is improved.
  • the first electrode 4 may have an auxiliary electrode portion 4f that connects the end portions of the main electrode portions 4a.
  • the auxiliary electrode portion 4f has a function of electrically connecting adjacent linear main electrode portions 4a.
  • the first electrode 4 includes an auxiliary electrode portion 4f that connects one end of each main electrode portion 4a and an auxiliary electrode portion 4f that connects the other ends of each main electrode portion 4a. Yes. According to such a form, even if a disconnection occurs in some of the main electrode portions 4a, carriers can be guided to the other main electrode portions 4a through the auxiliary electrode portions 4f. Thereby, the output fall of the solar cell element 10 is reduced.
  • the portion formed on the first surface 1F side that is the light receiving surface of the first electrode 4 is the light receiving surface electrode portion, the entire surface of the first surface 1F that is the light receiving surface is formed. Compared with this, since the ratio of the light receiving surface electrode portion is very small, high light receiving efficiency is realized. In addition, since the light-receiving surface electrode portion is uniformly formed on the first surface 1F, carriers generated on the first surface 1F can be collected efficiently.
  • the first electrode 4 includes a plurality of first electrodes 4 at positions corresponding to the plurality of conductive portions 4 b (through holes 3) on the second surface 1 S of the semiconductor substrate 1. 1st output extraction part 4c.
  • the first output extraction portion 4c is sequentially arranged in a direction different from the longitudinal direction of the main electrode portion 4a (in this embodiment, the arrangement direction of the conducting portions 4b). And the 1st output extraction part 4c is formed in the elongate shape which has a longitudinal direction in this arrangement direction.
  • one first output extraction portion 4c and a plurality of conduction portions 4b are connected. Specifically, as shown in FIG. 4, one first output extraction portion 4c is connected to six or eight conduction portions 4b.
  • the first output extraction portion 4c is formed in a plurality of rows (three rows in FIG. 2) corresponding to the arrangement of the conducting portions 4b.
  • a direction in which the plurality of first output extraction parts 4c are arranged that is, a direction along the reference side BS (a direction parallel to the reference side BS) is referred to as an arrangement direction.
  • This arrangement direction is the same as the direction in which the conductive portions 4b are arranged.
  • the second electrode 5 has a polarity different from that of the first electrode 4.
  • the second electrode 5 is disposed so as to be electrically insulated from the first electrode 4. As shown in FIGS. 2 and 4, the second electrode 5 has a second output extraction portion 5a and a current collecting portion 5b.
  • the second output extraction unit 5a is provided on the second surface 1S.
  • the current collector 5b is located on both sides of the first output extraction portion 4c in plan view of the second surface 1S.
  • the current collector 5b collects the carriers generated on the second surface 1S side.
  • the current collector 5 b is formed on the semiconductor unit 6 provided on the second surface 1S of the semiconductor substrate 1.
  • the current collector 5b is provided on substantially the entire second surface 1S excluding the first output extraction portion 4c and its peripheral portion, and part of the region where the second output extraction portion 5a is formed. In other words, the current collector 5b is paired so as to sandwich the first output extraction portion 4c when the second surface 1S is viewed in plan.
  • substantially the entire surface refers to a surface of 70% or more of the entire area of the second surface 1S when the second surface 1S of the semiconductor substrate 1 is viewed in plan.
  • 2nd output extraction part 5a has a role as a wiring connection part connected with the wiring which electrically connects adjacent solar cell elements 10 mutually. Moreover, what is necessary is just to form the 2nd output extraction part 5a so that the at least one part may overlap with the current collection part 5b. As a result, the carriers collected by the current collector 5b are output to the outside. In addition, as shown to Fig.3 (a), you may arrange
  • the second output extraction unit 5a is arranged in parallel with each of the plurality of first output extraction units 4c. Moreover, the 2nd output extraction part 5a has comprised the elongate shape which has a longitudinal direction in an arrangement direction similarly to the 1st output extraction part 4c. In the present embodiment, a plurality of the first output extraction portion 4c and the second output extraction portion 5a are formed along the arrangement direction of the first output extraction portion 4c or the second output extraction portion 5a. It may be formed by one.
  • standard side BS of the 1st output extraction part 4c and the 2nd output extraction part 5a may mutually differ, or may be the same.
  • the current collector 5b can be made of aluminum, for example.
  • the 2nd output extraction part 5a can be formed with silver, for example.
  • the 1st output extraction part 4c is connected to the conduction
  • the conduction region 4c1 is provided so as to cover a part of the plurality of conduction portions 4b.
  • the conduction region 4c1 is located on the second surface 1S of the semiconductor substrate 1 immediately below the plurality of conduction portions 4b (through holes 3).
  • the conduction region 4c1 has a long shape having a longitudinal direction in the arrangement direction of the conduction portions 4b (direction along the reference side BS). That is, the conduction region 4c1 is provided along the arrangement direction of the conduction parts 4b.
  • region 4c1 should just be substantially equal to the diameter of the conduction
  • one conduction region 4c1 is connected to a plurality of conduction portions 4b, and a plurality of such conduction regions 4c1 are arranged along the arrangement direction of the conduction portions 4b. Specifically, as shown in FIG. 4, the conduction region 4c1 is connected to the six conduction parts 4b.
  • the extraction region 4c2 is adjacent to each conduction region 4c1 and connected to each conduction region portion 4c1 on the second surface 1S.
  • the extraction region 4c2 is disposed between the conduction region 4c1 and the current collector 5b.
  • the extraction region 4c2 has a long shape having a longitudinal direction along the arrangement direction of the conductive portions 4b, similarly to the conductive region 4c1. As shown in FIG. 4, such an extraction region 4c2 is connected and arranged with the conduction region 4c1 along the arrangement direction of the conduction parts 4b.
  • the conduction region 4c1 and the extraction region 4c2 are formed in a plurality of rows (three rows in FIG. 2) corresponding to the number of rows of the conduction portions 4b arranged.
  • region 4c2 is shorter than the length of the conduction
  • the semiconductor part 6 has the expansion part 6a located between the extraction area
  • the first output extraction portion 4c has a protruding portion (extraction region 4c2).
  • a protruding portion may not be provided.
  • the second layer 2b since the second layer 2b has a higher sheet resistance than the first layer 2a, the distance between the second layer 2b and the second electrode 5 is reduced to increase the area of the second electrode 5. be able to. As a result, since the amount of carriers taken out from the second electrode 5 can be increased, the output characteristics of the solar cell element 10 can be improved. In addition, even if variations in electrode formation position occur in the process of mass production, the failure rate such as leakage failure can be reduced.
  • the sheet resistance of the first layer 2a may be set to 40 to 100 ⁇ / ⁇ , for example, and the sheet resistance of the second layer 2b may be set to 100 to 600 ⁇ / ⁇ , for example.
  • the sheet resistance of each layer of the reverse conductivity type layer 2 can be measured using, for example, a four-terminal method. More specifically, the sheet resistance of each layer of the reverse conductivity type layer 2 is calculated from, for example, an average value of values measured by applying a measurement probe to any 10 points.
  • the maximum value of the dopant concentration of the second layer 2b may be smaller than the maximum value of the dopant concentration of the first layer 2a. This also makes it possible to reduce the distance between the second layer 2b and the second electrode 5 while reducing the occurrence of leakage. Therefore, the above-described output characteristics can be further improved.
  • the maximum value of the dopant concentration of the second layer 2b is smaller than the maximum value of the dopant concentration of the first layer 2a.
  • the maximum value of the dopant concentration of the first layer 2a is about 8 ⁇ 10 20 atoms / cm 3
  • the maximum value of the dopant concentration of the second layer 2b is set to 8 ⁇ 10 19 atoms / cm 3 or less.
  • the doping concentration of each layer can be measured using secondary ion mass spectrometry (SIMS), for example.
  • the dopant concentration of each layer of the reverse conductivity type layer 2 is, for example, the maximum value of each dopant concentration measured using an SIMS device (Model 6650 manufactured by ULVAC-PHI) with respect to an arbitrary total of five points of each layer. It is calculated from the average value.
  • the distance between the second layer 2b and the second electrode 5 is set to about 0.3 to 0.6 mm.
  • a pn isolation region may not be provided between the second layer 2b and the second electrode 5.
  • a pn isolation region may be provided between the second layer 2b and the second electrode 5 and in the peripheral portion of the second surface 1S of the semiconductor substrate 1. In such a pn isolation region, a region of one conductivity type of the semiconductor substrate 1 exists.
  • the sheet resistance of the third layer 2c only needs to be substantially equal to or lower than the sheet resistance of the first layer 2a. Thereby, the increase in surface resistance can be reduced more.
  • the second layer 2b may have a higher sheet resistance than the third layer 2c.
  • the dopant concentration of the second layer 2b may be lowered as the distance from the through hole 3 and the third layer 3c increases. Thereby, the resistance loss of carriers can be reduced in the vicinity of the through hole 3, and the occurrence of leakage can be reduced in a region away from the through hole 3 adjacent to the second electrode 5.
  • the dopant concentration at the end of the second layer 2b is in the vicinity of the third layer 3c (near the outline of the through hole 3).
  • the dopant concentration at the end of the second layer 2b is about 7 ⁇ 10 19 atoms / cm 3
  • 8 ⁇ 10 19 atoms / cm 3 It is good also as a grade.
  • the solar cell element 10 can be used alone, but is also used as an element constituting the solar cell module. That is, the solar cell element 10 is arranged so as to be adjacent to a plurality of solar cell elements 10 having the same structure, and further, the solar cell module 20 can be configured by connecting each other in series.
  • a solar cell module 20 includes a plurality of solar cell elements 10 according to the embodiment arranged adjacent to each other and a wiring member 15 that electrically connects the adjacent solar cell elements 10. .
  • the solar cell module 20 further includes a translucent member 11, a front side filler 12, a back side filler 13, and a back surface protective material 14.
  • the translucent member 11 is disposed on the first surface 1F side of the solar cell element 10 and has a function of protecting the first surface 1F, and is made of, for example, glass.
  • the front-side filler 12 is disposed between the first surface 1F of the solar cell element 10 and the translucent member 11 and has a function of sealing the solar cell element 10, for example, transparent ethylene vinyl It consists of acetate copolymer (EVA) and the like.
  • EVA acetate copolymer
  • the back side filler 13 is disposed on the second surface 1S side of the solar cell element 10 and has a function of sealing the solar cell element 10, and is made of, for example, transparent or white EVA.
  • the back surface protective material 14 has a function of protecting the second surface 1S side of the solar cell element 10, and is made of, for example, a single layer or a laminated structure such as polyethylene terephthalate (PET) or polyvinyl fluoride resin (PVF). Become.
  • PET polyethylene terephthalate
  • PVF polyvinyl fluoride resin
  • the plurality of solar cell elements 10 are formed by connecting adjacent solar cell elements 10 in series with each other by a wiring member 15 having a function as a connecting member.
  • the wiring member 15 has a base sheet and a wiring formed on the base sheet.
  • the wiring has a first wiring connected to the first electrode 4 (first output extraction portion 4c). Furthermore, the wiring has a second wiring connected to the second electrode 5 (second output extraction portion 5a). Further, the wiring includes a third wiring that connects the first wiring connected to one adjacent solar cell element 10 and the second wiring connected to the other solar cell element 10.
  • the first wiring and the second wiring are alternately arranged one by one at a predetermined interval.
  • an insulating sheet may be formed on the wiring, and an opening is provided in a portion where each wiring and each electrode are connected.
  • the material for the base sheet and the insulating sheet for example, polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polyvinyl fluoride resin (PVF) can be used. Also, use a resin with excellent heat resistance such as polyimide (PI), polyamideimide (PAI), polyether ether ketone (PEEK), tetrafluoroethylene (PTFE) or polyethersulfone (PES). Also good.
  • the base sheet and the insulating sheet may have a single layer structure or a multilayer structure.
  • the wiring material may be any conductive material.
  • metals such as copper, aluminum, and silver, can be used, for example.
  • the wiring member 15 is connected to the first output extraction portion 4c and the second output extraction portion 5a of the solar cell element 10 using a solder paste or a conductive adhesive. Note that the wiring member 15 may not include a base sheet.
  • the back surface protective material 14 can be made of a material having a high reflectance such as white. Thereby, the light irradiated between the solar cell elements 10 is diffusely reflected by the back surface protective material 14 and irradiated to the solar cell elements 10. As a result, the amount of received light in the solar cell element 10 can be further increased.
  • white PET can be used as a material of the back surface protective material 14.
  • a semiconductor substrate 1 exhibiting a p-type conductivity is prepared.
  • the semiconductor substrate 1 can be obtained by cutting a single crystal silicon ingot to a predetermined thickness.
  • a single crystal silicon ingot produced by a known production method such as FZ method or CZ method can be used.
  • a polycrystalline silicon substrate is used as the semiconductor substrate 1, the semiconductor substrate 1 can be obtained by cutting a polycrystalline silicon ingot to a predetermined thickness.
  • the polycrystalline silicon ingot those produced by a known production method such as a casting method or an in-mold solidification method can be used.
  • the semiconductor substrate 1 has p-type conductivity.
  • the mechanical damage layer and the contamination layer in the surface layer portion of the semiconductor substrate 1 due to the cutting (slicing) are removed.
  • the surface layer portions on the front surface side and the back surface side of the cut-out semiconductor substrate 1 may be etched by about 10 to 20 ⁇ m with NaOH, KOH, or a mixed solution of hydrofluoric acid and nitric acid, and then washed with pure water or the like. Thereby, an organic component and a metal component are removed.
  • the through hole 3 is formed between the first surface 1F and the second surface 1S of the semiconductor substrate 1.
  • the through-hole 3 can be formed using a drill, a water jet, a laser processing apparatus, or the like.
  • the through hole 3 is formed by processing from the second surface 1S side of the semiconductor substrate 1 toward the first surface 1F side so that the first surface 1F serving as the light receiving surface is not damaged. Like that. However, if there is little damage to the semiconductor substrate 1 due to the processing, the processing may be performed from the first surface 1F side to the second surface 1S side.
  • a texture structure 1 a having fine protrusions (convex portions) 1 b is formed on the light receiving surface side of the semiconductor substrate 1 in which the through holes 3 are formed.
  • a wet etching method using an alkaline aqueous solution such as NaOH or KOH or a hydrofluoric acid solution can be used.
  • a dry etching method using an etching gas having a property of etching the material of the semiconductor substrate 1 can be used.
  • the reverse conductivity type layer 2 is formed as a first layer 2 a on the first surface 1 F of the semiconductor substrate 1, a second layer 2 b on the second surface 1 S, and a third layer 2 c on the inner surface of the through hole 3.
  • the reverse conductivity type layer 2 has an n-type. Therefore, for example, P (phosphorus) can be used as an n-type doping element for forming the reverse conductivity type layer 2.
  • P phosphorus
  • the reverse conductivity type layer 2 can be formed using, for example, the following method.
  • a coating thermal diffusion method in which P 2 O 5 in a paste state is applied to the first surface 1F and the through hole 3 in the semiconductor substrate 1 and thermally diffused.
  • the second layer 2b having a sheet resistance higher than that of the first layer 2a can be formed by diffusing the dopant evaporated from the paste into the second surface 1S.
  • a second method there is a gas phase thermal diffusion method in which POCl 3 (phosphorus oxychloride) in a gas state is diffused as a diffusion source to a formation target site.
  • POCl 3 phosphorus oxychloride
  • the reverse conductivity type layer 2 can be formed in the same process at the formation target portion on both main surfaces of the semiconductor substrate 1 and the inner surface of the through hole 3.
  • a second layer 2b having a sheet resistance higher than that of the first layer 2a is formed by forming a diffusion reduction layer having a small thickness and reducing the diffusion amount of the dopant. can do.
  • the second layer 2b can be formed by etching the surface of the second surface 1S.
  • the following method may be used. First, a cassette having a groove for holding a plurality of semiconductor substrates 1 is prepared. Next, the two semiconductor substrates 1 are inserted into the cassette groove so that the second surfaces 1S face each other. Then POCl 3 is diffused. At this time, since the interval between the semiconductor substrates 1 is narrow, the amount of dopant diffused into the second surface 1S is reduced as compared with the first surface 1F. Thereby, the 2nd layer 2b whose sheet resistance is higher than the 1st layer 2a can be formed.
  • the through hole 3 is provided in the semiconductor substrate 1, the vicinity of the through hole 3 in the second surface 1S can increase the amount of dopant diffusion, and the dopant concentration of the second layer 2b. Can be lowered as the distance from the through hole 3 (third layer 3c) increases.
  • the reverse conductivity type layer 2 when the semiconductor part 6 is formed with an aluminum paste as will be described later, the semiconductor part 6 is diffused to a sufficient depth with a sufficient concentration of aluminum as a p-type dopant element. Can be formed. Therefore, in this case, the existence of the shallow diffusion region that has already been formed can be ignored. That is, in this case, the reverse conductivity type layer 2 existing at the formation target portion of the semiconductor layer 6 may not be removed.
  • pn separation may be performed by a known method such as laser irradiation around the region where the first electrode 4 is formed or the peripheral portion of the second surface 1S of the semiconductor substrate 1.
  • the antireflection layer 7 is formed on the first layer 2a.
  • a PECVD method a vapor deposition method, a sputtering method, or the like can be used.
  • the reaction chamber is set to about 500 ° C. and silane (Si 3 H 4 ) diluted with nitrogen (N 2 ) and ammonia (NH 3 ).
  • the anti-reflective layer 7 is formed by depositing the gas mixture with) into plasma by glow discharge decomposition.
  • the antireflection layer 7 may also be formed on the third layer 2c.
  • the semiconductor portion 6 is formed on the second surface 1S of the semiconductor substrate 1.
  • boron is used as a dopant element, it can be formed at a temperature of about 800 to 1100 ° C. by a thermal diffusion method using BBr 3 (boron tribromide) as a diffusion source.
  • BBr 3 boron tribromide
  • a reduction layer may be formed prior to the formation of the semiconductor portion 6, a diffusion made of an oxide film or the like on a region other than the formation target portion of the semiconductor portion 6, for example, on the already formed reverse conductivity type layer 2 or the like.
  • a reduction layer may be formed.
  • the diffusion reduction layer may be removed after the semiconductor portion 6 is formed.
  • an aluminum paste made of aluminum powder and an organic vehicle or the like is applied to the second surface 1S of the semiconductor substrate 1 by a printing method, followed by heat treatment (baking at a temperature of about 700 to 850 ° C. )do it.
  • the semiconductor part 6 is formed by diffusing aluminum toward the semiconductor substrate 1.
  • the semiconductor part 6 which is a desired diffusion region can be formed only on the second surface 1S which is the printing surface of the aluminum paste.
  • a layer made of aluminum formed on the second surface 1S after firing can also be used as the current collector 5b.
  • the light-receiving surface electrode part and the conduction part 4b are formed using, for example, a coating method. Specifically, a coating film is formed on the first surface 1F of the semiconductor substrate 1 by applying a conductive paste in the formation pattern of the light receiving surface electrode portion shown in FIG. By baking the formed coating film at a maximum temperature of 500 to 850 ° C. for several tens of seconds to several tens of minutes, the light receiving surface electrode portion and the conductive portion 4b can be formed.
  • the conductive paste used here for example, 10 to 30 parts by weight of an organic vehicle and 0.1 to 10 parts by weight of glass frit can be added to 100 parts by weight of a metal powder made of silver or the like. .
  • the conductive portion 4b can also be formed in the same step as the step of forming the light receiving surface electrode portion by filling the through hole 3 with the conductive paste when applying the conductive paste.
  • the through-hole 3 may not be sufficiently filled with the conductive paste when the conductive paste is applied to the first surface 1F. This is because the conductive paste is applied again from the second surface 1S side when the first output extraction portion 4c to be described later is formed, so that the conductive paste is again filled in the through hole 3. It is.
  • the solvent in a coating film may be evaporated at a predetermined temperature before baking, and this coating film may be dried.
  • the light-receiving surface electrode part (including the main electrode part 4a) and the conductive part 4b may be separately applied and baked.
  • the conductive paste is filled and dried only in the through-holes 3 in advance, and then the conductive pattern is used in the pattern of the light-receiving surface electrode portion (including the main electrode portion 4a) shown in FIG. The paste may be applied and fired.
  • the light receiving surface electrode portion may be formed after the antireflection film 7 is patterned. Further, the light receiving surface electrode portion may be formed by a fire-through method after the antireflection film 7 is formed.
  • the antireflection layer 7 may be formed after the light receiving surface electrode portion is formed.
  • the conditions for forming the light-receiving surface electrode portion are moderate. If it is such a process, a light-receiving surface electrode part can be formed, without baking at the high temperature of about 800 degreeC, for example. As a result, damage to the semiconductor substrate 1 due to heat can be reduced.
  • the current collector 5b is formed on the second surface 1S of the semiconductor substrate 1.
  • the current collector 5b can also be formed using a coating method.
  • a conductive paste is applied on the second surface 1S of the semiconductor substrate 1 so as to form a pattern of the current collector 5b as shown in FIG.
  • the current collector 5b is formed by baking the formed coating film at a maximum temperature of 500 to 850 ° C. for about several tens of seconds to several tens of minutes.
  • the conductive paste used here for example, a paste obtained by adding 10 to 30 parts by mass of an organic vehicle and 0.1 to 10 parts by mass of glass frit to 100 parts by mass of metal powder made of aluminum or silver or the like is used. be able to.
  • the semiconductor part 6 and the current collection part 5b can be formed in the same process.
  • the 1st output extraction part 4c and the 2nd output extraction part 5a are formed on the second surface 1S of the semiconductor substrate 1.
  • the 1st output extraction part 4c and the 2nd output extraction part 5a can be formed in one process using a coating method, for example.
  • a conductive paste is applied to the second surface 1S of the semiconductor substrate 1 so as to have a pattern as shown in FIG. 2 or FIG.
  • the formed coating film can be formed by baking at a maximum temperature of 500 to 850 ° C. for several tens of seconds to several tens of minutes.
  • the conductive paste used here for example, a paste obtained by adding 10 to 30 parts by weight of an organic vehicle and 0.1 to 10 parts by weight of glass frit to 100 parts by weight of metal powder made of silver or the like can be used. .
  • the 1st output extraction part 4c and the 2nd output extraction part 5a may be formed in a separate process, and may be formed using the conductive paste of a different composition.
  • the semiconductor part 6 and the current collection part 5b are formed in one process using an aluminum paste, a part of 2nd output extraction part 5a may be formed on the 2nd layer 2b.
  • the solar cell element 10 according to the present embodiment can be manufactured by the procedure as described above.
  • the metal member in a predetermined region is removed to form the first wiring, the second wiring, and the third wiring.
  • an insulating sheet having an opening is placed on the base sheet to prepare the wiring material 15.
  • the wiring material 15 is connected to the first output extraction portion 4 c and the second output extraction portion 5 a by heating the connection portion between the wiring material 15 and the solar cell element 10. Moreover, you may connect each string with a connection material as needed.
  • the conductive adhesive for example, a conductive filler such as silver, nickel, or carbon may be used.
  • the binder contained in the conductive adhesive may be, for example, an epoxy resin, a silicon resin, a polyimide resin, or a polyurethane resin.
  • a plurality of solar cell elements 10 connected to each other by the front side filler 12, the wiring material 15, the back side filler 13, and the back surface protective material 14 are sequentially laminated, A module substrate is produced.
  • the module base is pressed while being heated by a laminator or the like, thereby integrating the constituent members of the module base.
  • the solar cell module 20 is produced through the above steps.
  • the solar cell module 20 may provide the frames 16, such as aluminum, in the outer periphery of the solar cell module 20. As shown in FIG.
  • Such a solar cell module 20 has the solar cell element 10 described above, it has excellent output characteristics.
  • the solar cell element 10 may have a passivation film on the second surface 1S side.
  • the passivation film has a role of reducing carrier recombination on the second surface 1S of the semiconductor substrate 1.
  • Si nitride films such as silicon nitride (Si 3 N 4 ), amorphous Si nitride film (a-SiNx), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ) 2 ) etc. can be used.
  • the thickness of the passivation film may be about 100 to 2000 mm.
  • the semiconductor substrate 1 is exemplified as having a plurality of through-holes.
  • the semiconductor substrate 1 having no through-holes such as a wrap-around solar cell is used. May be.
  • the reverse conductivity type layer 2 corresponding to the second conductivity type semiconductor layer passes through the first layer 2 a located on the first surface 1 F and the side surface of the semiconductor substrate 1. It differs from the above-described solar cell element 10 in that it has a second layer 2b located on the second surface 1S continuously to the first layer 2a.
  • the first electrode 4 is electrically connected to the main electrode portion 4 a via the main electrode portion 4 a located on the first layer 2 a and the side surface of the semiconductor substrate 1.
  • the first output extraction portion 4c is located on the second layer 2b.
  • the reverse conductivity type layer 2 and the first electrode 4 located on the light receiving surface side of the semiconductor substrate 1 are connected to the back surface of the semiconductor substrate 1 via the side surface of the semiconductor substrate 1. Is led to the side. Thereby, a back contact structure is realized. And even if it is such a form, if the sheet resistance of the 1st layer 2a and the sheet resistance of the 2nd layer 2b have the relationship mentioned above, an output characteristic will be improved like the solar cell element 10. FIG. Can be made. Therefore, even in the solar cell module including the solar cell element having such a configuration, the output characteristics can be improved similarly to the solar cell module 20.

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  • Sustainable Development (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Photovoltaic Devices (AREA)

Abstract

L'objectif de la présente invention est de fournir un élément de cellule solaire et un module de cellules solaires dont les caractéristiques de sortie sont améliorées. L'élément de cellule solaire comprend : un substrat semi-conducteur d'un premier type de conductivité (1) possédant une première surface (1F) et une seconde surface (1S) à l'opposé de la première surface ; une couche semi-conductrice d'un second type de conductivité (2) comprenant une première couche (2a) placée sur la première surface (1F) et une seconde couche (2b) placée sur la seconde surface (1S), la seconde couche poursuivant la première couche en traversant le substrat semi-conducteur ou en passant par une surface latérale de celui-ci ; une première électrode (4) comprenant une partie principale d'électrode (4a) placée sur la première couche (2a) et une première partie d'extraction de sortie (4c) placée sur la seconde couche (2b), la première partie d'extraction de sortie étant connectée électriquement à la partie principale d'électrode en traversant le substrat semi-conducteur ou en passant par une surface latérale de celui-ci ; et une seconde électrode (5) placée sur une partie de la seconde surface où la seconde couche (2b) n'est pas présente. Dans cet élément de cellule solaire, la résistance-carrée de la seconde couche (2b) est supérieure à la résistance-carrée de la première couche (2a).
PCT/JP2012/068977 2011-07-28 2012-07-26 Élément de cellule solaire et module de cellules solaires WO2013015362A1 (fr)

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JP2013525752A JP5726308B2 (ja) 2011-07-28 2012-07-26 太陽電池素子および太陽電池モジュール
CN201280037684.1A CN103718305B (zh) 2011-07-28 2012-07-26 太阳能电池元件及太阳能电池模块

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005310830A (ja) * 2004-04-16 2005-11-04 Sharp Corp 太陽電池および太陽電池の製造方法
JP2008270743A (ja) * 2007-03-29 2008-11-06 Kyocera Corp 太陽電池モジュール
WO2009152378A1 (fr) * 2008-06-11 2009-12-17 Solar Implant Technologies Inc. Formation d'un émetteur sélectif de cellule solaire en utilisant un procédé d’implantation et de recuit
JP2011091316A (ja) * 2009-10-26 2011-05-06 Kyocera Corp 太陽電池素子および太陽電池モジュール
JP2011142210A (ja) * 2010-01-07 2011-07-21 Sharp Corp 太陽電池およびその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005310830A (ja) * 2004-04-16 2005-11-04 Sharp Corp 太陽電池および太陽電池の製造方法
JP2008270743A (ja) * 2007-03-29 2008-11-06 Kyocera Corp 太陽電池モジュール
WO2009152378A1 (fr) * 2008-06-11 2009-12-17 Solar Implant Technologies Inc. Formation d'un émetteur sélectif de cellule solaire en utilisant un procédé d’implantation et de recuit
JP2011091316A (ja) * 2009-10-26 2011-05-06 Kyocera Corp 太陽電池素子および太陽電池モジュール
JP2011142210A (ja) * 2010-01-07 2011-07-21 Sharp Corp 太陽電池およびその製造方法

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CN103718305A (zh) 2014-04-09
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JP5726308B2 (ja) 2015-05-27

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