WO2013008415A1 - Wiring board and method for manufacturing three-dimensional wiring board - Google Patents

Wiring board and method for manufacturing three-dimensional wiring board Download PDF

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Publication number
WO2013008415A1
WO2013008415A1 PCT/JP2012/004324 JP2012004324W WO2013008415A1 WO 2013008415 A1 WO2013008415 A1 WO 2013008415A1 JP 2012004324 W JP2012004324 W JP 2012004324W WO 2013008415 A1 WO2013008415 A1 WO 2013008415A1
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WO
WIPO (PCT)
Prior art keywords
substrate
resist
wiring
cavity
surface layer
Prior art date
Application number
PCT/JP2012/004324
Other languages
French (fr)
Japanese (ja)
Inventor
貴之 北
中村 禎志
勇 森田
裕史 不破
Original Assignee
パナソニック株式会社
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Filing date
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Publication of WO2013008415A1 publication Critical patent/WO2013008415A1/en

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4614Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination
    • H05K3/4617Manufacturing multilayer circuits by laminating two or more circuit boards the electrical connections between the circuit boards being made during lamination characterized by laminating only or mainly similar single-sided circuit boards
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4697Manufacturing multilayer circuits having cavities, e.g. for mounting components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227Other objects, e.g. metallic pieces
    • H05K2201/10378Interposers
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/05Patterning and lithography; Masks; Details of resist
    • H05K2203/0562Details of resist
    • H05K2203/058Additional resists used for the same purpose but in different areas, i.e. not stacked
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4069Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in organic insulating substrates
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated

Definitions

  • the present invention relates to a wiring board widely used in various electronic devices such as personal computers, mobile phones for mobile communication, video cameras and the like, and a method of manufacturing the same.
  • Patent Document 1 is known as a method of using a three-dimensional wiring substrate having a cavity as one of methods for easily realizing such reduction in height and three-dimensional mounting of a semiconductor package.
  • Patent Document 2 As a method for preventing the flow of the conductive paste filled in the connection portion, for example, Patent Document 2 is known.
  • the conventional three-dimensional wiring substrate disclosed in Patent Document 1 generally uses a prepreg for the bonding portion, but since the prepreg contains a core material such as a woven fabric, a non-woven fabric, or a film, it is particularly conductive. Although it is effective for shape retention of vias made of paste, it is difficult to embed the wiring patterns formed on the upper and lower printed wiring board surfaces.
  • two wiring boards are attached at the bonding portion to form a three-dimensional wiring board, and then through holes are formed in the three-dimensional wiring board with a drill or the like.
  • a technique for forming a via hole by plating was also proposed, but in this case, the via hole penetrates both the bonding portion and the two wiring boards (or IVH does not have an IVH structure, so IVH means the meaning of Interstitial Via Hole).
  • IVH means the meaning of Interstitial Via Hole.
  • the present invention has been made in view of the above problems, and is a wiring board in which a first substrate and a second substrate are connected by an adhesive portion, and a wire which prevents the adhesive portion from flowing out into the cavity. It will be a substrate. Therefore, high density mounting of semiconductors and the like in the cavity and wiring density are enhanced.
  • a wiring substrate which is one aspect of the present invention has a first substrate having an opening and a first surface wiring disposed in the surface, and a second surface wiring disposed in the surface. It is a wiring board which has a 2nd substrate. And an adhesion part is arranged between the 1st substrate and the 2nd substrate, and the 1st substrate and the 2nd substrate are pasted up mutually. Furthermore, a resist portion is disposed between the first substrate and the second substrate, and the resist portion is in contact with the first substrate and the second substrate. Furthermore, the opening forms a cavity whose bottom surface is the second substrate, and the bonding part has a via made of a conductive paste filled in a hole formed in the bonding part. The via electrically connects the first surface layer wiring and the second surface layer wiring, and at least a portion of the resist portion is formed in a region where the first substrate and the second substrate face each other and which surrounds the cavity. It is characterized by
  • the outflow of the bonding portion into the cavity can be prevented, so that further miniaturization, thinness, light weight, high definition, multifunctionalization and the like of the three-dimensional wiring substrate can be realized.
  • the manufacturing method of the three-dimensional wiring board which is the other aspect of this invention can manufacture the said wiring board.
  • FIG. 1 is an enlarged cross-sectional view of a part of the three-dimensional wiring substrate in the first embodiment of the present invention.
  • FIG. 2 is a perspective view schematically showing the situation in which the three-dimensional wiring substrate in the first embodiment of the present invention is formed.
  • FIG. 3 is a perspective view schematically showing the entire three-dimensional wiring board in the first embodiment of the present invention.
  • FIG. 4A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 4B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 4A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 4B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Em
  • FIG. 4C is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 4D is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 5A is a cross-sectional view showing an example of a method of manufacturing a body wiring board in the first embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention.
  • FIG. 6 is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the first embodiment of the present invention.
  • FIG. 5A is a cross-sectional view showing an example of a method of manufacturing a body wiring board in the first embodiment of the present invention.
  • FIG. 5B is a cross-sectional view showing an example of
  • FIG. 7 is an enlarged sectional view of a part of the three-dimensional wiring substrate in the second embodiment of the present invention.
  • FIG. 8A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 2 of the present invention.
  • FIG. 8B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 2 of the present invention.
  • FIG. 9A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the second embodiment of the present invention.
  • FIG. 9B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the second embodiment of the present invention.
  • FIG. 10 is a perspective view schematically showing a part of a cross section taken along arrow 10 in FIG. 11A is a perspective view schematically showing a part of a cross section taken along arrow 11 in FIG. 11B is a perspective view schematically showing a part of a cross section taken along arrow 11 in FIG.
  • FIG. 12A is a perspective view schematically showing a state in which the adhesive layer is prevented from flowing out to the cavity side.
  • FIG. 12B is a perspective view schematically showing a state in which the adhesive layer is prevented from flowing out to the cavity side.
  • FIG. 13A is a cross-sectional view showing how the resists adhere or adhere to each other.
  • FIG. 13B is a cross-sectional view showing how the resists adhere or adhere to each other.
  • FIG. 13A is a cross-sectional view showing how the resists adhere or adhere to each other.
  • FIG. 13C is a cross-sectional view showing how the resists adhere or adhere to each other.
  • FIG. 14 (a) is a cross-sectional view showing the state of the fixed surface
  • FIG. 14 (b) is a top view of the interface portion of the fixed surface.
  • FIG. 15 is a view showing a photomicrograph of the peeled surface of the sample actually prepared.
  • FIG. 16 is a plan view schematically showing the microphotograph of FIG.
  • FIG. 17 is an enlarged sectional view of a part of a three-dimensional wiring board according to a modification of the second embodiment of the present invention.
  • FIG. 18 is an enlarged sectional view of a part of the three-dimensional wiring substrate according to the third embodiment of the present invention.
  • FIG. 19 is a perspective view schematically showing a part of a cross section of a three-dimensional wiring substrate in the third embodiment of the present invention.
  • FIG. 20 is a perspective view schematically showing a part of a cross section of a three-dimensional wiring substrate in the third embodiment of the present invention.
  • FIG. 21 is a cross-sectional view showing a part of the semiconductor mounted structure in an enlarged manner, in the fourth embodiment of the present invention.
  • FIG. 22A is a cross-sectional view schematically illustrating how metal powder is deformed.
  • FIG. 22B is a cross-sectional view schematically illustrating how the metal powder is deformed.
  • FIG. 23 is a diagram showing an example of a trial production result.
  • FIG. 24 is a perspective view for explaining the first comparison substrate.
  • FIG. 24 is a perspective view for explaining the first comparison substrate.
  • FIG. 25 is a perspective view for explaining the first comparison substrate.
  • FIG. 26 is a perspective view for explaining the first comparison substrate.
  • FIG. 27A is a cross-sectional view showing a second method of manufacturing a three-dimensional wiring substrate.
  • FIG. 27B is a cross-sectional view showing a second method of manufacturing the three-dimensional wiring substrate.
  • FIG. 27C is a cross-sectional view showing a second method of manufacturing the three-dimensional wiring substrate.
  • Embodiment 1 ⁇ Structure of Embodiment 1>
  • Embodiment 1 of the present invention will be described with reference to the drawings.
  • FIG. 1 is an enlarged cross-sectional view of a part of the three-dimensional wiring substrate in the first embodiment of the present invention.
  • the three-dimensional wiring substrate 110 is formed by bonding the first substrate 120 and the second substrate 130 at the bonding portion 140.
  • the first substrate 120 is formed of an insulating layer 160 and a first surface layer wiring 170 formed on the surface of the insulating layer 160.
  • the second substrate 130 is formed of an insulating layer 160 and a second surface layer wiring 180 formed on the surface of the insulating layer 160. Holes (numbers are not assigned to the holes, and are illustrated as holes 270 in FIG. 4B described later) are formed in the bonding portion 140, and the holes are filled with the conductive paste 150.
  • the conductive paste 150 also functions as a via, and electrically connects the first surface wiring 170 and the second surface wiring 180.
  • the first substrate 120 has an opening, and the opening becomes a cavity 190. The configuration of the cavity will be described later with reference to FIGS. 2 and 3.
  • the resist 220 is disposed in a region (peripheral portion 200) in which the first substrate 120 and the second substrate 130 face each other and surrounds the cavity 190, the upper surface is in contact with the first substrate, and the lower surface is in contact with the second substrate. ing.
  • a conductive paste 150 containing metal powder is used.
  • FIG. 2 is a perspective view schematically showing the situation in which the three-dimensional wiring substrate in the first embodiment of the present invention is formed.
  • FIG. 3 is a perspective view schematically showing the entire three-dimensional wiring board in the first embodiment of the present invention.
  • an opening 290 is formed in the first substrate 120.
  • the first substrate 120 and the second substrate 130 are integrated as indicated by an arrow 280 via an adhesive portion (not shown in FIGS. 2 and 3).
  • a three-dimensional wiring board (hereinafter referred to as a three-dimensional wiring board) having a cavity 190 is formed.
  • the wiring board having a cavity as in this embodiment is referred to as a three-dimensional wiring board, it may be called a wiring board without any problem.
  • a wiring substrate (so-called completed wiring substrate) using an insulating layer 160 as the first substrate 120 and the second substrate 130, using a commercially available glass epoxy resin (using an insulating layer formed by impregnating glass fiber with the epoxy resin) Can be used.
  • a first surface layer wiring 170 and a second surface layer wiring 180 are formed on the surfaces of the first substrate 120 and the second substrate 130 that face each other through the bonding portion 140.
  • As the first surface layer wiring 170 and the second surface layer wiring 180 those obtained by etching a commercially available copper foil (for example, having a thickness of 18 to 36 ⁇ m or the like) can be used. It is also useful to use an ALIVH substrate (ALIVH is a registered trademark of Panasonic Corporation) as the first substrate 120 and the second substrate 130.
  • ALIVH substrate ALIVH is a registered trademark of Panasonic Corporation
  • the ALIVH substrate has the Any Layer Interstitial Via Hole, the degree of freedom in wiring design of the three-dimensional wiring substrate 110 is enhanced.
  • via paste (not shown in FIG. 1 and the like) is used for interlayer connection of the ALIVH substrate, the reliability of the via portion at the time of compression is improved with respect to a wiring substrate using ordinary plated vias. high. Therefore, in order to increase the adhesion between the first surface layer wiring 170 and the second surface layer wiring 180 and the conductive paste 150, the effects of the pressure and the heating of the first substrate 120 and the second substrate 130 in the case of pressing and heating. It is hard to receive.
  • the resist 220 a commercially available solder resist can be used.
  • 4A to 4D, 5A, 5B, and 6 are cross-sectional views showing an example of a method of manufacturing the three-dimensional wiring substrate 110.
  • the protective film 260 is formed in the both surfaces of the adhesion part 140.
  • a resin film with a thickness of 5 to 50 microns such as a PET film, can be used.
  • the bonding part 140 for example, a bonding part having a thickness of 5 to 200 microns, which contains a thermosetting resin and an inorganic filler for adjusting the thermal expansion coefficient, can be used.
  • holes 270 are opened in the protective film 260 and the bonding part 140.
  • a drill or a laser can be used to form the holes 270.
  • the holes 270 are filled with the conductive paste 150.
  • a commercially available screen printer can be used for the filling of the conductive paste 150.
  • an opening 290 b is formed in the bonding portion 140 and the protective film 260.
  • a punching method or a cutting method using a mold or a laser can be selected.
  • a part of the bonding part 140 is removed as shown by the arrow 280, and the opening 290 is also provided in the bonding part 140.
  • the protective film 260 is removed (step of removing the protective film 260 is not shown in FIG. 4).
  • the method for forming the opening 290 and the like has been described with reference to FIGS. 4A to 4D, the method for forming the opening 290 is not limited to this, and the order of the steps is also limited to this. It is not something to be done.
  • the adhesive film 140 and the conductive paste 150 shown in FIG. 5A are obtained by removing the protective film 260 from the structure shown in FIG. 4D.
  • the trace from which the protective film has been removed is a portion (protruding portion 300) where the conductive paste 150 protrudes from the surface of the bonding portion 140.
  • the thickness of the protrusion 300 can be adjusted by the thickness of the protective film 260.
  • the first substrate 120 has an opening 290 a and has a first surface wiring 170 on the surface.
  • the second substrate 130 has the surface layer second surface wiring 180.
  • a resist 220 is formed on the second surface wiring 180.
  • the resist 220 is formed on the periphery (peripheral portion 200) of the opening of the first substrate 120 with the first substrate 120 and the second substrate 130 facing each other.
  • the resist 220 is formed at a position closer to the cavity than the bonding portion 140.
  • the resist 220 is formed on the second surface layer wiring 180 in FIG. 1 and the like, the surface layer wiring does not necessarily have to be formed under the resist 220, and is formed on the insulating layer 160. May be
  • a conductive paste 150 having a bonding portion 140 and a projecting portion 300 shown in FIG. 4D is set between the first substrate 120 and the second substrate 130.
  • the opening 290 b provided in the bonding unit 140 is made larger than the opening 290 a provided in the first substrate 120.
  • the opening 290 b formed in the bonding part 140 is provided outside the resist 220 (or on the side farther from the cavity 190 formed by stacking these). By this, the overlap between the bonding portion 140 and the resist 220 can be reduced.
  • FIG. 5A is pressed, and a state in which the first substrate 120 and the second substrate 130 are integrated by the bonding part 140 sandwiched in the middle is shown in FIG. 5B, and the result of pressing is shown in FIG.
  • the pressing device and the mold are not shown.
  • a gap 310 is formed in the process of pressing, and the vented arrow 320 indicates, for example, a state in which air remaining in the gap between the first substrate 120, the second substrate 130, and the bonding portion 140 is released (or ventilated) to the outside.
  • the vented arrow 320 indicates, for example, a state in which air remaining in the gap between the first substrate 120, the second substrate 130, and the bonding portion 140 is released (or ventilated) to the outside.
  • a contact portion in which the resist 220 and the first substrate 120 are in close contact with the region (peripheral portion 200) where the first substrate 120 and the second substrate 130 face each other.
  • the contact portion is shown in FIG.
  • an adhesion portion in which parts of the surface of the resist 220 adhere to each other is formed.
  • the adhesion portion 140 which has been pressurized, heated and softened is reliably prevented from flowing into the interior of the cavity 190 from the gap of the resist 220. can do.
  • the side surface is formed by the opening of the first substrate 120, the resist 220, and the bottom surface is formed by the second substrate 130.
  • the first substrate 120 and the second substrate 130 are connected by the resist 220 at the periphery of the cavity.
  • the flow out of the bonding portion 140 into the cavity 190 can be more reliably prevented.
  • the effect of preventing the bonding portion 140 from flowing into the cavity 190 can be obtained without necessarily forming the resist 220 so as to surround the entire peripheral region of the cavity 190.
  • the second surface layer wiring 180 provided on the surface layer of the second substrate 130 is drawn out into the cavity 190, whereby a fanout-type routing is made at the peripheral portion 200 of the cavity 190.
  • the formation of the pattern is very easy. That is, the second surface layer wiring 180 provided on the surface layer of the second substrate 130 can be drawn directly into the cavity 190 at the shortest distance, and a semiconductor chip or the like is directly mounted on the second surface layer wiring 180. Can. As a result, the line length of the wiring can be kept shortest on the same plane without via holes and the like, and the ESR (equivalent series resistance) and ESL (equivalent series inductance) of the three-dimensional wiring board 110 can be reduced.
  • the conductive paste 150 filling the electrical connection between the first surface layer wiring 170 and the second surface layer wiring 180 is used, the first surface layer wiring 170 and the second surface layer wiring 180 are used. It is possible to increase the design freedom of the wiring pattern of the inner layer to be formed and the like (both not shown in FIG. 1). The reason for the increased design freedom is that the via made of the conductive paste 150 can be made IVH.
  • FIG. 7 is an enlarged sectional view of a part of the three-dimensional wiring substrate in the second embodiment of the present invention.
  • the same components as in the first embodiment described with reference to FIG. 1 will be assigned the same reference numerals and descriptions thereof will be omitted.
  • the configuration of the first embodiment differs from the configuration of the second embodiment in the structure of the resist portion, which is the resist 220 in the first embodiment shown in FIG. 1, while in the second embodiment shown in FIG. The point is that the portion is formed of the first resists 220a and 220b.
  • description is abbreviate
  • the manufacturing method of the bonding portion 140 and the conductive paste 150 in the first embodiment described with reference to FIGS. 4A to 4D is the same as that of the first embodiment, and thus the drawings are omitted.
  • 8A, 8B, and 9A are cross-sectional views showing an example of a method of manufacturing the three-dimensional wiring substrate 110 according to the second embodiment.
  • the difference from the first embodiment is that the first resist 220 a is formed on the insulating layer 160 forming the first substrate 120, and the second resist 220 b is formed on the insulating layer 160 forming the second substrate 130. It is only a point.
  • the first resist 220a and the second resist 220b are mutually heated and pressed to be in close contact with each other, so that the surface shapes of the first and second resists 220a and 220b are matched (or a surface formed by fitting) with each other. It remains to correspond to each other. This is because the first resist 220a and the second resist 220b are softened together when pressurized and heated. Even if the trace parts 340 are in contact with each other or apart from each other, there is no influence on the flow preventing effect of the adhesive part 140 into the cavity 190.
  • the reason why the flow prevention effect is not affected is that, even if the first resist 220a and the second resist 220b constituting the trace portion 340 are separated from each other, the distance is substantially constant (further, all around the cavity 190). Because it is narrow.
  • FIG. 10 is a schematic view showing a part of the cross section in arrow 10 of FIG.
  • FIG. 10 corresponds to an enlarged perspective view in which the side surface of the cavity 190 is observed from the inside of the cavity 190.
  • the undeformed resist 370 corresponds to, for example, a first resist 220a provided on the peripheral portion 200 of the cavity 190 shown in FIG.
  • the concavo-convex resist 380 corresponds to a second resist 220 b that covers a part of the second surface layer wiring 180 provided on the surface layer of the second substrate 130.
  • the unevenness of the uneven resist 380 is caused by the thickness of the second surface layer wiring (for example, fan-out wiring) embedded in the second resist 220 b.
  • the thickness of the second surface layer wiring is effective for ensuring air permeability at the time of lamination. Further, the unevenness does not have to depend only on the thickness of each second surface layer wiring. In addition to the unevenness generated due to the presence or absence of the surface layer wiring, even if the unevenness is caused by the waviness or the like of the second substrate, it is effective for ensuring air permeability at the time of lamination.
  • An arrow 280 indicates that the first resist 220a and the second resist 220b are pressed, heated, and brought into close contact with each other in a state of facing each other.
  • FIG. 11A is a perspective view schematically showing a state in which the first resist 220 a and the second resist 220 b facing each other are provided on the peripheral portion 200 of the cavity 190 of the first substrate 120 and the second substrate 130.
  • a ventilation arrow 320 in FIG. 11A indicates a state in which internal air escapes (vents) to the outside through the gap 310 of the unevenness due to the second surface layer wiring 180 in which the second resist 220b is embedded.
  • FIG. 11B is a perspective view schematically showing a state in which the first resist 220 a and the second resist 220 b facing each other are provided on the peripheral portion 200 of the cavity 190 of the first substrate 120 and the second substrate 130. is there. Even when the first resist 220a and the second resist 220b are in close contact with each other as shown in FIG. 11B, air permeability can be maintained as shown by the air flow arrow 320 from the gap of the unevenness of the surface of the second resist 220b. It becomes possible. Thereafter, they can be brought into close contact with each other by pressurizing and heating them.
  • FIGS. 12A and 12B schematically show that the first resist 220 a and the second resist 220 b are mutually heated and adhered in a softened state, thereby preventing the softened adhesive portion 140 from flowing out to the cavity 190 side. It is a perspective view shown to.
  • both 390a and 390b are deformed resists, and the first resist 220a and the second resist 220b in a heated state are pressed against each other, and they are mutually deformed.
  • FIG. 12A shows that the first resist 220a and the second resist 220b still maintain close contact with each other as the deformed resists 390a and 390b even after completion (that is, after the adhesive portion 140 is thermally cured).
  • the adhesive surface is shown by dotted line 330 in FIG. 12A.
  • the first resist 220a and the second resist 220b which are in close contact with each other are in close contact with each other after completion (that is, after the adhesive portion 140 is thermally cured).
  • the gap 310 is uniform and sufficiently narrow, thereby preventing the adhesive portion 140 from flowing out to the cavity 190 side. You can do it.
  • first resist 220a and the second resist 220b are heated and brought into close contact with each other to form a replica state in which the shape of the other is transferred to itself. Therefore, the contact surfaces of the first resist 220a and the second resist 220b are deformed. This deformed contact surface is called a deformed portion.
  • 13A to 13C are cross-sectional views showing how a part of the first resist 220a and a part of the second resist 220b adhere or adhere to each other.
  • the bonding portion 140 has not flowed to the vicinity of the first resist 220a and the second resist 220b.
  • the arrow SR1 indicates the thickness of the first resist 220a
  • the arrow SR2 indicates the thickness of the second resist 220b
  • the arrow T indicates the thickness of the bonding portion 140.
  • the first substrate 120 and the second substrate 130 are pressurized and heated.
  • an adhered surface or an adhered surface is formed in which a part of the first resist 220a and a part of the second resist 220b adhere or adhere to each other.
  • the adhesive or bonding surface is indicated by a dotted line 330.
  • the close contact surface means that the first resist 220a and the second resist 220b are in close contact with each other. When the first resist 220a and the second resist 220b are in close contact with each other, they may be deformed due to the influence of their surface shapes.
  • cohesive failure may not occur even if it is attempted to peel off the close contacts.
  • adhere refers to a state in which parts are physically and chemically integrated while being in close contact with each other. Therefore, when it is going to peel away the adhering partner, the part may carry out cohesive failure.
  • FIGS. 14A and 14B when a part of the first resist and a part of the second resist are mutually adhered and integrated, or a part of the first resist and a part of the second resist are integrated. They are sectional drawing explaining the adhering surface at the time of adhering and integrating mutually via an adhesion part, and a top view of the interface portion.
  • a part of the first resist 220a and a part of the second resist 220b are adhered and integrated with each other, or a part of the first resist 220a and a part of the second resist 220b are adhered. They are formed by being fixed and integrated with each other through the portion 140.
  • FIG. 14B is a top view showing an example of the peeling portion in the dotted line 330 (that is, the adhesion surface or the adhesion surface) of the adhesion resist 400.
  • the peeling surface of the fixing resist 400 can be obtained, for example, by peeling the first substrate 120 and the second substrate 130 that constitute the three-dimensional wiring substrate 110 from each other.
  • FIG. 14 (b) is an example of the peeling surface.
  • the second resist 220b serving as a base, the liquid bonding portion 410, and the trace portion (or aggregation portion) 340 can be observed on the peeling surface.
  • the inorganic filler or the like contained in the adhesive portion 140 intrudes into the gap between the first resist 220a and the second resist 220b as shown by the arrow 380, the inorganic filler or the like in the gap Is a cured product of the liquid resin component obtained by filtration.
  • the trace portion 340 may be used as an aggregation portion.
  • the aggregation portion 340 is a peeling surface formed by peeling a part of the first resist 220a, a part of the second resist 220b, the liquid bonding part 410, or a part of the bonding part 140 Or cohesively broken parts (when they are stuck to each other).
  • the trace portion 340 may be an aggregation portion 340 formed by aggregation and destruction. This is because there is no difference whether it is a trace part or an aggregation part.
  • the first resist 220a and the second resist 220b are in close contact with each other, or with the entire surface and a part, or all surfaces, and adhere An adhesion resist 400 is formed. Further, the adhering surface by the adhering resist 400 prevents the exudation or the exudation of the resin component constituting the adhesive portion 140.
  • a liquid component for example, liquid adhesive portion 410 that has leaked out from the adhesive portion 140 is also useful for forming such a sticking resist 400.
  • FIG. 15 is a view showing a micrograph of the peeled surface of a sample actually prepared by the inventor.
  • FIG. 16 is a plan view schematically showing the microphotograph of FIG.
  • a region indicated by an arrow 480 in FIGS. 15 and 16 corresponds to a peeling portion between the first resist 220a and the second resist 220b.
  • the fixing resist 400 desirably has the members fixed, but may be in close contact with each other. This is because they are in close contact with each other, and when these members are peeled off as shown in FIGS. Therefore, if the interface of the exfoliation part of these members is observed with a microscope or SEM, and if the trace of these adhering (or adhering) is observed, it is sufficient.
  • the purpose of the present invention is to achieve the effects of the present invention.
  • a special and expensive analysis method is required to distinguish adhesion and adhesion, and in the present invention, the operation and effect are the same whether it is adhesion or adhesion.
  • the first resist 220a and a portion of the second resist 220b are in close contact or adhered to each other, or a portion of the first resist 220a and a portion of the second resist 220b are If the members are in close contact or adhered through the adhesive portion, the excellent effects of the present invention can be exhibited.
  • the resist and the insulating layer 160 are bonded in the first embodiment, since the resists are in close contact with each other in the second embodiment, the adhesion is higher than in the first embodiment. Therefore, in the second embodiment, compared to the first embodiment, it is possible to prevent the adhesive from flowing into the cavity more reliably.
  • FIG. 17 is a cross-sectional view enlarging a part of a three-dimensional wiring board in a modification of the second embodiment of the present invention.
  • the point different from the second embodiment is that the resist 220a protrudes into the cavity. As shown in FIG. 17, a part of the resist 220 protrudes into the cavity 190, so that an effect of absorbing an alignment error with the peripheral portion 200 of the first substrate 120 can be obtained.
  • the manufacturing method can also be manufactured by the same method as that of the second embodiment.
  • Embodiment 3 of the present invention will be described with reference to the drawings.
  • FIG. 18 is an enlarged sectional view of a part of the three-dimensional wiring board in the third embodiment of the present invention.
  • the same components as in the second embodiment described with reference to FIG. 7 are assigned the same reference numerals and descriptions thereof will be omitted.
  • the difference from the configuration of the second embodiment is that in the second embodiment shown in FIG. 7, the first surface layer wiring 170 does not enter between the first resist 220 a and the insulating layer 160.
  • the third embodiment shown in FIG. 18 is only that the first surface layer wiring 170a is formed between the first resist 220a and the insulating layer 160.
  • explanation is omitted.
  • the manufacturing method of the third embodiment is the same as the manufacturing method of the three-dimensional wiring substrate of the first embodiment and the second embodiment, so the description will be omitted.
  • the peripheral portion 200 is provided with a first resist 220 a and a first surface layer wiring 170 overlapping the first resist 220 a, and the second substrate 130 constituting the peripheral portion 200 of the cavity 190 is a second
  • the second surface layer wiring overlapping with the resist 220 b and the second resist 220 b is provided will be described.
  • the first substrate 120 constituting the peripheral portion 200 of the cavity 190 is provided with a first resist 220 a and a first surface layer wiring 170 overlapping the first resist 220 a to form the peripheral portion 200 of the cavity 190.
  • the second substrate 130 is provided with a second resist 220 b and a second surface wiring overlapping the second resist 220 b. As described above, by providing the surface layer wiring so as to overlap the resist facing each other at the peripheral portion of the cavity 190, it is possible to reduce the bleeding of the bonding portion 140 to the cavity 190 side.
  • FIG. 19 is a cross-sectional view for explaining the case where a line-shaped surface layer wiring is provided so as to overlap with the opposing resist at the peripheral portion of the cavity 190.
  • the line-shaped first surface layer wiring 170 is formed on the first substrate 120 side so that the second surface layer wiring 180 consisting of fan-out wiring overlaps the second resist 220 b. It is provided to overlap 220a.
  • the line-shaped first surface layer wiring 170 is desirably provided so as to be orthogonal to the second surface layer wiring 180 which is a fan-out wiring.
  • FIG. 20 is a cross-sectional view for explaining the case where a surface layer wiring of a reverse (for example, a negative-positive reverse pattern) surface layer is provided so as to overlap with the opposing resist at the peripheral portion of the cavity 190.
  • a line-shaped first surface layer wiring 170 is formed on the first substrate 120 side so that the second surface layer wiring 180 consisting of fan-out wiring overlaps the second resist 220b on the second substrate 130 side. It is provided to overlap 220a.
  • the line-shaped first surface layer wiring 170 is desirably provided so as to fill (or invert) the unevenness of the second surface layer wiring 180 which is a fan-out wiring.
  • FIG. 21 is a three-dimensional wiring substrate in which the semiconductor element 230 is mounted inside the cavity 190 of the three-dimensional wiring substrate 110 described with reference to FIG. 7.
  • a semiconductor mounted product in which a semiconductor element is connected to a wiring board is referred to as a semiconductor mounted structure 250.
  • the semiconductor element 230 is mounted on the second surface layer wiring 180 exposed in the cavity 190 provided in the three-dimensional wiring substrate 110 shown in FIG. 7.
  • a solder bump is used as the mounting portion 240.
  • the semiconductor element 230 is not limited to a silicon semiconductor, and includes a bare chip, a chip part, an optical element such as a lens, or an optical element. Wire bonding or the like may be used as the mounting unit 240.
  • the semiconductor element 230 can be resin-sealed using a commercially available potting resin (sealing resin) or the like as necessary.
  • the semiconductor mounting structure 250 in which the semiconductor element 230 is mounted on the wiring substrate can contribute to downsizing and high performance of various mobile terminals such as mobile phones.
  • FIGS. 22A and 22B are cross-sectional views schematically illustrating how metal powders contained in the conductive paste 150 are compressed and deformed with each other by the function and effect of the protrusion 300.
  • FIG. 22A is a cross-sectional view before the conductive paste 150 is pressure-compressed
  • FIG. 22B is a cross-sectional view after the conductive paste 150 is pressure-compressed.
  • the metal powder 350 contained in the conductive paste 150 is deformed to form a surface contact portion to form a deformed powder 360.
  • a thermosetting resin such as an epoxy resin, a dispersant, an additive, a solvent, and the like may be added to the conductive paste 150 as necessary.
  • the various members such as these thermosetting resins are not shown in FIGS. 22A and 22B.
  • Arrow 280 a corresponds to the thickness of conductive paste 150 before compression.
  • the conductive paste is compressed more by the thickness of the first surface layer wiring 170 and the second surface layer wiring 180 provided so as to project from the surface of the protrusion 300, the first substrate 120, and the second substrate 130. , The state shown in FIG. 22B.
  • the plurality of metal powders 350 form deformed powder 360 which is in surface contact via a surface contact portion (or surface contact surface) indicated by dotted lines 330 which are compressed and deformed with each other. Also, at the interface between the deformed powder 360 and the deformed powder 360, a surface contact portion (or an interface in surface contact) indicated by a dotted line 330 is formed. Then, the plurality of metal powders 350 are electrically connected via the surface contact portion indicated by the dotted line 330, and the via resistance between the first surface layer wiring 170 and the second surface layer wiring 180 is reduced.
  • Arrow 280 b in FIG. 22B indicates the thickness of the conductive paste 150 after being compressed. It goes without saying that the relationship “280a> 280b” is shown as described above.
  • the prototype of the comparative substrate 1 will be described below with reference to FIGS. 24 to 26.
  • FIG. 24 is a perspective view for explaining the first comparison substrate 420.
  • the first comparison resist 430 is disposed in the cavity.
  • the first substrate 120 and the second substrate 130 are brought into pressure contact with each other, resulting in the state of FIG.
  • FIG. 25 is an enlarged perspective view of the vicinity of the cavity 190 of the first comparison substrate 420. As shown in FIG. 25, a gap 310 a is formed between the first comparison resist 430 and the first substrate 120. Further, a gap 310 b resulting from the thickness of the second surface layer wire 180 is formed between the first substrate 120 and the second substrate 130.
  • the ventilation arrow 320 indicates how internal air leaks to the outside through the gaps 310 b and 310 a.
  • FIG. 26 is a perspective view schematically showing how the bonding part 440 flows into the cavity side in the first comparison substrate 420. As shown in FIG. The heated and softened bonding portion 440 leaks to the outside through the gaps 310 b and 310 a shown in FIG. 24.
  • the prototype of the present invention shown in FIG. 23 is a trial result using a test pattern in which several tens of approximately 10 mm square cavities 190 are formed in an outer dimension of approximately 300 ⁇ 300 mm.
  • a 4-layer ALIVH substrate (ALIVH is a registered trademark of Panasonic Corporation) was used. This is because the ALIVH substrate is more resistant to pressure and heating than a multilayer substrate using a glass epoxy resin using general through-hole plating.
  • the bonding portion 140 a sheet-like bonding layer (kneaded product of an inorganic filler and an epoxy resin) in which the thermal expansion coefficient is matched to the ALIVH substrate was used.
  • the conductive paste 150 a conductive paste for an ALIVH substrate, which is obtained by kneading copper powder (3 to 10 microns) in an epoxy resin as the metal powder 350, was used.
  • the pressure applied to the first substrate 120, the second substrate 130, and the bonding portion 140 can be increased stepwise from room temperature (20.degree. C.) to about 200.degree. C. while maintaining the pressure, using a vacuum press. And adjusted the heating condition profile.
  • a negative resist was used as the first resist 220a and the second resist 220b.
  • the Tg of this negative resist was selected to be 200 ° C. or less (desirably 150 ° C. or less). Then, after the conductive paste 150 is started to be pressurized at around room temperature (20 ° C.) and brought into the state of FIG. 8B, these members are heated and the first resist 220a and the second resist 220b do not break even when they contact each other. It was softened to a certain degree, brought into close contact with each other, and softened the bonding portion 140.
  • the prototype of the present application shown in FIG. 23 corresponds to the second embodiment described with reference to FIG.
  • the first comparison substrate corresponds to the first comparison substrate 420 shown in FIGS. 24 to 26 described above.
  • the first substrate 120, the second substrate 130, the bonding portion 140, the conductive paste 150, and the like are common.
  • the presence or absence of a void is the result of having observed the cross section of a part of each sample produced experimentally.
  • the protrusion of the bonding part is an example of the observation result of whether or not a part of the bonding part 140 inserted between the first substrate 120 and the second substrate 130 leaks into the cavity 190 with a stereomicroscope, It is shown in FIG.
  • the first substrate having the first opening 290 a is bonded to the second substrate.
  • the cavity is formed after bonding.
  • an adhesive portion 140 having a conductive paste 150 is set between the first substrate 120 and the second substrate 130.
  • the method of manufacturing the bonding portion 140 having the conductive paste 150 is the same as the method of manufacturing the three-dimensional wiring substrate described with reference to FIGS. 4A to 4D, and thus the description thereof is omitted here.
  • these members are pressurized and integrated.
  • a part of any one or more of the first substrate 120 or the second substrate 130 is removed. Mechanical (router etc.), laser etc. can be used for removal.
  • a copper foil for example, a part of surface wiring
  • a stopper for the laser so that no laser processing mark is left on the surface (or the bottom) of the cavity 190. Thereafter, as shown by an arrow 340c in FIG. 27C, the unnecessary portion is removed to form a cavity 190.
  • a portion of the first resist 220a and a portion of the second resist 220b are integrated so that they face each other at the peripheral portion of the cavity.
  • the coplanarity of the mounting surface of the cavity 190 (Coplanarity means the uniformity of the lower surface of each terminal or electrode of the component with respect to the mounting surface). In this case, the terminal bottom surface uniformity can be improved.
  • the resist 220 cover the circumference of the cavity 190. However, even if the resist does not completely go around the cavity 190 completely by providing an opening or the like, it is not necessary to completely go around the circumference if the outflow from the bonding part 140 can be prevented.
  • the resists formed of the wiring substrates described in the first to fourth embodiments can generally be disposed in the remaining area of the peripheral edge portion of the cavity, and therefore, the same may be applied without increasing the area of the wiring substrate. It has a function and can prevent the flow out of the bonding part.
  • the first comparative substrate 420 shown in FIG. 25 since the first comparative resist 430 is formed in the cavity, it affects the area in the cavity. That is, in the case where the first comparative resist is formed in the cavity, for example, when the semiconductor element is disposed in the cavity, it is necessary to make the surface contact of the cavity larger than in the first to fourth embodiments of the present application.
  • first surface layer wiring 170 and the second surface layer wiring 180 are formed on the first surface layer wiring 170 and the second surface layer wiring 180 by the conductive paste 150 filled in the bonding portion. It is possible to increase the design freedom of the wiring patterns of the inner layer etc. and vias (both not shown in FIG. 1). This is because the via formed of the conductive paste 150 can be IVH. Depending on the application, it is possible to form a through hole through the three-dimensional wiring substrate 110 with a drill or the like, and to form a through hole while applying a plating technique to this through hole.
  • the second surface wiring 180 is drawn into the cavity 190, but the second surface wiring 180 is not necessarily drawn into the cavity 190.
  • the pattern of the resist 220 provided on the peripheral portion 200 is a quadrangle in the present embodiment, but is not necessarily limited thereto.
  • the pattern of the resist 220 is preferably square.
  • the pattern width of the resist 220 may be arbitrarily designed to be 50 microns or more (or 100 microns or more) or 2000 microns or less.
  • the overlapping width between the peripheral portion 200 of the first substrate 120 and the resist 220 is preferably 50 microns or more. If the pattern width of the resist 220 (in particular, the pattern width of the narrowest portion) is less than 50 microns, the width of the overlapping portion between the peripheral portion 200 of the first substrate 120 and the resist 220 may be insufficient. If it exceeds 2000 microns, there is no problem if the pattern width of the resist 220 is changed (the pattern width is locally expanded or locally narrowed). For such pattern design, a solder resist design method may be applied.
  • the resist 220 is formed on the peripheral portion 200 of the first substrate 120, the area of the substrate is generally obtained by spreading the first resist where the surface layer wiring does not exist on the peripheral portion 200. It is possible to easily secure a region for arranging the resist 220 without the need to expand the
  • the thickness of the second surface layer wiring 180 depends on the thickness (eg, 9 to 36 microns) of the copper foil used for the second surface layer wiring 180. It is desirable to make the thickness of the resist 220 thicker than the thickness of the second surface layer wiring 180. Also, by setting the thickness of the resist 220 to 100 microns or less, the possibility of affecting the total thickness of the three-dimensional wiring substrate 110 is reduced.
  • the resist 220 is formed only in part of the cavity 190 (for example, a portion near the mounting area where the fan-out wiring is formed or the bottom of the cavity 190, for example, within 2 mm from the mounting area). You may make it oppose the peripheral part of 1 board
  • FIG. The position where the resist 220 is formed in this manner is on the entire circumference (or the entire peripheral edge) of the cavity 190 or on a part of the cavity 190 (at least 50% or more of the entire circumference of the cavity 190, or 60% or more. In the case of less than the above, the effect of preventing the flow of the bonding portion 140 into the cavity 190 may be affected.
  • a multilayer wiring substrate (a via may be a plated via or a paste via) using a commercially available glass epoxy resin.
  • a buildup layer (the buildup layer is a kind of multilayer substrate having a blind via or the like) may be formed on the surface layer of the first substrate 120 and the second substrate 130.
  • a wiring substrate having a buildup layer is referred to as a first substrate 120
  • a surface wiring of the buildup layer is referred to as a first surface wiring 170 of the first substrate 120
  • a wiring substrate having another buildup layer is referred to as a first wiring.
  • the surface wiring of this second buildup layer is used as the second surface wiring 180 of the second substrate 130, and IVH connection is performed with the conductive paste 150 filled in the holes formed in the conductive paste 150. It is also useful to set it to 110. By doing this, the second surface layer wiring 180 of the second substrate 130 exposed to the bottom surface of the cavity 190 of the three-dimensional wiring substrate 110 can be made more functional (fine patterning or the like). As described above, also in the case where the buildup layers of the wiring substrate are made to face each other and are laminated and integrated through the bonding portion 140 to form the three-dimensional wiring substrate 110, the flow into the cavity 190 of the bonding portion 140 This can be effectively stopped by the resist 220 provided in the opposite buildup layer.
  • the three-dimensional wiring board, the semiconductor mounting structure, and the method of manufacturing the same according to the present invention make it possible to further reduce the size, thickness, weight, high definition, and multifunctionality of personal computers, digital cameras, mobile phones and the like.

Abstract

Disclosed is a wiring board, wherein a first substrate, which has an opening and first surface layer wiring disposed on a surface layer, and a second substrate, which has second surface layer wiring disposed on a surface layer, are bonded to each other by having a bonding section therebetween, and the opening forms a cavity having the second substrate as the bottom surface. At least a part of a resist section is formed in a region, which has the first substrate and the second substrate facing each other, and surrounds the cavity. A possibility of having a part of the bonding section protrude to the cavity side through a gap between the first substrate and the second substrate is eliminated, and a three-dimensional wiring board necessary for the purpose of achieving size reduction, thickness reduction, weight reduction, high accuracy, multifunctional characteristics, and the like of mobile apparatuses is provided.

Description

配線基板および立体配線基板の製造方法Wiring board and method of manufacturing three-dimensional wiring board
 本発明は、パソコン、移動体通信用電話機、ビデオカメラ等の各種電子機器に広く用いられる配線基板とその製造方法に関する。 The present invention relates to a wiring board widely used in various electronic devices such as personal computers, mobile phones for mobile communication, video cameras and the like, and a method of manufacturing the same.
 最近、モバイル商品としてパソコン、デジタルカメラ、携帯電話などが普及し、特にその小型、薄型、軽量、高精細、多機能化等の要望が強く、それに対応するため半導体の実装形態も、パッケージの小型・低背化、三次元実装化が進んでいる。このような半導体パッケージの低背化、三次元実装化を容易に実現する方法の一つとして、キャビティを有する立体配線基板を用いる方法として、例えば、特許文献1が知られている。 Recently, personal computers, digital cameras, mobile phones, etc. have become widespread as mobile products, and in particular there is a strong demand for small size, thin type, light weight, high definition, multi-functionalization etc.・ Lower height, three-dimensional implementation is in progress. For example, Patent Document 1 is known as a method of using a three-dimensional wiring substrate having a cavity as one of methods for easily realizing such reduction in height and three-dimensional mounting of a semiconductor package.
 また、接続部に充填された導電ペーストが流れるのを防止する方法として、例えば特許文献2が知られている。 In addition, as a method for preventing the flow of the conductive paste filled in the connection portion, for example, Patent Document 2 is known.
特開2004-253774号公報JP 2004-253774 A 特開2009-28364号公報JP, 2009-28364, A
 特許文献1に開示された従来の立体配線基板は、接着部に一般的にプリプレグを用いることになるが、プリプレグでは織布、不織布、フィルムなどの芯材を含んでいるために、特に導電性ペーストからなるビアの形状保持には有効であるが、上側および下側のプリント配線板表面に形成された配線パターンの埋め込みが困難であった。 The conventional three-dimensional wiring substrate disclosed in Patent Document 1 generally uses a prepreg for the bonding portion, but since the prepreg contains a core material such as a woven fabric, a non-woven fabric, or a film, it is particularly conductive. Although it is effective for shape retention of vias made of paste, it is difficult to embed the wiring patterns formed on the upper and lower printed wiring board surfaces.
 また、接着部にボンディングシートを用いた場合、配線パターンの埋め込みは容易であるが、接着部に充填された導電ペーストが流れるという課題を有していた。 In addition, when a bonding sheet is used for the bonding portion, embedding of the wiring pattern is easy, but there is a problem that the conductive paste filled in the bonding portion flows.
 こうした課題に対して、2枚の配線基板(一方はキャビティ付き)同士を、接着部で貼り付け、立体配線基板とした後、ドリル等でこの立体配線基板に貫通孔を形成し、この貫通孔にメッキでビアホールを形成する技術も提案されていたが、この場合、ビアホールは、接着部と2枚の配線基板とを共に貫通するため(あるいはIVH構造でないため、なおIVHはInterstitial Via Holeの意味)、立体配線基板の配線パターンの設計自由度に影響を与え、高密度実装に対応できないという課題を有していた。 In order to solve these problems, two wiring boards (one with a cavity) are attached at the bonding portion to form a three-dimensional wiring board, and then through holes are formed in the three-dimensional wiring board with a drill or the like. In this case, a technique for forming a via hole by plating was also proposed, but in this case, the via hole penetrates both the bonding portion and the two wiring boards (or IVH does not have an IVH structure, so IVH means the meaning of Interstitial Via Hole). And the freedom of design of the wiring pattern of the three-dimensional wiring board, which has a problem that it can not cope with high density mounting.
 本発明は、上記課題を鑑みて成されたものであり、第1基板と第2基板を接着部で接続してなる配線基板であって、この接着部のキャビティ内への流れ出しを防止した配線基板とする。よって、キャビティ内への半導体等の高密度実装や配線密度を高めるものである。 The present invention has been made in view of the above problems, and is a wiring board in which a first substrate and a second substrate are connected by an adhesive portion, and a wire which prevents the adhesive portion from flowing out into the cavity. It will be a substrate. Therefore, high density mounting of semiconductors and the like in the cavity and wiring density are enhanced.
 上記目的を達成するために、本発明の一局面である配線基板は、開口部と表層に配置された第1表層配線とを有する第1基板と、表層に配置された第2表層配線を有する第2基板とを有する配線基板である。そして、第1基板と第2基板の間に接着部が配置され、第1基板と第2基板とを互いに接着している。さらに、第1基板と第2基板の間にレジスト部が配置され、レジスト部は、第1基板と第2基板とに接する。さらに、開口部は第2基板を底面とするキャビティを形成し、接着部は、接着部に形成された孔に充填された導電ペーストからなるビアを有する。そして、ビアは、第1表層配線と第2表層配線とを電気的に接続し、レジスト部の少なくとも一部は、第1基板と第2基板が対向し、かつ、キャビティを囲む領域に形成されていることを特徴とする。 In order to achieve the above object, a wiring substrate which is one aspect of the present invention has a first substrate having an opening and a first surface wiring disposed in the surface, and a second surface wiring disposed in the surface. It is a wiring board which has a 2nd substrate. And an adhesion part is arranged between the 1st substrate and the 2nd substrate, and the 1st substrate and the 2nd substrate are pasted up mutually. Furthermore, a resist portion is disposed between the first substrate and the second substrate, and the resist portion is in contact with the first substrate and the second substrate. Furthermore, the opening forms a cavity whose bottom surface is the second substrate, and the bonding part has a via made of a conductive paste filled in a hole formed in the bonding part. The via electrically connects the first surface layer wiring and the second surface layer wiring, and at least a portion of the resist portion is formed in a region where the first substrate and the second substrate face each other and which surrounds the cavity. It is characterized by
 よって、接着部のキャビティ内への流れ出しを防止しすることができるので、立体配線基板の更なる小型、薄型、軽量、高精細、多機能化等を実現する。 Therefore, the outflow of the bonding portion into the cavity can be prevented, so that further miniaturization, thinness, light weight, high definition, multifunctionalization and the like of the three-dimensional wiring substrate can be realized.
 また本発明の他の局面である、立体配線基板の製造方法は、上記配線基板を製造することができる。 Moreover, the manufacturing method of the three-dimensional wiring board which is the other aspect of this invention can manufacture the said wiring board.
図1は、本発明の実施の形態1における立体配線基板の一部を拡大した断面図である。FIG. 1 is an enlarged cross-sectional view of a part of the three-dimensional wiring substrate in the first embodiment of the present invention. 図2は、本発明の実施の形態1における立体配線基板が形成される状況を模式的に示す斜視図である。FIG. 2 is a perspective view schematically showing the situation in which the three-dimensional wiring substrate in the first embodiment of the present invention is formed. 図3は、本発明の実施の形態1における立体配線基板の全体を模式的に示す斜視図である。FIG. 3 is a perspective view schematically showing the entire three-dimensional wiring board in the first embodiment of the present invention. 図4Aは、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 4A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention. 図4Bは、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 4B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention. 図4Cは、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 4C is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention. 図4Dは、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 4D is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention. 図5Aは、本発明の実施の形態1における体配線基板の製造方法の一例を示す断面図である。FIG. 5A is a cross-sectional view showing an example of a method of manufacturing a body wiring board in the first embodiment of the present invention. 図5Bは、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 5B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 1 of the present invention. 図6は、本発明の実施の形態1における立体配線基板の製造方法の一例を示す断面図である。FIG. 6 is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the first embodiment of the present invention. 図7は、本発明の実施の形態2における立体配線基板の一部を拡大した断面図である。FIG. 7 is an enlarged sectional view of a part of the three-dimensional wiring substrate in the second embodiment of the present invention. 図8Aは、本発明の実施の形態2における立体配線基板の製造方法の一例を示す断面図である。FIG. 8A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 2 of the present invention. 図8Bは、本発明の実施の形態2における立体配線基板の製造方法の一例を示す断面図である。FIG. 8B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate according to Embodiment 2 of the present invention. 図9Aは、発明の実施の形態2における立体配線基板の製造方法の一例を示す断面図である。FIG. 9A is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the second embodiment of the present invention. 図9Bは、発明の実施の形態2における立体配線基板の製造方法の一例を示す断面図である。FIG. 9B is a cross-sectional view showing an example of a method of manufacturing a three-dimensional wiring substrate in the second embodiment of the present invention. 図10は、図2の矢印10における断面の一部を模式的に示す斜視図である。FIG. 10 is a perspective view schematically showing a part of a cross section taken along arrow 10 in FIG. 図11Aは、図3の矢印11における断面の一部を模式的に示す斜視図である。11A is a perspective view schematically showing a part of a cross section taken along arrow 11 in FIG. 図11Bは、図3の矢印11における断面の一部を模式的に示す斜視図である。11B is a perspective view schematically showing a part of a cross section taken along arrow 11 in FIG. 図12Aは、接着層のキャビティ側への流出を防止した様子を模式的に示す斜視図である。FIG. 12A is a perspective view schematically showing a state in which the adhesive layer is prevented from flowing out to the cavity side. 図12Bは、接着層のキャビティ側への流出を防止した様子を模式的に示す斜視図である。FIG. 12B is a perspective view schematically showing a state in which the adhesive layer is prevented from flowing out to the cavity side. 図13Aは、レジストが、互いに密着もしくは固着する様子を示す断面図である。FIG. 13A is a cross-sectional view showing how the resists adhere or adhere to each other. 図13Bは、レジストが、互いに密着もしくは固着する様子を示す断面図である。FIG. 13B is a cross-sectional view showing how the resists adhere or adhere to each other. 図13Cは、レジストが、互いに密着もしくは固着する様子を示す断面図である。FIG. 13C is a cross-sectional view showing how the resists adhere or adhere to each other. 図14(a)は、固着面の様子を示す断面図で、図14(b)は、固着面の界面部分の上面図である。FIG. 14 (a) is a cross-sectional view showing the state of the fixed surface, and FIG. 14 (b) is a top view of the interface portion of the fixed surface. 図15は、実際に作成したサンプルにおける剥離面の顕微鏡写真を示す図である。FIG. 15 is a view showing a photomicrograph of the peeled surface of the sample actually prepared. 図16は、図15の顕微鏡写真を模式的に示す平面図である。FIG. 16 is a plan view schematically showing the microphotograph of FIG. 図17は、本発明の実施の形態2の変形例における立体配線基板の一部を拡大した断面図である。FIG. 17 is an enlarged sectional view of a part of a three-dimensional wiring board according to a modification of the second embodiment of the present invention. 図18は、本発明の実施の形態3における立体配線基板の一部を拡大した断面図である。FIG. 18 is an enlarged sectional view of a part of the three-dimensional wiring substrate according to the third embodiment of the present invention. 図19は、本発明の実施の形態3における立体配線基板の断面の一部を模式的に示す斜視図である。FIG. 19 is a perspective view schematically showing a part of a cross section of a three-dimensional wiring substrate in the third embodiment of the present invention. 図20は、本発明の実施の形態3における立体配線基板の断面の一部を模式的に示す斜視図である。FIG. 20 is a perspective view schematically showing a part of a cross section of a three-dimensional wiring substrate in the third embodiment of the present invention. 図21は、本発明の実施の形態4における、半導体実装構造物の一部を拡大して示す断面図である。FIG. 21 is a cross-sectional view showing a part of the semiconductor mounted structure in an enlarged manner, in the fourth embodiment of the present invention. 図22Aは、金属粉同士が変形する様子を模式的に説明する断面図である。FIG. 22A is a cross-sectional view schematically illustrating how metal powder is deformed. 図22Bは、金属粉同士が変形する様子を模式的に説明する断面図である。FIG. 22B is a cross-sectional view schematically illustrating how the metal powder is deformed. 図23は、試作結果の一例を示す図である。FIG. 23 is a diagram showing an example of a trial production result. 図24は、第1比較基板について説明する斜視図である。FIG. 24 is a perspective view for explaining the first comparison substrate. 図25は、第1比較基板について説明する斜視図である。FIG. 25 is a perspective view for explaining the first comparison substrate. 図26は、第1比較基板について説明する斜視図である。FIG. 26 is a perspective view for explaining the first comparison substrate. 図27Aは、立体配線基板の第2の製造方法を示す断面図である。FIG. 27A is a cross-sectional view showing a second method of manufacturing a three-dimensional wiring substrate. 図27Bは、立体配線基板の第2の製造方法を示す断面図である。FIG. 27B is a cross-sectional view showing a second method of manufacturing the three-dimensional wiring substrate. 図27Cは、立体配線基板の第2の製造方法を示す断面図である。FIG. 27C is a cross-sectional view showing a second method of manufacturing the three-dimensional wiring substrate.
 (実施の形態1)
 <実施の形態1の構造>
 以下、本発明の実施の形態1について、図面を参照しながら説明する。
Embodiment 1
<Structure of Embodiment 1>
Hereinafter, Embodiment 1 of the present invention will be described with reference to the drawings.
 図1は、本発明の実施の形態1における、立体配線基板の一部を拡大した断面図である。図1において、立体配線基板110は、第1基板120と、第2基板130を接着部140で貼り合わせて形成されている。第1基板120は、絶縁層160と、絶縁層160の表面に形成されている第1表層配線170で形成されている。さらに、第2基板130は、絶縁層160と、絶縁層160の表面に形成されている第2表層配線180で形成されている。接着部140には孔(孔に番号は付与していない。なお後述する図4(B)では孔270として図示している)が形成され、その孔に導電ペースト150が充填されている。また、導電ペースト150はビアとして機能し、第1表層配線170と第2表層配線180を電気的に接続している。第1基板120には開口部があり、その開口部がキャビティ190となる。なお、キャビティの構成については、図2、図3を参照しながら後述する。レジスト220は、第1基板120と第2基板130が対向し、かつ、キャビティ190を囲む領域(周縁部200)に配置されており、上面は第1基板に接し、下面は第2基板に接している。なお、本実施形態では金属粉を含む導電ペースト150が用いられている。 FIG. 1 is an enlarged cross-sectional view of a part of the three-dimensional wiring substrate in the first embodiment of the present invention. In FIG. 1, the three-dimensional wiring substrate 110 is formed by bonding the first substrate 120 and the second substrate 130 at the bonding portion 140. The first substrate 120 is formed of an insulating layer 160 and a first surface layer wiring 170 formed on the surface of the insulating layer 160. Furthermore, the second substrate 130 is formed of an insulating layer 160 and a second surface layer wiring 180 formed on the surface of the insulating layer 160. Holes (numbers are not assigned to the holes, and are illustrated as holes 270 in FIG. 4B described later) are formed in the bonding portion 140, and the holes are filled with the conductive paste 150. The conductive paste 150 also functions as a via, and electrically connects the first surface wiring 170 and the second surface wiring 180. The first substrate 120 has an opening, and the opening becomes a cavity 190. The configuration of the cavity will be described later with reference to FIGS. 2 and 3. The resist 220 is disposed in a region (peripheral portion 200) in which the first substrate 120 and the second substrate 130 face each other and surrounds the cavity 190, the upper surface is in contact with the first substrate, and the lower surface is in contact with the second substrate. ing. In the present embodiment, a conductive paste 150 containing metal powder is used.
 次に、本発明の実施の形態1における、第1基板120および第2基板130の全体の構成について、図2および図3を参照しながら説明する。図2は、本発明の実施の形態1における立体配線基板が形成される状況を模式的に示す斜視図である。図3は、本発明の実施の形態1における立体配線基板の全体を模式的に示す斜視図である。 Next, the entire configuration of the first substrate 120 and the second substrate 130 in the first embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a perspective view schematically showing the situation in which the three-dimensional wiring substrate in the first embodiment of the present invention is formed. FIG. 3 is a perspective view schematically showing the entire three-dimensional wiring board in the first embodiment of the present invention.
 図2に示す通り、第1基板120には、開口部290が形成されている。そして、第1基板120と第2基板130を、接着部(図2、図3には図示せず)を介し、矢印280に示すように一体化させる。その結果、図3に示すように、キャビティ190を有する立体的は配線基板(以下、立体配線基板と呼ぶ)が形成される。なお、本実施の形態のようなキャビティを有する配線基板を、立体配線基板と称しているが、配線基板と呼んでも何ら問題はない。 As shown in FIG. 2, an opening 290 is formed in the first substrate 120. Then, the first substrate 120 and the second substrate 130 are integrated as indicated by an arrow 280 via an adhesive portion (not shown in FIGS. 2 and 3). As a result, as shown in FIG. 3, a three-dimensional wiring board (hereinafter referred to as a three-dimensional wiring board) having a cavity 190 is formed. Although the wiring board having a cavity as in this embodiment is referred to as a three-dimensional wiring board, it may be called a wiring board without any problem.
 なお、図2および図3では、図1に示した接着部140、導電ペースト150、絶縁層160、第1表層配線170、第2表層配線180などの記載は省略している。 In FIG. 2 and FIG. 3, the description of the bonding portion 140, the conductive paste 150, the insulating layer 160, the first surface wiring 170, the second surface wiring 180, etc. shown in FIG. 1 is omitted.
 <実施の形態1の具体的な材料およびサイズの例>
 図1を参照しながら説明した実施の形態1の配線構造において、具体的な材料およびサイズの例を以下、説明する。
<Example of Specific Material and Size of Embodiment 1>
In the wiring structure of the first embodiment described with reference to FIG. 1, specific examples of materials and sizes will be described below.
 第1基板120、第2基板130としては、市販のガラスエポキシ樹脂(ガラス繊維にエポキシ樹脂を含浸させてなる絶縁層を用いたもの)を絶縁層160とした配線基板(いわゆる完成済みの配線基板)を用いることができる。なお第1基板120、第2基板130の、接着部140を介して対向する面には第1表層配線170、第2表層配線180が形成されている。なお第1表層配線170、第2表層配線180としては、市販の銅箔(例えば、厚み18~36μm等)をエッチングしたものを使うことができる。また第1基板120、第2基板130として、ALIVH基板(ALIVHは、Panasonic株式会社の登録商標)を用いることは有用である。ALIVH基板は、Any Layer Interstitial Via Holeを有するため、立体配線基板110の配線設計の自由度を高める。またALIVH基板の層間接続にはビアペースト(図1等には図示していない)が用いられているため、通常のメッキビアを用いた配線基板に対して、圧縮時でのビア部分の信頼性が高い。そのため第1表層配線170、第2表層配線180と、導電ペースト150との密着を高めるために、加圧、加熱した場合での、第1基板120、第2基板130が加圧、加熱の影響を受けにくい。 A wiring substrate (so-called completed wiring substrate) using an insulating layer 160 as the first substrate 120 and the second substrate 130, using a commercially available glass epoxy resin (using an insulating layer formed by impregnating glass fiber with the epoxy resin) Can be used. A first surface layer wiring 170 and a second surface layer wiring 180 are formed on the surfaces of the first substrate 120 and the second substrate 130 that face each other through the bonding portion 140. As the first surface layer wiring 170 and the second surface layer wiring 180, those obtained by etching a commercially available copper foil (for example, having a thickness of 18 to 36 μm or the like) can be used. It is also useful to use an ALIVH substrate (ALIVH is a registered trademark of Panasonic Corporation) as the first substrate 120 and the second substrate 130. Since the ALIVH substrate has the Any Layer Interstitial Via Hole, the degree of freedom in wiring design of the three-dimensional wiring substrate 110 is enhanced. In addition, since via paste (not shown in FIG. 1 and the like) is used for interlayer connection of the ALIVH substrate, the reliability of the via portion at the time of compression is improved with respect to a wiring substrate using ordinary plated vias. high. Therefore, in order to increase the adhesion between the first surface layer wiring 170 and the second surface layer wiring 180 and the conductive paste 150, the effects of the pressure and the heating of the first substrate 120 and the second substrate 130 in the case of pressing and heating. It is hard to receive.
 また、レジスト220としては、市販のソルダーレジストを用いることができる。 Moreover, as the resist 220, a commercially available solder resist can be used.
 <実施の形態1の配線基板の製造方法の一例>
 次に、図1を参照しながら説明した実施の形態1の立体配線基板110の製造方法の一例について、図面を参照しながら説明する。
<One Example of Method of Manufacturing Wiring Board of First Embodiment>
Next, an example of a method of manufacturing the three-dimensional wiring substrate 110 of the first embodiment described with reference to FIG. 1 will be described with reference to the drawings.
 図4A~図4D、図5A、図5B、図6は、立体配線基板110の製造方法の一例を示す断面図である。 4A to 4D, 5A, 5B, and 6 are cross-sectional views showing an example of a method of manufacturing the three-dimensional wiring substrate 110.
 なお、図1を参照しながら説明した立体配線基板110と同一の構成には同一の符号を付して説明を省略する。 The same components as those of the three-dimensional wiring substrate 110 described with reference to FIG. 1 will be assigned the same reference numerals and descriptions thereof will be omitted.
 図4Aに示す通り、接着部140の両面には保護フィルム260が形成される。保護フィルム260としては、例えば、PETフィルム等の厚み5~50ミクロンの樹脂フィルムを用いることができる。 As shown to FIG. 4A, the protective film 260 is formed in the both surfaces of the adhesion part 140. As shown in FIG. As the protective film 260, for example, a resin film with a thickness of 5 to 50 microns, such as a PET film, can be used.
 接着部140としては、例えば、熱硬化樹脂と、熱膨張係数の調整用の無機フィラーとを含む、厚み5~200ミクロンの接着部を用いることができる。 As the bonding part 140, for example, a bonding part having a thickness of 5 to 200 microns, which contains a thermosetting resin and an inorganic filler for adjusting the thermal expansion coefficient, can be used.
 次に、図4Bに示す通り、保護フィルム260と接着部140に孔270が開けられる。孔270の形成には、ドリルやレーザーを用いることができる。 Next, as shown in FIG. 4B, holes 270 are opened in the protective film 260 and the bonding part 140. A drill or a laser can be used to form the holes 270.
 その後、図4Cに示す通り、孔270に導電ペースト150が充填される。導電ペースト150の充填には、例えば、市販のスクリーン印刷機等を用いることができる。 Thereafter, as shown in FIG. 4C, the holes 270 are filled with the conductive paste 150. For the filling of the conductive paste 150, for example, a commercially available screen printer can be used.
 その後、図4Dに示す通り、接着部140および保護フィルム260に、開口部290bが形成される。開口部290bの形成方法としては、金型やレーザーを使用した打ち抜き、あるいは切り抜き方法を選ぶことができる。そして接着部140の一部を矢印280に示すように除去し、開口部290を、接着部140にも設ける。その後、保護フィルム260が除去される(図4では保護フィルム260を除去するステップは図示せず)。 Thereafter, as shown in FIG. 4D, an opening 290 b is formed in the bonding portion 140 and the protective film 260. As a method of forming the opening 290b, a punching method or a cutting method using a mold or a laser can be selected. Then, a part of the bonding part 140 is removed as shown by the arrow 280, and the opening 290 is also provided in the bonding part 140. Thereafter, the protective film 260 is removed (step of removing the protective film 260 is not shown in FIG. 4).
 なお、開口部290等の形成方法について、図4A~図4Dを参照しながら説明したが、開口部290の形成方法はこれに限定されるものではなく、各ステップの順番についても、これに限定されるものではない。 Although the method for forming the opening 290 and the like has been described with reference to FIGS. 4A to 4D, the method for forming the opening 290 is not limited to this, and the order of the steps is also limited to this. It is not something to be done.
 次に、第1基板120と第2基板130とを貼り付ける方法について説明する。 Next, a method of attaching the first substrate 120 and the second substrate 130 will be described.
 図5Aに示す通り、図4Dに示した構造物から、保護フィルム260を除去したものが、図5Aに示す接着部140および導電ペースト150である。保護フィルムを除去した跡が、接着部140の表面から導電ペースト150が突出した部分(突出部300)となる。突出部300の厚みは、保護フィルム260の厚みで調整することができる。 As shown in FIG. 5A, the adhesive film 140 and the conductive paste 150 shown in FIG. 5A are obtained by removing the protective film 260 from the structure shown in FIG. 4D. The trace from which the protective film has been removed is a portion (protruding portion 300) where the conductive paste 150 protrudes from the surface of the bonding portion 140. The thickness of the protrusion 300 can be adjusted by the thickness of the protective film 260.
 第1基板120は、開口部290aを有しており、表層に第1表層配線170を有する。また、第2基板130は、表層の第2表層配線180を有する。そして、第2表層配線180の上にレジスト220が形成されている。レジスト220は、第1基板120と第2基板130とが対向し、かつ、第1基板120の開口部の周辺部(周縁部200)に形成されている。レジスト220は、接着部140よりキャビティにより近い位置に形成される。 The first substrate 120 has an opening 290 a and has a first surface wiring 170 on the surface. In addition, the second substrate 130 has the surface layer second surface wiring 180. Then, a resist 220 is formed on the second surface wiring 180. The resist 220 is formed on the periphery (peripheral portion 200) of the opening of the first substrate 120 with the first substrate 120 and the second substrate 130 facing each other. The resist 220 is formed at a position closer to the cavity than the bonding portion 140.
 なお、図1などでは、レジスト220は第2表層配線180の上に形成されているが、レジスト220の下に表層配線が必ず形成されている必要はなく、絶縁層160の上に形成されていてもよい。 Although the resist 220 is formed on the second surface layer wiring 180 in FIG. 1 and the like, the surface layer wiring does not necessarily have to be formed under the resist 220, and is formed on the insulating layer 160. May be
 そして第1基板120と第2基板130の間に、図4Dに示す接着部140および突出部300を有する導電ペースト150をセットする。 Then, a conductive paste 150 having a bonding portion 140 and a projecting portion 300 shown in FIG. 4D is set between the first substrate 120 and the second substrate 130.
 なお、第1基板120に設けた開口部290aより、接着部140に設けた開口部290bの方を大きくする。そして、接着部140に形成した開口部290bは、レジスト220より外側(あるいはこれらが積層されてなるキャビティ190より遠い側)に設けている。こうすることで、接着部140とレジスト220との重なりを低減できる。 The opening 290 b provided in the bonding unit 140 is made larger than the opening 290 a provided in the first substrate 120. The opening 290 b formed in the bonding part 140 is provided outside the resist 220 (or on the side farther from the cavity 190 formed by stacking these). By this, the overlap between the bonding portion 140 and the resist 220 can be reduced.
 そして、図5Aをプレスし、第1基板120、第2基板130を、途中に挟んだ接着部140で一体化する様子を図5Bに示し、プレスした結果を図6に示す。なお、プレス装置や金型は、共に図示していない。 Then, FIG. 5A is pressed, and a state in which the first substrate 120 and the second substrate 130 are integrated by the bonding part 140 sandwiched in the middle is shown in FIG. 5B, and the result of pressing is shown in FIG. The pressing device and the mold are not shown.
 図5Bにおいて、プレスする過程で隙間310が出来、通気矢印320は、例えば、第1基板120、第2基板130や接着部140の隙間に残った空気が、外部に抜ける(あるいは通気する)様子を示す。この通気矢印320で示すような通気性を積層時にキャビティ190の側面に設けることで、接着部140と第1基板120、第2基板130等との界面のボイド発生の抑制効果が得られる。 In FIG. 5B, a gap 310 is formed in the process of pressing, and the vented arrow 320 indicates, for example, a state in which air remaining in the gap between the first substrate 120, the second substrate 130, and the bonding portion 140 is released (or ventilated) to the outside. Indicates By providing the air permeability as shown by the air flow arrow 320 on the side surface of the cavity 190 at the time of stacking, the effect of suppressing the generation of a void at the interface between the bonding portion 140 and the first substrate 120, the second substrate 130 and the like can be obtained.
 最終的に、図6に示す通り、第1基板120と第2基板130が対向する領域(周縁部200)に、レジスト220と第1基板120とが密着してなる密着部(または、密着面)ができる。密着部(または密着面)は点線330で図6に示す。 Finally, as shown in FIG. 6, a contact portion (or a contact surface) in which the resist 220 and the first substrate 120 are in close contact with the region (peripheral portion 200) where the first substrate 120 and the second substrate 130 face each other. Can) The contact portion (or contact surface) is shown in FIG.
 点線330で示すように、第1基板120の表面状態(あるいは第1基板120の表面の凹凸やうねり等)に応じて、レジスト220の表面の一部同士が密着してなる密着部を形成することで、加圧、加熱して軟化した(更には第1表層配線170、第2表層配線180を埋設した)接着部140が、レジスト220の隙間からキャビティ190の内部に流れ込むことを確実に防止することができる。 As indicated by a dotted line 330, in accordance with the surface condition of the first substrate 120 (or unevenness or waviness of the surface of the first substrate 120, etc.), an adhesion portion in which parts of the surface of the resist 220 adhere to each other is formed. As a result, the adhesion portion 140 which has been pressurized, heated and softened (further, the first surface wiring 170 and the second surface wiring 180 are embedded) is reliably prevented from flowing into the interior of the cavity 190 from the gap of the resist 220. can do.
 図6におけるキャビティ190は、側面は、第1基板120の開口部、レジスト220、底面は、第2基板130で形成されている。 In the cavity 190 in FIG. 6, the side surface is formed by the opening of the first substrate 120, the resist 220, and the bottom surface is formed by the second substrate 130.
 以上、図1~図6を参照しながら説明した実施の形態1の配線基板によれば、キャビティ周辺部において、第1基板120および第2基板130との間をレジスト220によって接続している。よって、接着部140からのキャビティ190への流れ出しをより確実に防止することができる。 As described above, according to the wiring substrate of the first embodiment described with reference to FIGS. 1 to 6, the first substrate 120 and the second substrate 130 are connected by the resist 220 at the periphery of the cavity. Thus, the flow out of the bonding portion 140 into the cavity 190 can be more reliably prevented.
 なお、接着部140などの形状によっては、キャビティ190の周辺領域を全て囲むようにレジスト220を必ずしも形成しなくても、接着部140のキャビティ190内への流れ込み防止の効果を得ることはできる。 Depending on the shape of the bonding portion 140 or the like, the effect of preventing the bonding portion 140 from flowing into the cavity 190 can be obtained without necessarily forming the resist 220 so as to surround the entire peripheral region of the cavity 190.
 また、本実施の形態では、第2基板130の表層に設けた第2表層配線180は、キャビティ190の中に引き出すことにより、キャビティ190の周縁部200においては、ファンアウト(Fanout)形の引き回しパターンの形成が非常に容易となる。つまり、キャビティ190中に、第2基板130の表層に設けた第2表層配線180を直接、最短距離で引き出すことができ、この第2表層配線180に、半導体チップ等を、直接、実装することができる。この結果、配線の線路長を、ビアホール等を介することなく同一平面上で最短に保つことができ、立体配線基板110のESR(等価直列抵抗)やESL(等価直列インダクタンス)を小さくできる。 Further, in the present embodiment, the second surface layer wiring 180 provided on the surface layer of the second substrate 130 is drawn out into the cavity 190, whereby a fanout-type routing is made at the peripheral portion 200 of the cavity 190. The formation of the pattern is very easy. That is, the second surface layer wiring 180 provided on the surface layer of the second substrate 130 can be drawn directly into the cavity 190 at the shortest distance, and a semiconductor chip or the like is directly mounted on the second surface layer wiring 180. Can. As a result, the line length of the wiring can be kept shortest on the same plane without via holes and the like, and the ESR (equivalent series resistance) and ESL (equivalent series inductance) of the three-dimensional wiring board 110 can be reduced.
 また、本実施の形態では、第1表層配線170と第2表層配線180との間の電気的接続を充填した導電ペースト150によって行っているので、第1表層配線170、第2表層配線180に形成する内層等の配線パターンやビア(共に図1においては図示していない)の設計自由度を高めることができる。設計自由度が高まる理由は、導電ペースト150からなるビアを、IVHとすることができるためである。 Further, in the present embodiment, since the conductive paste 150 filling the electrical connection between the first surface layer wiring 170 and the second surface layer wiring 180 is used, the first surface layer wiring 170 and the second surface layer wiring 180 are used. It is possible to increase the design freedom of the wiring pattern of the inner layer to be formed and the like (both not shown in FIG. 1). The reason for the increased design freedom is that the via made of the conductive paste 150 can be made IVH.
 (実施の形態2)
 <実施の形態2の構造>
 以下本発明の実施の形態2について、図面を参照しながら説明する。
Second Embodiment
<Structure of Embodiment 2>
Second Embodiment A second embodiment of the present invention will be described below with reference to the drawings.
 図7は、本発明の実施の形態2における、立体配線基板の一部を拡大した断面図である。図1を参照しながら説明した実施の形態1と同様の構成については、同一の符号を付して説明を省略する。 FIG. 7 is an enlarged sectional view of a part of the three-dimensional wiring substrate in the second embodiment of the present invention. The same components as in the first embodiment described with reference to FIG. 1 will be assigned the same reference numerals and descriptions thereof will be omitted.
 実施の形態1と実施の形態2の構成で異なる点はレジスト部の構造で、図1に示す実施の形態1ではレジスト220であったのに対し、図7に示す実施の形態2では、レジスト部が第1レジスト220aおよび220bで形成されている点だけである。斜視図については、図2および図3を参照しながら説明した実施の形態1と同様であるので、説明を省略する。 The configuration of the first embodiment differs from the configuration of the second embodiment in the structure of the resist portion, which is the resist 220 in the first embodiment shown in FIG. 1, while in the second embodiment shown in FIG. The point is that the portion is formed of the first resists 220a and 220b. About a perspective view, since it is the same as that of Embodiment 1 demonstrated with reference to FIG. 2 and FIG. 3, description is abbreviate | omitted.
 また、具体的な材料およびサイズの例についても、実施の形態1と同様であるので説明を省略する。 In addition, the specific material and the example of the size are also the same as in the first embodiment, so the description will be omitted.
 <実施の形態2の配線基板の製造方法の一例>
 次に、図7を参照しながら説明した実施の形態2の立体配線基板110の製造方法の一例について、図面を参照しながら説明する。図3~図6を参照しながら説明した実施の形態1の配線基板の製造方法と同様の構成については、同一の符号を付して説明を省略する。
<One Example of Method of Manufacturing Wiring Substrate of Second Embodiment>
Next, an example of a method of manufacturing the three-dimensional wiring substrate 110 of the second embodiment described with reference to FIG. 7 will be described with reference to the drawings. The same members of the present embodiment as those of the wiring board manufacturing method according to the first embodiment described with reference to FIGS.
 なお、図4A~図4Dを参照しながら説明した実施の形態1における接着部140および導電ペースト150の製造方法は、実施の形態1と同様であるので図面を省略する。 The manufacturing method of the bonding portion 140 and the conductive paste 150 in the first embodiment described with reference to FIGS. 4A to 4D is the same as that of the first embodiment, and thus the drawings are omitted.
 図8A、図8B、図9Aは、実施の形態2における立体配線基板110の製造方法の一例を示す断面図である。 8A, 8B, and 9A are cross-sectional views showing an example of a method of manufacturing the three-dimensional wiring substrate 110 according to the second embodiment.
 実施の形態1と異なる点は、第1基板120を形成する絶縁層160に第1レジスト220aが形成されており、第2基板130を形成する絶縁層160に第2レジスト220bが形成されている点だけである。 The difference from the first embodiment is that the first resist 220 a is formed on the insulating layer 160 forming the first substrate 120, and the second resist 220 b is formed on the insulating layer 160 forming the second substrate 130. It is only a point.
 次に、図9Bを参照しながら、第1レジスト220aおよび第2レジスト220bの密着部について説明する。 Next, the contact portion of the first resist 220a and the second resist 220b will be described with reference to FIG. 9B.
 第1レジスト220aおよび第2レジスト220bが互いに加熱、加圧されて密着することで、互いの表面形状を合わせてなる(あるいは嵌合してなる面)であり、互いが密着した痕跡がその形状に互いに対応するように残っている。これは加圧、加熱時に、第1レジスト220a、第2レジスト220bが、共に軟化するためである。なお痕跡部340は互いに接触していても、互いに離れていても、共に接着部140のキャビティ190中への流れ防止効果には影響はない。流れ防止効果に影響がない理由は、痕跡部340を構成する第1レジスト220a、第2レジスト220bが互いに離れていても、その距離は略一定で(更にはキャビティ190の全周において)、充分に狭いためである。 The first resist 220a and the second resist 220b are mutually heated and pressed to be in close contact with each other, so that the surface shapes of the first and second resists 220a and 220b are matched (or a surface formed by fitting) with each other. It remains to correspond to each other. This is because the first resist 220a and the second resist 220b are softened together when pressurized and heated. Even if the trace parts 340 are in contact with each other or apart from each other, there is no influence on the flow preventing effect of the adhesive part 140 into the cavity 190. The reason why the flow prevention effect is not affected is that, even if the first resist 220a and the second resist 220b constituting the trace portion 340 are separated from each other, the distance is substantially constant (further, all around the cavity 190). Because it is narrow.
 上記した実施の形態2については、実施の形態1と同様の効果が得られる。 The same effects as in the first embodiment can be obtained in the second embodiment described above.
 以下、レジスト同士の接合面について、図2、図7および図10から図12を参照しながら更に詳細に説明する。 Hereinafter, the bonding surface between the resists will be described in more detail with reference to FIGS. 2, 7 and 10 to 12.
 図10は、図2の矢印10における断面の一部を示す模式図である。図10はキャビティ190の側面をキャビティ190の内側から観察した拡大斜視図に相当する。図10において、未変形レジスト370は、例えば、図7に示すキャビティ190の周縁部200に設けられた第1レジスト220aに相当する。凹凸レジスト380は、第2基板130の表層に設けられた第2表層配線180の一部を覆う、第2レジスト220bに相当する。 FIG. 10 is a schematic view showing a part of the cross section in arrow 10 of FIG. FIG. 10 corresponds to an enlarged perspective view in which the side surface of the cavity 190 is observed from the inside of the cavity 190. In FIG. 10, the undeformed resist 370 corresponds to, for example, a first resist 220a provided on the peripheral portion 200 of the cavity 190 shown in FIG. The concavo-convex resist 380 corresponds to a second resist 220 b that covers a part of the second surface layer wiring 180 provided on the surface layer of the second substrate 130.
 凹凸レジスト380の凹凸は、第2レジスト220bに埋め込まれた第2表層配線(例えば、ファンアウト配線)の厚みに起因する。第2表層配線の厚みは積層時の通気性確保に有効である。また凹凸は個々の第2表層配線の厚みにのみ依存する必要はない。表層配線の有無で発生する凹凸以外に、第2基板のうねり等に起因する凹凸であっても、積層時の通気性確保に有効である。 The unevenness of the uneven resist 380 is caused by the thickness of the second surface layer wiring (for example, fan-out wiring) embedded in the second resist 220 b. The thickness of the second surface layer wiring is effective for ensuring air permeability at the time of lamination. Further, the unevenness does not have to depend only on the thickness of each second surface layer wiring. In addition to the unevenness generated due to the presence or absence of the surface layer wiring, even if the unevenness is caused by the waviness or the like of the second substrate, it is effective for ensuring air permeability at the time of lamination.
 このようにキャビティ190の周縁部200において、第2表層配線180の上に第2レジスト220bを重ねることで、この第2表層配線180の厚みに応じた凹凸形状をその表面に設けることは有用である。矢印280は、第1レジスト220a、第2レジスト220bが互いに対向した状態で、加圧、加熱され、密着する様子を示す。 As described above, by overlapping the second resist 220b on the second surface layer wiring 180 at the peripheral portion 200 of the cavity 190, it is useful to provide the surface with a concavo-convex shape according to the thickness of the second surface layer wiring 180. is there. An arrow 280 indicates that the first resist 220a and the second resist 220b are pressed, heated, and brought into close contact with each other in a state of facing each other.
 図11Aは、第1基板120、第2基板130のキャビティ190の周縁部200に設けられた、互いに対向する第1レジスト220a、第2レジスト220bが接触した様子を模式的に示す斜視図である。図11Aにおける通気矢印320は、第2レジスト220bが埋設する第2表層配線180に起因する凹凸の隙間310から、内部の空気が外部に逃げる(通気する)様子を示す。図11Aに示すように、第2表層配線180を、キャビティ190の外側から、キャビティ190の内部へ伸びる配線パターン(いわゆる、ファンアウト配線、あるいはFANOUT配線)とすることは有用である。 FIG. 11A is a perspective view schematically showing a state in which the first resist 220 a and the second resist 220 b facing each other are provided on the peripheral portion 200 of the cavity 190 of the first substrate 120 and the second substrate 130. . A ventilation arrow 320 in FIG. 11A indicates a state in which internal air escapes (vents) to the outside through the gap 310 of the unevenness due to the second surface layer wiring 180 in which the second resist 220b is embedded. As shown in FIG. 11A, it is useful to form the second surface wiring 180 as a wiring pattern (so-called fan-out wiring or FANOUT wiring) extending from the outside of the cavity 190 into the inside of the cavity 190.
 図11Bは、第1基板120、第2基板130のキャビティ190の周縁部200に設けられた、互いに対向する第1レジスト220a、第2レジスト220bが互いに密着した様子を模式的に示す斜視図である。図11Bに示すように、第1レジスト220aと第2レジスト220bが互いに密着した場合においても、第2レジスト220bの表面の凹凸の隙間から、通気矢印320に示すように通気性を保持することが可能となる。その後、更にこれらを加圧、加熱することで互いに密着することができる。 FIG. 11B is a perspective view schematically showing a state in which the first resist 220 a and the second resist 220 b facing each other are provided on the peripheral portion 200 of the cavity 190 of the first substrate 120 and the second substrate 130. is there. Even when the first resist 220a and the second resist 220b are in close contact with each other as shown in FIG. 11B, air permeability can be maintained as shown by the air flow arrow 320 from the gap of the unevenness of the surface of the second resist 220b. It becomes possible. Thereafter, they can be brought into close contact with each other by pressurizing and heating them.
 図12A、図12Bは、共に第1レジスト220a、第2レジスト220bは互いに加熱され、軟化した状態で密着することによって、軟化した接着部140のキャビティ190側への流出を防止した様子を模式的に示す斜視図である。図12Aにおいて390a、390bは共に変形済レジストであり、互いに加熱状態の第1レジスト220a、第2レジスト220bが押し当てられ、互いに変形してなるものである。 FIGS. 12A and 12B schematically show that the first resist 220 a and the second resist 220 b are mutually heated and adhered in a softened state, thereby preventing the softened adhesive portion 140 from flowing out to the cavity 190 side. It is a perspective view shown to. In FIG. 12A, both 390a and 390b are deformed resists, and the first resist 220a and the second resist 220b in a heated state are pressed against each other, and they are mutually deformed.
 図12Aは、完成後(すなわち接着部140が熱硬化した後)にも、まだ第1レジスト220a、第2レジスト220bが、互いに変形済レジスト390a、390bとして密着状態を保った様子を示す。密着面は図12Aに点線330で示す。 FIG. 12A shows that the first resist 220a and the second resist 220b still maintain close contact with each other as the deformed resists 390a and 390b even after completion (that is, after the adhesive portion 140 is thermally cured). The adhesive surface is shown by dotted line 330 in FIG. 12A.
 図12Bは、完成後(すなわち接着部140が熱硬化した後)に、互いに密着した第1レジスト220a、第2レジスト220bが、互いに軟化してなる変形済レジスト390a、390bの互いに密着してなる密着面(あるいは密着面の痕跡)に相当する痕跡部を介して隙間310を形成した場合を示す斜視図である。図12Bに示すように、たとえ、第1レジスト220a、第2レジスト220bが互いに離れたとしてもその隙間310は均一であって、充分に狭いため、接着部140のキャビティ190側への流出を防止する事できる。これは第1レジスト220a、第2レジスト220bが互いに加熱され密着することで、相手の形状が自分に転写してなるレプリカ状態を形成するためである。そのために、第1レジスト220aおよび第2レジスト220bの密着面は変形している。この変形している密着面を変形部と呼ぶ。 In FIG. 12B, the first resist 220a and the second resist 220b which are in close contact with each other are in close contact with each other after completion (that is, after the adhesive portion 140 is thermally cured). It is a perspective view which shows the case where the clearance gap 310 is formed via the trace part corresponded to a contact surface (or the trace of a contact surface). As shown in FIG. 12B, even if the first resist 220a and the second resist 220b are separated from each other, the gap 310 is uniform and sufficiently narrow, thereby preventing the adhesive portion 140 from flowing out to the cavity 190 side. You can do it. This is because the first resist 220a and the second resist 220b are heated and brought into close contact with each other to form a replica state in which the shape of the other is transferred to itself. Therefore, the contact surfaces of the first resist 220a and the second resist 220b are deformed. This deformed contact surface is called a deformed portion.
 次に図13~図15を参照しながら、更に詳しく説明する。 A more detailed description will now be given with reference to FIGS. 13-15.
 図13A~13Cは、第1レジスト220aの一部と、第2レジスト220bの一部が、互いに密着もしくは固着する様子を示す断面図である。 13A to 13C are cross-sectional views showing how a part of the first resist 220a and a part of the second resist 220b adhere or adhere to each other.
 図13Aにおいて、接着部140は、まだ第1レジスト220a、第2レジスト220bの近傍までは流動していない。また矢印SR1は第1レジスト220aの厚みを、矢印SR2は第2レジスト220bの厚みを、矢印Tは接着部140の厚みを示す。図13Aにおいて、「(SR1+SR2)≦T」の関係式が成立することが望ましい。 In FIG. 13A, the bonding portion 140 has not flowed to the vicinity of the first resist 220a and the second resist 220b. The arrow SR1 indicates the thickness of the first resist 220a, the arrow SR2 indicates the thickness of the second resist 220b, and the arrow T indicates the thickness of the bonding portion 140. In FIG. 13A, it is desirable that the relational expression “(SR1 + SR2) ≦ T” holds.
 図13B、図13Cに示すように、矢印280に示すように、第1基板120、第2基板130を加圧、加熱する。こうすることで、第1レジスト220aの一部と、第2レジスト220bの一部が、互いに密着もしくは固着してなる密着面または固着面が形成される。図12Aに、密着面または固着面は点線330で示している。なお、密着面とは第1レジスト220aと第2レジスト220bとが互いに密着してなることであり、互いに密着することで、互いの表面形状の影響を受け、互いに変形することがある。また密着の場合、密着した相手同士を剥がそうとしても、凝集破壊しない場合がある。また固着とは互いに密着下状態で、その一部が物理的、化学的に一体化した状態である。そのため固着した相手同士を剥がそうとした場合、その一部が凝集破壊する場合がある。なお必ずしも第1レジスト220aの一部と第2レジスト220bの一部が、直接、密着あるいは固着することに限定する必要は無い。これは第1レジスト220aの一部と前記第2レジスト220bの一部が、接着部140を介して密着もしくは固着しても同様の効果が得られるためである。 As shown in FIGS. 13B and 13C, as indicated by arrows 280, the first substrate 120 and the second substrate 130 are pressurized and heated. As a result, an adhered surface or an adhered surface is formed in which a part of the first resist 220a and a part of the second resist 220b adhere or adhere to each other. In FIG. 12A, the adhesive or bonding surface is indicated by a dotted line 330. Here, the close contact surface means that the first resist 220a and the second resist 220b are in close contact with each other. When the first resist 220a and the second resist 220b are in close contact with each other, they may be deformed due to the influence of their surface shapes. Further, in the case of close contact, cohesive failure may not occur even if it is attempted to peel off the close contacts. Further, the term "adhesion" refers to a state in which parts are physically and chemically integrated while being in close contact with each other. Therefore, when it is going to peel away the adhering partner, the part may carry out cohesive failure. In addition, it is not necessary to necessarily limit that a part of 1st resist 220a and a part of 2nd resist 220b contact | adhere directly or adhere. This is because the same effect can be obtained even if a part of the first resist 220 a and a part of the second resist 220 b are in close contact or adhered via the bonding part 140.
 また第1レジスト220aの一部と第2レジスト220bの一部が、互いに固着し一体化した場合、あるいは第1レジスト220aの一部と第2レジスト220bの一部が、接着部140を介して互いに固着し一体化した場合、これらを固着レジスト400とする。 When a part of the first resist 220 a and a part of the second resist 220 b are adhered and integrated with each other, or a part of the first resist 220 a and a part of the second resist 220 b via the adhesive portion 140. When they are fixed to each other and integrated, they are used as a fixed resist 400.
 図14(a)、(b)は、それぞれ第1レジストの一部と第2レジストの一部が、互いに固着し一体化した場合、あるいは第1レジストの一部と第2レジストの一部が、接着部を介して互いに固着し一体化した場合の固着面について説明する断面図と、その界面部分の上面図である。 In FIGS. 14A and 14B, when a part of the first resist and a part of the second resist are mutually adhered and integrated, or a part of the first resist and a part of the second resist are integrated. They are sectional drawing explaining the adhering surface at the time of adhering and integrating mutually via an adhesion part, and a top view of the interface portion.
 固着レジスト400は、第1レジスト220aの一部と第2レジスト220bの一部が、互いに固着し一体化したものから、あるいは第1レジスト220aの一部と第2レジスト220bの一部が、接着部140を介して互いに固着し一体化したものから、形成されている。 In the fixing resist 400, a part of the first resist 220a and a part of the second resist 220b are adhered and integrated with each other, or a part of the first resist 220a and a part of the second resist 220b are adhered. They are formed by being fixed and integrated with each other through the portion 140.
 図14(b)は、固着レジスト400の点線330(すなわち、密着面または固着面)における剥離部分の一例を示す上面図である。固着レジスト400の剥離面は、例えば、立体配線基板110を構成する第1基板120と、第2基板130とを互いに剥離することで得られる。 FIG. 14B is a top view showing an example of the peeling portion in the dotted line 330 (that is, the adhesion surface or the adhesion surface) of the adhesion resist 400. The peeling surface of the fixing resist 400 can be obtained, for example, by peeling the first substrate 120 and the second substrate 130 that constitute the three-dimensional wiring substrate 110 from each other.
 図14(b)は、剥離面の一例である。図14(b)に示すように、剥離面には、下地となる第2レジスト220bや、液状接着部410、痕跡部(または凝集部)340が観察できる。液状接着部410とは、接着部140に含まれている無機フィラー等が、第1レジスト220aと第2レジスト220bとの隙間に、矢印380で示すように侵入する際、その隙間で無機フィラー等が濾し取られてなる液状樹脂成分の硬化物である。また痕跡部340を、凝集部としても良い。この場合、凝集部340とは、第1レジスト220aの一部や、第2レジスト220bの一部、液状接着部410、あるいは接着部140の一部が剥離してなる剥離面(互いに密着していた場合)、あるいは凝集破壊された部分(互いに固着していた場合)である。なお痕跡部340は、凝集破壊されてなる凝集部340であっても良い。これは痕跡部であっても、凝集部であっても差が無いためである。 FIG. 14 (b) is an example of the peeling surface. As shown in FIG. 14B, the second resist 220b serving as a base, the liquid bonding portion 410, and the trace portion (or aggregation portion) 340 can be observed on the peeling surface. In the liquid adhesive portion 410, when the inorganic filler or the like contained in the adhesive portion 140 intrudes into the gap between the first resist 220a and the second resist 220b as shown by the arrow 380, the inorganic filler or the like in the gap Is a cured product of the liquid resin component obtained by filtration. In addition, the trace portion 340 may be used as an aggregation portion. In this case, the aggregation portion 340 is a peeling surface formed by peeling a part of the first resist 220a, a part of the second resist 220b, the liquid bonding part 410, or a part of the bonding part 140 Or cohesively broken parts (when they are stuck to each other). The trace portion 340 may be an aggregation portion 340 formed by aggregation and destruction. This is because there is no difference whether it is a trace part or an aggregation part.
 図14(b)に示すように、プレスで加圧、加熱することで、第1レジスト220aと第2レジスト220bとが、一部同士、あるいは全面と一部、あるいは全面同士が密着し、固着してなる固着レジスト400を形成している。またこの固着レジスト400による固着面が、接着部140を構成する樹脂成分の染み出し、あるいは滲み出しを防止することになる。また接着部140から染み出た液状成分(例えば、液状接着部410)もこうした固着レジスト400の形成に有用となる。 As shown in FIG. 14 (b), by pressing and heating with a press, the first resist 220a and the second resist 220b are in close contact with each other, or with the entire surface and a part, or all surfaces, and adhere An adhesion resist 400 is formed. Further, the adhering surface by the adhering resist 400 prevents the exudation or the exudation of the resin component constituting the adhesive portion 140. In addition, a liquid component (for example, liquid adhesive portion 410) that has leaked out from the adhesive portion 140 is also useful for forming such a sticking resist 400.
 図15は、発明者が実際に作成したサンプルにおける剥離面の顕微鏡写真を示す図である。また図16は、図15の顕微鏡写真を模式的に示す平面図である。 FIG. 15 is a view showing a micrograph of the peeled surface of a sample actually prepared by the inventor. FIG. 16 is a plan view schematically showing the microphotograph of FIG.
 図15、図16の矢印480で示す領域が、第1レジスト220aと第2レジスト220bとの剥離部分に相当する。図15、図16の矢印480で示す領域には、前述の図14で説明したように、これら部材が固着(あるいは密着)してなる痕跡が残っている。なお固着レジスト400は、各部材が固着することが望ましいが、密着した状態であっても良い。これは密着した状態であって、図14、図15のようにこれら部材を剥離した場合、互いに固着してなる痕跡が残る場合があるためである。そのためこれら部材の剥離部分の界面を、顕微鏡やSEMで観察し、これらの固着した(あるいは密着した)ことの痕跡が観察されれば、それで充分である。これは顕微鏡やSEMで観察された痕跡部分が、固着してなるものか、密着してなるものか、の区別を行なう前に、痕跡が残るだけの密着(あるいは固着)が行なわれていれば、本発明の作用効果を奏するためである。また密着と固着を区別するには、特殊で高価な分析方法が必要なためであり、本発明において、密着であっても固着であっても、その作用効果は同じためである。 A region indicated by an arrow 480 in FIGS. 15 and 16 corresponds to a peeling portion between the first resist 220a and the second resist 220b. In the region indicated by the arrow 480 in FIGS. 15 and 16, as described in FIG. 14 described above, there remains a trace that these members adhere (or adhere to). The fixing resist 400 desirably has the members fixed, but may be in close contact with each other. This is because they are in close contact with each other, and when these members are peeled off as shown in FIGS. Therefore, if the interface of the exfoliation part of these members is observed with a microscope or SEM, and if the trace of these adhering (or adhering) is observed, it is sufficient. This means that if the trace portion observed with the microscope or the SEM is adhered or adhered, it is adhered (or adhered) with only the trace remaining. The purpose of the present invention is to achieve the effects of the present invention. In addition, a special and expensive analysis method is required to distinguish adhesion and adhesion, and in the present invention, the operation and effect are the same whether it is adhesion or adhesion.
 このように、少なくとも第1レジスト220aの一部と、第2レジスト220bの一部が、互いに密着もしくは固着しているか、あるいは、第1レジスト220aの一部と第2レジスト220bの一部が、前記接着部を介して密着もしくは固着していれば、本発明の優れた作用効果を奏することができる。 Thus, at least a portion of the first resist 220a and a portion of the second resist 220b are in close contact or adhered to each other, or a portion of the first resist 220a and a portion of the second resist 220b are If the members are in close contact or adhered through the adhesive portion, the excellent effects of the present invention can be exhibited.
 また実施の形態1では、レジストと絶縁層160を接着しているのに対し、本実施の形態2ではレジスト同士を密着しているので、実施の形態1と比較してより密着性は高い。よって実施の形態2では、実施の形態1に比べ、より確実に接着部がキャビティへ流れ出すのを防止することができる。 Further, while the resist and the insulating layer 160 are bonded in the first embodiment, since the resists are in close contact with each other in the second embodiment, the adhesion is higher than in the first embodiment. Therefore, in the second embodiment, compared to the first embodiment, it is possible to prevent the adhesive from flowing into the cavity more reliably.
 (実施の形態2の変形例)
 次に実施の形態2の変形例について図17を参照しながら説明する。図17は本発明の実施の形態2の変形例における、立体配線基板の一部を拡大した断面図である。
(Modification of Embodiment 2)
Next, a modification of the second embodiment will be described with reference to FIG. FIG. 17 is a cross-sectional view enlarging a part of a three-dimensional wiring board in a modification of the second embodiment of the present invention.
 実施の形態2と異なる点は、レジスト220aがキャビティ内まではみ出ている点である。図17に示すように、レジスト220の一部が、キャビティ190の中にはみ出ていることによって、第1基板120の周縁部200とのアライメント誤差を吸収する効果が得られる。 The point different from the second embodiment is that the resist 220a protrudes into the cavity. As shown in FIG. 17, a part of the resist 220 protrudes into the cavity 190, so that an effect of absorbing an alignment error with the peripheral portion 200 of the first substrate 120 can be obtained.
 なお、本実施形態は、実施の形態2と同様の効果が得られる。また製造方法についても実施の形態2と同様の方法で製造することができる。 In the present embodiment, the same effects as in the second embodiment can be obtained. The manufacturing method can also be manufactured by the same method as that of the second embodiment.
 (実施の形態3)
 <実施の形態3の構造>
 以下、本発明の実施の形態3について、図面を参照しながら説明する。
Third Embodiment
<Structure of Embodiment 3>
Hereinafter, Embodiment 3 of the present invention will be described with reference to the drawings.
 図18は、本発明の実施の形態3における、立体配線基板の一部を拡大した断面図である。図7を参照しながら説明した実施の形態2と同様の構成については、同一の符号を付して説明を省略する。 FIG. 18 is an enlarged sectional view of a part of the three-dimensional wiring board in the third embodiment of the present invention. The same components as in the second embodiment described with reference to FIG. 7 are assigned the same reference numerals and descriptions thereof will be omitted.
 実施の形態2の構成と異なる点は、図7に示す実施の形態2では第1レジスト220aと絶縁層160との間には第1表層配線170が入り込んでいなかった。一方、図18に示す実施の形態3では、第1レジスト220aと絶縁層160との間に第1表層配線170aが形成されている点だけである。斜視図および具体的な材料およびサイズの例については、実施の形態2と同様であるので説明を省略する。 The difference from the configuration of the second embodiment is that in the second embodiment shown in FIG. 7, the first surface layer wiring 170 does not enter between the first resist 220 a and the insulating layer 160. On the other hand, the third embodiment shown in FIG. 18 is only that the first surface layer wiring 170a is formed between the first resist 220a and the insulating layer 160. About a perspective view and an example of a concrete material and a size, since it is the same as that of Embodiment 2, explanation is omitted.
 また、実施の形態3の製造方法は、実施の形態1および実施の形態2の立体配線基板の製造方法と同様であるので説明を省略する。 Further, the manufacturing method of the third embodiment is the same as the manufacturing method of the three-dimensional wiring substrate of the first embodiment and the second embodiment, so the description will be omitted.
 次に、レジスト同士の接合面について、図18~図20を参照しながら更に詳細に説明する。 Next, the bonding surface between the resists will be described in more detail with reference to FIGS. 18 to 20.
 図18に示す通り、周縁部200には、第1レジスト220aと、第1レジスト220aに重なる第1表層配線170を設け、キャビティ190の周縁部200を構成する第2基板130には、第2レジスト220bと、第2レジスト220bに重なる第2表層配線を設けた場合について説明する。 As shown in FIG. 18, the peripheral portion 200 is provided with a first resist 220 a and a first surface layer wiring 170 overlapping the first resist 220 a, and the second substrate 130 constituting the peripheral portion 200 of the cavity 190 is a second The case where the second surface layer wiring overlapping with the resist 220 b and the second resist 220 b is provided will be described.
 図18において、キャビティ190の周縁部200を構成する第1基板120には、第1レジスト220aと、第1レジスト220aに重なる第1表層配線170を設け、キャビティ190の周縁部200を構成する第2基板130には、第2レジスト220bと、第2レジスト220bに重なる第2表層配線を設けている。このように、キャビティ190の周縁部で対向するレジストに、重なるように表層配線を設けることで、接着部140のキャビティ190側への滲みを低減できる。 In FIG. 18, the first substrate 120 constituting the peripheral portion 200 of the cavity 190 is provided with a first resist 220 a and a first surface layer wiring 170 overlapping the first resist 220 a to form the peripheral portion 200 of the cavity 190. The second substrate 130 is provided with a second resist 220 b and a second surface wiring overlapping the second resist 220 b. As described above, by providing the surface layer wiring so as to overlap the resist facing each other at the peripheral portion of the cavity 190, it is possible to reduce the bleeding of the bonding portion 140 to the cavity 190 side.
 図19は、キャビティ190の周縁部で対向するレジストに重なるように、ライン状の表層配線を設けた場合について説明する断面図である。図19において、第2基板130側にはファンアウト配線からなる第2表層配線180を第2レジスト220bに重なるように、第1基板120側にはライン状の第1表層配線170を第1レジスト220aに重なるように設けている。なおライン状の第1表層配線170は、ファンアウト配線からなる第2表層配線180に直交するように設けることが望ましい。 FIG. 19 is a cross-sectional view for explaining the case where a line-shaped surface layer wiring is provided so as to overlap with the opposing resist at the peripheral portion of the cavity 190. In FIG. 19, on the second substrate 130 side, the line-shaped first surface layer wiring 170 is formed on the first substrate 120 side so that the second surface layer wiring 180 consisting of fan-out wiring overlaps the second resist 220 b. It is provided to overlap 220a. The line-shaped first surface layer wiring 170 is desirably provided so as to be orthogonal to the second surface layer wiring 180 which is a fan-out wiring.
 図20は、キャビティ190の周縁部で対向するレジストに重なるように、反転状(例えば、ネガ-ポジ状の逆パターン)の表層配線を設けた場合について説明する断面図である。図20において、第2基板130側にはファンアウト配線からなる第2表層配線180を第2レジスト220bに重なるように、第1基板120側にはライン状の第1表層配線170を第1レジスト220aに重なるように設けている。なおライン状の第1表層配線170は、ファンアウト配線からなる第2表層配線180の凹凸を埋めるように(あるいは反転するように)に設けることが望ましい。 FIG. 20 is a cross-sectional view for explaining the case where a surface layer wiring of a reverse (for example, a negative-positive reverse pattern) surface layer is provided so as to overlap with the opposing resist at the peripheral portion of the cavity 190. In FIG. 20, a line-shaped first surface layer wiring 170 is formed on the first substrate 120 side so that the second surface layer wiring 180 consisting of fan-out wiring overlaps the second resist 220b on the second substrate 130 side. It is provided to overlap 220a. The line-shaped first surface layer wiring 170 is desirably provided so as to fill (or invert) the unevenness of the second surface layer wiring 180 which is a fan-out wiring.
 (第4の実施の形態)
 <実施の形態4の構造>
 実施の形態4について、図21を参照しながら説明する。
Fourth Embodiment
<Structure of Embodiment 4>
Fourth Embodiment A fourth embodiment will be described with reference to FIG.
 図21に示す実施の形態は、図7を参照しながら説明した立体配線基板110のキャビティ190の内部に半導体素子230を実装した立体配線基板である。なお、配線基板に半導体素子が接続された半導体実装物を、以下、半導体実装構造物250と呼ぶ。 The embodiment shown in FIG. 21 is a three-dimensional wiring substrate in which the semiconductor element 230 is mounted inside the cavity 190 of the three-dimensional wiring substrate 110 described with reference to FIG. 7. Hereinafter, a semiconductor mounted product in which a semiconductor element is connected to a wiring board is referred to as a semiconductor mounted structure 250.
 図7に示す立体配線基板110に設けられたキャビティ190内に露出した第2表層配線180に半導体素子230が実装されている。本実施形態では、実装部240として例えば半田バンプを用いている。半導体素子230は、シリコン半導体に限定する必要は無く、ベアチップ、チップ部品、レンズ等の光学素子、あるいは光学電気子等も含まれる。実装部240として、ワイヤーボンディング等を用いてもよい。またキャビティ190内に、半導体素子230等を実装した後、必要に応じて市販のポッティング樹脂(封止樹脂)等を用いて、半導体素子230を樹脂封止することもできる。 The semiconductor element 230 is mounted on the second surface layer wiring 180 exposed in the cavity 190 provided in the three-dimensional wiring substrate 110 shown in FIG. 7. In the present embodiment, for example, a solder bump is used as the mounting portion 240. The semiconductor element 230 is not limited to a silicon semiconductor, and includes a bare chip, a chip part, an optical element such as a lens, or an optical element. Wire bonding or the like may be used as the mounting unit 240. In addition, after the semiconductor element 230 and the like are mounted in the cavity 190, the semiconductor element 230 can be resin-sealed using a commercially available potting resin (sealing resin) or the like as necessary.
 配線基板に半導体素子230を実装した半導体実装構造物250では、携帯電話等の各種携帯端末の小型化、高性能化に貢献することができる。 The semiconductor mounting structure 250 in which the semiconductor element 230 is mounted on the wiring substrate can contribute to downsizing and high performance of various mobile terminals such as mobile phones.
 (その他の実施の形態)
 <導電ペースト面接触の様子>
 次に図22A、図22Bを参照しながら、導電ペースト150として、金属粉を含む導電ペーストを用いることで、金属粉が互いに変形し、面接触する様子を示す。
(Other embodiments)
<State of conductive paste surface contact>
Next, referring to FIGS. 22A and 22B, the use of a conductive paste containing metal powder as the conductive paste 150 shows that the metal powders are deformed to be in surface contact with each other.
 図22A、図22Bは、共に導電ペースト150に含まれる金属粉同士が、突出部300の作用効果によって互いに圧縮され、変形する様子を模式的に説明する断面図である。 FIGS. 22A and 22B are cross-sectional views schematically illustrating how metal powders contained in the conductive paste 150 are compressed and deformed with each other by the function and effect of the protrusion 300.
 図22Aは、導電ペースト150が加圧圧縮される前の断面図、図22Bは、導電ペースト150が加圧圧縮された後の断面図である。 FIG. 22A is a cross-sectional view before the conductive paste 150 is pressure-compressed, and FIG. 22B is a cross-sectional view after the conductive paste 150 is pressure-compressed.
 図22Bでは、導電ペースト150中に含まれる金属粉350が変形して面接触部を形成し変形粉360となる。導電ペースト150には、金属粉350以外に、エポキシ樹脂等の熱硬化樹脂、分散剤、添加剤、溶剤等を必要に応じて添加すれば良い。なおこれらの熱硬化樹脂等の各種部材は図22A、図22Bにおいて図示していない。矢印280aは、圧縮前の導電ペースト150の厚みに相当する。次にこの導電ペーストは、突出部300や、第1基板120、第2基板130の表面に突出するように設けられた第1表層配線170、第2表層配線180の厚み分、より強く圧縮され、図22Bに示す状態となる。 In FIG. 22B, the metal powder 350 contained in the conductive paste 150 is deformed to form a surface contact portion to form a deformed powder 360. In addition to the metal powder 350, a thermosetting resin such as an epoxy resin, a dispersant, an additive, a solvent, and the like may be added to the conductive paste 150 as necessary. The various members such as these thermosetting resins are not shown in FIGS. 22A and 22B. Arrow 280 a corresponds to the thickness of conductive paste 150 before compression. Next, the conductive paste is compressed more by the thickness of the first surface layer wiring 170 and the second surface layer wiring 180 provided so as to project from the surface of the protrusion 300, the first substrate 120, and the second substrate 130. , The state shown in FIG. 22B.
 図22Bに示すように、複数の金属粉350は、互いに加圧され変形してなる点線330で示す面接触部(あるいは面接触面)を介して面接触した、変形粉360を形成する。また変形粉360と変形粉360の界面には、点線330で示す面接触部(あるいは面接触した界面)が形成されている。そしてこの点線330で示す面接触部を介して、複数の金属粉350が電気的に接続し、第1表層配線170と、第2表層配線180との間のビア抵抗を小さくする。図22Bにおける矢印280bは、圧縮された後の導電ペースト150の厚みを示す。以上のように、「280a>280b」の関係を示すことは言うまでもない。 As shown in FIG. 22B, the plurality of metal powders 350 form deformed powder 360 which is in surface contact via a surface contact portion (or surface contact surface) indicated by dotted lines 330 which are compressed and deformed with each other. Also, at the interface between the deformed powder 360 and the deformed powder 360, a surface contact portion (or an interface in surface contact) indicated by a dotted line 330 is formed. Then, the plurality of metal powders 350 are electrically connected via the surface contact portion indicated by the dotted line 330, and the via resistance between the first surface layer wiring 170 and the second surface layer wiring 180 is reduced. Arrow 280 b in FIG. 22B indicates the thickness of the conductive paste 150 after being compressed. It goes without saying that the relationship “280a> 280b” is shown as described above.
 <導電ペーストの流れ出しの比較例>
 次に、本願発明の優位性を確認するために、キャビティ190内に第1比較レジスト430を配置した試作品(以下、「比較基板1」と、呼ぶ)と、本願の実施の形態2の試作品それぞれについて、接着部140の染み出しの状況の結果を説明する。なお、試作結果の一例を図23に示す。
Comparative Example of Flowing Out of Conductive Paste
Next, in order to confirm the superiority of the present invention, a trial product (hereinafter referred to as “comparative substrate 1”) in which the first comparative resist 430 is disposed in the cavity 190, and the trial of the second embodiment of the present application. For each of the works, the result of the exuding situation of the bonding part 140 will be described. In addition, an example of a trial production result is shown in FIG.
 図24~図26を参照しながら、比較基板1の試作品について以下、説明する。 The prototype of the comparative substrate 1 will be described below with reference to FIGS. 24 to 26.
 図24は、第1比較基板420について説明する斜視図である。第1比較レジスト430は、キャビティ内に配置されている。矢印280に示すように、第1基板120と第2基板130とを加圧密着させ、図25の状態となる。 FIG. 24 is a perspective view for explaining the first comparison substrate 420. The first comparison resist 430 is disposed in the cavity. As shown by the arrow 280, the first substrate 120 and the second substrate 130 are brought into pressure contact with each other, resulting in the state of FIG.
 図25は、第1比較基板420のキャビティ190付近を拡大して説明する斜視図である。図25に示すように、第1比較レジスト430と、第1基板120との間には隙間310aが形成されている。また第1基板120と第2基板130との間には、第2表層配線180の厚みに起因する隙間310bが形成されている。通気矢印320は、隙間310b、310aを介して、内部の空気が外部へ漏れる様子を示す。 FIG. 25 is an enlarged perspective view of the vicinity of the cavity 190 of the first comparison substrate 420. As shown in FIG. 25, a gap 310 a is formed between the first comparison resist 430 and the first substrate 120. Further, a gap 310 b resulting from the thickness of the second surface layer wire 180 is formed between the first substrate 120 and the second substrate 130. The ventilation arrow 320 indicates how internal air leaks to the outside through the gaps 310 b and 310 a.
 図26は、第1比較基板420において接着部440がキャビティ側に流入した様子を模式的に示す斜視図である。加熱され軟化した接着部440は、図24に示した隙間310b、310aを介して、外部にはみ出してしまう。 FIG. 26 is a perspective view schematically showing how the bonding part 440 flows into the cavity side in the first comparison substrate 420. As shown in FIG. The heated and softened bonding portion 440 leaks to the outside through the gaps 310 b and 310 a shown in FIG. 24.
 次に、図23に試作結果の一例を示す表を用いて説明する。図23に示す本願試作品は、外形寸法約300×300mmの中に、約10mm角のキャビティ190が、数十個形成されたテストパターンを用いた試作結果である。第1基板120、第2基板130には4層のALIVH基板(ALIVHは、Panasonic株式会社の登録商標)を用いた。これはALIVH基板が、一般的なスルーホールメッキを用いたガラスエポキシ樹脂を用いた多層基板に比べて、加圧、加熱に強いためである。また接着部140には、ALIVH基板に熱膨張係数をマッチングさせたシート状の接着層(無機フィラーとエポキシ樹脂との混練物)を用いた。また導電ペースト150としては、金属粉350として、銅粉(3~10ミクロン)を、エポキシ樹脂の中に混練してなる、ALIVH基板用の導電ペーストを用いた。また第1基板120、第2基板130と、接着部140との加圧は、真空プレス装置を用い、室温(20℃)~約200℃まで、加圧を保ったまま段階的に加圧圧力や加熱条件のプロファイルを調整した。第1レジスト220a、第2レジスト220bには、ネガレジストを用いた。またこのネガレジストのTgは200℃以下(望ましくは150℃以下)のものを選んだ。そして、導電ペースト150を室温(20℃)付近から加圧を開始し、図8Bの状態とした後、これら部材を加熱し、第1レジスト220a、第2レジスト220bが互いに接触しても割れない程度まで軟化させ、互いに密着させ、接着部140を軟化させるようにした。 Next, it demonstrates using the table | surface which shows an example of a trial production result in FIG. The prototype of the present invention shown in FIG. 23 is a trial result using a test pattern in which several tens of approximately 10 mm square cavities 190 are formed in an outer dimension of approximately 300 × 300 mm. For the first substrate 120 and the second substrate 130, a 4-layer ALIVH substrate (ALIVH is a registered trademark of Panasonic Corporation) was used. This is because the ALIVH substrate is more resistant to pressure and heating than a multilayer substrate using a glass epoxy resin using general through-hole plating. Further, for the bonding portion 140, a sheet-like bonding layer (kneaded product of an inorganic filler and an epoxy resin) in which the thermal expansion coefficient is matched to the ALIVH substrate was used. Further, as the conductive paste 150, a conductive paste for an ALIVH substrate, which is obtained by kneading copper powder (3 to 10 microns) in an epoxy resin as the metal powder 350, was used. The pressure applied to the first substrate 120, the second substrate 130, and the bonding portion 140 can be increased stepwise from room temperature (20.degree. C.) to about 200.degree. C. while maintaining the pressure, using a vacuum press. And adjusted the heating condition profile. A negative resist was used as the first resist 220a and the second resist 220b. Further, the Tg of this negative resist was selected to be 200 ° C. or less (desirably 150 ° C. or less). Then, after the conductive paste 150 is started to be pressurized at around room temperature (20 ° C.) and brought into the state of FIG. 8B, these members are heated and the first resist 220a and the second resist 220b do not break even when they contact each other. It was softened to a certain degree, brought into close contact with each other, and softened the bonding portion 140.
 図23に示す本願試作品とは、図7を参照しながら説明した実施の形態2に相当する。第1比較基板とは、上述した図24~図26で示した第1比較基板420に相当する。第1基板120、第2基板130や、接着部140、導電ペースト150等は、共通とした。 The prototype of the present application shown in FIG. 23 corresponds to the second embodiment described with reference to FIG. The first comparison substrate corresponds to the first comparison substrate 420 shown in FIGS. 24 to 26 described above. The first substrate 120, the second substrate 130, the bonding portion 140, the conductive paste 150, and the like are common.
 またボイドの有無は、試作した各サンプルの一部の断面を観察した結果である。また接着部のはみ出しとは、第1基板120、第2基板130の間に挿入した接着部140の一部が、キャビティ190内に染み出したかどうかを、実体顕微鏡で観察した結果の一例を、図23に示す。 Moreover, the presence or absence of a void is the result of having observed the cross section of a part of each sample produced experimentally. Further, the protrusion of the bonding part is an example of the observation result of whether or not a part of the bonding part 140 inserted between the first substrate 120 and the second substrate 130 leaks into the cavity 190 with a stereomicroscope, It is shown in FIG.
 図23に示す通り、本願試作品、第1比較基板にボイドは発生しなかった。これは第1基板120、第2基板130に加熱、加圧性に優れたALIVH基板を用いたためと考えられる。また、接着部140の、キャビティ190内部へのはみ出しは、第1比較基板420で観察された。一方、本願試作品(立体配線基板110)では接着部140の、キャビティ190内への、はみ出しは観察されなかった。これは本願発明品では、図5B、図11Aに示すように、ボイド発生の原因となる、隙間からの空気の外部への排出性に優れると共に、接着部140が軟化し、その流動性を高めた温度域(あるいは加圧条件)では、第1レジスト220a、第2レジスト220b同士を密着させることで、接着部140のキャビティ190側へのはみ出しを止めたからと考えられる。 As shown in FIG. 23, no void was generated in the prototype of the present invention and the first comparison substrate. It is considered that this is because an ALIVH substrate excellent in heating and pressurizing properties is used for the first substrate 120 and the second substrate 130. In addition, the protrusion of the bonding part 140 into the inside of the cavity 190 was observed at the first comparison substrate 420. On the other hand, in the prototype of the present application (the three-dimensional wiring substrate 110), the protrusion of the bonding portion 140 into the cavity 190 was not observed. In the product of the present invention, as shown in FIG. 5B and FIG. 11A, it is excellent in the dischargeability of air from the gap to the outside, which causes the generation of voids, and the bonding portion 140 is softened to enhance its flowability. In the temperature range (or under the pressure condition), it is considered that the sticking of the first resist 220 a and the second resist 220 b prevents the sticking of the bonding portion 140 to the cavity 190 side.
 <製造方法の別の例(立体配線基板の第2の製造方法)>
 次に、実施の形態1~3の第2の立体配線基板の製造方法について図26を参照しながら説明する。
<Another Example of Manufacturing Method (Second Manufacturing Method of Three-Dimensional Wiring Board)>
Next, a method of manufacturing the second three-dimensional wiring substrate of Embodiments 1 to 3 will be described with reference to FIG.
 上記実施の形態では図4~図6を参照しながら説明した立体配線基板の製造方法では、第1の開口部290aを有する第1基板と、第2基板を貼り合わせる方法をとっていたが、以下、説明する立体配線基板の第2の製造方法では、張り合わせた後にキャビティを形成している。 In the above embodiment, in the method of manufacturing a three-dimensional wiring substrate described with reference to FIGS. 4 to 6, the first substrate having the first opening 290 a is bonded to the second substrate. In the second method of manufacturing a three-dimensional wiring substrate to be described below, the cavity is formed after bonding.
 まず図27Aに示すように、第1基板120と第2基板130との間に、導電ペースト150を有する接着部140をセットする。なお、導電ペースト150を有する接着部140の製造方法は、図4A~図4Dを参照しながら説明した立体配線基板の製造方法と同様であるので、ここでは説明を省略する。そして矢印340aに示すように、これら部材を加圧し一体化する。その後、図27Bにおける矢印340bで示すように、第1基板120、あるいは第2基板130のいずれか一つ以上の一部を除去する。除去には機械的(ルーター等)、レーザー等を用いることができる。またレーザーを用いる場合、キャビティ190の表面(あるいは底面)に、レーザー加工痕が残らないように、銅箔(例えば表層配線の一部)を、レーザーに対するストッパーとすることは有用である。その後、図27Cにおける矢印340cで示すように、不要部を除去することで、キャビティ190を形成する。 First, as shown in FIG. 27A, an adhesive portion 140 having a conductive paste 150 is set between the first substrate 120 and the second substrate 130. The method of manufacturing the bonding portion 140 having the conductive paste 150 is the same as the method of manufacturing the three-dimensional wiring substrate described with reference to FIGS. 4A to 4D, and thus the description thereof is omitted here. Then, as shown by an arrow 340a, these members are pressurized and integrated. Thereafter, as shown by an arrow 340 b in FIG. 27B, a part of any one or more of the first substrate 120 or the second substrate 130 is removed. Mechanical (router etc.), laser etc. can be used for removal. When a laser is used, it is useful to use a copper foil (for example, a part of surface wiring) as a stopper for the laser so that no laser processing mark is left on the surface (or the bottom) of the cavity 190. Thereafter, as shown by an arrow 340c in FIG. 27C, the unnecessary portion is removed to form a cavity 190.
 図27A~図27Cに示すように、第1基板120、第2基板130を、第1レジスト220aの一部と第2レジスト220bの一部は、キャビティの周縁部で互いに対向した状態として、一体化した後で、キャビティ190を形成することで、キャビティ190の実装面のコプラナリティ(Coplanarityとは取付面に対する部品の各端子や電極の最下面の均一性を言い、例えば日本電子機械工業会規格EIAJでは端子最下面均一性としている)を高めることができる。 As shown in FIGS. 27A to 27C, in the first substrate 120 and the second substrate 130, a portion of the first resist 220a and a portion of the second resist 220b are integrated so that they face each other at the peripheral portion of the cavity. After forming the cavity 190, the coplanarity of the mounting surface of the cavity 190 (Coplanarity means the uniformity of the lower surface of each terminal or electrode of the component with respect to the mounting surface). In this case, the terminal bottom surface uniformity can be improved.
 なお、上記した第2の製造方法は実施の形態1~4の全てに適応できるのは言うまでもない。 Needless to say, the second manufacturing method described above can be applied to all of the first to fourth embodiments.
 なお、実施の形態1~4においては、レジスト220が、キャビティ190の周囲を一周して覆うのが望ましい。しかしながら、レジストに開口部を設けるなどして、完全にキャビティ190を完全に一周しなくても、接着部140からの流れ出しが防止できていれば、必ず周囲を完全に一周する必要はない。 In the first to fourth embodiments, it is desirable that the resist 220 cover the circumference of the cavity 190. However, even if the resist does not completely go around the cavity 190 completely by providing an opening or the like, it is not necessary to completely go around the circumference if the outflow from the bonding part 140 can be prevented.
 なお、本実施の形態1~4に記載の配線基板で形成されるレジストは、通常、キャビティの周縁部の余った領域に配置することができるため、配線基板の面積を増加させることなく、同じ機能を持ち、かつ、接着部の流れ出しを防止することができる。例えば、図25に示す第1比較基板420では、キャビティ内に第1比較レジスト430を形成しているため、キャビティ内の面積に影響する。つまり、キャビティ内に第1比較レジストを形成する場合は、キャビティ内に例えば半導体素子を配置する場合は、本願の実施の形態1~4よりもキャビティの面請を大きくする必要がある。 The resists formed of the wiring substrates described in the first to fourth embodiments can generally be disposed in the remaining area of the peripheral edge portion of the cavity, and therefore, the same may be applied without increasing the area of the wiring substrate. It has a function and can prevent the flow out of the bonding part. For example, in the first comparative substrate 420 shown in FIG. 25, since the first comparative resist 430 is formed in the cavity, it affects the area in the cavity. That is, in the case where the first comparative resist is formed in the cavity, for example, when the semiconductor element is disposed in the cavity, it is necessary to make the surface contact of the cavity larger than in the first to fourth embodiments of the present application.
 また、第1表層配線170、第2表層配線180との間の電気的な接続は、接着部内に充填した導電ペースト150によって行うことにより、第1表層配線170、第2表層配線180に形成する内層等の配線パターンやビア(共に図1においては図示していない)の設計自由度を高めることができる。これは導電ペースト150からなるビアを、IVHとすることができるためである。なお用途によっては、立体配線基板110を貫通する孔をドリル等で形成し、この貫通孔にメッキ技術を適用しながら、スルーホールを形成しても何ら問題はない。 In addition, electrical connection between the first surface layer wiring 170 and the second surface layer wiring 180 is formed on the first surface layer wiring 170 and the second surface layer wiring 180 by the conductive paste 150 filled in the bonding portion. It is possible to increase the design freedom of the wiring patterns of the inner layer etc. and vias (both not shown in FIG. 1). This is because the via formed of the conductive paste 150 can be IVH. Depending on the application, it is possible to form a through hole through the three-dimensional wiring substrate 110 with a drill or the like, and to form a through hole while applying a plating technique to this through hole.
 なお、実施の形態1~4において、キャビティ190内に第2表層配線180が引き出されているが、必ずしも第2表層配線180をキャビティ190内に引き出す必要はない。 In the first to fourth embodiments, the second surface wiring 180 is drawn into the cavity 190, but the second surface wiring 180 is not necessarily drawn into the cavity 190.
 なお、本実施の形態では、周縁部200に設けるレジスト220のパターンは、本実施の形態では四角形であるが、必ずしもそれに限定されない。キャビティ190が四角形の場合、レジスト220のパターンは、四角形が望ましい。 In the present embodiment, the pattern of the resist 220 provided on the peripheral portion 200 is a quadrangle in the present embodiment, but is not necessarily limited thereto. When the cavity 190 is square, the pattern of the resist 220 is preferably square.
 なお、レジスト220のパターン幅は、50ミクロン以上(更には100ミクロン以上)、2000ミクロン以下で任意に設計すれば良い。 The pattern width of the resist 220 may be arbitrarily designed to be 50 microns or more (or 100 microns or more) or 2000 microns or less.
 なお、第1基板120の周縁部200と、レジスト220が互いに対向した状態で、互いに重なる幅は、50ミクロン以上が望ましい。レジスト220のパターン幅(特に最細部分のパターン幅)が50ミクロン未満の場合、第1基板120の周縁部200と、レジスト220との重なり部分の幅が不足する場合がある。また2000ミクロンを超えた場合、レジスト220のパターン幅に変化を持たせたり(パターン幅を局所的に広げたり、局所的に狭くしたり)すれば問題はない。こうしたパターン設計は、ソルダーレジストの設計手法を適用すれば良い。 The overlapping width between the peripheral portion 200 of the first substrate 120 and the resist 220 is preferably 50 microns or more. If the pattern width of the resist 220 (in particular, the pattern width of the narrowest portion) is less than 50 microns, the width of the overlapping portion between the peripheral portion 200 of the first substrate 120 and the resist 220 may be insufficient. If it exceeds 2000 microns, there is no problem if the pattern width of the resist 220 is changed (the pattern width is locally expanded or locally narrowed). For such pattern design, a solder resist design method may be applied.
 なお、本実施の形態では、第1基板120の周縁部200にレジスト220を形成しているので、一般的に周縁部200に表層配線が存在しない第1のレジストを広げることにより、基板の面積を拡大する必要なく、容易にレジスト220を配置する領域を確保することができる。 In the present embodiment, since the resist 220 is formed on the peripheral portion 200 of the first substrate 120, the area of the substrate is generally obtained by spreading the first resist where the surface layer wiring does not exist on the peripheral portion 200. It is possible to easily secure a region for arranging the resist 220 without the need to expand the
 なお、第2表層配線180の厚みは、第2表層配線180に使用する銅箔の厚み(例えば、9~36ミクロン)に依存する。第2表層配線180の厚みより、レジスト220の厚みを厚くすることが望ましい。また、レジスト220の厚みを100ミクロン以下にすることで、立体配線基板110の総厚に影響を与える可能性が低くなる。 The thickness of the second surface layer wiring 180 depends on the thickness (eg, 9 to 36 microns) of the copper foil used for the second surface layer wiring 180. It is desirable to make the thickness of the resist 220 thicker than the thickness of the second surface layer wiring 180. Also, by setting the thickness of the resist 220 to 100 microns or less, the possibility of affecting the total thickness of the three-dimensional wiring substrate 110 is reduced.
 なお、必要に応じて、キャビティ190の一部のみに(例えば、ファンアウト配線が形成されている部分、あるいはキャビティ190底部の実装領域に近い領域、例えば実装領域から2mm以内)、レジスト220を第1基板120の周縁部に対向するようにしても良い。このようにレジスト220を形成する位置を、キャビティ190の全周(あるいは全周縁部)に、あるいはキャビティ190の一部に(少なくともキャビティ190全周の50%以上、更には60%以上。50%未満の場合は接着部140のキャビティ190内への流れ込み防止効果に影響がある場合がある)なるようにしても良い。 Note that, if necessary, the resist 220 is formed only in part of the cavity 190 (for example, a portion near the mounting area where the fan-out wiring is formed or the bottom of the cavity 190, for example, within 2 mm from the mounting area). You may make it oppose the peripheral part of 1 board | substrate 120. FIG. The position where the resist 220 is formed in this manner is on the entire circumference (or the entire peripheral edge) of the cavity 190 or on a part of the cavity 190 (at least 50% or more of the entire circumference of the cavity 190, or 60% or more. In the case of less than the above, the effect of preventing the flow of the bonding portion 140 into the cavity 190 may be affected.
 なお第1基板120、第2基板130としては、市販のガラスエポキシ樹脂を用いた多層配線基板(ビアはメッキビアでもペーストビアでも良い)とすることは有用である。また第1基板120、第2基板130の表層にビルドアップ層(ビルドアップ層は、ブラインドビア等を有する多層基板の一種である)としても良い。また図1において、ビルドアップ層を有する配線基板を第1基板120とし、このビルドアップ層の表層配線を第1基板120の第1表層配線170とし、別のビルドアップ層を有する配線基板を第2基板130とし、この別のビルドアップ層の表層配線を第2基板130の第2表層配線180とし、これらを導電ペースト150に形成した孔に充填した導電ペースト150でIVH接続し、立体配線基板110とすることも有用である。こうすることで、立体配線基板110のキャビティ190の底面に露出した第2基板130の第2表層配線180を更に機能的(ファインパターン化等)とすることができる。このように、配線基板のビルドアップ層同士を互いに対向させて、接着部140を介して積層、一体化して立体配線基板110とする場合も、接着部140のキャビティ190内への流れ込みを、互いに対向するビルドアップ層に設けた、レジスト220によって効果的に食い止めることができる。 As the first substrate 120 and the second substrate 130, it is useful to use a multilayer wiring substrate (a via may be a plated via or a paste via) using a commercially available glass epoxy resin. Alternatively, a buildup layer (the buildup layer is a kind of multilayer substrate having a blind via or the like) may be formed on the surface layer of the first substrate 120 and the second substrate 130. Further, in FIG. 1, a wiring substrate having a buildup layer is referred to as a first substrate 120, a surface wiring of the buildup layer is referred to as a first surface wiring 170 of the first substrate 120, and a wiring substrate having another buildup layer is referred to as a first wiring. The surface wiring of this second buildup layer is used as the second surface wiring 180 of the second substrate 130, and IVH connection is performed with the conductive paste 150 filled in the holes formed in the conductive paste 150. It is also useful to set it to 110. By doing this, the second surface layer wiring 180 of the second substrate 130 exposed to the bottom surface of the cavity 190 of the three-dimensional wiring substrate 110 can be made more functional (fine patterning or the like). As described above, also in the case where the buildup layers of the wiring substrate are made to face each other and are laminated and integrated through the bonding portion 140 to form the three-dimensional wiring substrate 110, the flow into the cavity 190 of the bonding portion 140 This can be effectively stopped by the resist 220 provided in the opposite buildup layer.
 本発明にかかる立体配線基板と半導体実装構造物とその製造方法によって、パソコン、デジタルカメラ、携帯電話などの更なる小型、薄型、軽量、高精細、多機能化が可能となる。 The three-dimensional wiring board, the semiconductor mounting structure, and the method of manufacturing the same according to the present invention make it possible to further reduce the size, thickness, weight, high definition, and multifunctionality of personal computers, digital cameras, mobile phones and the like.
 110  立体配線基板
 120  第1基板
 130  第2基板
 140  接着部
 150  導電ペースト
 160  絶縁層
 170  第1表層配線
 180  第2表層配線
 190  キャビティ
 200  周縁部
 220,220a,220b  レジスト
 230  半導体素子
 240  実装部
 250  半導体実装構造物
 260  保護フィルム
 270  孔
 280,280a,280b  矢印
 290,290a,290b  開口部
 300  突出部
 310,310a,310b  隙間
 320  通気矢印
 330  点線
 350  金属粉
 360  変形粉
 370  未変形レジスト
 380  凹凸レジスト
 420  第1比較基板
 430  第1比較レジスト
DESCRIPTION OF SYMBOLS 110 Three-dimensional wiring board 120 1st board | substrate 130 2nd board | substrate 140 Bonding part 150 Conductive paste 160 Insulating layer 170 1st surface layer wiring 180 2nd surface layer wiring 190 Cavity 200 Peripheral part 220, 220a, 220b Resist 230 Semiconductor element 240 Mounting part 250 Semiconductor Mounting structure 260 Protective film 270 Hole 280, 280a, 280b Arrow 290, 290a, 290b Opening 300 Projection 310, 310a, 310b Clearance 320 Vented arrow 330 Dotted line 350 Metal powder 360 Deformed powder 370 Undeformed resist 380 Irregularity resist 420 1 Comparison substrate 430 1st comparison resist

Claims (9)

  1.  開口部と表層に配置された第1表層配線とを有する第1基板と、
     表層に配置された第2表層配線を有する第2基板と、
     前記第1基板と前記第2基板の間に配置され、前記第1基板と前記第2基板とを互いに接着する接着部と、
     前記第1基板と前記第2基板の間に配置され、前記第1基板と前記第2基板とに接するレジスト部と、
    を有する配線基板であって、
     前記開口部は前記第2基板を底面とするキャビティを形成し、
     前記接着部は、前記接着部に形成された孔に充填された導電ペーストからなるビアを有し、
     前記ビアは、前記第1表層配線と前記第2表層配線とを電気的に接続し、
     前記レジスト部の少なくとも一部は、前記第1基板と前記第2基板が対向し、かつ、前記キャビティを囲む領域に形成されている
     ことを特徴とする配線基板。
    A first substrate having an opening and a first surface wiring disposed on the surface;
    A second substrate having a second surface wiring disposed on the surface;
    An adhesive unit disposed between the first substrate and the second substrate and adhering the first substrate and the second substrate to each other;
    A resist portion disposed between the first substrate and the second substrate and in contact with the first substrate and the second substrate;
    A wiring board having
    The opening forms a cavity whose bottom surface is the second substrate,
    The bonding portion has a via made of a conductive paste filled in a hole formed in the bonding portion,
    The via electrically connects the first surface layer wiring and the second surface layer wiring,
    A wiring substrate, wherein at least a part of the resist portion is formed in a region where the first substrate and the second substrate face each other and which surrounds the cavity.
  2.  請求項1記載の配線基板であって、
     前記レジスト部は、第1のレジストおよび第2のレジストで形成され、
     前記第1のレジストは前記第1基板に接し、前記第2のレジストは前記第2基板に接している
     ことを特徴とする配線基板。
    The wiring board according to claim 1, wherein
    The resist portion is formed of a first resist and a second resist,
    The wiring substrate, wherein the first resist is in contact with the first substrate, and the second resist is in contact with the second substrate.
  3.  請求項2記載の配線基板であって、
     前記第1基板と前記第2基板とが対向し、かつ、前記キャビティを囲む領域で、前記第1のレジストおよび前記第2のレジストが互いに密着してなる密着部が形成されている
     ことを特徴とする配線基板。
    The wiring board according to claim 2, wherein
    In a region where the first substrate and the second substrate face each other and surrounds the cavity, an adhesion portion in which the first resist and the second resist are in close contact with each other is formed. Wiring board to be.
  4.  請求項3記載の配線基板であって、
     前記密着部が変形部である
     ことを特徴とする配線基板。
    The wiring board according to claim 3, wherein
    The wiring board, wherein the adhesion portion is a deformation portion.
  5.  請求項2記載の配線基板であって、
     前記第1基板と前記第2基板とが対向するキャビティの周縁領域で、前記第1のレジストの少なくとも一部と、前記第2のレジストの少なくとも一部が、直接または前記接着部を介して、密着または固着している
     ことを特徴とする配線基板。
    The wiring board according to claim 2, wherein
    At least a portion of the first resist and at least a portion of the second resist are directly or through the bonding portion in the peripheral region of the cavity where the first substrate and the second substrate face each other. A wiring board characterized by adhering or adhering.
  6.  請求項2記載の配線基板であって、
     前記第1のレジストと前記第1基板とは、表層配線を介して接していることを特徴とする配線基板。
    The wiring board according to claim 2, wherein
    A wiring substrate in which the first resist and the first substrate are in contact with each other through surface wiring.
  7.  請求項1記載の配線基板であって、
     さらに、前記キャビティ内に配置される半導体素子を有し、
     前記半導体素子は、前記キャビティ内の前記第2基板の表層に配置された表層配線と接続されていることを特徴とする配線基板。
    The wiring board according to claim 1, wherein
    Furthermore, it has a semiconductor element disposed in the cavity,
    The wiring substrate, wherein the semiconductor element is connected to a surface layer wiring disposed on a surface layer of the second substrate in the cavity.
  8.  表面に保護フィルムが貼られる接着部に孔を開口する第1のステップと、
    前記第1のステップで開口された前記接着部の孔に導電ペーストを充填する第2のステプと、
     前記保護フィルムを剥離する第3のステップと、
     開口部と表層に配置される第1表層配線とを有する第1基板と、表層に配置される第2表層配線を有する第2基板とを前記接着部を介して貼り合わせ、前記第1基板の開口部を側面とし前記第2基板を底面とするキャビティが形成される第4のステップと
    を有する配線基板の製造方法であって、
     前記第4のステップで前記第1基板と前記第2基板を貼り合せる際、前記レジスト部の少なくとも一部が、前記第1基板と前記第2基板が対向し、かつ、前記キャビティを囲む領域に形成されることを特徴とする配線基板の製造方法。
    A first step of opening a hole in a bonding portion to which a protective film is attached on the surface;
    A second step of filling the hole of the bonding portion opened in the first step with a conductive paste;
    A third step of peeling the protective film;
    A first substrate having an opening portion and a first surface layer wiring disposed in the surface layer, and a second substrate having a second surface layer wiring disposed in the surface layer are pasted through the adhesive portion, and the first substrate And a fourth step in which a cavity having an opening as a side surface and the second substrate as a bottom surface is formed,
    When bonding the first substrate and the second substrate in the fourth step, at least a part of the resist portion is in a region where the first substrate and the second substrate face each other and surrounds the cavity. A manufacturing method of a wiring board characterized by being formed.
  9.  表面に保護フィルムが貼られる接着部に孔を開口する第1のステップと、
     前記第1のステップで開口された前記接着部の孔に導電ペーストを充填する第2のステップと、
     前記保護フィルムを剥離する第3のステップと、
     表層に配置される第1表層配線とを有する第1基板と、表層に配置される第2表層配線を有する第2基板とを前記接着部を介して貼り合わせる第4のステップと、
    前記第1基板または前記第2基板の少なくともいずれか1つの一部を除去しキャビティを形成する第5のステップと
    を有する配線基板の製造方法であって、
     前記第4のステップで前記第1基板と前記第2基板を貼り合せる際、前記レジスト部の少なくとも一部が、前記第1基板と前記第2基板が対向し、かつ、前記キャビティを囲む領域に形成されることを特徴とする配線基板の製造方法。
    A first step of opening a hole in a bonding portion to which a protective film is attached on the surface;
    Filling the conductive paste in the holes of the bonding portion opened in the first step;
    A third step of peeling the protective film;
    A fourth step of bonding a first substrate having a first surface layer wiring disposed on the surface layer, and a second substrate having a second surface layer wiring disposed on the surface layer, through the adhesive portion;
    A fifth step of removing a part of at least one of the first substrate and the second substrate to form a cavity,
    When bonding the first substrate and the second substrate in the fourth step, at least a part of the resist portion is in a region where the first substrate and the second substrate face each other and surrounds the cavity. A manufacturing method of a wiring board characterized by being formed.
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