JP2012023100A - Wiring board equipped with buried component, and method of manufacturing wiring board equipped with buried component - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve productivity in a wiring board equipped with a buried component and a method of manufacturing the same.SOLUTION: A wiring board equipped with a buried component comprises a first platy insulation layer; an electric/electronic component disposed on the first platy insulation layer, having a first surface opposite to the first platy insulation layer and a second surface on the opposite side to the first surface, and provided on the second surface so as to expose an electrically conducting member; a second platy insulation layer provided at a position laminating to the first platy insulation layer, and having an opening portion of an edge separated from the electric/electronic component while corresponding to an area where the electric/electronic component exists; an insulation resin portion provided so as to fill between the first and second platy insulation layers and to fill the edge of the opening portion of the second platy insulation layer and the electric/electronic component; a wiring pattern provided on a surface on the opposite side to the side opposing to the first platy insulation layer of the second platy insulation layer; and a conductive member electrically connecting the wiring pattern and the electrically conducting member on the second surface of the electric/electronic component.

Description

  The present invention relates to an embedded component-equipped wiring board in which components are embedded and a manufacturing method thereof, and more particularly to an embedded component-equipped wiring board suitable for improving the production efficiency and a manufacturing method thereof.

  As a wiring board with a structure that absorbs the thickness of a component, a hole is formed up to a part of the multilayer insulation layer to form a recess in the insulation layer, and the component is positioned within this recess to insulate the component terminal There is a configuration in which the outermost wiring pattern on the layer is electrically connected to a component connection pad (see, for example, JP-A-8-37378). If the concave portion is formed in this way and the component is positioned inside this, while maintaining the advantage that a three-dimensional higher density wiring pattern useful for multi-terminal component mounting can be formed, and after the component mounting, The thickness of the wiring board (circuit board) can be reduced.

  Formation of the recesses in the wiring board as described above can be performed by performing mechanical processing using an end mill or the like, or by performing laser processing. In that case, it is necessary to perform processing for each concave portion to be provided, and the production efficiency is not improved.

  In addition, as a similar concave portion for positioning a component, an insulating layer having no hole and an insulating layer having a hole (through hole) are bonded via a prepreg in which a hole (through hole) is formed. There is also a method of laminating to obtain a recess. In this case, the efficiency of the processing is improved by the formation of the through hole in the insulating layer before lamination, but the point that the controllability of the hole shape cannot be maintained due to the flow of the prepreg during lamination. To cope with this, it is necessary to form a hole that is larger than the size of the component. This is not advantageous in terms of downsizing of the wiring board area and reliability of electrical connection between the component and the wiring board.

JP-A-8-37378

  The present invention has been made in consideration of the above circumstances, and in an embedded component-equipped wiring board in which components are embedded and a manufacturing method thereof, an embedded component-equipped wiring board capable of improving the production efficiency and a manufacturing method thereof The purpose is to provide.

  In order to solve the above problems, an embedded component-equipped wiring board according to an aspect of the present invention is disposed on a first plate-like insulating layer and the first plate-like insulating layer, and the first plate-like insulating plate is provided. The first surface facing the insulating layer and the second surface opposite to the first surface are provided on the second surface such that a member that conducts electricity is exposed. An opening at an edge spaced from the electrical / electronic component corresponding to a region where the electrical / electronic component and the electrical / electronic component are provided at a position where the electrical / electronic component is laminated with respect to the first plate-like insulating layer A second plate-like insulating layer having a portion, and the opening of the second plate-like insulating layer so as to satisfy a space between the first plate-like insulating layer and the second plate-like insulating layer. An insulating resin portion provided so as to satisfy a space between the edge of the portion and the electric / electronic component, and the first plate-like insulating layer of the second plate-like insulating layer. A wiring pattern provided on a surface opposite to the side to be connected, and a conductive member that electrically connects the wiring pattern and the electrically conductive member of the second surface of the electrical / electronic component. It is characterized by doing.

  That is, in this embedded component-equipped wiring board, an opening is provided in the second plate-like insulating layer corresponding to the position (existing region) of the embedded electric / electronic component. And an insulating resin part exists so that the space between the second plate-like insulating layer and the first plate-like insulating layer located on the lower side of the embedded part may be filled. This insulating resin portion also fills the electrical / electronic component inside the opening of the second plate-like insulating layer. Such an insulating resin portion is deformed by a lamination process at the time of manufacture, and although it has a complicated shape, its formation is easy. An electrically conductive member exposed on the second surface of the electric / electronic component (the surface opposite to the surface facing the first plate insulating layer) is formed on the second plate wiring layer. The conductive pattern is electrically connected to the provided wiring pattern. Thereby, electrical connection between the electrical / electronic component and the wiring board is established.

  Therefore, this embedded component-equipped wiring board is a wiring board in which electrical / electronic components are disposed and mounted in a wiring board including a plate-like insulating layer. The manufacture is much more efficient than a wiring board that requires the formation of recesses by mechanical processing, and there is no difficulty in that the controllability of the hole shape cannot be maintained because the prepreg flows during lamination.

  According to another aspect of the present invention, there is provided a method of manufacturing an embedded component-equipped wiring board, the step of forming a peelable material layer on the functional surface of a semiconductor chip component having a terminal pad on the functional surface, and the semiconductor chip component Fixing the surface opposite to the functional surface of the first plate-like insulating layer with an adhesive, and a through-opening at an edge spaced from the semiconductor chip component corresponding to the position of the semiconductor chip component A laminated member in which a prepreg is disposed on the side facing the first plate-like insulating layer and is laminated on the prepreg and the second plate-like insulating layer is arranged, A step of arranging the first insulating plate layer, the first insulating plate layer, the prepreg, and the second insulating plate layer, pressurizing and heating the first insulating plate layer, the first pre insulating plate, and the first pre insulating plate; Fills between the plate-like insulating layer and the second plate-like insulating layer In addition, the first and second plate-like insulating layers are integrated so as to be changed to an insulating resin portion that fills between the edge of the through-opening portion of the second plate-like insulating layer and the semiconductor chip component. A step of peeling off the peelable material layer on the functional surface of the semiconductor chip component viewed through the through-opening portion of the second plate-like insulating layer, and the second plate-like wiring Forming a wiring pattern on a surface of the plate opposite to the side facing the first plate-like wiring layer, the terminal pads provided on the functional surface of the semiconductor chip component, and the second And a step of electrically connecting the wiring pattern provided on the plate-like insulating layer with a bonding wire.

  This manufacturing method is one method for manufacturing the above-described embedded component-equipped wiring board, and particularly when a semiconductor chip component is used as an electric / electronic component. As a feature, when the first plate-like insulating layer, the prepreg, and the second plate-like insulating layer are laminated and integrated by pressurization and heating, the prepreg does not flow and the functional surface of the semiconductor chip component is not contaminated. In addition, a peelable material layer is provided in advance on the functional surface. After the lamination, the peelable material layer is peeled, and then the functional terminal pads and the wiring pattern provided on the second plate-like insulating layer are electrically connected by bonding wires.

  This manufacturing method is much more efficient than a wiring board that requires the formation of recesses by mechanical processing, and the gap in the opening is filled with the prepreg during lamination, so that the prepreg flows and has a hole shape. There is no need to worry about being unable to maintain controllability.

  According to the present invention, in an embedded component-equipped wiring board in which components are embedded and a manufacturing method thereof, the production efficiency can be improved.

Sectional drawing which shows typically the structure of the embedded component-equipped wiring board which concerns on one Embodiment of this invention. Process drawing which shows a part of manufacturing process of the embedded component-equipped wiring board shown in FIG. Process drawing which shows another part of manufacturing process of the embedded component-equipped wiring board shown in FIG. FIG. 9 is a process view schematically showing still another part of the manufacturing process of the embedded component-equipped wiring board shown in FIG. 1. Sectional drawing explaining an example of the state when the semiconductor chip component 41 used is supplied to the wiring board with an embedded component shown in FIG. Sectional drawing which shows typically the structure of the wiring board with an embedded component which concerns on another embodiment of this invention. Sectional drawing which shows typically the structure of the wiring board with an embedded component which concerns on another embodiment of this invention.

  As an embodiment of the present invention, the wiring pattern is a wiring pattern of an outermost wiring layer having no multi-layered wiring structure on a surface facing the surface in contact with the second plate-like insulating layer. it can. According to this, it can be set as a thinner wiring board as a wiring board which absorbed the thickness of components.

  As an embodiment, the third plate-like insulating layer provided on the second plate-like insulating layer so as to cover the wiring pattern and the wiring pattern of the third plate-like insulating layer are located. And a second wiring pattern provided on a surface opposite to the side. According to this, the electric / electronic component including the electrically conductive member exposed on one surface of the embedded electric / electronic component is surrounded by the inside of the wiring board. It can be said to be a normal component built-in wiring board. Also, high density wiring can be realized by multilayering.

  Further, as an embodiment, the electrical / electronic component has a functional surface as the second surface, and the first surface facing the functional surface is an adhesive on the first plate-like insulating layer. The electrically conductive member on the second surface of the electrical / electronic component is a terminal pad of the semiconductor chip component, and the conductive member is the semiconductor chip component of the semiconductor chip component. It is a bonding wire that electrically connects the terminal pad and the wiring pattern, and may further include a resin provided to seal the bonding wire.

  This is a semiconductor chip component provided as an electrical / electronic component. Semiconductor chip components are generally multi-terminal, but according to this aspect, a wiring board having components is provided while maintaining the advantage of being able to form a three-dimensional higher density wiring pattern useful for multi-terminal component mounting. The thickness can be reduced as a (circuit board).

  Further, as an embodiment, further comprising a second wiring pattern including a component connection land provided on a surface of the first plate-like insulating layer on the side where the electrical / electronic component is disposed, The electric / electronic component is a surface-mount type passive element component that is fixed to the land of the second wiring pattern with solder with the first surface side facing the second wiring pattern, The conductive member is a member of a conductive composition that electrically connects the portion appearing on the second surface of the surface of the surface-mounted passive element component and the wiring pattern. be able to.

  This is a surface mount type passive element component provided as an electric / electronic component. In particular, a conductive member that electrically connects a portion appearing on the second surface of the surface of the terminal of the surface-mounted passive element component and the wiring pattern is a conductive composition. Such a conductive composition can be formed by, for example, screen printing, ink jet printing, a dispenser, etc., and does not hinder the improvement of production efficiency.

  Based on the above, embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing a configuration of an embedded component-equipped wiring board according to an embodiment of the present invention. As shown in FIG. 1, this wiring board includes an insulating layer 11 (first plate-like insulating layer), an insulating layer 12 (plate-like insulating layer, insulating resin portion), an insulating layer (plate-like insulating layer) 13, and the like. 14, 15 (13, 14, 15 is the second plate-like insulating layer), wiring layer (wiring pattern) 21, 22, 23, 24, 25, 26 (= 6 layers in total), interlayer Connector 31, 32, 33, 34, 35, semiconductor chip component 41 (electric / electronic component), adhesive layer 42, bonding wire 43 (conductive member), sealing resin 44, solder resist 51, 52 Have

  This wiring board has a configuration intended to make the entire wiring board thin by embedding the semiconductor chip component 41 in the thickness direction of the wiring board. In particular, the embedded semiconductor chip component 41 may have a large number of terminal pads 41a. In this case, the wiring board is required to have a high density wiring pattern for electrical connection with the wiring board side. . Considering this point, this embodiment is a multilayer (that is, three-dimensionally high) that can be electrically connected to the wiring pattern 26 under the outermost wiring pattern 26 to which the semiconductor chip component 41 is electrically connected. This is a configuration in which wiring patterns (wiring layers 25 to 21) can be arranged.

  As will be described later, in this wiring board, it is not necessary to form a recess in the wiring board in order to place the semiconductor chip component 41 in the thickness direction of the wiring board. Also, as will be described later, the idea of controlling the shape of the recess for positioning the semiconductor chip component 41 is not necessary, and the component 41 can be arranged spatially and efficiently.

  The semiconductor chip component 41 embedded in this embodiment has a first surface (back surface) facing the insulating layer 11 and a second surface (functional surface) opposite to the first surface. The insulating layer 11 is disposed via the adhesive layer 42 (and the pattern included in the wiring layer 22). A terminal pad 41a, which is a member that conducts electricity, is exposed on the functional surface.

  The semiconductor chip component 41 is electrically connected from the terminal pad 41a to a connection pad included in the outermost wiring pattern 26 of the wiring board through, for example, a bonding wire 43 of gold (Au). A sealing resin 44 is provided so as to cover the bonding wire 43 and seal the component 41. In general, connection using a bonding wire is an inexpensive aspect compared to flip connection, which is also a technique for electrically connecting semiconductor chips.

  The wiring layers 21 and 26 are wiring layers on both main surfaces (outermost) as wiring boards. A land (not shown) can also be provided thereon so as to mount various components (not shown). Except for the land area and the sealing resin 44 area, solder resists 51 and 52 functioning as protective layers are formed on both main surfaces (thickness is about 20 μm, for example). Since the wiring layer 26 to which the component 41 is directly electrically connected is the outermost wiring layer, the entire wiring board that absorbs the thickness of the component is configured to be thinner.

  The wiring layers 22, 23, 24, and 25 are inner wiring layers, and the insulating layer 11 is disposed between the wiring layer 21 and the wiring layer 22, and the insulating layer 12 is disposed between the wiring layer 22 and the wiring layer 23, respectively. However, the insulating layer 13 is between the wiring layer 23 and the wiring layer 24, the insulating layer 14 is between the wiring layer 24 and the wiring layer 25, and the insulating layer 15 is between the wiring layer 25 and the wiring layer 26. The wiring layers 21 to 26 are spaced apart from each other. Each of the wiring layers 21 to 26 is made of, for example, a metal (copper) foil having a thickness of 18 μm.

  Each of the insulating layers 11 to 15 has a thickness of 100 μm and is a rigid material made of, for example, a glass epoxy resin. The insulating layers 13, 14, and 15 have an opening corresponding to an edge separated from the component 41 in a region corresponding to the embedded component 41, and provide a space for embedding the component 41. In particular, the insulating layer 12 is deformed so as to be filled between the embedded component 41 and the edge of the opening of the insulating layer 13, and there is no space that becomes a void inside. That is, the inside of the opening provided in the insulating layers 13, 14, 15 is filled with the insulating layer 12 while being in close contact with the component 41.

  The wiring layer 21 and the wiring layer 22 can be conducted by an interlayer connector 31 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 11. Similarly, the wiring layer 22 and the wiring layer 23 can be conducted by an interlayer connector 32 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 12. The wiring layer 23 and the wiring layer 24 can be conducted by an interlayer connector 33 that is sandwiched between the surfaces of the patterns and penetrates the insulating layer 13. The wiring layer 24 and the wiring layer 25 can be conducted by an interlayer connector 34 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 14. The wiring layer 25 and the wiring layer 26 can be conducted by an interlayer connector 35 that is sandwiched between the surfaces of these patterns and penetrates the insulating layer 15.

  These interlayer connectors 31 to 35 are derived from conductive bumps formed by screen printing of a conductive composition, and depend on the manufacturing process in the axial direction (up and down in the illustration of FIG. 1). The diameter changes in the direction of stacking. The diameter is, for example, 200 μm on the thick side.

  Next, a manufacturing process of the embedded component-equipped wiring board shown in FIG. 1 will be described with reference to FIGS. 2 to 4 are process diagrams schematically showing a part of the manufacturing process of the embedded component-equipped wiring board shown in FIG. In these figures, the same or equivalent components as those shown in FIG.

  It demonstrates from FIG. FIG. 2 shows a manufacturing process of a portion centering on the insulating layer 11 in each configuration shown in FIG. First, as shown in FIG. 2 (a), a paste-like conductive composition to be an interlayer connection 31 is formed on a metal foil (electrolytic copper foil) 22A having a thickness of 18 μm, for example, by screen printing. It is formed in a bump shape (bottom diameter, for example, 200 μm, height, for example, 160 μm). This conductive composition is obtained by dispersing fine metal particles such as silver, gold and copper or fine carbon particles in a paste-like resin. Although printed on the lower surface of the metal foil 22A for convenience of explanation, the upper surface may be used. After the interlayer connector 31 is printed, it is dried and cured.

  Next, as shown in FIG. 2B, an FR-4 prepreg 11A having a thickness of, for example, 100 μm is laminated on the metal foil 22A to penetrate the interlayer connector 31, so that the head is exposed. To do. At the time of exposure or thereafter, the tip thereof may be crushed by plastic deformation (shown by a broken line. In any case, the shape of the interlayer connector 31 has an axis that coincides with the stacking direction, and the diameter changes in the axial direction. .) Subsequently, as shown in FIG. 2 (c), a metal foil (electrolytic copper foil) 21A is laminated on the prepreg 11A, and is pressed and heated to integrate the whole. At this time, the metal foil 21A is in electrical continuity with the interlayer connector 31, and the prepreg 11A is completely cured to become the insulating layer 11.

  Next, as shown in FIG. 2D, the metal foils 21A and 22A are patterned by, for example, well-known photolithography, and processed into wiring patterns 21 and 22, respectively. As for the wiring pattern 22, as shown in the figure, a solid pattern may be formed corresponding to the position of the component 41 to be arranged on the insulating layer 11. Such a solid pattern plays a role of mechanical reinforcement for the component 41.

  Next, as shown in FIG. 2E, the semiconductor chip component 41 is placed at a predetermined position on the insulating layer 11 with, for example, a mounter through the adhesive layer 42, and then the adhesive layer 42 is cured and fixed. To do. The mounted semiconductor chip component 41 is accompanied by a peelable material layer 41b on its functional surface as shown in the figure. The peelable material layer 41b is peeled off later (= when the terminal pad 41a is subjected to the wire bonding process), and prevents the surface of the terminal pad 41a from being contaminated until then. .

  Further, the semiconductor chip component 41 to be placed is provided with an adhesive layer before curing to be the adhesive layer 42 on the back surface in advance. As such a layer, for example, a layer of a thermosetting resin (for example, epoxy resin) can be given. This is heated and hardened after placing the semiconductor chip component 41, and the semiconductor chip component 41 is fixed on the insulating layer 11 (the wiring pattern 22 thereof). Regarding the semiconductor chip component 41 placed here, an example of the state when it is supplied will be described later (FIG. 5).

  As described above, as shown in FIG. 2E, the laminated member 1 in a state where the back surface of the semiconductor chip component 41 is fixed on the insulating layer 11 (the wiring pattern 22 thereof) with the adhesive layer 42 is obtained. The subsequent steps using the laminated member 1 will be described with reference to FIG.

  Next, a description will be given with reference to FIG. FIG. 3 shows a manufacturing process of a portion centering on the insulating layers 13, 14, and 15 in each configuration shown in FIG. First, lamination as shown in FIG. 3A is performed to integrate the two members.

  The member shown on the upper side of FIG. 3A has substantially the same configuration as that shown in FIG. 2D (however, the metal foil 26A is not patterned). Further, the member shown on the lower side of FIG. 3A is a plate-like member shown on the upper side of FIG. 3A instead of the metal foil 22 used in the steps shown in FIGS. 2A and 2B. And a member having the same configuration (having insulating layer 13, metal foil 23A, wiring pattern 24, and interlayer connector 33), and obtained through the same steps as FIGS. 2 (a) and 2 (b) ( As a process corresponding to FIG. 2A, an interlayer connector 34 is formed on the wiring pattern 24).

  With this integration, the wiring pattern 25 is brought into electrical conduction with the interlayer connector 34, and the prepreg 14 </ b> A is completely cured to become the insulating layer 14. After the integration, as shown in FIG. 3B, the metal foils 23A and 26A included in the obtained plate-like member are predeterminedly patterned using well-known photolithography to form wiring layers 23 and 26. . As for the wiring layer 26, it is preferable to apply a gold bonding technique to form a Ni / Au plating layer in a partial region in order to perform wire bonding connection with the component 41.

  Next, as shown in FIG. 3C, an interlayer connector 32 is formed on a predetermined position of the wiring pattern 23, and a prepreg 12A is further laminated. This step can be associated as a step using the plate-like member shown in FIG. 3B in place of the metal foil 22 used in the steps shown in FIGS. An interlayer connector 32 is formed on the wiring pattern 23 as a process corresponding to FIG.

  After the prepreg 12A is laminated, as shown by a thick line in FIG. 3C, a through opening having a circular cross section, for example, is formed corresponding to the position of the embedded component 41 (removal region 410). The plate-like member after the through opening is formed is subjected to the stacking step shown in FIG. Note that the process shown in FIG. 3 can be a procedure in which through-holes are separately formed in the plate-like member shown in FIG. 3B and the prepreg 12A, and then stacked. is there.

  Next, a description will be given with reference to FIG. FIG. 4 is a diagram (FIG. 4A) showing a positional relationship in which the laminated members 1 and the like obtained above are laminated and a diagram (FIG. 4B) showing the configuration after the lamination. The upper laminated member 2 in FIG. 4A is obtained by the process described in FIG.

  Laminate members 1 and 2 are arranged in the arrangement as shown in FIG. 4A, and are pressed and heated by a press. Thereby, the prepreg 12A is completely cured, and the whole is laminated and integrated. At this time, due to the fluidity of the prepreg 12 </ b> A obtained by heating, the prepreg 12 </ b> A is deformed and in close contact with the space around the semiconductor chip component 41, so that no gap is generated. That is, the idea of shape control of the recess for positioning the semiconductor chip component 41 is unnecessary, and the component 41 can be arranged spatially and efficiently. In addition, the wiring layer 22 is electrically connected to the interlayer connector 32 by stacking and integration.

  After stacking and integration, as shown in FIG. 4B, the peelable material layer 41b attached on the functional surface of the semiconductor chip component 41 is peeled off. After that, although not shown, the bonding wires 43 are connected and attached, the sealing resin 44 is subsequently formed, and the solder resists 51 and 52 are further formed (both see FIG. 1). A bonding tool can be used to connect and attach the bonding wires 43, and a transfer mold can be used to form the sealing resin 44, for example. Potting may be used instead of the transfer mold.

  In this manufacturing process, even if the prepreg 12A flows when integrated in the laminating process shown in FIG. 4 (a), the functional surface of the semiconductor chip component 41 is preliminarily peelable so that the functional surface is not contaminated. The point that the layer 41b is provided is a great advantage. Such contamination is likely to occur when the height at which the semiconductor chip component 41 is located is lower than the upper surface of the insulating layer 15 (usually often in design). Thus, from the advantage of preventing contamination, the wire bonding process after peeling of the peelable material layer 41b can be performed with high reliability.

  The manufacturing process described above with reference to FIGS. 2 to 4 may be modified as follows. First, the formation time of the wiring layer 26 is not limited to the stage shown in FIG. 3B, but may be performed after the stage shown in FIG. In this way, there is no need to worry that the connection pads for the semiconductor chip component 41 included in the wiring layer 26 may be contaminated by the fluidized prepreg 12A (normally, the position of the semiconductor chip component 41). Since the height of the contact pad is designed to be lower than the upper surface of the insulating layer 15, the connection pad is less likely to be contaminated.

  The wiring layer 21 can be formed at the stage shown in FIG. 4B in addition to the stage shown in FIG. Moreover, although it is a modified example including a difference in configuration, the plate member shown in FIG. 3B is not limited to the four-layer plate shown in the drawing, depending on the required three-dimensional density of the wiring pattern. It can be set as the board member which has a 2 layer board (double-sided board | substrate) and 3 or more wiring layers.

  Next, the semiconductor chip component 41 will be supplementarily described with reference to FIG. FIG. 5 is a cross-sectional view illustrating an example of a state when the semiconductor chip component 41 used is supplied to the embedded component-equipped wiring board shown in FIG. In FIG. 5, the same reference numerals are given to the same or equivalent components as those shown in the already described drawings.

  The semiconductor chip component 41 can be supplied in a state of being diced by a dicing wall 200 on a carrier tape (dicing tape) 100 as shown in the figure. The dicing in this state is performed to the intermediate depth of the carrier tape 100 using a dicing blade with respect to the wafer. According to such a state, a slight tension is applied to the carrier tape 100 to eliminate the adhesive state between the carrier tape 100 and the semiconductor chip component 41, and the individual pick-up is easily performed by the mounter as shown in FIG. It can be used for other processes.

  The process for obtaining the state shown in FIG. 5 is, for example, as follows. First, a peelable material layer 41b is attached to one surface of a wafer that has not been diced on the functional surface side. Further, an adhesive layer 42A before curing is formed on one side on the back side of the wafer. As the peelable material layer 41b, for example, the same material as the carrier tape 100 can be used (the side that adheres to the functional surface side is affixed). The adhesive layer 42A is, for example, a film-like thermosetting resin (for example, epoxy resin) layer.

  The wafer with the peelable material layer 41b on the functional side and the adhesive layer 42A on the back side is then placed on the carrier tape 100 and fixed with the adhesiveness of the carrier tape 100. . Then, a dicing blade is used to cut the peelable material layer 41b, the semiconductor chip component 41, and the adhesive layer 42A from the side opposite to the carrier tape 100, and further dicing so as to cut to the middle thickness of the carrier tape 100. Do. As described above, a state as shown in FIG. 5 is obtained.

  Next, another embodiment will be described with reference to FIG. FIG. 6 is a cross-sectional view schematically showing a configuration of an embedded component-equipped wiring board according to another embodiment. In FIG. 6, the same reference numerals are given to the same or equivalent components as those shown in the already described drawings. The description of the portion is omitted unless there is a matter to be added.

  In this embodiment, a surface-mounted passive element component 45 (for example, a chip resistor) is embedded instead of the semiconductor chip component 41 embedded in the embodiment shown in FIG. The component 45 is a terminal 45a (a member that conducts electricity) in a circumferential shape including both ends in the longitudinal direction. The component 45 is electrically and mechanically connected by solder 46 to a land included in the wiring pattern 22 around the side of the terminal 45a facing the insulating layer 11. The component 45 is electrically connected to the wiring layer 26 on the upper surface by a conductive composition pattern 61 which is a conductive member on the surface of the terminal 45a opposite to the side facing the insulating layer 11. Yes.

  The manufacturing process of the wiring board of this embodiment is as follows. For mounting the surface mount type passive element component 45 on the insulating plate 11, a normal surface mount technology may be applied with reference to FIG. Corresponding to FIG. 4B, providing a layer similar to the peelable material layer 41a in advance is not as necessary as the semiconductor chip component 41 because bonding connection is not performed.

  The conductive composition pattern 61 can be formed by, for example, screen printing, ink jet printing, dispenser, or the like. According to these, it does not become a hindrance in improving production efficiency. The wiring board is designed to be thinned by embedding the component 45 in the thickness direction of the wiring board, so that the electrical connection between the component 45 and the wiring layer 22 is a dummy. It is good also as a connection. That is, the connection land for the component 45 included in the wiring layer 22 may function only as a land for mechanical connection with solder and may be a dummy without an electrical connection destination.

  Next, still another embodiment will be described with reference to FIG. FIG. 7 is a cross-sectional view schematically showing a configuration of an embedded component-equipped wiring board according to still another embodiment. In FIG. 7, the same reference numerals are given to the same or equivalent components as those shown in the already described drawings. The description of the portion is omitted unless there is a matter to be added.

  In this embodiment, a build-up portion 90 is added to the embodiment shown in FIG. The build-up portion 90 includes insulating layers 16 and 17 (16 and 17 are third plate-like insulating layers), wiring layers 27 and 28, and interlayer connectors 36 and 37. The solder resist 52 is provided on the outermost surface. According to this embodiment, the component 41 including the electrically conductive member exposed on one surface of the embedded component 41 is surrounded by the wiring board. It can be said to be a normal wiring board with built-in components. Further, high density wiring can be realized by further multilayering.

  The manufacturing process of the wiring board of this embodiment is as follows. As the build-up portion 90, a member having the same configuration as the member shown on the lower side of FIG. 3A is prepared (the arrangement on the small diameter side and the large diameter side of the interlayer connector 37 is the lower side of FIG. 3A). Is the opposite of that shown in, but can be used in both cases as well). Then, the build-up portion 90 is laminated and integrated on the laminated body including the component 41 by applying pressure and heating. Thereafter, solder resists 51 and 52 are formed.

  DESCRIPTION OF SYMBOLS 1 ... Laminated member, 2 ... Laminated member, 11 ... Insulating layer (plate-like insulating layer), 11A ... Pre-preg, 12 ... Insulating layer (insulating resin part), 12A ... Pre-preg, 13 ... Insulating layer (plate-like insulating layer), DESCRIPTION OF SYMBOLS 14 ... Insulating layer (plate-like insulating layer), 14A ... Prepreg, 15 ... Insulating layer (plate-like insulating layer), 16 ... Insulating layer (plate-like insulating layer), 17 ... Insulating layer (plate-like insulating layer), 21 ... Wiring layer (wiring pattern), 21A ... metal foil (copper foil), 22 ... wiring layer (wiring pattern), 22A ... metal foil (copper foil), 23 ... wiring layer (wiring pattern), 23A ... metal foil (copper foil) ), 24 ... wiring layer (wiring pattern), 25 ... wiring layer (wiring pattern), 26 ... wiring layer (wiring pattern), 26A ... metal foil (copper foil), 27 ... wiring layer (wiring pattern), 28 ... wiring Layer (wiring pattern), 31, 32, 33, 34, 35, 36, 37 ... interlayer Continuum (conductive bump by conductive composition printing), 41... Semiconductor chip component (electric / electronic component), 41 a... Terminal pad, 41 b .. peelable material layer, 42... Adhesive layer, 42 A. Before curing), 43... Bonding wire (conductive member), 44... Sealing resin, 45... Surface mount type passive element component (electric / electronic component), 45 a. ... conductive composition pattern (conductive member), 90 ... build-up portion, 100 ... carrier tape (dicing tape), 200 ... dicing wall, 410 ... removal region.

Claims (6)

A first plate-like insulating layer;
A first surface disposed on the first plate-like insulating layer and facing the first plate-like insulating layer; and a second surface opposite to the first surface; An electrical / electronic component provided on the second surface such that an electrically conducting member is exposed;
A second opening provided at a position to be laminated with respect to the first plate-like insulating layer and having an opening at an edge separated from the electric / electronic component corresponding to a region where the electric / electronic component exists. A plate-like insulating layer;
The space between the first plate-like insulating layer and the second plate-like insulating layer is filled, and between the edge of the opening of the second plate-like insulating layer and the electric / electronic component. Insulating resin portion provided so as to satisfy
A wiring pattern provided on a surface of the second plate insulating layer opposite to the side facing the first plate insulating layer;
An embedded component-equipped wiring board, comprising: a conductive member that electrically connects the wiring pattern and the electrically conductive member on the second surface of the electrical / electronic component.   2. The embedded part according to claim 1, wherein the wiring pattern is a wiring pattern of an outermost wiring layer having no multilayered wiring structure on a surface facing the surface in contact with the second plate-like insulating layer. Inherent wiring board. A third plate-like insulating layer provided on the second plate-like insulating layer so as to cover the wiring pattern;
2. The embedded component-equipped wiring according to claim 1, further comprising: a second wiring pattern provided on a surface of the third plate-like insulating layer opposite to the side on which the wiring pattern is located. Board. The electric / electronic component has a functional surface as the second surface, and the first surface opposite to the functional surface is fixed on the first plate-like insulating layer with an adhesive. Parts,
The electrically conductive member of the second surface of the electrical / electronic component is a terminal pad of the semiconductor chip component;
The conductive member is a bonding wire that electrically connects the terminal pad of the semiconductor chip component and the wiring pattern;
The embedded component-equipped wiring board according to claim 1, further comprising a resin provided to seal the bonding wire. A second wiring pattern including a land for connecting components provided on a surface of the first plate-like insulating layer on which the electrical / electronic components are disposed;
The electric / electronic component is a surface-mount type passive element component that is fixed to the land of the second wiring pattern with solder with the first surface side facing the second wiring pattern,
The conductive member is a member of a conductive composition that electrically connects the portion appearing on the second surface of the surface of the surface-mounted passive element component and the wiring pattern. The embedded component-equipped wiring board according to claim 1. Forming a peelable material layer on the functional surface of the semiconductor chip component having terminal pads on the functional surface;
Fixing the surface of the semiconductor chip component opposite to the functional surface on the first plate-like insulating layer with an adhesive;
Corresponding to the position of the semiconductor chip component, a through-opening portion at an edge spaced from the semiconductor chip component is formed, and a prepreg is disposed on the side facing the first plate-like insulating layer, and further on the prepreg Laminating a laminated member in which a second plate-like insulating layer is arranged in a laminated manner with respect to the first plate-like insulating layer;
The first plate-like insulating layer, the prepreg, and the second plate-like insulating layer are pressurized and heated, and the prepreg is moved between the first plate-like insulating layer and the second plate-like insulating layer. The first and second plate-like shapes are changed to an insulating resin portion that fills between the edge of the through-opening portion of the second plate-like insulating layer and the semiconductor chip component. Integrating the insulating layer;
Peeling off the peelable material layer on the functional surface of the semiconductor chip component looking into the through opening of the second plate-like insulating layer;
Forming a wiring pattern on a surface of the second plate-like wiring board on the side opposite to the side facing the first plate-like wiring layer;
Electrically connecting the terminal pad provided on the functional surface of the semiconductor chip component and the wiring pattern provided on the second plate-like insulating layer with a bonding wire. A method of manufacturing an embedded component-equipped wiring board.

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