JP2009239224A - Multilayer wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer wiring board that is sufficiently enhanced in substrate strength and reduces a region where mismatching of a coefficient of thermal expansion is caused. <P>SOLUTION: A plurality of terminal pads 27 for mounting an IC chip 31 are provided on a principal surface 12 of a coreless wiring board 10, and a plurality of pads 41 for a BGA for electric connection with an external substrate are provided on the reverse surface 13. The coreless wiring board 10 has solder resist 42 formed covering the reverse surface 13, and a resin-made reinforcing plate 50 is fixed to the solder resist 42 in surface contact across an adhesive layer 51. The reinforcing plate 50 has an openings 52 formed at positions corresponding to the pads 41 for the BGA. The openings 52 decrease in diameter from the non-adhesion surface side to the adhesion surface side of the reinforcing plate 50. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multilayer wiring board having a structure in which a core board is not provided and conductor layers and insulating layers are alternately laminated to form a multilayer structure.

  In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally employed in which a package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the package is mounted on a motherboard.

  As an IC chip mounting wiring board constituting this type of package, a multilayer wiring board in which build-up layers are formed on the front surface and the back surface of a core substrate has been put into practical use. In this multilayer wiring board, for example, a resin substrate (a glass epoxy substrate or the like) in which a reinforcing fiber is impregnated with a resin is used as the core substrate. Then, by utilizing the rigidity of the core substrate, an interlayer insulating layer and a conductor layer are alternately stacked on the front surface and the back surface of the core substrate to form a buildup layer. That is, in this multilayer wiring board, the core board plays a role of reinforcement and is formed much thicker than the build-up layer. In addition, wiring (specifically, a through-hole conductor or the like) is formed through the core substrate for conduction between buildup layers formed on the front surface and the back surface.

  By the way, in recent years, with the increase in the speed of semiconductor integrated circuit elements, the signal frequency used has become a high frequency band. In this case, the wiring penetrating the core substrate contributes as a large inductance, leading to transmission loss of high-frequency signals and circuit malfunction, which hinders speeding up. In order to solve this problem, a coreless wiring board having no core board has been proposed as an IC chip mounting wiring board (see, for example, Patent Document 1). In this coreless wiring board, since the entire wiring length is shortened by omitting a relatively thick core board, the transmission loss of high-frequency signals is reduced, and the semiconductor integrated circuit element can be operated at high speed.

Since the coreless wiring substrate is manufactured by omitting the core substrate, the strength cannot be sufficiently ensured. For this reason, the strength of the coreless wiring board is secured by joining and reinforcing the frame on the element mounting surface on which the IC chip is mounted. The frame is provided on the outer edge of the substrate so as to surround the IC chip. Moreover, in patent document 1, the metal plate which performed the insulation process is adhere | attached and fixed to the back surface side opposite to the element mounting surface, and the coreless wiring substrate is sandwiched between the frame and the metal plate, thereby A technique for ensuring strength and preventing warping of a wiring board is disclosed. In this coreless wiring substrate, a plurality of through holes for exposing the external connection terminal pads are formed in the reinforcing metal plate provided on the back side.
Japanese Patent No. 3664720

  When the package form of the coreless wiring board is, for example, a ball grid array (BGA), a BGA pad 81 is provided on the back surface of the coreless wiring board 80 as shown in FIG. Solder bumps 82 are provided. Then, a metal reinforcing plate 85 is fixed to the back surface of the coreless wiring substrate 80 in a surface contact state via an adhesive layer 84. In this case, it is necessary to form a through hole 86 having a larger diameter than the solder bump 82 in the reinforcing plate 85. In the coreless wiring substrate 80, since a plurality of through holes 87 having a large diameter are formed in the reinforcing plate 85, a sufficient bonding area of the reinforcing plate 85 cannot be secured, and the rigidity of the wiring substrate 80 is insufficient. End up. Further, in the back surface of the coreless wiring board 80, the location where the through hole 87 of the reinforcing plate 85 is formed has a problem that the reliability of the wiring board 80 is lowered because of a mismatch in coefficient of thermal expansion (CTE). End up.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a coreless wiring board capable of increasing the bonding area of the reinforcing plate and reducing the region where the thermal expansion coefficient mismatch occurs. There is to do.

  A means (means 1) for solving the above problems is a laminated structure in which a conductor layer and an interlayer insulating layer are alternately laminated to form a multilayer structure without having a core substrate, and a semiconductor is formed on the main surface. A plurality of front surface side connection terminals for mounting integrated circuit elements are provided, and a plurality of back surface side connection terminals for electrical connection with an external substrate are provided on the back surface opposite to the main surface. A multilayer wiring board comprising a plurality of reinforcing plate openings at positions corresponding to the plurality of back surface side connection terminals, the reinforcing plate being fixed in surface contact with the back surface, and the reinforcing plate There is a multilayer wiring board characterized in that the diameter of the opening of the reinforcing plate becomes smaller from the non-adhesive surface side to the adhesive surface side.

  Therefore, according to the multilayer wiring board of the means 1, a plurality of back surface side connection terminals for electrical connection with the external substrate are provided on the back surface, and reinforcement is provided at positions corresponding to the respective back surface side connection terminals. A reinforcing plate having a plate opening is fixed in a surface contact state. The diameter of the reinforcing plate opening in the reinforcing plate decreases as it goes from the non-adhesive surface side to the adhesive surface side. In this way, it is possible to secure a sufficient adhesion area of the reinforcing plate to the back surface of the substrate, and the rigidity of the multilayer wiring board is improved. Further, by increasing the reinforcement area by the reinforcing plate on the back surface of the multilayer wiring board, it is possible to reduce the region where the thermal expansion coefficient (CTE) mismatch occurs, and to improve the reliability of the multilayer wiring board.

  It is preferable that the minimum diameter of the reinforcing plate opening is set to be smaller than the diameter of the back-side connection terminal. In this case, for example, when connecting the connection pin on the external substrate side and the back surface side connection terminal, the side wall of the reinforcing plate opening serves as a guide, and the connection pin can be reliably guided to the back surface side connection terminal. Further, for example, when the solder ball is joined onto the back surface side connection terminal, the side wall of the reinforcing plate opening serves as a guide so that the solder ball can be reliably mounted on the back surface side connection terminal.

  A solder ball is bonded onto the back side connection terminal, the maximum diameter of the reinforcing plate opening is larger than the diameter of the solder ball, and the minimum diameter of the reinforcing plate opening is the diameter of the solder ball. It is preferable that it is set to be smaller. If it does in this way, while being able to join a solder ball reliably on a back surface side connection terminal via a reinforcement board opening part of a reinforcement board, the adhesion area of a reinforcement board can fully be secured.

  Although the material of the said reinforcement board is not limited, For example, it is preferable to consist of nonmetallic materials. Since the reinforcing plate made of a non-metallic material is excellent in workability compared to that made of a metallic material, the reinforcing plate opening can be easily formed, and the material cost can be reduced.

  The reinforcing plate made of non-metallic material is preferably made of synthetic resin as a main material. Specifically, when a solder bump is provided on the back surface side connection terminal on the back surface of the multilayer wiring board, a solder resist is formed so as to cover the back surface. The solder resist is formed of a resin material having excellent heat resistance. Therefore, if a synthetic resin reinforcing plate is used, it can be securely bonded and fixed to a solder resist that is a resin material.

  In addition, the multilayer wiring board having no core of the present invention refers to “a multilayer wiring board mainly composed mainly of the same interlayer insulating layer” or “each conductor layer only by vias whose diameter is expanded in the same direction”. The connected multilayer wiring board can be mentioned.

  The interlayer insulating layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the material for forming the interlayer insulating layer include thermosetting resins such as epoxy resins, phenol resins, urethane resins, silicone resins, and polyimide resins, and thermoplastic resins such as polycarbonate resins, acrylic resins, polyacetal resins, and polypropylene resins. Etc. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

  The conductor layer is patterned on the interlayer insulating layer by a known method such as a subtractive method, a semi-additive method, or a full additive method. Examples of the metal material used for forming the conductor layer include copper, copper alloy, nickel, nickel alloy, tin, tin alloy and the like.

  The metal forming the solder ball may be appropriately selected according to the material of the connection terminal of the electronic component to be mounted, etc., but Pb-Sn solder such as 90Pb-10Sn, 95Pb-5Sn, 40Pb-60Sn Examples of the solder include Sn—Sb solder, Sn—Ag solder, Sn—Ag—Cu solder, Au—Ge solder, Au—Sn solder.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view showing a schematic configuration of a coreless wiring board (multilayer wiring board) according to the present embodiment.

  As shown in FIG. 1, the coreless wiring substrate 10 of the present embodiment does not have a core substrate, and includes four resin insulating layers (interlayer insulating layers) 21, 22, 23, 24 made of epoxy resin and copper The laminated structure is formed by alternately laminating the conductor layers 26 made of. The resin insulation layers 21 to 24 are interlayer insulation layers made of the same thickness and material, and are formed using a sheet-like buildup material made of an epoxy resin.

  On the main surface 12 of the coreless wiring substrate 10 (on the surface of the fourth resin insulating layer 24), terminal pads 27 (surface side connection terminals) are arranged in an array. Further, the surface of the resin insulating layer 24 is almost entirely covered with the solder resist 28. The solder resist 28 has openings 29 through which the terminal pads 27 are exposed. A plurality of solder bumps 30 are disposed on the surface of the terminal pad 27. Each solder bump 30 is electrically connected to a surface connection terminal 32 of an IC chip 31 (semiconductor integrated circuit element) having a rectangular flat plate shape. The area where each terminal pad 27 and each solder bump 30 is formed is an IC chip mounting area 33 in which an IC chip 31 can be mounted.

  On the back surface 13 of the coreless wiring substrate 10 (on the lower surface of the first resin insulating layer 21), BGA (ball grid array) pads 41 as back surface side connection terminals are arranged in an array. Further, the lower surface of the resin insulating layer 21 is almost entirely covered with a solder resist 42. In the solder resist 42, an opening 45 (solder resist opening) for exposing the BGA pad 41 is formed at a position corresponding to the BGA pad 41. Furthermore, via holes 46 and via conductors 47 are provided in the resin insulating layers 21, 22, 23, and 24, respectively. Each via hole 46 has an inverted frustoconical shape, and is formed by drilling each resin insulating layer 21 to 24 using a YAG laser or a carbon dioxide gas laser. Each via conductor 47 is a conductor whose diameter is expanded in the same direction (upward in the drawing), and electrically connects each conductor layer 26, terminal pad 27, and BGA pad 41.

  In the coreless wiring substrate 10 of the present embodiment, the reinforcing plate 50 is bonded and fixed to the solder resist 42 in a surface contact state via the adhesive layer 51. The adhesive layer 51 is a cured product of a thermosetting resin excellent in heat resistance, and is formed, for example, by curing a film-like adhesive sheet made of an epoxy resin. In the adhesive layer 51, a plurality of openings 53 are formed at positions corresponding to the plurality of BGA pads 41.

  As the reinforcing plate 50, a non-metallic plate material having a thickness of about 0.5 mm, for example, a glass epoxy substrate made of epoxy resin and glass fiber is used. In the reinforcing plate 50, a plurality of openings 52 (reinforcing plate openings) are formed at positions corresponding to the plurality of BGA pads 41.

  In the present embodiment, the plurality of BGA pads 41 are formed so as to have a circular shape in plan view, and the openings 45, 52, 53 formed in the solder resist 42, the reinforcing plate 50, and the adhesive layer 51 are also included. The shape in plan view is circular. Further, solder bumps 55 (solder balls) are joined to the respective BGA pads 41 through the openings 45, 52 and 53. Each BGA pad 41 is electrically connected to a mother board (external board) (not shown) via solder bumps 55.

  As shown in FIG. 2, in the coreless wiring substrate 10 of the present embodiment, the opening 52 of the reinforcing plate 50 has a truncated cone shape, from the non-adhesive surface side (the lower surface side in FIG. 2) of the reinforcing plate 50. The diameter of the opening 52 becomes smaller toward the bonding surface side (upper surface side in FIG. 2). The minimum diameter D1 (upper diameter) of the opening 52 is set to be smaller than the diameter D2 of the BGA pad 41. Further, the maximum diameter D3 of the opening 52 is set to be larger than the diameter D4 of the solder bump 55, and the minimum diameter D1 of the opening 52 is set to be smaller than the diameter D4 of the solder bump 55. Further, the diameter D5 of the opening 53 of the adhesive layer 51 is larger than the minimum diameter D1 of the opening 52 and the diameter of the opening 45 of the solder resist 42, and the adhesive layer 51 is made of the reinforcing plate 50 or the solder resist. 42 so that it does not protrude inside the openings 45 and 52 of 42.

  The coreless wiring substrate 10 having the above configuration is manufactured, for example, by the following procedure.

  In the present embodiment, a support substrate (such as a glass epoxy substrate) having sufficient strength is prepared, and the resin insulating layers 21 to 24 and the conductor layer 26 of the coreless wiring substrate 10 are built up on the support substrate. The method is adopted. 3-13 is explanatory drawing which shows the manufacturing method, and has shown the resin insulation layers 21-24, the conductor layer 26, etc. which are formed in the upper surface side of a support substrate. Although not shown, the resin insulating layers 21 to 24 and the conductor layer 26 are similarly formed on the lower surface side of the support substrate.

  More specifically, as shown in FIG. 3, a base resin insulating layer 61 is formed on a support substrate 60 by pasting a sheet-like insulating resin base material made of epoxy resin in a semi-cured state. Then, as shown in FIG. 4, a laminated metal sheet body 62 is disposed on the upper surface of the base resin insulating layer 61. Here, by arranging the laminated metal sheet body 62 on the base resin insulating layer 61 in a semi-cured state, the adhesiveness is such that the laminated metal sheet body 62 is not peeled off from the base resin insulating layer 61 in the subsequent manufacturing process. Secured. The laminated metal sheet body 62 is formed by closely attaching two copper foils 62a and 62b in a peelable state. Specifically, the laminated metal sheet body 62 is formed by laminating the copper foils 62a and 62b through metal plating (for example, chromium plating).

  After that, as shown in FIG. 5, the sheet-like insulating resin base material 63 is disposed so as to wrap the laminated metal sheet body 62, and is heated under pressure using a vacuum pressure hot press machine (not shown). As a result, the insulating resin base material 63 is cured to form the first resin insulating layer 21. Here, the resin insulating layer 21 is in close contact with the laminated metal sheet body 62, and in close contact with the base resin insulating layer 61 in the peripheral region of the laminated metal sheet body 62, thereby sealing the laminated metal sheet body 62.

  Then, as shown in FIG. 6, laser processing is performed to form via holes 46 at predetermined positions of the resin insulating layer 21, and then desmear processing for removing smears in the via holes 46 is performed. Thereafter, electroless copper plating and electrolytic copper plating are performed according to a conventionally known method, thereby forming the via conductor 47 in each via hole 46 and the conductor layer 26 on the resin insulating layer 21. Further, the conductor layer 26 is patterned on the resin insulating layer 21 by performing etching by a conventionally known method (for example, a semi-additive method) (see FIG. 7).

  The second to fourth resin insulation layers 22 to 23 and the conductor layer 26 are also formed by the same method as the first resin insulation layer 21 and the conductor layer 26 described above, and build on the resin insulation layer 21. I will go up. Then, a solder resist 28 is formed by applying and curing a photosensitive epoxy resin on the resin insulating layer 24 on which the terminal pads 27 are formed. Next, exposure and development are performed with a predetermined mask placed, and the opening 29 is patterned in the solder resist 28. Through the above manufacturing process, a laminated body 70 in which the laminated metal sheet body 62, the resin insulating layers 21 to 24, and the conductor layer 26 are laminated on the support substrate 60 is formed (see FIG. 8). In this laminated body 70, the region located on the laminated metal sheet body 62 is the wiring laminated portion 20 (laminated structure) that should become the coreless wiring substrate 10.

  The laminated body 70 is cut by a dicing apparatus (not shown), and the peripheral area of the wiring laminated portion 20 in the laminated body 70 is removed. At this time, as shown in FIG. 8, the base resin insulating layer 61 and the support substrate 60 below the wiring laminated portion 20 are cut at the boundary between the wiring laminated portion 20 and the peripheral portion 71. By this cutting, the outer edge portion of the laminated metal sheet body 62 sealed with the resin insulating layer 21 is exposed. That is, due to the removal of the peripheral portion 71, the adhesion portion between the base resin insulating layer 61 and the resin insulating layer 21 is lost. As a result, the wiring laminated portion 20 and the support substrate 60 are connected via the laminated metal sheet body 62 only.

  Here, as shown in FIG. 9, the wiring laminated portion 20 is separated from the support substrate 60 by peeling at the interface between the two copper foils 62 a and 62 b in the laminated metal sheet body 62. Then, as shown in FIG. 10, the copper foil 62 a on the back surface 13 (lower surface) of the wiring laminated portion 20 (resin insulating layer 21) is patterned by etching to form a BGA pad 41. After that, as shown in FIG. 11, by applying and curing a photosensitive epoxy resin on the resin insulating layer 21 on which the BGA pads 41 are formed, a solder resist is formed so as to cover the back surface 13 of the wiring laminated portion 20. 42 is formed. Next, exposure and development are performed with a predetermined mask disposed, and the opening 45 is patterned in the solder resist 42.

  Thus, after preparing the wiring laminated part 20 which laminated | stacked the conductor layer 26 and the resin insulating layers 21-24 alternately, as shown in FIG. 12, it has the some opening part 52 and is not in the one side. A reinforcing plate 50 having a cured adhesive layer 51 is prepared. Here, the opening 52 of the reinforcing plate 50 is formed by, for example, drilling using a conventionally known drilling device. Moreover, the opening part 53 of the adhesive bond layer 51 is formed by punching using the conventionally well-known punching die with respect to a film-like adhesive sheet, for example. The opening 53 of the adhesive layer 51 is formed to be larger than the diameter of the opening 52 of the reinforcing plate 50.

  Then, as shown in FIG. 13, the reinforcing plate 50 is fixed to the solder resist 42 in a surface-bonded state via the adhesive layer 51, and heated at a predetermined temperature (for example, 150 ° C.) to be in an uncured state. The adhesive layer 51 is cured.

  Then, solder bumps 30 are formed on the plurality of terminal pads 27 formed on the main surface 12 side of the wiring laminated portion 20. Specifically, after solder balls are arranged on each terminal pad 27 using a solder ball mounting device (not shown), the solder balls are heated to a predetermined temperature and reflowed, whereby solder bumps are formed on each terminal pad 27. 30 is formed. Similarly, solder bumps 55 are also formed on the plurality of BGA pads 41 formed on the back surface 13 side of the wiring laminated portion 20. Thereby, the coreless wiring substrate 10 shown in FIG. 1 is obtained.

  Therefore, according to the present embodiment, the following effects can be obtained.

  (1) In the coreless wiring substrate 10 of the present embodiment, the reinforcing plate 50 having the openings 52 at positions corresponding to the plurality of BGA pads 41 is fixed in a surface contact state. The opening 52 in the reinforcing plate 50 has a diameter that decreases from the non-bonding surface side to the bonding surface side. In this way, the adhesion area of the reinforcing plate 50 to the back surface of the substrate can be increased, and the rigidity of the coreless wiring substrate 10 is improved. In addition, by increasing the bonding area of the reinforcing plate 50 on the back surface 13 of the coreless wiring substrate 10, it is possible to reduce the region where the thermal expansion coefficient (CTE) mismatch occurs, and to improve the reliability of the coreless wiring substrate 10. Can do.

  (2) In the case of the coreless wiring substrate 10 of the present embodiment, the minimum diameter D1 of the opening 52 of the reinforcing plate 50 is set to be smaller than the diameter D2 of the BGA pad 41. In this way, in the step of providing the solder bump 55 on the BGA pad 41, the side wall of the opening 52 serves as a guide, whereby the solder ball can be reliably mounted on the BGA pad 41, and the solder bump 55 Can be provided quickly.

  (3) In the coreless wiring substrate 10 of the present embodiment, the maximum diameter D3 of the opening 52 in the reinforcing plate 50 is larger than the diameter D4 of the solder bump 55, and the minimum diameter D1 of the opening 52 is the solder bump 55. It is set to be smaller than the diameter D4. In this way, the solder bump 55 can be more reliably bonded onto the BGA pad 41 through the opening 52 of the reinforcing plate 50, and a sufficient bonding area of the reinforcing plate 50 can be secured.

  (4) In the case of the coreless wiring substrate 10 of the present embodiment, the resin reinforcing plate 50 made of a glass epoxy substrate is bonded and fixed to the solder resist 42 in a surface contact state. Compared to the case where the reinforcing plate 85 is fixed, sufficient adhesive strength can be obtained. Further, since the reinforcing plate 50 is made of a resin material and has excellent workability, the frustoconical opening 52 can be easily formed at a position corresponding to the BGA pad 41, and the material cost can be reduced. .

  (5) In the coreless wiring substrate 10 of the present embodiment, the diameter D5 of the opening 53 of the adhesive layer 51 is larger than the minimum diameter D1 of the opening 52 and the diameter of the opening 45 of the solder resist 42. The adhesive layer 51 does not protrude inside the openings 45 and 52 of the reinforcing plate 50 and the solder resist 42. In this way, when the solder bump 55 is formed on the BGA pad 41, the solder bump 55 does not come into contact with the adhesive layer 51, and the adhesive component is mixed into the molten solder bump 55. It can be avoided.

  In addition, you may change embodiment of this invention as follows.

  In the above embodiment, the package form of the coreless wiring substrate 10 is BGA (ball grid array), but an LGA (land grid array) package form may be adopted. FIG. 14 shows the coreless wiring substrate 10A. In the coreless wiring substrate 10A, on the back surface 13 (on the bottom surface of the first resin insulating layer 21), LGA pads 41A as back surface side connection terminals are arranged in an array, and an adhesive layer 51 is provided. The reinforcing plate 50A is fixed via the. That is, no solder resist is formed on the back surface 13 of the coreless wiring substrate 10 </ b> A, and the reinforcing plate 50 </ b> A is directly fixed on the resin insulating layer 21.

  As shown in FIGS. 14 and 15, in the reinforcing plate 50 </ b> A, a concave portion that matches the size and shape of the LGA pad 41 </ b> A is provided on the surface side (upper surface side in the drawing) arranged to face the resin insulating layer 21. 57 is formed, and the LGA pad 41 </ b> A is disposed in the recess 57. An opening 52A (reinforcing plate opening) that exposes the LGA pad 41A is formed in the bottom surface 58 of the recess 57. In the reinforcing plate 50A, the diameter of the opening 52A decreases from the non-bonding surface side (lower surface side in FIG. 15) to the bonding surface side (upper surface side in FIG. 15). Furthermore, the minimum diameter D1 (upper diameter) of the opening 52A is set to be smaller than the diameter D2 of the LGA pad 41A.

  Even if the coreless wiring substrate 10A is configured in this way, a sufficient bonding area of the reinforcing plate 50A to the back surface of the substrate can be secured, and the rigidity of the coreless wiring substrate 10A is improved. Further, by increasing the adhesion area of the reinforcing plate 50A on the back surface 13 of the coreless wiring substrate 10A, it is possible to reduce the region where the thermal expansion coefficient mismatch occurs, and to improve the reliability of the coreless wiring substrate 10A. Further, in the coreless wiring substrate 10A, for example, when connecting a terminal pin of a socket (not shown) on the motherboard side to the LGA pad 41A, the side wall of the opening 52A of the reinforcing plate 50A serves as a guide to connect the terminal pin to the LGA. It can be reliably guided to the pad 41A.

  In the coreless wiring substrates 10 and 10A of the above embodiment, the reinforcing plates 50 and 50A are formed using a glass epoxy substrate, but the present invention is not limited to this. Specifically, for example, a small amount of metal powder (for example, copper filler) that can maintain insulation is mixed into the synthetic resin material to form the reinforcing plates 50 and 50A, thereby radiating heat from the reinforcing plates 50 and 50A. You may comprise so that property may be improved.

  Next, the technical ideas grasped by the embodiment described above are listed below.

  (1) A multi-layer structure in which conductor layers and interlayer insulation layers are alternately stacked without having a core substrate, and a plurality of surface side connections for mounting semiconductor integrated circuit elements on the main surface A multilayer wiring board provided with a plurality of back side connection terminals for providing electrical connection with an external board on the back side opposite to the main surface, the terminal being provided on the back side A plurality of solder resist openings at positions corresponding to the connection terminals, a solder resist formed so as to cover the back surface, and a plurality of reinforcing plate openings at positions corresponding to the plurality of back surface side connection terminals A reinforcing plate, and an adhesive layer having a plurality of adhesive layer openings at positions corresponding to the plurality of back surface side connection terminals, and fixing the reinforcing plate to the solder resist in a surface contact state. In the reinforcing plate Multilayered wiring board, characterized in that the diameter of the reinforcing plate opening toward the bonding surface side is smaller from the adhesive surface.

  (2) The multilayer wiring board according to the above 1, wherein the diameter of the solder resist opening and the diameter of the reinforcing plate opening are set to be smaller than the diameter of the adhesive layer opening. .

  (3) A multi-layered structure that does not have a core substrate and is formed by alternately laminating conductor layers and interlayer insulating layers, and a plurality of surface side connections for mounting semiconductor integrated circuit elements on the main surface A multilayer wiring board provided with terminals and provided with a plurality of back side connection terminals for electrical connection with an external board on the back side opposite to the main surface, facing the back side On the surface side arranged in this manner, a recess that matches the size and shape of the plurality of back surface side connection terminals is formed, and a reinforcing plate is provided on the bottom surface of the recess to expose a part of the back surface side connection terminals. A reinforcing plate having an opening formed therein and an adhesive layer that fixes the reinforcing plate in a surface contact state with respect to the back surface, the closer to the bonding surface side from the non-bonding surface side of the reinforcing plate The diameter of the opening of the reinforcing plate is small Multilayer wiring substrate which is characterized.

Sectional drawing which shows schematic structure of the coreless wiring board of this Embodiment. The expanded sectional view which shows the principal part of a coreless wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Explanatory drawing of the manufacturing method of a core wiring board. Sectional drawing which shows schematic structure of the coreless wiring board of another embodiment. The expanded sectional view which shows the principal part of the core wiring board of another embodiment. The expanded sectional view which shows the principal part of the conventional core wiring board.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 10A ... Coreless wiring board as a multilayer wiring board 12 ... Main surface 13 ... Back surface 20 ... Wiring laminated part as a laminated structure 21-24 ... Resin insulating layer as an interlayer insulation layer 26 ... Conductive layer 27 ... Surface side connection Terminal pad 31 as a terminal IC chip as a semiconductor integrated circuit element 41 BPA pad as a back side connection terminal 41A ... LGA pad as a back side connection terminal 42 ... Solder resist 45 ... Solder resist opening 50, 50A ... Reinforcing plate 52, 52A ... Reinforcing plate opening 55 ... Solder bump as solder ball D1 ... Minimum diameter of reinforcing plate opening D2 ... Diameter of back side connection terminal D3 ... Maximum diameter of reinforcing plate opening D4 ... Solder bump diameter

Claims (5)

A multi-layered structure that does not have a core substrate and is formed by alternately laminating conductor layers and interlayer insulating layers, and a plurality of surface side connection terminals for mounting semiconductor integrated circuit elements are provided on the main surface. A multilayer wiring board provided with a plurality of back side connection terminals for electrical connection with an external board on the back side opposite to the main surface,
A plurality of reinforcing plate openings at positions corresponding to the plurality of back surface side connection terminals, comprising a reinforcing plate fixed in a surface contact state with respect to the back surface;
The multilayer wiring board according to claim 1, wherein the diameter of the opening portion of the reinforcing plate is reduced from the non-bonding surface side to the bonding surface side of the reinforcing plate.   The multilayer wiring board according to claim 1, wherein a minimum diameter of the reinforcing plate opening is set to be smaller than a diameter of the back-side connection terminal.   A solder ball is bonded onto the back side connection terminal, the maximum diameter of the reinforcing plate opening is larger than the diameter of the solder ball, and the minimum diameter of the reinforcing plate opening is the diameter of the solder ball. The multilayer wiring board according to claim 1, wherein the multilayer wiring board is set to be smaller than that of the multilayer wiring board.   The multilayer wiring board according to any one of claims 1 to 3, wherein the reinforcing plate is made of a non-metallic material.   The multilayer wiring board according to claim 1, wherein the reinforcing plate is made of synthetic resin as a main material.

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