JP5350829B2 - Manufacturing method of wiring board with reinforcing material, wiring board for wiring board with reinforcing material - Google Patents

Manufacturing method of wiring board with reinforcing material, wiring board for wiring board with reinforcing material Download PDF

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JP5350829B2
JP5350829B2 JP2009033313A JP2009033313A JP5350829B2 JP 5350829 B2 JP5350829 B2 JP 5350829B2 JP 2009033313 A JP2009033313 A JP 2009033313A JP 2009033313 A JP2009033313 A JP 2009033313A JP 5350829 B2 JP5350829 B2 JP 5350829B2
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wiring board
substrate
main surface
resin
reinforcing material
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JP2010192545A (en
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俊哉 浅野
真之介 前田
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Niterra Co Ltd
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NGK Spark Plug Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate

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  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board with a reinforcing material, which has almost no warpage while securing rigidity. <P>SOLUTION: A wiring board 11 with a reinforcing material includes a wiring board 40 and a stiffener 31. The wiring board 40 has a substrate main surface 41 and a substrate rear surface 42, and is formed by laminating a plurality of resin insulating layers 43-46 and a plurality of conductor layers 51, without including a core substrate. The stiffener 31 is joined only to the substrate main surface 41 side of the wiring board 40. When the thermal expansion coefficient of the wiring board 40 is larger than that of the stiffener 31, a wiring board 40 having warpage that the substrate main surface 41 side becomes a recess is formed and the stiffener 31 is bonded to the substrate main surface 41 of the wiring board 40 having the warpage. The wiring board 11 with a reinforcing material is thus manufactured. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

本発明は、配線基板の反りを防止するための補強材を備えた補強材付き配線基板の製造方法、補強材付き配線基板用の配線基板に関するものである。   The present invention relates to a method of manufacturing a wiring board with a reinforcing material provided with a reinforcing material for preventing warping of the wiring board, and a wiring board for a wiring board with a reinforcing material.

コンピュータのマイクロプロセッサ等として使用される半導体集積回路素子(ICチップ)は、近年ますます高速化、高機能化しており、これに付随して端子数が増え、端子間ピッチも狭くなる傾向にある。一般的にICチップの底面には多数の端子が密集してアレイ状に配置されており、このような端子群はマザーボード側の端子群に対してフリップチップの形態で接続される。ただし、ICチップ側の端子群とマザーボード側の端子群とでは端子間ピッチに大きな差があることから、ICチップをマザーボード上に直接的に接続することは困難である。そのため、通常はICチップをICチップ搭載用配線基板上に搭載してなる半導体パッケージを作製し、その半導体パッケージをマザーボード上に搭載するという手法が採用される(例えば特許文献1参照)。   In recent years, semiconductor integrated circuit elements (IC chips) used as computer microprocessors and the like have become increasingly faster and more functional, with an accompanying increase in the number of terminals and a tendency to narrow the pitch between terminals. . In general, a large number of terminals are densely arranged on the bottom surface of an IC chip, and such a terminal group is connected to a terminal group on the motherboard side in the form of a flip chip. However, it is difficult to connect the IC chip directly on the mother board because there is a large difference in the pitch between the terminals on the IC chip side terminal group and the mother board side terminal group. For this reason, a method is generally adopted in which a semiconductor package is prepared by mounting an IC chip on an IC chip mounting wiring board, and the semiconductor package is mounted on a motherboard (see, for example, Patent Document 1).

なお、ICチップは、一般に熱膨張係数が2.0ppm/℃〜5.0ppm/℃程度の半導体材料(例えばシリコン等)を用いて形成される。一方、ICチップ搭載用配線基板は、それよりも熱膨張係数がかなり大きい樹脂材料等を用いて形成された樹脂配線基板であることが多い。この樹脂配線基板の一例としては、コア基板の表面及び裏面にビルドアップ層を形成したものが実用化されている。この樹脂配線基板においては、コア基板として、例えば、補強繊維に樹脂を含浸させた樹脂基板(ガラスエポキシ基板など)が用いられている。そして、そのコア基板の剛性を利用して、コア基板の表面及び裏面に樹脂絶縁層と導体層とを交互に積層することにより、ビルドアップ層が形成される。つまり、この樹脂配線基板において、コア基板は、補強の役割を果たしており、ビルドアップ層と比べて非常に厚く形成されている。また、コア基板には、表面及び裏面に形成されたビルドアップ層間の導通を図るための配線(具体的には、スルーホール導体など)が貫通形成されている。   The IC chip is generally formed using a semiconductor material (for example, silicon) having a thermal expansion coefficient of about 2.0 ppm / ° C. to 5.0 ppm / ° C. On the other hand, the IC chip mounting wiring board is often a resin wiring board formed using a resin material having a considerably larger thermal expansion coefficient. As an example of this resin wiring board, a structure in which a buildup layer is formed on the front surface and the back surface of a core substrate has been put into practical use. In this resin wiring substrate, for example, a resin substrate (glass epoxy substrate or the like) in which a reinforcing fiber is impregnated with a resin is used as a core substrate. Then, by utilizing the rigidity of the core substrate, a resin layer and a conductor layer are alternately laminated on the front surface and the back surface of the core substrate, thereby forming a buildup layer. That is, in this resin wiring substrate, the core substrate plays a role of reinforcement and is formed much thicker than the build-up layer. In addition, wiring (specifically, a through-hole conductor or the like) is formed through the core substrate for conduction between buildup layers formed on the front surface and the back surface.

ところで近年では、半導体集積回路素子の高速化に伴い、使用される信号周波数が高周波帯域となってきている。この場合、コア基板を貫通する配線が大きなインダクタンスとして寄与し、高周波信号の伝送ロスや回路誤動作の発生につながり、高速化の妨げとなってしまう。この問題を解決するために、樹脂配線基板を、コア基板を有さない基板とすることが提案されている(例えば特許文献2参照)。この基板は、比較的に厚いコア基板を省略することにより全体の配線長を短くしたものであるため、高周波信号の伝送ロスが低減され、半導体集積回路素子を高速で動作させることが可能となる。   By the way, in recent years, with the increase in the speed of semiconductor integrated circuit elements, the signal frequency used has become a high frequency band. In this case, the wiring penetrating the core substrate contributes as a large inductance, leading to transmission loss of high-frequency signals and circuit malfunction, which hinders speeding up. In order to solve this problem, it has been proposed that the resin wiring substrate is a substrate that does not have a core substrate (see, for example, Patent Document 2). Since this substrate is obtained by shortening the overall wiring length by omitting a relatively thick core substrate, the transmission loss of high-frequency signals is reduced, and the semiconductor integrated circuit element can be operated at high speed. .

しかし、コア基板を省略すると樹脂配線基板が薄肉化されるため、樹脂配線基板の剛性の低下が避けられなくなる。この場合、フリップチップ接続に用いたはんだが冷却される際に、チップ材料と基板材料との熱膨張係数差に起因する熱応力の影響を受けて、樹脂配線基板がチップ搭載面側に反りやすくなる。その結果、チップ接合部分にクラックが起こり、オープン不良などが生じやすくなる。つまり、上記のようなICチップを用いて半導体パッケージを構成した場合、高い歩留まりや信頼性を実現できないという問題が生じる。   However, if the core substrate is omitted, the resin wiring board is thinned, and thus the rigidity of the resin wiring board is inevitably lowered. In this case, when the solder used for flip chip connection is cooled, the resin wiring board tends to warp to the chip mounting surface side due to the influence of thermal stress caused by the difference in thermal expansion coefficient between the chip material and the substrate material. Become. As a result, cracks occur in the chip bonding portion, and open defects are likely to occur. That is, when a semiconductor package is configured using the above IC chip, there arises a problem that high yield and reliability cannot be realized.

上記の問題を解決するために、樹脂配線基板101の片面(ICチップ106の搭載面102またはその裏面103)に、環状の金属製スティフナ105(補強材)を貼付した半導体パッケージ100が提案されている(図14参照)。   In order to solve the above problem, a semiconductor package 100 is proposed in which an annular metal stiffener 105 (reinforcing material) is attached to one side of the resin wiring substrate 101 (the mounting surface 102 of the IC chip 106 or its back surface 103). (See FIG. 14).

特開2002−26500号公報(図1など)JP 2002-26500 A (FIG. 1 and the like) 特開2002−26171号公報(図5など)Japanese Unexamined Patent Publication No. 2002-26171 (FIG. 5 etc.)

ところが、上記半導体パッケージ100では、樹脂配線基板101の熱膨張係数は、金属製スティフナ105の熱膨張係数よりも大きくなる。このため、樹脂配線基板101に金属製スティフナ105を接着する際に熱が加わると、熱膨張係数差に起因する熱応力の影響を受けて樹脂配線基板101に反りが発生してしまう(図15参照)。この場合、チップ搭載面102の平坦度を十分に確保することができないため、ICチップ106の搭載が困難となり、製品信頼性が低下してしまう。   However, in the semiconductor package 100, the thermal expansion coefficient of the resin wiring substrate 101 is larger than the thermal expansion coefficient of the metal stiffener 105. For this reason, when heat is applied when the metal stiffener 105 is bonded to the resin wiring board 101, the resin wiring board 101 is warped due to the influence of thermal stress caused by the difference in thermal expansion coefficient (FIG. 15). reference). In this case, since the flatness of the chip mounting surface 102 cannot be ensured sufficiently, it is difficult to mount the IC chip 106 and the product reliability is lowered.

本発明は上記の課題に鑑みてなされたものであり、その目的は、剛性を確保しつつ反りの少ない補強材付き配線基板の製造方法、及びその補強材付き配線基板用の配線基板を提供することにある。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a method of manufacturing a wiring board with a reinforcing material with less warping while ensuring rigidity, and a wiring board for the wiring board with the reinforcing material. There is.

そして上記課題を解決するための手段(手段1)としては、基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設された配線基板と、前記基板主面側にのみ接合され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材とを備える補強材付き配線基板の製造方法であって、前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも大きい場合には前記基板主面側が凹となる反りを有する配線基板を作製し、前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも小さい場合には前記基板裏面側が凹となる反りを有する配線基板を作製する配線基板作製工程と、反りを有する前記配線基板の前記基板主面に前記補強材を接着する接着工程とを含むことを特徴とする補強材付き配線基板の製造方法がある。 As a means for solving the above problems (means 1), it has a structure in which a plurality of resin insulation layers and a plurality of conductor layers are laminated without including a core substrate, including a substrate main surface and a substrate back surface. A plurality of main surface side connection terminals to which a semiconductor integrated circuit chip can be connected are bonded to the wiring substrate disposed on the substrate main surface only on the substrate main surface side, and the plurality of main surface side connection terminals A wiring board with a reinforcing material, comprising a reinforcing material having an opening through which the opening is exposed, wherein the thermal expansion coefficient of the plurality of resin insulation layers having the largest number of layers is the heat of the reinforcing material. When the expansion coefficient is larger than that, a wiring board having a warp in which the substrate main surface side is concave is manufactured, and the thermal expansion coefficient of the plurality of resin insulating layers having the largest number of layers is the thermal expansion coefficient of the reinforcing material. If the substrate back side is smaller than Manufacturing a wiring board with a reinforcing material, comprising: a wiring board manufacturing process for manufacturing a wiring board having a warping; and an adhesion process for bonding the reinforcing material to the substrate main surface of the wiring board having a warping. There is a way.

従って、手段1に記載の発明によると、配線基板は、コア基板を含まずに形成されているのでそれ自体では十分な剛性を確保することができない。このため、配線基板の基板主面側に補強材が接合されて補強材付き配線基板が製造される。この補強材付き配線基板において、配線基板の熱膨張係数が補強材の熱膨張係数よりも大きい場合、熱膨張係数差によって基板裏面側が凹となる反りが発生してしまう。この場合、配線基板作成工程にて、基板主面側が凹となる反りを有する配線基板を予め作成した後、接着工程にて、反りを有する配線基板の基板主面側に補強材を接着する。また逆に、配線基板の熱膨張係数が補強材の熱膨張係数よりも小さい場合、熱膨張係数差によって基板主面側が凹となる反りが発生してしまう。この場合、配線基板作成工程にて、基板裏面側が凹となる反りを有する配線基板を予め作成した後、接着工程にて、反りを有する配線基板の基板主面側に補強材を接着する。このようにすると、配線基板及び補強材の熱膨張係数差によって配線基板の反りを解消する方向に変形することで、反りの少ないフラットな形状の補強材付き配線基板を製造することができる。この結果、補強材付き配線基板に半導体集積回路チップを容易に搭載することができ、配線基板の製品歩留まりを向上することができる。   Therefore, according to the invention described in the means 1, since the wiring board is formed without including the core board, sufficient rigidity cannot be secured by itself. For this reason, a reinforcing material is joined to the board main surface side of the wiring board, and a wiring board with a reinforcing material is manufactured. In the wiring board with a reinforcing material, when the thermal expansion coefficient of the wiring board is larger than the thermal expansion coefficient of the reinforcing material, a warp in which the back surface side of the board becomes concave due to the thermal expansion coefficient difference occurs. In this case, after a wiring board having a warp in which the substrate main surface side is concave is prepared in advance in the wiring board preparation step, a reinforcing material is bonded to the substrate main surface side of the wiring substrate having warpage in the bonding step. On the other hand, when the thermal expansion coefficient of the wiring board is smaller than the thermal expansion coefficient of the reinforcing material, a warp in which the board main surface side becomes concave due to the difference in thermal expansion coefficient occurs. In this case, after a wiring board having a warp in which the back side of the board is concave is created in advance in the wiring board creating process, a reinforcing material is bonded to the main surface side of the wiring board having the warping in the bonding process. If it does in this way, it deform | transforms in the direction which eliminates the curvature of a wiring board by the thermal expansion coefficient difference of a wiring board and a reinforcing material, and can manufacture the wiring board with a reinforcing material of a flat shape with few curvature. As a result, the semiconductor integrated circuit chip can be easily mounted on the wiring board with the reinforcing material, and the product yield of the wiring board can be improved.

前記接着工程前における前記配線基板の前記反りの大きさは限定されないが、例えば100μm以上500μm以下とされる。この場合、前記接着工程後における前記配線基板の前記反りの大きさは限定されないが、例えば0μm以上50μm以下とされる。   Although the magnitude | size of the said curvature of the said wiring board before the said adhesion process is not limited, For example, you may be 100 micrometers or more and 500 micrometers or less. In this case, although the magnitude | size of the said curvature of the said wiring board after the said adhesion process is not limited, For example, you may be 0 micrometer or more and 50 micrometers or less.

前記配線基板としては、基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設された構造のものが使用される。前記配線基板において、前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径していることが好ましい。このようにすると、コア基板を含まないコアレス配線基板を確実に製造することができる。   The wiring board has a substrate main surface and a substrate back surface, has a structure in which a plurality of resin insulating layers and a plurality of conductor layers are laminated without including a core substrate, and can connect a semiconductor integrated circuit chip. A structure in which a plurality of main surface side connection terminals are arranged on the main surface of the substrate is used. In the wiring board, it is preferable that a plurality of via conductors are formed in the plurality of resin insulation layers, and the plurality of via conductors are expanded in the same direction in each layer of the plurality of resin insulation layers. In this way, a coreless wiring board that does not include a core board can be reliably manufactured.

前記配線基板の熱膨張係数が補強材の熱膨張係数よりも大きい場合、前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板裏面となる側に配置して積層を行うことが好ましい。このようにすると、各樹脂絶縁層の熱膨張係数差を利用して熱応力を加えることにより、基板主面側が凹となる反りを有する配線基板を容易に作製することができる。   When the thermal expansion coefficient of the wiring board is larger than the thermal expansion coefficient of the reinforcing material, in the wiring board manufacturing process, from a material having a relatively small thermal expansion coefficient compared to the other of the plurality of resin insulating layers. It is preferable to perform lamination by arranging at least one resin insulating layer on the side to be the back surface of the substrate. If it does in this way, the wiring board which has the curvature from which the board | substrate principal surface side becomes concave can be easily produced by applying a thermal stress using the thermal expansion coefficient difference of each resin insulating layer.

前記配線基板の熱膨張係数が補強材の熱膨張係数よりも小さい場合、前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板主面となる側に配置して積層を行うことが好ましい。このようにすると、各樹脂絶縁層の熱膨張係数差を利用して熱応力を加えることにより、基板裏面側が凹となる反りを有する配線基板を容易に作製することができる。   When the thermal expansion coefficient of the wiring board is smaller than the thermal expansion coefficient of the reinforcing material, in the wiring board manufacturing process, from a material having a relatively small thermal expansion coefficient compared to the other of the plurality of resin insulating layers. It is preferable that at least one resin insulating layer is disposed on the side to be the main surface of the substrate for lamination. If it does in this way, the wiring board which has the curvature by which a board | substrate back surface side becomes concave can be easily produced by applying a thermal stress using the thermal expansion coefficient difference of each resin insulating layer.

前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層は、樹脂材料中に無機材料を含有させた複合材料からなることが好ましい。このような複合材料を用いれば、前記反りを有する配線基板を確実に形成することができる。また、樹脂材料中に無機材料を含有させた複合材料を用いることにより、配線基板の剛性を高めることができる。   It is preferable that at least one resin insulating layer made of a material having a relatively small coefficient of thermal expansion compared to the other of the plurality of resin insulating layers is made of a composite material containing an inorganic material in the resin material. . By using such a composite material, it is possible to reliably form a wiring board having the warp. Moreover, the rigidity of a wiring board can be improved by using the composite material which contained the inorganic material in the resin material.

なお、本発明において、補強材、配線基板の「熱膨張係数」とは、厚み方向(Z方向)に対して垂直な方向(XY方向)の熱膨張係数のことを意味し、0℃〜100℃の間のTMA(熱機械分析装置)にて測定した値のことをいう。「TMA」とは、熱機械的分析をいい、例えばJPCA−BU01に規定されるものをいう。   In the present invention, “thermal expansion coefficient” of the reinforcing material and the wiring board means a thermal expansion coefficient in a direction (XY direction) perpendicular to the thickness direction (Z direction), and is 0 ° C. to 100 ° C. It means the value measured with TMA (thermomechanical analyzer) between ℃. “TMA” refers to thermomechanical analysis, such as that defined in JPCA-BU01.

前記樹脂絶縁層は、絶縁性、耐熱性、耐湿性等を考慮して適宜選択することができる。樹脂絶縁層を形成するための高分子材料の好適例としては、エポキシ樹脂、フェノール樹脂、ウレタン樹脂、シリコーン樹脂、ポリイミド樹脂などの熱硬化性樹脂、ポリカーボネート樹脂、アクリル樹脂、ポリアセタール樹脂、ポリプロピレン樹脂などの熱可塑性樹脂等が挙げられる。そのほか、これらの樹脂とガラス繊維(ガラス織布やガラス不織布)やポリアミド繊維等の有機繊維との複合材料、あるいは、連続多孔質PTFE等の三次元網目状フッ素系樹脂基材にエポキシ樹脂などの熱硬化性樹脂を含浸させた樹脂−樹脂複合材料等を使用してもよい。   The resin insulation layer can be appropriately selected in consideration of insulation, heat resistance, moisture resistance, and the like. Preferred examples of the polymer material for forming the resin insulation layer include thermosetting resins such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, polycarbonate resin, acrylic resin, polyacetal resin, polypropylene resin, etc. And other thermoplastic resins. In addition, composite materials of these resins and organic fibers such as glass fibers (glass woven fabrics and glass nonwoven fabrics) and polyamide fibers, or three-dimensional network fluorine-based resin base materials such as continuous porous PTFE, epoxy resins, etc. A resin-resin composite material impregnated with a thermosetting resin may be used.

前記導体層及び前記主面側接続端子は主として銅からなり、サブトラクティブ法、セミアディティブ法、フルアディティブ法などといった公知の手法によって形成される。具体的に言うと、例えば、銅箔のエッチング、無電解銅めっきあるいは電解銅めっきなどの手法が適用される。なお、スパッタやCVD等の手法により薄膜を形成した後にエッチングを行うことで導体層や主面側接続端子を形成したり、導電性ペースト等の印刷により導体層や主面側接続端子を形成したりすることも可能である。   The conductor layer and the main surface side connection terminal are mainly made of copper, and are formed by a known method such as a subtractive method, a semi-additive method, or a full additive method. Specifically, for example, techniques such as etching of copper foil, electroless copper plating, or electrolytic copper plating are applied. After forming a thin film by a method such as sputtering or CVD, etching is performed to form a conductor layer or a main surface side connection terminal, or a conductor layer or main surface side connection terminal is formed by printing a conductive paste or the like. It is also possible to do.

また、前記複数の主面側接続端子に接続可能な半導体集積回路チップとしては、コンピュータのマイクロプロセッサとして使用されるICチップ、DRAM(Dynamic Random Access Memory)やSRAM(Static Random Access Memory )などのICチップを挙げることができる。   As the semiconductor integrated circuit chip connectable to the plurality of main surface side connection terminals, an IC chip used as a microprocessor of a computer, an IC such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). A chip can be mentioned.

上記補強材は、前記配線基板を構成する樹脂材料よりも高剛性であることが好ましい。その理由は、補強材自体に高い剛性が付与されていれば、それを面接合することで配線基板に高い剛性を付与することができ、外部から加わる応力に対していっそう強くなるからである。また、高い剛性を有する補強材であれば、補強材を薄くしても配線基板に十分高い剛性を付与することができるため、補強材付き配線基板全体の薄肉化を阻害しないからである。   The reinforcing material is preferably more rigid than the resin material constituting the wiring board. The reason is that if the reinforcing material itself is given high rigidity, it can be given high rigidity to the wiring board by surface bonding, and becomes stronger against externally applied stress. In addition, if the reinforcing material has high rigidity, the wiring board can be provided with sufficiently high rigidity even if the reinforcing material is thinned, so that the thinning of the entire wiring board with reinforcing material is not hindered.

なお、前記補強材は、例えば、剛性の高い金属材料やセラミック材料を用いて形成することが好ましいく、例えば、樹脂材料中に無機材料を含有させた複合材料によって形成するものでもよい。   The reinforcing material is preferably formed using, for example, a highly rigid metal material or ceramic material. For example, the reinforcing material may be formed of a composite material containing an inorganic material in a resin material.

前記補強材を構成する金属材料としては、鉄、金、銀、銅、銅合金、鉄ニッケル合金、珪素、ガリウム砒素などがある。また、前記補強材を構成するセラミック材料としては、例えばアルミナ、ガラスセラミック、結晶化ガラス等の低温焼成材料、窒化アルミニウム、炭化珪素、窒化珪素などがある。前記補強材を構成する樹脂材料としては、エポキシ樹脂、ポリブテン樹脂、ポリアミド樹脂、ポリブチレンテレフタレート樹脂、ポリフェニレンサルファイド樹脂、ポリイミド樹脂、ビスマレイミド・トリアジン樹脂、ポリカーボネート樹脂、ポリフェニレンエーテル樹脂、アクリロニトリルブタジエンスチレン共重合体(ABS樹脂)などがある。   Examples of the metal material constituting the reinforcing material include iron, gold, silver, copper, copper alloy, iron nickel alloy, silicon, and gallium arsenide. Examples of the ceramic material constituting the reinforcing material include low-temperature fired materials such as alumina, glass ceramic, and crystallized glass, aluminum nitride, silicon carbide, and silicon nitride. As the resin material constituting the reinforcing material, epoxy resin, polybutene resin, polyamide resin, polybutylene terephthalate resin, polyphenylene sulfide resin, polyimide resin, bismaleimide / triazine resin, polycarbonate resin, polyphenylene ether resin, acrylonitrile butadiene styrene copolymer There is a coalescence (ABS resin).

前記補強材は配線基板の基板主面に接合されるが、接合の手法は特に限定されることはなく、補強材を形成している材料の性質、形状等に合った周知の手法を採用することができる。例えば、補強材の接合面を、前記基板主面に対して接着剤を介して接合することが好ましい。このようにすれば、配線基板に対して補強材を確実かつ容易に接合することができる。なお、接着剤としては、アクリル系接着剤、エポキシ系接着剤、シアノアクリレート系接着剤、ゴム系接着剤などが挙げられる。   The reinforcing material is bonded to the main surface of the wiring board, but the bonding method is not particularly limited, and a well-known method suitable for the nature, shape, etc. of the material forming the reinforcing material is adopted. be able to. For example, the joining surface of the reinforcing material is preferably joined to the substrate main surface via an adhesive. In this way, the reinforcing material can be reliably and easily joined to the wiring board. Examples of the adhesive include an acrylic adhesive, an epoxy adhesive, a cyanoacrylate adhesive, and a rubber adhesive.

また、上記課題を解決するための別の手段(手段2)としては、基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材が接合されるべき配線基板であって、100μm以上500μm以下の大きさの反りを有し、前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径しており、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる樹脂絶縁層を少なくとも1つ有することを特徴とする補強材付き配線基板用の配線基板がある。 Further, as another means (means 2) for solving the above-mentioned problem, a plurality of resin insulating layers and a plurality of conductor layers are laminated without including a core substrate, having a substrate main surface and a substrate back surface. A plurality of main surface side connection terminals that have a structure and can be connected to a semiconductor integrated circuit chip are disposed on the main surface of the substrate, and have openings that expose the plurality of main surface side connection terminals. A wiring board to which a material is to be bonded, having a warp of 100 μm or more and 500 μm or less, wherein a plurality of via conductors are formed in the plurality of resin insulating layers, and the plurality of via conductors are the plurality of via conductors. In each layer of the resin insulation layer, the diameter is expanded in the same direction, and the resin insulation layer has at least one resin insulation layer made of a material having a relatively small thermal expansion coefficient compared to the other of the plurality of resin insulation layers. For circuit board with reinforcing material There is a wiring board.

従って、手段2に記載の発明によると、前記配線基板は、コア基板を含まずに形成されているのでそれ自体では十分な剛性を確保することができないため、基板主面側に補強材が接合された補強材付き配線基板として使用される。ここで、補強材が接合される前の配線基板は、100μm以上500μm以下の大きさの反りを有し、複数の樹脂絶縁層には複数のビア導体が形成され、複数のビア導体は複数の樹脂絶縁層の各層において同一方向に拡径している。この反りを有する配線基板に補強材を接合すると、配線基板及び補強材の熱膨張係数の差によって配線基板の反りを解消する方向に変形させることができ、反りのないフラットな形状の補強材付き配線基板を製造することができる。   Therefore, according to the invention described in Means 2, since the wiring board is formed without including the core board, sufficient rigidity cannot be secured by itself, so that the reinforcing material is bonded to the board main surface side. Used as a reinforcing wiring board with a reinforcing material. Here, the wiring board before the reinforcing material is bonded has a warp with a size of 100 μm or more and 500 μm or less, a plurality of via conductors are formed in the plurality of resin insulating layers, and the plurality of via conductors are a plurality of via conductors. In each layer of the resin insulating layer, the diameter is expanded in the same direction. When a reinforcing material is joined to a wiring board having warpage, it can be deformed in a direction to eliminate the warping of the wiring board due to the difference in thermal expansion coefficient between the wiring board and the reinforcing material. A wiring board can be manufactured.

本実施形態における半導体パッケージの概略構成を示す概略断面図。1 is a schematic cross-sectional view illustrating a schematic configuration of a semiconductor package according to an embodiment. 半導体パッケージを示す概略平面図。The schematic plan view which shows a semiconductor package. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. スティフナ付き配線基板の製造方法を示す説明図。Explanatory drawing which shows the manufacturing method of a wiring board with a stiffener. 従来技術の半導体パッケージを示す斜視図。The perspective view which shows the semiconductor package of a prior art. 同じく、半導体パッケージを示す概略断面図。Similarly, the schematic sectional drawing which shows a semiconductor package.

以下、本発明を補強材付き配線基板に具体化した一実施の形態を図面に基づき詳細に説明する。   Hereinafter, an embodiment in which the present invention is embodied in a wiring board with a reinforcing material will be described in detail with reference to the drawings.

図1及び図2に示されるように、本実施形態の半導体パッケージ10は、スティフナ付き配線基板11(補強材付き配線基板)と、ICチップ21(半導体集積回路チップ)とからなるBGA(ボールグリッドアレイ)である。なお、半導体パッケージ10の形態は、BGAのみに限定されず、例えばPGA(ピングリッドアレイ)やLGA(ランドグリッドアレイ)等であってもよい。ICチップ21は、縦15.0mm×横15.0mm×厚さ0.8mmの矩形平板状であって、熱膨張係数が4.2ppm/℃のシリコンからなる。   As shown in FIGS. 1 and 2, the semiconductor package 10 of this embodiment includes a BGA (ball grid) including a stiffener-equipped wiring substrate 11 (a wiring substrate with a reinforcing material) and an IC chip 21 (semiconductor integrated circuit chip). Array). Note that the form of the semiconductor package 10 is not limited to BGA alone, and may be PGA (pin grid array), LGA (land grid array), or the like. The IC chip 21 is a rectangular flat plate having a length of 15.0 mm, a width of 15.0 mm, and a thickness of 0.8 mm, and is made of silicon having a thermal expansion coefficient of 4.2 ppm / ° C.

スティフナ付き配線基板11は、配線基板40と、補強材である配線基板用スティフナ(以下「スティフナ」という)31とを備えている。本実施の形態の配線基板40は、基板主面41及び基板裏面42を有し、縦50.0mm×横50.0mm×厚さ0.4mmの平面視略矩形状に形成されている。また、配線基板40は、コア基板を含まずに形成されたコアレス配線基板であって、エポキシ樹脂からなる4層の樹脂絶縁層43,44,45,46と銅からなる導体層51とを交互に積層した構造を有する。   The wiring board 11 with a stiffener includes a wiring board 40 and a wiring board stiffener (hereinafter referred to as “stiffener”) 31 that is a reinforcing material. The wiring substrate 40 of the present embodiment has a substrate main surface 41 and a substrate back surface 42 and is formed in a substantially rectangular shape in plan view of 50.0 mm long × 50.0 mm wide × 0.4 mm thick. The wiring board 40 is a coreless wiring board formed without including a core board, and is composed of four resin insulation layers 43, 44, 45, 46 made of epoxy resin and conductor layers 51 made of copper alternately. It has a laminated structure.

本実施の形態の配線基板40において、最下層である第1の樹脂絶縁層43は、エポキシ樹脂中にガラスクロス48(無機材料)を含有させた複合材料からなり、それより上層側の第2層〜第4層の樹脂絶縁層44〜46はガラスクロス48を含まないエポキシ樹脂からなる。従って、第1の樹脂絶縁層43は、他の樹脂絶縁層44〜46と比べて熱膨張係数が小さくなっている。具体的には、第1の樹脂絶縁層43の熱膨張係数は約16ppm/℃となっており、第2層〜第4層の樹脂絶縁層44〜46の熱膨張係数は約30ppm/℃となっている。また、導体層51の熱膨張係数は約17ppm/℃となっている。   In the wiring substrate 40 of the present embodiment, the first resin insulating layer 43 that is the lowest layer is made of a composite material in which a glass cloth 48 (inorganic material) is contained in an epoxy resin. The resin insulation layers 44 to 46 of the layers to the fourth layer are made of an epoxy resin that does not include the glass cloth 48. Therefore, the first resin insulating layer 43 has a smaller thermal expansion coefficient than the other resin insulating layers 44 to 46. Specifically, the thermal expansion coefficient of the first resin insulating layer 43 is about 16 ppm / ° C., and the thermal expansion coefficients of the second to fourth resin insulating layers 44 to 46 are about 30 ppm / ° C. It has become. The thermal expansion coefficient of the conductor layer 51 is about 17 ppm / ° C.

図1に示されるように、配線基板40の基板主面41上(第4層の樹脂絶縁層46の表面上)には、端子パッド52(主面側接続端子)がアレイ状に配置されている。さらに、端子パッド52の表面上には、複数の主面側はんだバンプ54が配設されている。各主面側はんだバンプ54は、前記ICチップ21の面接続端子22に電気的に接続されている。即ち、ICチップ21は、配線基板40の基板主面41側に搭載されている。なお、各端子パッド52及び各主面側はんだバンプ54が形成されている領域は、ICチップ21を搭載可能なICチップ搭載領域23である。   As shown in FIG. 1, terminal pads 52 (main surface side connection terminals) are arranged in an array on the substrate main surface 41 of the wiring substrate 40 (on the surface of the fourth resin insulating layer 46). Yes. Furthermore, a plurality of main surface side solder bumps 54 are disposed on the surface of the terminal pad 52. Each main surface side solder bump 54 is electrically connected to the surface connection terminal 22 of the IC chip 21. That is, the IC chip 21 is mounted on the substrate main surface 41 side of the wiring substrate 40. In addition, the area | region in which each terminal pad 52 and each main surface side solder bump 54 is formed is the IC chip mounting area 23 in which the IC chip 21 can be mounted.

一方、配線基板40の基板裏面42上(第1層の樹脂絶縁層43の下面上)には、BGA用パッド53がアレイ状に配設されている。また、各BGA用パッド53の表面上には、マザーボード接続用の複数の裏面側はんだバンプ55が配設されており、各裏面側はんだバンプ55により、配線基板40は図示しないマザーボード上に実装される。   On the other hand, BGA pads 53 are arranged in an array on the substrate rear surface 42 of the wiring substrate 40 (on the lower surface of the first resin insulating layer 43). A plurality of backside solder bumps 55 for connecting the motherboard are disposed on the surface of each BGA pad 53, and the wiring board 40 is mounted on the motherboard (not shown) by each backside solder bump 55. The

各樹脂絶縁層43〜46には、それぞれビア穴56及びビア導体57が設けられている。各ビア穴56は、円錐台形状をなし、各樹脂絶縁層43〜46に対してYAGレーザまたは炭酸ガスレーザを用いた穴あけ加工を施すことで形成される。各ビア導体57は、基板裏面42側(図1では下方向)に行くに従って拡径した導体であって、各導体層51、前記端子パッド52及びBGA用パッド53を相互に電気的に接続している。   Each resin insulation layer 43 to 46 is provided with a via hole 56 and a via conductor 57. Each via hole 56 has a truncated cone shape, and is formed by drilling the resin insulation layers 43 to 46 using a YAG laser or a carbon dioxide gas laser. Each via conductor 57 is a conductor whose diameter increases toward the back side 42 of the substrate (downward in FIG. 1), and electrically connects each conductor layer 51, the terminal pad 52 and the BGA pad 53 to each other. ing.

図1及び図2に示されるように、前記スティフナ31は、縦50.0mm×横50.0mm×厚さ2.0mmの平面視矩形枠状である。なお、スティフナ31は、金属材料(例えば、銅)を用いて配線基板40よりも厚く形成されている。従って、スティフナ31は、配線基板40よりも高剛性となっている。さらに、スティフナ31の熱膨張係数は、約17ppm/℃であり、配線基板40を構成する樹脂絶縁層44〜46の熱膨張係数(約30ppm/℃)よりも小さい値となっている。   As shown in FIGS. 1 and 2, the stiffener 31 has a rectangular frame shape in plan view of 50.0 mm long × 50.0 mm wide × 2.0 mm thick. The stiffener 31 is formed thicker than the wiring board 40 using a metal material (for example, copper). Therefore, the stiffener 31 is more rigid than the wiring board 40. Furthermore, the thermal expansion coefficient of the stiffener 31 is about 17 ppm / ° C., which is smaller than the thermal expansion coefficient (about 30 ppm / ° C.) of the resin insulating layers 44 to 46 constituting the wiring board 40.

スティフナ31は、配線基板40に接合される接合面32と、接合面32の反対側に位置する非接合面33とを有している。接合面32は、基板主面41の外周部(即ち、基板主面41において前記ICチップ搭載領域23を除く領域)に面接触可能となっている。   The stiffener 31 has a bonding surface 32 bonded to the wiring substrate 40 and a non-bonding surface 33 located on the opposite side of the bonding surface 32. The bonding surface 32 can come into surface contact with the outer peripheral portion of the substrate main surface 41 (that is, the region excluding the IC chip mounting region 23 in the substrate main surface 41).

また、スティフナ31には、接合面32の中央部及び非接合面33の中央部にて開口する平面視で矩形状の開口部35が貫通形成されている。開口部35は、端子パッド52及び前記主面側はんだバンプ54を露出させるようになっている。具体的に言うと、開口部35は、縦20mm×横20mmで、四隅に半径1.5mmのアールを有する断面略正方形状の孔である。   The stiffener 31 is formed with a rectangular opening 35 penetrating in a plan view opening at the center of the joint surface 32 and the center of the non-joint surface 33. The opening 35 exposes the terminal pad 52 and the main surface side solder bump 54. Specifically, the opening 35 is a hole having a substantially square shape in cross section having a radius of 1.5 mm at four corners with a length of 20 mm × width of 20 mm.

そして図1に示されるように、スティフナ31の接合面32は、基板主面41の外周部に対して接着剤30(例えば、エポキシ系接着剤)を介して面接合(接合固定)される。このようにスティフナ付き配線基板11を構成すれば、スティフナ31により配線基板11に高い剛性を付与することができる。   As shown in FIG. 1, the bonding surface 32 of the stiffener 31 is surface bonded (bonded and fixed) to the outer peripheral portion of the substrate main surface 41 via an adhesive 30 (for example, an epoxy-based adhesive). If the stiffener-equipped wiring board 11 is configured in this way, the stiffener 31 can impart high rigidity to the wiring board 11.

次に、スティフナ付き配線基板11の製造方法について説明する。   Next, the manufacturing method of the wiring board 11 with a stiffener is demonstrated.

準備工程において、配線基板40及びスティフナ31を作製し、あらかじめ準備しておく。   In the preparation step, the wiring board 40 and the stiffener 31 are prepared and prepared in advance.

配線基板40は、以下の配線基板作製工程を経て作製される。配線基板作製工程では、まず、図3に示されるように、ガラスエポキシ基板などの十分な強度を有する支持基板70を準備する。次に、支持基板70上に、エポキシ樹脂からなるシート状の絶縁樹脂基材を貼り付けて下地樹脂絶縁層71を形成することにより、支持基板70及び下地樹脂絶縁層71からなる基材69を得る。そして、図4に示されるように、基材69の片面(具体的には下地樹脂絶縁層71の上面)に、積層金属シート体72を配置する。ここで、下地樹脂絶縁層71上に積層金属シート体72を配置することにより、以降の製造工程で積層金属シート体72が下地樹脂絶縁層71から剥がれない程度の密着性が確保される。積層金属シート体72は、2枚の銅箔73,74を剥離可能な状態で密着させてなる。具体的には、金属めっき(例えば、クロムめっき)を介して各銅箔73,74を積層することで積層金属シート体72が形成されている。   The wiring board 40 is manufactured through the following wiring board manufacturing process. In the wiring substrate manufacturing process, first, as shown in FIG. 3, a support substrate 70 having sufficient strength such as a glass epoxy substrate is prepared. Next, a base resin insulating layer 71 is formed by pasting a sheet-like insulating resin base material made of epoxy resin on the support substrate 70 to form a base material 69 made of the support substrate 70 and the base resin insulating layer 71. obtain. Then, as shown in FIG. 4, the laminated metal sheet body 72 is disposed on one surface of the base material 69 (specifically, the upper surface of the base resin insulating layer 71). Here, by disposing the laminated metal sheet body 72 on the base resin insulating layer 71, adhesiveness is secured to such an extent that the laminated metal sheet body 72 is not peeled off from the base resin insulating layer 71 in the subsequent manufacturing process. The laminated metal sheet body 72 is formed by closely attaching two copper foils 73 and 74 in a peelable state. Specifically, the laminated metal sheet body 72 is formed by laminating the copper foils 73 and 74 via metal plating (for example, chromium plating).

その後、図5に示されるように、積層金属シート体72を包むようにシート状の絶縁樹脂基材75を配置し、真空圧着熱プレス機(図示略)を用いて真空下にて加圧加熱することにより、絶縁樹脂基材75を硬化させて第4層の樹脂絶縁層46を形成する。ここで、樹脂絶縁層46は、積層金属シート体72と密着するとともに、その積層金属シート体72の周囲領域において下地樹脂絶縁層71と密着することで、積層金属シート体72を封止する。   Thereafter, as shown in FIG. 5, a sheet-like insulating resin base material 75 is disposed so as to wrap the laminated metal sheet body 72, and is heated under pressure using a vacuum press-bonding hot press (not shown). As a result, the insulating resin base material 75 is cured to form the fourth resin insulating layer 46. Here, the resin insulating layer 46 is in close contact with the laminated metal sheet body 72, and in close contact with the base resin insulating layer 71 in the peripheral region of the laminated metal sheet body 72, thereby sealing the laminated metal sheet body 72.

そして、図6に示されるように、レーザ加工を施すことによって樹脂絶縁層46の所定の位置にビア穴56を形成し、次いで各ビア穴56内のスミアを除去するデスミア処理を行う。その後、従来公知の手法に従って無電解銅めっき及び電解銅めっきを行うことで、各ビア穴56内にビア導体57を形成する。さらに、従来公知の手法(例えばセミアディティブ法)によってエッチングを行うことで、樹脂絶縁層46上に導体層51をパターン形成する(図7参照)。   Then, as shown in FIG. 6, laser processing is performed to form via holes 56 at predetermined positions of the resin insulating layer 46, and then desmear processing is performed to remove smears in the via holes 56. Then, via conductors 57 are formed in each via hole 56 by performing electroless copper plating and electrolytic copper plating according to a conventionally known method. Further, the conductor layer 51 is patterned on the resin insulating layer 46 by performing etching by a conventionally known method (for example, semi-additive method) (see FIG. 7).

また、第1層〜第3層の樹脂絶縁層43〜45及び導体層51についても、上述した第4層の樹脂絶縁層46及び導体層51と同様の手法によって形成し、樹脂絶縁層46上に積層していく。ただし、本実施の形態では、第2層〜第4層の樹脂絶縁層44〜46の形成時には、ガラスクロス48を含まない一般的なビルドアップ材(味の素製:ABF−GX13)を絶縁樹脂基材75として用いる。また、第1層の樹脂絶縁層43の形成時にのみ、エポキシ樹脂をガラスクロス48に含浸させてなるビルドアップ材(味の素製:ABF−GX13−PP)を絶縁樹脂基材として用いる。このように、異なるビルドアップ材を用いることにより、第1の樹脂絶縁層43の熱膨張係数は約16ppm/℃となり、第2層〜第4層の樹脂絶縁層44〜46の熱膨張係数は約30ppm/℃となる。   The first to third resin insulation layers 43 to 45 and the conductor layer 51 are also formed by the same method as the above-described fourth resin insulation layer 46 and conductor layer 51, and the resin insulation layer 46 is formed on the resin insulation layer 46. Laminate to. However, in this embodiment, when the second to fourth resin insulation layers 44 to 46 are formed, a general build-up material (Ajinomoto: ABF-GX13) that does not include the glass cloth 48 is used as the insulation resin group. Used as material 75. In addition, a build-up material (Ajinomoto: ABF-GX13-PP) obtained by impregnating a glass cloth 48 with an epoxy resin is used as an insulating resin base material only when the first resin insulating layer 43 is formed. Thus, by using different buildup materials, the thermal expansion coefficient of the first resin insulation layer 43 is about 16 ppm / ° C., and the thermal expansion coefficients of the second to fourth resin insulation layers 44 to 46 are About 30 ppm / ° C.

以上の工程によって、基材69上に積層金属シート体72、樹脂絶縁層43〜46及び導体層51を積層した積層体80を形成する(図8参照)。なお図8に示されるように、積層体80において積層金属シート体72上に位置する領域が、配線基板40となるべき配線積層部81となる。   The laminated body 80 which laminated | stacked the laminated metal sheet body 72, the resin insulating layers 43-46, and the conductor layer 51 on the base material 69 is formed by the above process (refer FIG. 8). As shown in FIG. 8, a region located on the laminated metal sheet body 72 in the laminated body 80 is a wiring laminated portion 81 to be the wiring board 40.

この積層体80をダイシング装置(図示略)により切断し、積層体80における配線積層部81の周囲領域を除去する。この際、図8に示すように、配線積層部81とその周囲部82との境界において、配線積層部81の下方にある基材69(支持基板70及び下地樹脂絶縁層71)ごと切断する。この切断によって、樹脂絶縁層46にて封止されていた積層金属シート体72の外縁部が露出した状態となる。つまり、周囲部82の除去によって、下地樹脂絶縁層71と樹脂絶縁層46との密着部分が失われる。この結果、配線積層部81と基材69とは積層金属シート体72のみを介して連結した状態となる。   The laminated body 80 is cut by a dicing device (not shown), and the peripheral area of the wiring laminated portion 81 in the laminated body 80 is removed. At this time, as shown in FIG. 8, the substrate 69 (the support substrate 70 and the base resin insulating layer 71) below the wiring laminated portion 81 is cut at the boundary between the wiring laminated portion 81 and the peripheral portion 82. By this cutting, the outer edge portion of the laminated metal sheet body 72 sealed with the resin insulating layer 46 is exposed. That is, due to the removal of the peripheral portion 82, the close contact portion between the base resin insulating layer 71 and the resin insulating layer 46 is lost. As a result, the wiring laminated portion 81 and the base material 69 are connected via the laminated metal sheet body 72 only.

ここで、図9に示されるように、積層金属シート体72における2枚の銅箔73,74の界面にて剥離して、配線積層部81を基材69から分離する。そして、図10に示されるように、配線積層部81(樹脂絶縁層46)の下面上にある銅箔73に対してエッチングによるパターニングを行うことにより、最表層の樹脂絶縁層46上に端子パッド52を形成する。   Here, as shown in FIG. 9, the wiring laminated portion 81 is separated from the base material 69 by peeling at the interface between the two copper foils 73 and 74 in the laminated metal sheet body 72. Then, as shown in FIG. 10, by patterning by etching the copper foil 73 on the lower surface of the wiring laminated portion 81 (resin insulating layer 46), terminal pads are formed on the outermost resin insulating layer 46. 52 is formed.

続くはんだバンプ形成工程では、最表層の樹脂絶縁層46上に形成された複数の端子パッド52上に、ICチップ接続用の主面側はんだバンプ54を形成する(図11参照)。具体的には、図示しないはんだボール搭載装置を用いて各端子パッド52上にはんだボールを配置した後、はんだボールを所定の温度に加熱してリフローすることにより、各端子パッド52上に主面側はんだバンプ54を形成する。同様に、樹脂絶縁層43上に形成された複数のBGA用パッド53上に、裏面側はんだバンプ55を形成する。   In the subsequent solder bump forming step, main surface side solder bumps 54 for IC chip connection are formed on the plurality of terminal pads 52 formed on the outermost resin insulation layer 46 (see FIG. 11). Specifically, a solder ball is placed on each terminal pad 52 using a solder ball mounting device (not shown), and then the solder ball is heated to a predetermined temperature and reflowed, whereby the main surface is placed on each terminal pad 52. Side solder bumps 54 are formed. Similarly, back-side solder bumps 55 are formed on the plurality of BGA pads 53 formed on the resin insulating layer 43.

ここで、配線基板40において、樹脂絶縁層43と樹脂絶縁層44〜46とは熱膨張係数が異なる。このため、はんだバンプ54,55の形成時には、熱膨張係数差に起因する熱応力が加わる結果、配線基板40が変形して基板主面41側が凹となる反りが発生する(図11参照)。この配線基板40の反りは、200μm〜300μm程度である。   Here, in the wiring board 40, the resin insulating layer 43 and the resin insulating layers 44 to 46 have different thermal expansion coefficients. For this reason, when the solder bumps 54 and 55 are formed, as a result of applying thermal stress due to the difference in thermal expansion coefficient, the wiring substrate 40 is deformed and warpage occurs in which the substrate main surface 41 side becomes concave (see FIG. 11). The warp of the wiring board 40 is about 200 μm to 300 μm.

スティフナ31は、従来周知の切断装置を用いて銅板を切断することにより矩形状に加工される。また、スティフナ31の開口部35は、座繰りカッター、メカニカルドリル、パンチング装置等を用いて孔あけ加工を行うことにより形成される。   The stiffener 31 is processed into a rectangular shape by cutting a copper plate using a conventionally known cutting device. Further, the opening 35 of the stiffener 31 is formed by drilling using a countersink cutter, a mechanical drill, a punching device, or the like.

接合工程では、反りを有する配線基板40の基板主面41にスティフナ31を接着する。具体的には、図12に示されるように、スティフナ31の接合面32に接着剤30を塗布した後、配線基板40の基板主面41上にスティフナ31を配置し、接合面32を基板主面41に接触させる。この状態で、例えば150℃程度で加熱処理(キュア)を行って接着剤30を固化させれば、加熱処理後に接着剤30が室温まで冷却されるとともに、スティフナ31が基板主面41に対して接着剤30を介して接合固定される(図13参照)。このとき、配線基板40及びスティフナ31の熱膨張係数差に起因する熱応力が加わることで、配線基板40の反りを解消する方向に変形する。これにより、配線基板40の反りが50μm以下に低減され、反りの少ないフラットな形状のスティフナ付き配線基板11が形成される。   In the bonding step, the stiffener 31 is bonded to the substrate main surface 41 of the wiring substrate 40 having warpage. Specifically, as shown in FIG. 12, after applying the adhesive 30 to the joint surface 32 of the stiffener 31, the stiffener 31 is disposed on the substrate main surface 41 of the wiring substrate 40, and the joint surface 32 is formed on the substrate main surface 41. Contact the surface 41. In this state, if the adhesive 30 is solidified by performing a heat treatment (curing) at about 150 ° C., for example, the adhesive 30 is cooled to room temperature after the heat treatment, and the stiffener 31 is attached to the substrate main surface 41. It is bonded and fixed via the adhesive 30 (see FIG. 13). At this time, when the thermal stress resulting from the difference in thermal expansion coefficient between the wiring board 40 and the stiffener 31 is applied, the wiring board 40 is deformed in a direction to eliminate the warp. Thereby, the warp of the wiring board 40 is reduced to 50 μm or less, and the flat-stiffened wiring board 11 with less warpage is formed.

その後、配線基板40のICチップ搭載領域23にICチップ21を載置する。このとき、ICチップ21側の面接続端子22と、配線基板40側の主面側はんだバンプ54とを位置合わせするようにする。そして、加熱して各主面側はんだバンプ54をリフローすることにより、面接続端子22と主面側はんだバンプ54とが接合され、配線基板40にICチップ21が搭載される(図1参照)。   Thereafter, the IC chip 21 is mounted on the IC chip mounting area 23 of the wiring board 40. At this time, the surface connection terminals 22 on the IC chip 21 side and the main surface side solder bumps 54 on the wiring board 40 side are aligned. Then, by heating and reflowing the main surface side solder bumps 54, the surface connection terminals 22 and the main surface side solder bumps 54 are joined, and the IC chip 21 is mounted on the wiring board 40 (see FIG. 1). .

従って、本実施の形態によれば以下の効果を得ることができる。   Therefore, according to the present embodiment, the following effects can be obtained.

(1)本実施の形態では、配線基板作成工程にて、基板主面41側が凹となる反りを有する配線基板40を予め作成した後、接着工程にて、反りを有する配線基板40の基板主面41側にスティフナ31を接着固定している。このようにすると、配線基板40及びスティフナ31の熱膨張係数差によって配線基板40の反りを解消する方向に変形することで、反りの少ないフラットな形状の補強材付き配線基板11を製造することができる。この結果、補強材付き配線基板11にICチップ21を確実に搭載することができ、製品の歩留まりが向上してその信頼性を確保することができる。   (1) In this embodiment, after the wiring board 40 having a warp in which the substrate main surface 41 side is concave is created in advance in the wiring board creation process, the substrate main of the wiring board 40 having a warp is produced in the bonding process. A stiffener 31 is bonded and fixed to the surface 41 side. In this way, the wiring board 11 with a reinforcing material having a flat shape with less warping can be manufactured by deforming the wiring board 40 in a direction to eliminate the warping due to the difference in thermal expansion coefficient between the wiring board 40 and the stiffener 31. it can. As a result, the IC chip 21 can be reliably mounted on the wiring board 11 with the reinforcing material, and the yield of the product can be improved and its reliability can be ensured.

(2)本実施の形態の配線基板作製工程では、複数の樹脂絶縁層43〜46のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる樹脂絶縁層43を基板裏面42となる側に配置して各樹脂絶縁層43〜46を積層している。このようにすると、各樹脂絶縁層43〜46の熱膨張係数差に起因する熱応力を加えることにより、基板主面41側が凹となる反りを有する配線基板40を容易に作製することができる。   (2) In the wiring board manufacturing process of the present embodiment, the resin insulating layer 43 made of a material having a relatively small thermal expansion coefficient as compared with the other of the plurality of resin insulating layers 43 to 46 is used as the substrate back surface 42. The resin insulating layers 43 to 46 are stacked on the side to be disposed. If it does in this way, the wiring board 40 which has the curvature by which the board | substrate main surface 41 side becomes concave can be easily produced by applying the thermal stress resulting from the thermal expansion coefficient difference of each resin insulation layers 43-46.

(3)本実施の形態の配線基板40のように、エポキシ樹脂をガラスクロス48(無機材料)に含浸させてなるビルドアップ材を用いて樹脂絶縁層43を形成することにより、基板自体の剛性を向上させることができる。   (3) By forming the resin insulating layer 43 using a build-up material obtained by impregnating a glass cloth 48 (inorganic material) with an epoxy resin like the wiring substrate 40 of the present embodiment, the rigidity of the substrate itself is formed. Can be improved.

なお、本発明の実施の形態は以下のように変更してもよい。   In addition, you may change embodiment of this invention as follows.

・上記実施の形態では、配線基板40の熱膨張係数がスティフナ31の熱膨張係数よりも大きく、基板主面41側が凹となる反りを有する配線基板40を作製するものであった。これとは逆に、スティフナ31の熱膨張係数が大きく配線基板40の熱膨張係数が小さい場合には、基板裏面42側が凹となる反りを有する配線基板40を作製して、その反りを有する配線基板40の基板主面41上にスティフナ31を接着固定するようにしてもよい。このようにしても、配線基板40及びスティフナ31の熱膨張係数差によって配線基板40の反りを解消する方向に変形することで、反りのないフラットな形状のスティフナ付き配線基板11を製造することができる。なお、前記基板裏面42側が凹となる反りを有する配線基板40を作製する場合には、複数の樹脂絶縁層43〜46のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる樹脂絶縁層46を基板主面41となる側に配置して積層を行うようにする。   In the above-described embodiment, the wiring board 40 having the warp that the thermal expansion coefficient of the wiring board 40 is larger than the thermal expansion coefficient of the stiffener 31 and the board main surface 41 side is concave is manufactured. On the contrary, when the thermal expansion coefficient of the stiffener 31 is large and the thermal expansion coefficient of the wiring board 40 is small, the wiring board 40 having a warp in which the back surface 42 side of the substrate is concave is produced, and the wiring having the warp is produced. The stiffener 31 may be bonded and fixed on the substrate main surface 41 of the substrate 40. Even in this case, the wiring board 11 with a stiffener having a flat shape without warping can be manufactured by deforming the wiring board 40 in a direction to eliminate the warping due to the difference in thermal expansion coefficient between the wiring board 40 and the stiffener 31. it can. When manufacturing the wiring board 40 having a warp in which the substrate back surface 42 side is concave, the wiring board 40 is made of a material having a relatively small thermal expansion coefficient compared to the other of the plurality of resin insulating layers 43 to 46. The resin insulating layer 46 is disposed on the side that becomes the substrate main surface 41 to perform lamination.

・上記実施の形態において、配線基板40は、4層の樹脂絶縁層43〜46を積層してなる基板であるが、これら樹脂絶縁層の層数を適宜変更してもよい。また、複数の樹脂絶縁層43〜46のうちの1層の樹脂絶縁層43を他のものと比べて相対的に熱膨張係数の小さい材料で形成するものであったが、2層以上の樹脂絶縁層を熱膨張係数の異なる材料で形成してもよい。   In the above embodiment, the wiring board 40 is a board formed by laminating four resin insulating layers 43 to 46, but the number of these resin insulating layers may be changed as appropriate. In addition, one resin insulating layer 43 among the plurality of resin insulating layers 43 to 46 is formed of a material having a relatively small coefficient of thermal expansion as compared with the other ones. The insulating layer may be formed of materials having different thermal expansion coefficients.

・上記実施の形態では、樹脂絶縁層43〜46の熱膨張係数差に起因する熱応力を利用して、反りを有する配線基板40を作製するものであったが、これに限定されるものではない。例えば、成形金型を用いて型押しすることによって反りを有する配線基板40を作製してもよい。また、基板の最表層をソルダーレジストで覆う配線基板においては、そのソルダーレジストの熱膨張係数を樹脂絶縁層43〜46の熱膨張係数と異ならせて形成し、ソルダーレジストと樹脂絶縁層との熱膨張係数差を利用して配線基板を反らせてもよい。   In the above embodiment, the wiring substrate 40 having a warp is produced using thermal stress caused by the difference in thermal expansion coefficients of the resin insulating layers 43 to 46. However, the present invention is not limited to this. Absent. For example, you may produce the wiring board 40 which has curvature by embossing using a shaping die. Moreover, in the wiring board which covers the outermost layer of the substrate with the solder resist, the thermal expansion coefficient of the solder resist is made different from the thermal expansion coefficient of the resin insulating layers 43 to 46, and the heat of the solder resist and the resin insulating layer is formed. The wiring board may be warped using a difference in expansion coefficient.

・上記実施の形態では、反りを有する配線基板40とスティフナ31とを個々に作製した後、それら配線基板40とスティフナ31とを接合してスティフナ付き配線基板11を作製するものであったが、これに限定されるものではない。例えば、配線基板40となるべき製品領域が複数形成された多数個取り用配線基板を作製し、その多数個取り用配線基板の製品領域にスティフナ31をそれぞれ接着固定する。そして、スティフナ31の接着固定後において、多数個取り用配線基板を切断することで、スティフナ付配線基板11を複数同時に作製してもよい。この多数個取り用配線基板においても、樹脂絶縁層43〜45と樹脂絶縁層46との熱膨張係数差により基板主面41側が凹となる反りを発生させる。そして、スティフナ31の接着時の加熱処理によって、多数個取り用配線基板とスティフナ31との熱膨張係数差により反りを解消する方向に配線基板を変形させる。このようにしても、反りの少ないフラットな形状のスティフナ付き配線基板11を製造することができる。   In the above embodiment, after the wiring board 40 and the stiffener 31 having warpage are individually manufactured, the wiring board 40 and the stiffener 31 are joined to manufacture the wiring board 11 with the stiffener. It is not limited to this. For example, a multi-cavity wiring board in which a plurality of product areas to be the wiring board 40 is formed is manufactured, and the stiffeners 31 are bonded and fixed to the product areas of the multi-cavity wiring board. Then, after the stiffener 31 is bonded and fixed, a plurality of wiring boards 11 with stiffeners may be simultaneously produced by cutting the multi-wiring board. Also in this multi-cavity wiring board, a warp in which the substrate main surface 41 side becomes concave due to the difference in thermal expansion coefficient between the resin insulating layers 43 to 45 and the resin insulating layer 46 is generated. Then, the heat treatment at the time of bonding of the stiffener 31 causes the wiring board to be deformed in a direction to eliminate the warp due to the difference in thermal expansion coefficient between the multi-piece wiring board and the stiffener 31. Even in this manner, the wiring board 11 with a stiffener having a flat shape with little warpage can be manufactured.

・上記実施の形態のスティフナ付き配線基板11では、補強材として銅からなるスティフナ31を用いたが、銅以外の金属製のスティフナを用いてもよいし、セラミック製のスティフナや樹脂製のスティフナを用いてもよい。さらに、樹脂材料からなる基材の表面に金属板やセラミック板を貼り付けてなるスティフナを用いてもよい。   In the wiring board 11 with a stiffener of the above embodiment, the stiffener 31 made of copper is used as a reinforcing material, but a metal stiffener other than copper may be used, or a ceramic stiffener or a resin stiffener is used. It may be used. Furthermore, you may use the stiffener which affixes a metal plate and a ceramic board on the surface of the base material which consists of resin materials.

11…補強材付き配線基板としてのスティフナ付き配線基板
21…半導体集積回路チップとしてのICチップ
31…補強材としてのスティフナ
35…開口部
40…配線基板
41…基板主面
42…基板裏面
43〜46…樹脂絶縁層
48…無機材料としてのガラスクロス
51…導体層
52…主面側接続端子としての端子パッド
57…ビア導体
DESCRIPTION OF SYMBOLS 11 ... Wiring board with a stiffener as a wiring board with a reinforcing material 21 ... IC chip as a semiconductor integrated circuit chip 31 ... Stiffener as a reinforcing material 35 ... Opening 40 ... Wiring board 41 ... Substrate main surface 42 ... Substrate back surface 43-46 ... Resin insulation layer 48 ... Glass cloth as inorganic material 51 ... Conductive layer 52 ... Terminal pad as main surface side connection terminal 57 ... Via conductor

Claims (7)

基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設された配線基板と、
前記基板主面側にのみ接合され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材と
を備える補強材付き配線基板の製造方法であって、
前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも大きい場合には前記基板主面側が凹となる反りを有する配線基板を作製し、前記複数の樹脂絶縁層のうち層数が最も多いものの熱膨張係数が前記補強材の熱膨張係数よりも小さい場合には前記基板裏面側が凹となる反りを有する配線基板を作製する配線基板作製工程と、
反りを有する前記配線基板の前記基板主面に前記補強材を接着する接着工程と
を含むことを特徴とする補強材付き配線基板の製造方法。
A plurality of main surface side connections that have a substrate main surface and a substrate back surface, have a structure in which a plurality of resin insulating layers and a plurality of conductor layers are laminated without including a core substrate, and can connect a semiconductor integrated circuit chip. A wiring board having terminals disposed on the board main surface;
A method of manufacturing a wiring board with a reinforcing material, comprising: a reinforcing material that is bonded only to the main surface side of the substrate and has an opening through which the plurality of main surface side connection terminals are exposed;
When the thermal expansion coefficient though out layer highest number of said plurality of resin insulation layer is greater than the thermal expansion coefficient of the reinforcement to produce a wiring board having a warp which the substrate main surface is concave, the plurality When the thermal expansion coefficient of the resin insulation layer having the largest number of layers is smaller than the thermal expansion coefficient of the reinforcing material, a wiring board manufacturing step of manufacturing a wiring board having a warp in which the back side of the substrate is concave,
And a bonding step of bonding the reinforcing material to the main surface of the wiring board having warpage.
前記接合工程前における前記配線基板の前記反りの大きさが100μm以上500μm以下であり、前記接合工程後における前記配線基板の前記反りの大きさが0μm以上50μm以下であることを特徴とする請求項1に記載の補強材付き配線基板の製造方法。   The size of the warp of the wiring substrate before the bonding step is 100 μm or more and 500 μm or less, and the size of the warp of the wiring substrate after the bonding step is 0 μm or more and 50 μm or less. A manufacturing method of a wiring board with a reinforcing material according to 1. 前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径していることを特徴とする請求項1または2に記載の補強材付き配線基板の製造方法。   The plurality of via conductors are formed in the plurality of resin insulation layers, and the plurality of via conductors are expanded in the same direction in each layer of the plurality of resin insulation layers. The manufacturing method of the wiring board with a reinforcing material of description. 前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板裏面となる側に配置して積層を行うことで、前記基板主面側が凹となる反りを有する配線基板を作製することを特徴とする請求項1乃至3のいずれか1項に記載の補強材付き配線基板の製造方法。   In the wiring board manufacturing step, at least one resin insulating layer made of a material having a relatively small coefficient of thermal expansion compared to the other of the plurality of resin insulating layers is arranged on the side to be the back surface of the substrate and laminated. 4. The method of manufacturing a wiring board with a reinforcing material according to claim 1, wherein a wiring board having a warp in which the main surface side of the board is concave is manufactured. 前記配線基板作製工程において、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層を前記基板主面となる側に配置して積層を行うことで、前記基板裏面側が凹となる反りを有する配線基板を作製することを特徴とする請求項1乃至3のいずれか1項に記載の補強材付き配線基板の製造方法。   In the wiring board manufacturing step, at least one resin insulation layer made of a material having a relatively small coefficient of thermal expansion as compared with the other of the plurality of resin insulation layers is disposed on the substrate main surface side. The method of manufacturing a wiring board with a reinforcing material according to any one of claims 1 to 3, wherein a wiring board having a warp in which the back surface side of the board is concave is produced by stacking. 前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる少なくとも1つの樹脂絶縁層は、樹脂材料中に無機材料を含有させた複合材料からなることを特徴とする請求項4または5に記載の補強材付き配線基板の製造方法。   At least one resin insulation layer made of a material having a relatively small coefficient of thermal expansion compared to the other of the plurality of resin insulation layers is made of a composite material containing an inorganic material in the resin material. The manufacturing method of the wiring board with a reinforcing material of Claim 4 or 5. 基板主面及び基板裏面を有し、コア基板を含まずに複数の樹脂絶縁層及び複数の導体層を積層してなる構造を有し、半導体集積回路チップを接続可能な複数の主面側接続端子が前記基板主面上に配設され、前記複数の主面側接続端子を露出させる開口部が貫通形成された補強材が接合されるべき配線基板であって、100μm以上500μm以下の大きさの反りを有し、前記複数の樹脂絶縁層には複数のビア導体が形成され、前記複数のビア導体は前記複数の樹脂絶縁層の各層において同一方向に拡径しており、前記複数の樹脂絶縁層のうち他のものと比べて相対的に熱膨張係数の小さい材料からなる樹脂絶縁層を少なくとも1つ有することを特徴とする補強材付き配線基板用の配線基板。 A plurality of main surface side connections that have a substrate main surface and a substrate back surface, have a structure in which a plurality of resin insulating layers and a plurality of conductor layers are laminated without including a core substrate, and can connect a semiconductor integrated circuit chip. A wiring board to which a reinforcing material having terminals disposed on the main surface of the substrate and having openings through which the plurality of main surface side connection terminals are exposed is to be bonded, and having a size of 100 μm or more and 500 μm or less has a warp, the the plurality of resin insulation layer is formed with a plurality of via conductors, the plurality of via conductors are then expanded in the same direction in each layer of the plurality of resin insulation layers, the plurality of resin A wiring board for a wiring board with a reinforcing material, comprising at least one resin insulating layer made of a material having a relatively small coefficient of thermal expansion as compared with the other insulating layers .
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