JPH0199227A - Hybrid integrated circuit structure - Google Patents
Hybrid integrated circuit structureInfo
- Publication number
- JPH0199227A JPH0199227A JP62256872A JP25687287A JPH0199227A JP H0199227 A JPH0199227 A JP H0199227A JP 62256872 A JP62256872 A JP 62256872A JP 25687287 A JP25687287 A JP 25687287A JP H0199227 A JPH0199227 A JP H0199227A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- elastic connector
- heat dissipation
- top plate
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 59
- 239000004020 conductor Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims abstract description 7
- 230000017525 heat dissipation Effects 0.000 claims description 35
- 238000009413 insulation Methods 0.000 claims description 3
- 239000010408 film Substances 0.000 description 28
- 239000002184 metal Substances 0.000 description 11
- 229910052751 metal Inorganic materials 0.000 description 11
- 229920001721 polyimide Polymers 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 8
- 239000000919 ceramic Substances 0.000 description 6
- 239000012790 adhesive layer Substances 0.000 description 5
- 239000013039 cover film Substances 0.000 description 5
- 230000010354 integration Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 3
- 239000011889 copper foil Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000010410 layer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229920002379 silicone rubber Polymers 0.000 description 2
- 239000004945 silicone rubber Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 1
- 230000005489 elastic deformation Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔概要〕
混成集積回路構造に関し、
放熱性及び高周波特性の向上及び電気的接続の改善を可
能とすることを目的とし、
放熱性に優れた基板と、該放熱基板に搭載された半導体
チップと、該半導体チップの上面に搭載された、厚み方
向に導電性を有し面方向には絶縁性を有するチップ状の
エラスチックコネクタと、その底面に、深さ寸法が上記
半導体チップとエラスチックコネクタとを合せた厚さ寸
法より若干小さく、形状が上記半導体チップに対応した
天板部付の凹部を有し、且つ上記天板部の下面に張り出
した電極導体を有し、更に配線用導体を有する誘電率の
低い材質製のフィルム体と、該フィルム体に搭載された
チップ部品とよりなり、上記フィルム体が、上記半導体
チップが搭載された放熱基板上に、上記凹部内に上記半
導体チップが嵌合し、且つ上記天板部が上記エラスチッ
クコネクタにより上方に相対的に弾性変形せしめられた
状態で接着固定されてなり、上記電極導体が上記天板部
自体の弾性力により上記エラスチックコネクタに押圧さ
れ、上記半導体チップ上の電極パッドと上記電極導体と
が上記エラスチックコネクタを介して電気的に接続され
るように構成する。[Detailed Description of the Invention] [Summary] The purpose of the present invention is to provide a substrate with excellent heat dissipation properties and a substrate with excellent heat dissipation properties, and to make it possible to improve heat dissipation properties and high frequency characteristics and improve electrical connections regarding hybrid integrated circuit structures. A mounted semiconductor chip, a chip-shaped elastic connector mounted on the top surface of the semiconductor chip and having conductivity in the thickness direction and insulation in the surface direction, and a semiconductor chip having the depth dimension described above on the bottom surface. It has a recess with a top plate portion that is slightly smaller than the combined thickness of the chip and the elastic connector and has a shape corresponding to the semiconductor chip, and has an electrode conductor projecting from the bottom surface of the top plate portion, and further It consists of a film body made of a material with a low dielectric constant and having a wiring conductor, and a chip component mounted on the film body, and the film body is placed in the recess on the heat dissipation board on which the semiconductor chip is mounted. The semiconductor chip is fitted, and the top plate is adhesively fixed in a state in which it is relatively elastically deformed upward by the elastic connector, and the electrode conductor is connected to the top plate by the elastic force of the top plate itself. The elastic connector is pressed so that the electrode pads on the semiconductor chip and the electrode conductors are electrically connected via the elastic connector.
〔産業上の利用分野〕 本発明は混成集積回路構造に関する。[Industrial application field] The present invention relates to hybrid integrated circuit structures.
混成集積回路構造は大規模集積化の方向にあり、これに
伴ない、放熱性及び高周波特性の向上、及び接続作業の
改善が必要とされる。Hybrid integrated circuit structures are moving toward large-scale integration, and this requires improvements in heat dissipation and high frequency characteristics, as well as improvements in connection work.
従来の混成集積回路構造を第8図に示す。図中、1は半
導体チップ、2 1.2 2はチップ部品であり、共に
共通のセラミック基板3上に搭載しである。A conventional hybrid integrated circuit structure is shown in FIG. In the figure, 1 is a semiconductor chip and 2 1.2 2 are chip components, both of which are mounted on a common ceramic substrate 3.
半導体チップ1の上面の各電極パッド4と、半導体チッ
プ1の周辺のセラミック基板3上の電極パッド5との間
はワイヤ6により接続しである。Each electrode pad 4 on the upper surface of the semiconductor chip 1 and the electrode pad 5 on the ceramic substrate 3 around the semiconductor chip 1 are connected by wires 6.
7は配線用導体であり、セラミック基板3上に形成しで
ある。Reference numeral 7 denotes a wiring conductor, which is formed on the ceramic substrate 3.
〔発明が解決しようとする問題点)
上記の混成集積回路構造では、その放熱性及び高周波特
性はセラミック基板3により決定されるものであり、大
規模集積化に伴う上記両者の特性の向上に対応できない
という問題点があった。[Problems to be Solved by the Invention] In the above-mentioned hybrid integrated circuit structure, its heat dissipation and high frequency characteristics are determined by the ceramic substrate 3, and it is necessary to respond to the improvement of both of the above characteristics with large-scale integration. The problem was that it couldn't be done.
また大規模集積化に伴い、ワイヤボンディングの接続作
業工数も増加してしまうという問題点があった。Furthermore, with large-scale integration, there is a problem in that the number of man-hours required for wire bonding connection increases.
本発明は放熱性及び高周波特性の向上及び電気的接続の
改善を可能とじつる混成集積回路構造を提供することを
目的とする。SUMMARY OF THE INVENTION An object of the present invention is to provide a hybrid integrated circuit structure capable of improving heat dissipation and high frequency characteristics, and improving electrical connections.
本発明の混成集積回路構造は、放熱性に優れた基板と、
該放熱基板に搭載された半導体チップと、該半導体チッ
プの上面に搭載された、厚み方向に導電性を有し面方向
には絶縁性を有するチップ状のエラスチックコネクタと
、その底面に、深さ寸法が上記半導体チップとエラスチ
ックコネクタとを合せた厚さ寸法より若干小さく、形状
が上記半導体チップに対応した天板部付の凹部を有し、
且つ上記天板部の下面に張り出した電極導体を有し、更
に配線用導体を有する誘電率の低い材質製のフィルム体
と、該フィルム体に搭載されたチップ部品とよりなり、
上記フィルム体が、上記半導体チップが搭載された放熱
基板上に、上記凹部内に上記半導体チップが嵌合し、且
つ上記天板部が上記エラスチックコネクタにより上方に
相対的に弾性変形せしめられた状態で接着固定されてな
り、上記電極導体が上記天板部自体の弾性力により上記
エラスチックコネクタに押圧され、上記半導体チップ上
の電極パッドと上記電極導体とが上記エラスチックコネ
クタを介して電気的に接続されてなる構成である。The hybrid integrated circuit structure of the present invention includes a substrate with excellent heat dissipation,
A semiconductor chip mounted on the heat dissipation board, a chip-shaped elastic connector mounted on the top surface of the semiconductor chip and having conductivity in the thickness direction and insulation in the surface direction, and a The dimensions are slightly smaller than the combined thickness of the semiconductor chip and the elastic connector, and the shape has a recess with a top plate corresponding to the semiconductor chip,
and a film body made of a material with a low dielectric constant, which has an electrode conductor protruding from the lower surface of the top plate part and further has a wiring conductor, and a chip component mounted on the film body,
A state in which the film body is placed on a heat dissipation board on which the semiconductor chip is mounted, the semiconductor chip is fitted into the recess, and the top plate portion is relatively elastically deformed upward by the elastic connector. The electrode conductor is pressed against the elastic connector by the elastic force of the top plate itself, and the electrode pad on the semiconductor chip and the electrode conductor are electrically connected via the elastic connector. The structure consists of:
放熱基板は放熱性を向上させ、誘電率の低い材質製のフ
ィルム体は高周波特性を向上させる。The heat dissipation substrate improves heat dissipation, and the film body made of a material with a low dielectric constant improves high frequency characteristics.
エラスチックコネクタを使用し、フィルム体の凹部の深
さ寸法を上記のように定めであることにより、半導体チ
ップの電極パッドと電極導体との電気的接続が簡単とな
る。By using an elastic connector and determining the depth of the recess in the film body as described above, electrical connection between the electrode pads of the semiconductor chip and the electrode conductor becomes easy.
これらにより、混成集積回路の大規模化に伴う諸問題を
解決することが可能となる。These make it possible to solve various problems associated with increasing the scale of hybrid integrated circuits.
第1図は本発明の一実施例による混成集積回路構造の一
部を示す断面図、第2図はこれを分解して示す図である
。FIG. 1 is a sectional view showing a part of a hybrid integrated circuit structure according to an embodiment of the present invention, and FIG. 2 is an exploded view of the structure.
各図中、10は半導体デツプ、11−1,11−2はチ
ップ部品である。In each figure, 10 is a semiconductor depth, and 11-1 and 11-2 are chip components.
12は放熱性に優れた基板であり、具体的には全屈板で
ある。Reference numeral 12 denotes a substrate with excellent heat dissipation, specifically a fully bent plate.
放熱基板12の上面には接着剤層13があり、半導体チ
ップ10はこの接着剤層13に接着されて放熱基板12
に搭載しである。There is an adhesive layer 13 on the upper surface of the heat dissipation board 12 , and the semiconductor chip 10 is adhered to this adhesive layer 13 and attached to the heat dissipation board 12 .
It is equipped with.
14はエラスチックコネクタであり、第3図及び第4図
に併せて示すように、シリコンゴム板15にその厚さ方
向に多数本の金属線片16が貫通して上下面に露出して
設けられた構造であり、厚さ方向に導電性を有し面方向
には絶縁性を有する。14 is an elastic connector, and as shown in FIGS. 3 and 4, a large number of metal wire pieces 16 are provided through a silicone rubber plate 15 in its thickness direction and exposed on the top and bottom surfaces. The structure is conductive in the thickness direction and insulating in the surface direction.
エラスチックコネクタ14は、半導体チップ10の平面
形状と同一形状を有し、金属線片16は半導体チップ1
0の上面の電極パッド17の配置と同じ配置で配されて
いる。The elastic connector 14 has the same planar shape as the semiconductor chip 10, and the metal wire piece 16 has the same planar shape as the semiconductor chip 10.
They are arranged in the same arrangement as the electrode pads 17 on the top surface of No.
このエラスチックコネクタ14は、各金属線片16の下
端をこれと対応する電極パッド17と接触させて、半導
体デツプ10の上面に搭載しである。This elastic connector 14 is mounted on the upper surface of the semiconductor dip 10 with the lower end of each metal wire piece 16 in contact with the corresponding electrode pad 17.
なお、金属線片16のピッチpは0.1M程度にまで狭
くすることが出来、電極パッド17のピッチが小となっ
ても適応できる。Note that the pitch p of the metal wire pieces 16 can be reduced to about 0.1M, and even if the pitch of the electrode pads 17 is small, it can be applied.
20はポリイミド製フィルム体であり、ポリイミド製の
ベースフィルム21と、この上側のポリイミド製のカバ
ーフィルム22とよりなる二層構造である。Reference numeral 20 denotes a polyimide film body, which has a two-layer structure consisting of a polyimide base film 21 and a polyimide cover film 22 above it.
フィルム体20には天板部付凹部23が形成しである。A recess 23 with a top plate portion is formed in the film body 20.
天板部24はカバーフィルム22により形成しである。The top plate portion 24 is formed from the cover film 22.
この天板部24の厚さは薄く、可撓性を有する。This top plate portion 24 is thin and flexible.
フィルム体20は放熱基板12と同じ形状を有し、凹部
23は放熱基板12上の半導体チップ10の搭載部位に
対応して形成しである。The film body 20 has the same shape as the heat dissipation board 12, and the recess 23 is formed to correspond to the mounting portion of the semiconductor chip 10 on the heat dissipation board 12.
各凹部23は半導体チップ10の形状に対応した形状を
有する。その深さ寸法dは、半導体チップ10の厚さ寸
法tt とエラスチックコネクタ14の厚さ寸法t2と
を加算した寸法tより若干小さく定めである。Each recess 23 has a shape corresponding to the shape of the semiconductor chip 10. The depth dimension d is determined to be slightly smaller than the dimension t which is the sum of the thickness dimension tt of the semiconductor chip 10 and the thickness dimension t2 of the elastic connector 14.
25は複数の電極導体であり、第5図に示すように、天
板部24の下面に、凹部23の周囲より四部23の内部
に張り出して設けである。第5図は天板部24を除去し
て電極導体25の配置を示す。また、第5図では、エラ
スチックコネクタ14も省略してあり、各電極導体25
は、先端部25aが電極パッド17に対向するように形
成しである。エラスチックコネクタ14についてみると
、各電極導体25の先端は、下端が電極パッド17に接
触した金属線片16の上端に対向する。Reference numeral 25 denotes a plurality of electrode conductors, which are provided on the lower surface of the top plate portion 24 so as to protrude from the periphery of the recessed portion 23 into the interior of the four portions 23, as shown in FIG. FIG. 5 shows the arrangement of the electrode conductors 25 with the top plate portion 24 removed. Further, in FIG. 5, the elastic connector 14 is also omitted, and each electrode conductor 25
is formed so that the tip portion 25a faces the electrode pad 17. Regarding the elastic connector 14, the tip of each electrode conductor 25 faces the upper end of the metal wire piece 16 whose lower end is in contact with the electrode pad 17.
26は配線用導体であり、フィルム体20の上面又は内
部に形成しである。26 is a wiring conductor, which is formed on the top surface or inside the film body 20.
上記構成のフィルム体20上に、チップ部品11−+
、 11−2が半田付けされて搭載しである。On the film body 20 having the above structure, the chip component 11-+
, 11-2 is soldered and installed.
フィルム体20は、凹部23内に半導体チップ10が嵌
合した状態で、ベースフィルム21の下面を接着剤層1
3と接着固定しである。With the semiconductor chip 10 fitted into the recess 23, the film body 20 covers the lower surface of the base film 21 with the adhesive layer 1.
3 and fixed with adhesive.
各電極導体25の先端部25aは、エラスチックコネク
タ14の金属線片16の上端に接触している。The tip portion 25a of each electrode conductor 25 is in contact with the upper end of the metal wire piece 16 of the elastic connector 14.
こ)で、d<tであるため、天板部24はエラスチック
コネクタ15により上方に相対的に押し上げられて若干
脹らんだように弾性変形しており、天板部24には矢印
27で示す下向きの力F1が蓄勢された状態となってい
る。In this case, since d<t, the top plate portion 24 is relatively pushed upward by the elastic connector 15 and is elastically deformed as if slightly inflated. The downward force F1 is in a stored state.
各電極導体25は天板部24内体に蓄勢された力F1に
より下方に押し付けられており、先端部25aは対応す
る金属線片16の上端に押圧して接触した状態で、金R
1a片16と電気的に確実に接続されている。Each electrode conductor 25 is pressed downward by the force F1 stored in the inner body of the top plate portion 24, and the tip portion 25a is pressed against and in contact with the upper end of the corresponding metal wire piece 16.
It is electrically connected reliably to the piece 1a 16.
これにより、半導体チ・ツブ10の上面の電極バッド1
7と電極導体25とがエラスチックコネクタ14を介し
て接続されている。As a result, the electrode pad 1 on the top surface of the semiconductor chip 10
7 and an electrode conductor 25 are connected via an elastic connector 14.
上記の混成集積回路構造によれば、以下に挙げる効果を
有する。The above hybrid integrated circuit structure has the following effects.
■ 放熱性が良い。■ Good heat dissipation.
混成集積回路構造のうち主な発熱体は半導体チップ10
である。この半導体チップ10は金屈板である放熱基板
2に搭載してあり、この放熱基板2の熱伝導率はセラミ
ック基板に比べて高い。このため半導体チップ10の熱
は放熱基板2を通して良好に逃がされ、放熱性は向上し
、大規模集積化されても十分な放熱性を有する。The main heating element in the hybrid integrated circuit structure is the semiconductor chip 10.
It is. This semiconductor chip 10 is mounted on a heat dissipation board 2 which is a bent metal plate, and the heat conductivity of this heat dissipation board 2 is higher than that of a ceramic substrate. Therefore, the heat of the semiconductor chip 10 is efficiently dissipated through the heat dissipation substrate 2, and the heat dissipation performance is improved, and even when integrated on a large scale, the semiconductor chip 10 has sufficient heat dissipation performance.
■ 高周波特性がよい。■ Good high frequency characteristics.
配線用導体26はポリイミド製フィルム体20上に形成
しである。ポリイミドの誘電率は約4であり、セラミッ
クの誘電率(約9)より低い。このため、上記の混成集
積回路構造は従来に比べて(至)れた高周波特性を有す
る。The wiring conductor 26 is formed on the polyimide film body 20. The dielectric constant of polyimide is about 4, which is lower than the dielectric constant of ceramic (about 9). Therefore, the above-described hybrid integrated circuit structure has higher frequency characteristics than the conventional one.
従って、大規模集積化しても、混成集積回路は高周波特
性に優れ、高速信号に好適となる。Therefore, even when integrated on a large scale, hybrid integrated circuits have excellent high frequency characteristics and are suitable for high-speed signals.
■ 接続が改善される。■ Connection is improved.
半導体チップ10の電極バッド17と電極導体25とが
エラスチックコネクタ14を介して電気的に接続された
構造であり、電極導体25とエラスチックコネクタ14
との間の電気的接続は抑圧接触である。The electrode pad 17 of the semiconductor chip 10 and the electrode conductor 25 are electrically connected via the elastic connector 14.
The electrical connection between the two is a suppressive contact.
各半導体チップ10についての複数の電気的接続は、後
述するように、フィルム体20を爪ねて放熱基板12に
接着することにより、接続個所の数に関係なく一度に行
なわれる。従って上記の電気的接続は、従来のワイVボ
ンディングによる方法に比べて格段に作業付臭く行なわ
れる。A plurality of electrical connections for each semiconductor chip 10 are made at once, regardless of the number of connection points, by folding the film body 20 and adhering it to the heat dissipation substrate 12, as will be described later. Therefore, the above-mentioned electrical connection is much more labor intensive than the conventional wire-V bonding method.
またエラスチックコネクタ14を使用しているため、接
続個所の間隔を狭くした高密度配線ら可能となる。Furthermore, since the elastic connector 14 is used, high-density wiring with narrow intervals between connection points is possible.
またエラスチックコネクタ14を使用して押圧接触によ
り電気的接続がなされているため、他の接続手段に比べ
て半導体チップ10が故障したとぎの半導体チップの交
換が容易に可能となる。Further, since the electrical connection is made by pressure contact using the elastic connector 14, it is easier to replace the semiconductor chip 10 when the semiconductor chip 10 breaks down compared to other connection means.
更に、上記押圧力27は、天板部24自体に蓄勢された
弾性力F1により得ており、特別の押え金具は使用して
いず、この点でも電気的接続の構造は簡単である。Further, the pressing force 27 is obtained by the elastic force F1 stored in the top plate part 24 itself, and no special presser metal fittings are used, and the electrical connection structure is simple in this respect as well.
■ 製造作業性がよい。■ Good manufacturing workability.
後述するように、半導体チップ10とチップ部品11−
1,112とを夫々別の部材に搭載し、最後に両部材を
組み合わせる作業である。このため半導体チップ10の
搭載作業とチップ部品11−1,112の搭載作業とを
併行して行なうことが出来、製造作業性がよく、製造コ
ストを低減できる。As described later, the semiconductor chip 10 and the chip component 11-
1 and 112 on separate members, and finally, the two members are assembled. Therefore, the work of mounting the semiconductor chip 10 and the work of mounting the chip components 11-1 and 112 can be performed concurrently, which improves manufacturing efficiency and reduces manufacturing costs.
次に上記混成集積回路構造の製造方法について第6図を
参照する。Next, reference will be made to FIG. 6 for a method of manufacturing the above hybrid integrated circuit structure.
半導体チップ10については、同図(A)に示すように
、放熱基板12の上面に接着剤を塗布し、接着剤層13
に接着して搭載する。次いで同図(8)に示すように、
半導体チップ10上にエラスチックコネクタ14を搭載
する。As for the semiconductor chip 10, as shown in FIG.
Glue and install. Next, as shown in the same figure (8),
An elastic connector 14 is mounted on the semiconductor chip 10.
一方、チップ部品11−+ 、 11−2については、
同図(C)に示すポリイミドフィルム体20上に、同図
(D)に示すように、半田付は等により搭載する。On the other hand, regarding chip parts 11-+ and 11-2,
It is mounted on the polyimide film body 20 shown in (C) of the same figure by soldering or the like, as shown in (D) of the same figure.
同図(E)に示すように、ポリイミドフィルム体20を
、その凹部23を半導体チップ10と嵌合させて、放熱
基板12上に載置する。d<tであるため、天板部24
がエラスチックコネクタ14に当接し、フィルム体20
と放熱基板12との間には隙間Qが形成される。As shown in FIG. 1E, the polyimide film body 20 is placed on the heat dissipation substrate 12 with its recess 23 fitted with the semiconductor chip 10. Since d<t, the top plate portion 24
contacts the elastic connector 14, and the film body 20
A gap Q is formed between and the heat dissipation board 12.
この状態で矢印28で示す圧力F2を加え、フィルム体
20を放熱基板12に接着固定する。このとき、天板部
24が相対的に上方に押し上げられて弾性変形し、この
とき天板部24に前記の弾性力F1が蓄勢され、この弾
性力F1により電極導体25がエラスチックコネクタ1
4へ押付けられる。従って押え金具は不要である。In this state, a pressure F2 indicated by an arrow 28 is applied to adhesively fix the film body 20 to the heat dissipation substrate 12. At this time, the top plate part 24 is pushed up relatively and deformed elastically, and at this time, the above-mentioned elastic force F1 is stored in the top plate part 24, and this elastic force F1 causes the electrode conductor 25 to move to the elastic connector 1.
Pushed to 4. Therefore, no presser fitting is required.
また電気的接続は、フィルム体20を載置して接着J”
ろ過程で、−括して行なわれる。In addition, for electrical connection, place the film body 20 and glue J"
This is done in batches during the filtering process.
また、半導体チップ10の搭載、チップ部品11−+
、 11−2の搭載、及び半導体チップ10とチップ部
品111.11−2との組み合せとを夫々併行して行な
うことが出来、製造作業性の点でも従来のものに比べて
良好となる。In addition, the mounting of the semiconductor chip 10, the chip component 11-+
, 11-2 and the combination of the semiconductor chip 10 and the chip components 111, 11-2 can be carried out simultaneously, and the manufacturing workability is also improved compared to the conventional one.
最後にポリイミド製フィルム体20の製造方法について
第7図を参照して説明する。Finally, a method for manufacturing the polyimide film body 20 will be explained with reference to FIG. 7.
まず同図(A)に示すように、厚さがtlのベースフィ
ルム21の上面に接着剤H30を形成する。First, as shown in FIG. 3A, an adhesive H30 is formed on the upper surface of the base film 21 having a thickness of tl.
次いで同図(B)に示すようにベースフィルム21の所
定部位に半導体チップ10の形状に対応した形状の開口
31をパンチで形成する。Next, as shown in FIG. 2B, an opening 31 having a shape corresponding to the shape of the semiconductor chip 10 is formed in a predetermined portion of the base film 21 using a punch.
次いで、同図(C)に示すように、ベースフィルム21
の上面に銅箔32を貼着する。Next, as shown in the same figure (C), the base film 21
Copper foil 32 is pasted on the top surface of.
次に、同図(D)に示すように、銅箔32の上面にレジ
ストを塗布してレジスト層33を形成する。Next, as shown in FIG. 3D, a resist is applied to the upper surface of the copper foil 32 to form a resist layer 33.
次に同図(E)に示すように、上面のレジスト層をバタ
ーニングし、下面をテープ34でマスキングする。Next, as shown in FIG. 3E, the upper resist layer is patterned, and the lower surface is masked with tape 34.
次に同図(F)に示すように、銅箔32をエツチングし
、同図(G)に示ザように、レジス]−及びテープ34
を除去して電極導体25及び配線用導体26付きのベー
スフィルム21を19る。Next, as shown in Figure (F), the copper foil 32 is etched, and as shown in Figure (G), the resist and tape 34 are etched.
is removed, and the base film 21 with the electrode conductor 25 and the wiring conductor 26 is separated.
一方、同図(H)に示−ff 、にうに、厚さがt2の
カバーフィルム22の下面に接着剤層35を形成し、同
図(1)に示ずように所定部位にパンチて゛穴36を開
ける。On the other hand, as shown in Figure (H), an adhesive layer 35 is formed on the lower surface of the cover film 22 with a thickness of t2, and holes are punched at predetermined locations as shown in Figure (1). Open 36.
このカバーフィルム22と上記のベースフィルム21と
を同図(J)に示すように貼り合し、フィルム体20を
496゜
まlζフィルム体20はポリエステル製でしよい。This cover film 22 and the above-mentioned base film 21 are pasted together as shown in FIG.
以上説明した様に、本発明によれば、発熱体である半導
体チップが放熱性を有する放熱!lt板に搭載された4
14造であるため、放熱性の向上を図ることが出来る。As explained above, according to the present invention, the semiconductor chip, which is a heating element, has heat dissipation properties! 4 mounted on the lt board
Since it is made of 14-piece construction, it is possible to improve heat dissipation.
配線導体は誘電率の低い材質製のフィルム体に形成しで
あるため、高周波特性の改善を図ることが出来る。これ
により、大規模集積化により顕在化する放熱+!1及び
高周波特性の両方の問題を解決することが出来、大規模
集積化を実現出来る。Since the wiring conductor is formed of a film body made of a material with a low dielectric constant, it is possible to improve high frequency characteristics. As a result, heat dissipation becomes more apparent due to large-scale integration! It is possible to solve both the problems of 1 and high frequency characteristics, and large-scale integration can be realized.
また半導体チップの電極パッドとの電気的接続がエラス
チックコネクタを介して行なわれるため、ワイヤボンデ
ィングに比べて、高密度配線が可能となり、接続作業性
も向上する。また半導体チップが故障したときの交換作
業が容易となる。Furthermore, since the electrical connection with the electrode pads of the semiconductor chip is made via the elastic connector, higher density wiring is possible than with wire bonding, and connection workability is improved. Furthermore, replacement work when a semiconductor chip breaks down becomes easier.
また押圧接触力は天板部の弾性変形により天板部自体に
蓄勢された力により得られるため、押圧力を与えるため
の金具は不要であり、接続構造を簡単に出来る。Further, since the pressing contact force is obtained from the force stored in the top plate itself due to the elastic deformation of the top plate, there is no need for metal fittings to apply the pressing force, and the connection structure can be simplified.
また、半導体チップは放熱基板に、チップ部品はフィル
ム体にと別々の部材に搭載されているため、上記の搭載
作業を併行して行なうことにより、生産性の向上を図る
ことも出来る。Furthermore, since the semiconductor chip is mounted on the heat dissipation board and the chip components are mounted on the film body, which are separate members, it is possible to improve productivity by performing the above-mentioned mounting operations in parallel.
第1図は本発明の一実施例の一部の断面図、第2図は第
1図に示す一実施例を分解して示す図、
第3図は第1図及び第2図中のエラスチックコネクタの
斜視図、
第4図はその一部の拡大断面図、
第5図は電極導体の配置を半導体チップと対応させて示
す図、
第6図は第1図の混成集積回路構造の製造工程を示す図
、
第7図は第1図、第2図、第6図中のフィルム体の製造
工程を示す図、
第8図は従来例を示す図である。
図中において、
1′0は半導体チップ、
11−1.112はデツプ部品、
12は放熱基板、
13は接着剤層、
14はエラスチックコネクタ、
15はシリコンゴム板、
16は金属線片、
17は電極パッド、
20はポリイミド製フィルム体、
21はベースフィルム、
22はカバーフィルム、
23は天板部イ・J凹部、
24は天板部、
25は電極導体、
25aは先端部、
2Gは配線用導体、
27は力を示す矢印、
28は圧力を示す矢印
を示す。
工θス+マ2コ+2ph’iP榊見図
第4図
男5図
本護シ哨の爽シ旨fitボす図
第1図
纂2図
第8図Fig. 1 is a cross-sectional view of a part of an embodiment of the present invention, Fig. 2 is an exploded view of the embodiment shown in Fig. 1, and Fig. 3 is an elastic material shown in Figs. FIG. 4 is a perspective view of the connector; FIG. 4 is an enlarged sectional view of a portion thereof; FIG. 5 is a diagram showing the arrangement of electrode conductors in correspondence with the semiconductor chip; FIG. 6 is a manufacturing process for the hybrid integrated circuit structure shown in FIG. 1. FIG. 7 is a diagram showing the manufacturing process of the film body in FIGS. 1, 2, and 6, and FIG. 8 is a diagram showing a conventional example. In the figure, 1'0 is a semiconductor chip, 11-1.112 is a deep part, 12 is a heat dissipation board, 13 is an adhesive layer, 14 is an elastic connector, 15 is a silicone rubber plate, 16 is a metal wire piece, and 17 is a Electrode pad, 20 is a polyimide film body, 21 is a base film, 22 is a cover film, 23 is a top plate A/J recess, 24 is a top plate, 25 is an electrode conductor, 25a is a tip, 2G is for wiring A conductor, 27 indicates an arrow indicating force, and 28 indicates an arrow indicating pressure. Work θ S + Pussy 2 Ko + 2 ph'iP Sakakimi diagram Figure 4 Male figure 5 Book Refreshment of the guard's body Figure 1 Figure 2 Figure 8
Claims (1)
と、 該半導体チップ(10)の上面に搭載された、厚み方向
に導電性を有し面方向には絶縁性を有するチップ状のエ
ラスチックコネクタ(14)と、その底面に、深さ寸法
(d)が上記半導体チップとエラスチックコネクタとを
合せた厚さ寸法(t)より若干小さく、形状が上記半導
体チップに対応した天板部付の凹部(23)を有し、且
つ上記天板部(24)の下面に張り出した電極導体(2
5)を有し、更に配線用導体(26)を有する誘電率の
低い材質製のフィルム体(20)と、該フィルム体(2
0)に搭載されたチップ部品(11−_1,11−_2
)とよりなり、 上記フィルム体(20)が、上記半導体チップ(10)
が搭載された放熱基板(12)上に、上記凹部(23)
内に上記半導体チップ(10)が嵌合し、且つ上記天板
部(24)が上記エラスチックコネクタ(14)により
上方に相対的に弾性変形せしめられた状態で接着固定さ
れてなり、上記電極導体(25)が上記天板部自体の弾
性力(F_1,27)により上記エラスチックコネクタ
(14)に押圧され、上記半導体チップ(10)上の電
極パッド(17)と上記電極導体(25)とが上記エラ
スチックコネクタ(14)を介して電気的に接続されて
なる構成を特徴とする混成集積回路構造。[Claims] A substrate (12) with excellent heat dissipation properties, and a semiconductor chip (10) mounted on the heat dissipation substrate (12).
A chip-shaped elastic connector (14) mounted on the top surface of the semiconductor chip (10) and having conductivity in the thickness direction and insulation in the surface direction, and a depth dimension (d) on the bottom surface thereof. ) is slightly smaller than the combined thickness dimension (t) of the semiconductor chip and the elastic connector, and has a recess (23) with a top plate portion whose shape corresponds to the semiconductor chip, and the top plate portion (24) ) protrudes from the bottom surface of the electrode conductor (2
5) and further includes a wiring conductor (26) and a film body (20) made of a material with a low dielectric constant;
Chip parts (11-_1, 11-_2) mounted on 0)
), and the film body (20) is the semiconductor chip (10).
The recess (23) is placed on the heat dissipation board (12) on which the
The semiconductor chip (10) is fitted therein, and the top plate (24) is adhesively fixed in a state in which it is relatively elastically deformed upward by the elastic connector (14), and the electrode conductor (25) is pressed against the elastic connector (14) by the elastic force (F_1, 27) of the top plate itself, and the electrode pad (17) on the semiconductor chip (10) and the electrode conductor (25) are pressed together. A hybrid integrated circuit structure characterized in that it is electrically connected via the elastic connector (14).
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62256872A JP2504486B2 (en) | 1987-10-12 | 1987-10-12 | Hybrid integrated circuit structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62256872A JP2504486B2 (en) | 1987-10-12 | 1987-10-12 | Hybrid integrated circuit structure |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0199227A true JPH0199227A (en) | 1989-04-18 |
JP2504486B2 JP2504486B2 (en) | 1996-06-05 |
Family
ID=17298588
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62256872A Expired - Fee Related JP2504486B2 (en) | 1987-10-12 | 1987-10-12 | Hybrid integrated circuit structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP2504486B2 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6822339B2 (en) | 2002-01-24 | 2004-11-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
KR100834466B1 (en) * | 2006-10-18 | 2008-06-05 | (주)선재하이테크 | A bar type ionizer using Piezo and nozzle |
JP2012023100A (en) * | 2010-07-12 | 2012-02-02 | Dainippon Printing Co Ltd | Wiring board equipped with buried component, and method of manufacturing wiring board equipped with buried component |
DE102016100585A1 (en) * | 2016-01-14 | 2017-07-20 | Epcos Ag | Device substrate with protective function and method of manufacture |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4814639B2 (en) | 2006-01-24 | 2011-11-16 | 富士通セミコンダクター株式会社 | Semiconductor device and manufacturing method of semiconductor device |
KR101046378B1 (en) * | 2008-01-10 | 2011-07-05 | 주식회사 하이닉스반도체 | Semiconductor package |
-
1987
- 1987-10-12 JP JP62256872A patent/JP2504486B2/en not_active Expired - Fee Related
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6822339B2 (en) | 2002-01-24 | 2004-11-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
DE10240415B4 (en) * | 2002-01-24 | 2011-09-22 | Mitsubishi Denki K.K. | A semiconductor device having a module embedded in a cavity and method for manufacturing the same |
KR100834466B1 (en) * | 2006-10-18 | 2008-06-05 | (주)선재하이테크 | A bar type ionizer using Piezo and nozzle |
JP2012023100A (en) * | 2010-07-12 | 2012-02-02 | Dainippon Printing Co Ltd | Wiring board equipped with buried component, and method of manufacturing wiring board equipped with buried component |
DE102016100585A1 (en) * | 2016-01-14 | 2017-07-20 | Epcos Ag | Device substrate with protective function and method of manufacture |
US11239010B2 (en) | 2016-01-14 | 2022-02-01 | Epcos Ag | Component substrate having a protective function |
Also Published As
Publication number | Publication date |
---|---|
JP2504486B2 (en) | 1996-06-05 |
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