WO2013000339A1 - 一种高倍聚光太阳能电池芯片 - Google Patents

一种高倍聚光太阳能电池芯片 Download PDF

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Publication number
WO2013000339A1
WO2013000339A1 PCT/CN2012/075135 CN2012075135W WO2013000339A1 WO 2013000339 A1 WO2013000339 A1 WO 2013000339A1 CN 2012075135 W CN2012075135 W CN 2012075135W WO 2013000339 A1 WO2013000339 A1 WO 2013000339A1
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Prior art keywords
solar cell
cell chip
chip according
concentration solar
gate
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PCT/CN2012/075135
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English (en)
French (fr)
Inventor
熊伟平
林桂江
宋明辉
吴志敏
梁兆煊
林志东
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厦门市三安光电科技有限公司
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Application filed by 厦门市三安光电科技有限公司 filed Critical 厦门市三安光电科技有限公司
Priority to US14/124,566 priority Critical patent/US9006562B2/en
Publication of WO2013000339A1 publication Critical patent/WO2013000339A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0224—Electrodes
    • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022433—Particular geometry of the grid contacts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy

Definitions

  • the invention relates to a high-concentration solar cell chip which is submitted to the Chinese Patent Office on June 28, 2011, and the application number is 201110176319.6, and the invention name is "a high-concentration solar cell chip," the priority of the Chinese patent application, The entire contents thereof are incorporated herein by reference.
  • the invention relates to a high-concentration solar cell chip, belonging to the field of semiconductor optoelectronic devices and technologies.
  • concentrating solar cells mostly use GaAs materials as multi-junction solar cells, and their concentrating ratio can reach 500 or even thousands of times with material performance and process technology, and the chip size is much smaller than that of conventional silicon materials. , greatly reducing the cost of semiconductor materials, is a solar cell with broad application prospects.
  • the photo-generated current generated by the solar cell chip will also increase proportionally. For example, under 1000 times of concentrating, the triple junction concentrating solar cell will generate a large-density current of 15-20 A/cm 2 , so high. The current density requires that the series resistance of the battery be small enough to reduce the resistive loss of the battery chip.
  • the current distribution is required to be sufficiently uniform to avoid current crowding, causing local overheating of the chip and seriously affecting the reliability of the chip. If the surface of the chip is evenly distributed, the currents inside and behind the epitaxial structure of the chip will be evenly distributed, but the problem of the upper electrode, especially the main gate current crowding, will not change due to the distribution of sunlight.
  • the main grid is an elongated regular rectangular structure, and the sub-gate is connected to the long side of the rectangle.
  • the current must flow through the main gate to the lead pad.
  • the resistor there are two extreme paths through which the current flows through the main gate. The first one is from the secondary gate. After that, it flows directly to the lead bonding area along the side of the main gate close to the sub-gate; the second line flows out from the sub-gate first, and then flows vertically to the edge of the main gate away from the side of the sub-gate, and then flows to the lead along the edge. Welding area. Obviously the current will flow along the first path with a shorter path.
  • Figure 1 to Figure 3 are schematic diagrams of a conventional electrode pattern and its current path, respectively.
  • a and B are the farthest and shortest extremes of the secondary gate electrode through the main gate to the lead soldering zone. Obviously, the current will flow along the shorter B route. All current flowing through the sub-gate will flow along the edge of the main gate near the side of the sub-gate, resulting in current crowding at high current density in the following figure; and current density on the main gate away from the sub-gate side 4 Small, the transmission of photogenerated current is not very large, actually wasting the effective illumination area of the battery surface. Summary of the invention
  • the present invention provides a high-concentration solar cell chip comprising an epitaxial layer structure, a patterned upper electrode formed on an upper surface of the epitaxial layer structure, and a lower surface formed on the epitaxial layer structure
  • the back electrode; the patterned upper electrode includes a main gate and a sub-gate, wherein the main gate is formed by a series of isosceles trapezoidal structures, the upper side of the trapezoid is on the same straight line, and points to the inside of the battery chip, below the upper side of the trapezoid
  • the area is the lead bonding area, and the sub-gate is connected to the two sides or the upper side of the trapezoidal main grid.
  • the number of isosceles trapezoids constituting the main grid is equal to the number of soldering leads on the main gate, and the area below the upper side of the trapezoid is a lead bonding area, and the length of the upper side is equal to the width of the lead bonding area in the direction perpendicular to the secondary gate. The length of the lower side is equal to the distance between the adjacent lead pads.
  • the sub-gates are equally spaced and are connected to the two waists or upper sides of the isosceles trapezoid forming the main grid.
  • the isosceles trapezoids constituting the main grid are sequentially arranged, the lower sides of the trapezoids are on the same straight line, the upper sides of the trapezoids are on the same straight line, and the upper sides of all the isosceles trapezoids are directed to the inside of the battery chip.
  • the main grid is two columns, which are oppositely distributed on both sides of the solar cell chip, wherein the upper side of the isosceles trapezoid is oppositely directed to the inside of the chip.
  • the main grids are arranged in four rows and distributed on four sides of the solar cell chip, and the upper sides of the two equal rows of the isosceles trapezoids are oppositely directed to the inside of the chip.
  • the length of the upper side of the isosceles trapezoid constituting the main grid is 0.1 to 2 mm
  • the length of the lower side is 2 to 5 mm
  • the height of the trapezoid is 0.1 to 1 mm.
  • the patterned upper electrode comprises: an ohmic contact layer covering the epitaxial layer structure, An adhesion layer overlying the ohmic contact layer, a conductive layer overlying the adhesion layer, and a protective layer overlying the conductive layer.
  • the surface of the patterned upper electrode and the exposed epitaxial layer is covered with an anti-reflection film.
  • the present invention has at least the following advantages:
  • the specially designed graphical upper electrode for the first time is effective in avoiding current crowding. Since the connection point between the secondary gate and the main grid is distributed on the two sides of the isosceles trapezoid or the upper side, that is, the hook is distributed in the direction perpendicular to the main grid, and according to the principle that the current is transmitted along the shortest path, the secondary gate is merged to the main The current of the gate will flow along the respective shortest path, and finally collect in the battery lead pad, thereby achieving uniform current spreading and avoiding the problem of current crowding.
  • the present invention avoids the problem of current crowding without increasing the resistive loss, increases the effective illumination area of the surface of the battery chip, and increases the photo-generated current, thereby improving the photoelectric conversion efficiency of the battery.
  • the present invention also optimizes the electrode multilayer structure, and the four-layer structure constituting the patterned upper electrode ensures good ohmic contact with the epitaxial layer of the battery while ensuring good electrical conductivity of the electrode.
  • the adhesion layer enhances the adhesion between the conductive layer and the ohmic contact layer, and prevents the two from interacting with each other due to diffusion;
  • the protective layer protects the conductive layer underneath to prevent oxidation and contamination, and at the same time, a suitable material may be selected Better wire bonding.
  • Figure 1 is a plan view of a conventional grid-like upper electrode.
  • Fig. 2 is a partial enlarged view of the grid-shaped upper electrode shown in Fig. 1.
  • FIG. 3 is a schematic diagram of the conventional patterned upper electrode current path shown in FIG. 1.
  • FIG. 4 is a side cross-sectional view of a high power concentrating solar cell chip in accordance with a preferred embodiment of the present invention.
  • Figure 5 is a plan view of a patterned upper electrode in accordance with a first preferred embodiment of the present invention.
  • 6 is a plan view of a patterned upper electrode according to another preferred embodiment of the present invention.
  • Figure 7 is a partial enlarged view of the patterned upper electrode main gate structure shown in Figure 5.
  • Figure 8 is a schematic diagram of the current path of the patterned upper electrode shown in Figure 5.
  • Figure 9 is a side cross-sectional view of a patterned upper electrode in accordance with a preferred embodiment of the present invention.
  • anti-reflection film 200 patterned upper electrode
  • main gate 202 lead bonding area
  • adhesion layer 206 conductive layer
  • protective layer 300 epitaxial layer structure
  • a high-concentration solar cell chip includes a high-concentration solar cell epitaxial layer structure 300, which is a tri-five compound, and may have a single junction or a multi-junction structure.
  • a specially designed patterned upper electrode 200 is formed on the upper surface of the epitaxial layer structure 300, and a back electrode 400 is formed on the lower surface of the epitaxial layer structure 300.
  • the upper electrode 200 and the exposed epitaxial layer 300 are covered with an anti-reflection film 100.
  • the patterned upper electrode 200 includes a main gate 201 and a sub-gate 203, wherein the main gate 201 is connected by a series of isosceles trapezoidal structures, and the trapezoid upper side b is on the same straight line and points to the battery.
  • the lead bonding area 202 Inside the chip.
  • the sub-gates 203 are equally spaced, and are connected to the two sides or the upper side of the trapezoidal main grid 201.
  • the number of the isosceles trapezoids of the main grid 201 is equal to the number of soldering leads on the main gate, and the area below the upper side of the trapezoid is the lead bonding area, and the length of the lower side a is adjacent to the adjacent lead.
  • the distance L between the weld zones is equal.
  • Ladder L-shaped upper side length b b according to the desired area of the welding wire determined by the size of the present invention, in a preferred embodiment, the upper side length L b with b equal to the wire bonding area along the width direction perpendicular to the gate times.
  • Isosceles trapezoidal upper main grid 201 may be a length L b 0.1 ⁇ 2 mm, a length L a lower side may be 2 ⁇ 5 mm, the height h of the trapezoid may be 0.1 ⁇ 1 mm.
  • the isosceles trapezoid has an upper side length of 0.5 mm, a lower side length of 2.5 mm, and a trapezoidal height of 0.3 mm.
  • the main gate 201 may be composed of a plurality of series of ladder structures, such as two series or four series.
  • Fig. 5 when composed of two, the two columns of trapezoidal main grids are relatively distributed on both sides of the solar cell chip, and the upper side b of the isosceles trapezoid is oppositely directed to the inside of the chip.
  • Fig. 6 when composed of four, four rows of trapezoidal main grids are distributed on four sides of the solar cell chip, and the upper sides of the opposite two rows of isosceles trapezoids are relatively directed toward the inside of the chip.
  • the current density is 4 ⁇ .
  • the electrode sub-gate needs to have a sufficiently large aspect ratio.
  • a single metal layer is difficult to meet both of the above applications, and thus a preferred embodiment of the present invention employs a multilayer electrode structure.
  • the patterned upper electrode 200 includes a four-layer structure: an ohmic contact layer 204, an adhesion layer
  • the ohmic contact layer 204 covers the epitaxial layer structure 300 for forming a good ohmic contact with the concentrating solar cell epitaxial layer structure 300, and has a thickness of between 10 and 300 nanometers.
  • the material may be selected from gold alloys, ruthenium and palladium. One or a combination thereof.
  • the ohmic contact layer 204 is a metal tantalum alloy having a thickness of 200 nanometers.
  • An adhesion layer 205 is overlaid on the ohmic contact layer 204 for increasing the adhesion of the ohmic contact layer 204 to the conductive layer 206, and the thickness thereof is controlled between 1 and 20 nanometers.
  • the material may be titanium, nickel, or the like. one. In a preferred embodiment of the invention, the adhesion layer 205 is titanium and has a thickness of 10 nanometers.
  • the conductive layer 206 is coated on the adhesion layer 205 and may have a thickness of between 1 and 10 microns.
  • the material is selected from a high conductivity material such as silver, aluminum or the like. In a preferred embodiment of the invention, the conductive layer 206 is made of silver and has a thickness of 6 microns.
  • a protective layer 207 is overlaid on the conductive layer 206 to protect the underlying conductive layer from oxidation and contamination, and has a thickness between 10 and 200 nanometers.
  • the protective layer may be of a suitable material to better achieve soldering of the leads.
  • gold is used and has a thickness of 20 nanometers.
  • the four layer structures 204 through 207 of the patterned upper electrode 200 each have the same patterned upper electrode 200 pattern.
  • FIG. 8 is a schematic diagram of a current path of a patterned upper electrode in accordance with a preferred embodiment of the present invention. Since the connection point of the secondary gate 203 and the main gate 201 is distributed on both sides of the isosceles trapezoid or the upper side, that is, evenly distributed in the direction perpendicular to the main gate, and according to the principle of the shortest path transmission according to the current 500, the sub-gate 203 The currents confluent to the main gate 201 will flow along their respective shortest paths, eventually collecting in the battery lead pad 202, thereby achieving uniform expansion of the current 500, avoiding the problem of current crowding.

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Abstract

一种高倍聚光太阳能电池芯片，其包括一外延层结构，一形成于所述外延层结构上表面的经特殊设计的图形化上电极，一形成于所述外延层结构下表面的背面电极。所述图形化上电极包括主栅及次栅，其中主栅由一系列等腰梯形结构连接而成，梯形上边在同一条直线上，并指向电池芯片内部；梯形上边以下至下边的区域为引线焊接区；次栅与梯形主栅的两腰连接。本发明的高倍聚光太阳能电池芯片，所述的图形化上电极经过特殊设计，可使得太阳电池芯片在高倍聚光下产生的大密度电流在流经主栅时充分扩展，防止电流拥挤；同时增加聚光太阳电池芯片有效光照面积，增加光生电流。

Description

一种高倍聚光太阳能电池芯片 本申请要求于 2011 年 06 月 28 日提交中国专利局、 申请号为 201110176319.6、 发明名称为"一种高倍聚光太阳能电池芯片，，的中国专利申请 的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种高倍聚光太阳能电池芯片，属于半导体光电子器件与技术 领域。
背景技术
目前聚光型太阳能电池多采用砷化镓材料系多结太阳能电池，其聚光倍数 随材料性能与工艺技术的进步可达到 500乃至数千倍，而芯片尺寸相比传统的 硅材料电池小很多， 大大降低了半导体材料耗费，是一种具有广泛应用前景的 太阳能电池。但是随着聚光倍数的增加， 太阳电池芯片产生的光生电流也将成 正比地增加， 如 1000倍聚光下， 三结聚光太阳能电池将产生 15-20A/cm2的大 密度电流，如此高的电流密度要求电池串联电阻足够小， 以降低电池芯片的电 阻性损耗， 同时还要求电流分布足够均匀， 以避免电流拥挤， 造成芯片局部过 热， 严重影响芯片的可靠性。 如果芯片表面太阳光均匀分布， 则芯片外延结构 内部及背面电极的电流将均匀分布，但上电极特别是主栅电流拥挤问题不会因 为太阳光的分布情况而有所改变。
在传统的栅状上电极中， 主栅为细长的规则矩形结构， 次栅均勾地与矩形 长边连接。考虑从某一次栅汇流至主栅的电流， 电流必须经主栅流至引线焊接 区， 则从电阻的角度考虑， 电流流经主栅的极端路线有两条， 第一条为自次栅 流出后， 直接沿主栅上靠近次栅的一侧汇流至引线焊接区； 第二条为自次栅流 出后， 首先垂直流向主栅上远离次栅一侧的边缘， 然后沿此边缘汇流至引线焊 接区。 显然电流将沿路径较短的第一条路线流过。 以此类推， 所有从次栅流出 的电流都将沿主栅上靠近次栅的一侧流过， 而远离次栅的一侧电流密度则较 小， 这种电流分布不均匀即造成电流拥挤， 特别是在高倍聚光条件下， 这种电 流拥挤现象将更明显， 造成的局部过热的影响也更大。
图 1〜图 3分别为传统电极图形及其电流路线示意图。 A、 B分别为次栅电 极经主栅汇流至引线焊接区的最远和最短两条极端路线，显然电流将沿较短的 B路线流过。 所有经次栅流出的电流都将沿主栅上靠近次栅一侧的边缘流过， 从而造成下图的在大电流密度情况下的电流拥挤；而主栅上远离次栅一侧电流 密度 4艮小，对光生电流的传输作用并不大， 实际上浪费了电池表面有效光照面 积。 发明内容
针对上述问题， 本发明提出了一种高倍聚光太阳能电池芯片， 其包括 一外延层结构， 一形成于所述外延层结构上表面的图形化上电极， 一形成 于所述外延层结构下表面的背面电极； 所述图形化上电极包括主栅及次栅， 其中主栅由一系列等腰梯形结构连接而成， 梯形上边在同一条直线上， 并 指向电池芯片内部， 梯形上边以下至下边的区域为引线焊接区， 次栅与梯 形主栅的两腰或上边连接。 优选地， 组成主栅的等腰梯形个数与主栅上焊接引线条数相等， 梯形 上边以下至下边的区域为引线焊接区， 上边的长度与引线焊接区沿垂直于 次栅方向的宽度相等， 下边的长度与相邻引线焊接区之间的距离相等。 优选地， 所述次栅的间距相等， 均勾地与所述组成主栅的等腰梯形的两腰 或上边连接。
优选地，所述组成主栅的等腰梯形依次排列 ,梯形下边处于同一条直线上， 梯形上边处于同一条直线上， 所有等腰梯形的上边指向电池芯片内部。
优选地， 所述主栅为两列， 相对地分布于太阳能电池芯片两边， 其中所述 等腰梯形的上边相对地指向芯片内部。
优选地， 所述主栅为四列， 分布于太阳能电池芯片四边， 每相对的两列所 述等腰梯形的上边相对地指向芯片内部。
优选地，所述组成主栅的等腰梯形上边长度为 0.1〜2毫米，下边长度为 2〜5 毫米， 梯形高度为 0.1〜1毫米。
优选地， 所述图形化上电极包括:一覆盖于所述外延层结构的欧姆接触层， 一覆盖于所述欧姆接触层上的粘附层， 一覆盖于所述粘附层上的导电层， 一覆 盖于所述导电层上的保护层。
优选地， 在图形化上电极及棵露出的外延层表面覆盖有减反射膜。
与现有技术相比， 本发明至少具有以下优点：
首次采用的经特殊设计的图形化上电极可有效避免电流拥挤的问题。由于 次栅与主栅的连接点在等腰梯形两腰或上边上均勾分布，即在垂直于主栅的方 向上均勾分布， 而按照电流沿最短路径传输原理， 经次栅汇流至主栅的电流将 沿各自的最短路径流过， 最终汇集于电池引线焊接区，从而实现电流的均匀扩 展， 避免了电流拥挤的问题。
其次， 本发明在避免了电流拥挤问题， 而又不增加电阻性损耗的同时， 增 加了电池芯片表面有效光照面积，提高了光生电流大小，从而提高电池光电转 换效率。
再次， 本发明还对电极多层结构进行优化设计， 组成所述图形化上电极的 四层结构既保证与电池外延层形成良好的欧姆接触，同时保证电极良好的导电 性能。 其中， 粘附层增强了导电层与欧姆接触层的粘附性， 并防止两者因扩散 而相互影响； 保护层对其下的导电层进行保护， 防止氧化和污染， 同时可选用 合适材料以更好地实现引线的焊接。
附图说明 附图用来提供对本发明的进一步理解， 并且构成说明书的一部分， 与本发 明的实施例一起用于解释本发明， 但并不构成对本发明的限制。 此外， 附图数 据是描述概要， 不是按比例绘制。
图 1为传统栅状上电极的平面图。
图 2为图 1所示栅状上电极的局部放大图。
图 3为图 1所示传统图形化上电极电流路线示意。
图 4为本发明优选实施方式的高倍聚光太阳能电池芯片侧面剖视图。 图 5为本发明第一优选实施方式的图形化上电极的平面图。 图 6为本发明另一优选实施方式的图形化上电极的平面图
图 7为图 5所示图形化上电极主栅结构的局部放大图。
图 8为图 5所示图形化上电极的电流路线示意图。
图 9为本发明优选实施方式的图形化上电极的侧面剖视图
图中：
100:减反射膜 200:图形化上电极
201 :主栅 202:引线焊接区
203:次栅 204:欧姆接触层
205:粘附层 206:导电层
207:保护层 300:外延层结构
400:背面电极 500:电流线。 具体实施方式
以下将结合附图及实施例来详细说明本发明的实施方式。 需要说明的是， 落在本发明的保护范围之内。
如图 4所示， 一种高倍聚光太阳能电池芯片， 其包括高倍聚光太阳电池外 延层结构 300, 其为三五族化合物， 可为单结或多结结构。 在外延层结构 300 的上表面形成一经特殊设计的图形化上电极 200, 在外延层结构 300下表面形 成背面电极 400。 在本发明的一个优选实施例中， 在上电极 200及棵露出的外 延层 300表面覆盖有一层减反射膜 100。
如图 5〜图 7所示， 图形化上电极 200包括主栅 201及次栅 203 , 其中主栅 201由一系列等腰梯形结构连接而成， 梯形上边 b在同一条直线上， 并指向电 池芯片内部。 梯形上边以下至下边的区域为引线焊接区 202, 次栅 203间距相 等，均勾地与梯形主栅 201的两腰或上边连接。在本发明的一个优选实施例中， 主栅 201等腰梯形个数与主栅上焊接引线条数相等，梯形上边以下至下边的区 域为引线焊接区， 下边 a的长度 1^与相邻引线焊接区之间的距离 L相等。 梯 形上边 b的长度 Lb根据引线焊接所需区域大小决定， 在本发明的一个优选实 施例中， 上边 b的长度 Lb与引线焊接区沿垂直于次栅方向的宽度相等。 主栅 201上的等腰梯形上边长度 Lb可为 0.1〜2毫米， 下边 a的长度 La可为 2〜5毫 米， 梯形高度 h可为 0.1〜1毫米。 在本发明的一个优选实施例中， 等腰梯形上 边长 0.5毫米， 下边长 2.5毫米， 梯形高 0.3毫米。
主栅 201可以由多个系列的梯形结构构成， 如两个系列或四个系列。 如图 5所示， 当由两个构成时， 两列梯形主栅相对地分布于太阳能电池芯片两边， 等腰梯形上边 b相对地指向芯片内部。 如图 6所示， 当由四个构成时， 四列梯 形主栅分布于太阳能电池芯片四边，每相对的两列等腰梯形的上边相对地指向 芯片内部。
由于电池芯片工作在高倍聚光条件下， 电流密度 4艮大， 考虑到电极与电池 外延层的欧姆接触、电极导电性能等问题，电极次栅还需具有足够大的高宽比。 单一的金属层较难同时满足上述应用需要，因此本发明的优选实施例采用多层 电极结构。
如图 9所示， 图形化上电极 200包括四层结构： 欧姆接触层 204, 粘附层
205 , 导电层 206, 保护层 207。
欧姆接触层 204覆盖于外延层结构 300上，用于与聚光太阳能电池外延层 结构 300形成良好的欧姆接触， 其厚度在 10至 300纳米之间， 其材料可选用 金诸合金、 锗、 钯等之一或其组合。 在本发明的一个优选实施例中， 欧姆接触 层 204选用金锗合金， 厚度为 200纳米。
粘附层 205覆盖于所述欧姆接触层 204上， 用于增加所述欧姆接触层 204 与导电层 206的粘附性， 其厚度控制在 1至 20纳米之间， 材料可选用钛、 镍 等之一。 在本发明的一个优选实施例中， 粘附层 205选用钛， 厚度为 10纳米。 导电层 206覆盖于粘附层 205上， 其厚度可在 1至 10微米之间， 材料选 用高电导率材料， 如银、 铝等。 在本发明的一个优选实施例中， 导电层 206 的材料选用银， 厚度为 6微米。
保护层 207覆盖于所述导电层 206上， 对其下的导电层进行保护， 防止氧 化和污染， 厚度在 10至 200纳米之间。 保护层可选用合适材料以更好地实现 引线的焊接， 在本发明的一个优选实施例中， 选用金， 厚度为 20纳米。 图形化上电极 200的四层结构 204 〜 207均具有相同的图形化上电极 200 图案。
图 8为本发明优选实施方式的图形化上电极的电流路线示意图。 由于次栅 203与主栅 201的连接点在等腰梯形两腰或上边上均勾分布， 即在垂直于主栅 的方向上均匀分布， 而按照电流 500沿最短路径传输原理， 经次栅 203汇流至 主栅 201的电流将沿各自的最短路径流过， 最终汇集于电池引线焊接区 202, 从而实现电流 500的均匀扩展， 避免了电流拥挤的问题。

Claims

权 利 要 求
1.一种高倍聚光太阳能电池芯片， 其包括：
一外延层结构；
一形成于所述外延层结构上表面的图形化上电极；
一形成于所述外延层结构下表面的背面电极;其特征在于：
所述图形化上电极包括主栅及次栅，其中主栅由一系列等腰梯形结构连接 而成， 梯形上边在同一条直线上， 并指向电池芯片内部， 梯形上边以下至下边 的区域为引线焊接区， 次栅与梯形主栅的两腰或上边连接。
2.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 组成主栅的等腰梯形个数与主栅上焊接引线条数相等，上边的长度与引线焊接 区沿垂直于次栅方向的宽度相等，下边的长度与相邻引线焊接区之间的距离相 等。
3.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 次栅的间距相等， 均匀地与所述组成主栅的等腰梯形的两腰或上边连接。
4.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 主栅为两列，相对地分布于电池芯片两边， 其中所述等腰梯形的上边相对地指 向电池芯片内部。
5.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 主栅为四列， 分布于电池芯片四边，每相对的两列所述等腰梯形的上边相对地 指向电池芯片内部。
6.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 组成主栅的等腰梯形上边长度为 0.1〜2毫米， 下边长度为 2〜5毫米， 梯形高度 为 0.1〜1毫米。
7.根据权利要求 1所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 组成主栅的等腰梯形依次排列，梯形下边处于同一条直线上，梯形上边处于同 一条直线上， 所有等腰梯形的上边指向电池芯片内部。
8.根据权利要求 1-7任一项所述的一种高倍聚光太阳能电池芯片， 其特征 在于:所述图形化上电极包括：
一覆盖于所述外延层结构的欧姆接触层； 一覆盖于所述欧姆接触层上的粘附层；
一覆盖于所述粘附层上的导电层；
一覆盖于所述导电层上的保护层。
9.根据权利要求 8所述的一种高倍聚光太阳能电池芯片，其特征在于:所述 欧姆接触层的厚度为 10〜300纳米之间， 其材料选用金锗合金、 锗、 钯之一或 其组合。
10.根据权利要求 8所述的一种高倍聚光太阳能电池芯片， 其特征在于:所 述粘附层的厚度为 1〜20纳米， 其材料选用钛或镍。
11.根据权利要求 8所述的一种高倍聚光太阳能电池芯片， 其特征在于:所 述导电层的厚度为 1〜10微米， 材料选自高电导率材料。
12.根据权利要求 8所述的一种高倍聚光太阳能电池芯片， 其特征在于:所 述保护层的材料为金， 其厚度为 10〜200纳米。
13.根据权利要求 1-7任一项所述的一种高倍聚光太阳能电池芯片，其特征 在于:在图形化上电极及棵露出的外延层表面覆盖有减反射膜。
PCT/CN2012/075135 2011-06-28 2012-05-07 一种高倍聚光太阳能电池芯片 WO2013000339A1 (zh)

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