WO2012174792A1 - 液晶显示装置及其信号驱动方法 - Google Patents

液晶显示装置及其信号驱动方法 Download PDF

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Publication number
WO2012174792A1
WO2012174792A1 PCT/CN2011/078958 CN2011078958W WO2012174792A1 WO 2012174792 A1 WO2012174792 A1 WO 2012174792A1 CN 2011078958 W CN2011078958 W CN 2011078958W WO 2012174792 A1 WO2012174792 A1 WO 2012174792A1
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Prior art keywords
pixel
sub
pixels
signal
data
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PCT/CN2011/078958
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English (en)
French (fr)
Inventor
康志聪
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/375,225 priority Critical patent/US20120327143A1/en
Publication of WO2012174792A1 publication Critical patent/WO2012174792A1/zh
Anticipated expiration legal-status Critical
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3614—Control of polarity reversal in general
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2074—Display of intermediate tones using sub-pixels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0252—Improving the response speed

Definitions

  • the present invention relates to a display device, and more particularly to a liquid crystal display device;
  • the present invention also relates to a signal driving method, and more particularly to a signal driving method of a liquid crystal display device.
  • Overdrive (Over Driving) technology is a technique for improving the display effect of a liquid crystal display panel.
  • Conventional overdrive technology generally compares the front and back image signals to look up the table to find the pre-defined internal difference voltage value to improve the response speed.
  • This method requires the use of a frame buffer (Frame). Buffer) to store the previous image, and then compare with the current image, the above-mentioned predefined internal difference voltage value also needs to be stored in the memory, in addition to the timing controller (Time Control Register, TCON).
  • TCON Time Control Register
  • the general way of driving the overdrive function by column drive is as shown in Figure 1.
  • the original signal is switched from 1V (the positive and negative polarity voltages are 6V/4V respectively) to 3V (the positive and negative polarity voltages are 8V/2V respectively).
  • a signal of 5V positive and negative polarity voltages of 10V/0V
  • the voltage in the pixel changes from 1V to 3V, it takes one frame to charge, so that it gets a voltage of 5V.
  • the pitch between the strip electrodes in the pixel electrode is designed to be large in order to achieve high transmittance, and the liquid crystal is instantaneously driven to cause the twist angle to be incorrect. Therefore, when switching from a low gray level to a high gray level, a so-called rhino horn phenomenon is often generated, which reduces the display effect.
  • Another object of the present invention is to provide a signal driving method of a liquid crystal display device.
  • the present invention constructs a liquid crystal display device comprising: a scan driving module for generating a scan signal and transmitting the scan signal to the scan line; and a data driving module for generating a data signal and transmitting the data signal Providing the data line; a thin film transistor array panel having pixels thereon, the pixel including a sub-pixel R, a sub-pixel G, and a sub-pixel B; a scan line, the scan line and at least one sub-pixel of the pixel
  • the scan signal sequentially scans the sub-pixels in the same row in columns; the data lines are coupled to at least one of the pixels, and the data lines are used to Before the signal is input to the sub-pixel, the sub-pixel input high voltage is pre-charged, and after pre-charging, a signal for displaying an image is input to the sub-pixel; the liquid crystal display device further includes a common line, a common line coupled to at least one of the sub-pixels for applying a high voltage or a low voltage to the sub-pixel according to a
  • each of the common lines is coupled to sub-pixels of the same polarity.
  • each of the data lines is coupled to a sub-pixel of the same polarity.
  • the present invention constructs a liquid crystal display device comprising: a scan driving module for generating a scan signal and transmitting the scan signal to the scan line; and a data driving module for generating a data signal and transmitting the data signal Providing the data line; a thin film transistor array panel having pixels thereon, the pixel including a sub-pixel R, a sub-pixel G, and a sub-pixel B; a scan line, the scan line and at least one sub-pixel of the pixel
  • the scan signal sequentially scans the sub-pixels in the same row in columns; the data lines are coupled to at least one of the pixels, and the data lines are used to
  • the sub-pixel input high voltage is pre-charged before the signal is input to the sub-pixel, and after pre-charging, a signal for displaying an image is input to the sub-pixel.
  • the liquid crystal display device further includes a common line, and the common line is coupled to at least one of the sub-pixels for the polarity of the sub-pixel coupled thereto
  • the sub-pixel applies a high voltage or a low voltage.
  • the three sub-pixel arrays of the pixel are arranged in a direction parallel to the scanning direction of the scanning signal.
  • the three sub-pixel arrays of the pixels are arranged in a direction perpendicular to the scanning direction of the scanning signal.
  • the common line is perpendicular to a direction in which the scanning signal scans the sub-pixels.
  • two adjacent sub-pixels of two adjacent pixels have opposite polarities.
  • each of the common lines is coupled to sub-pixels of the same polarity.
  • each of the data lines is coupled to a sub-pixel having the same polarity.
  • the present invention constructs a signal driving method for a liquid crystal display device, the liquid crystal display device comprising a scan driving module, a data driving module, a thin film transistor array panel, a scan line and a data line, and the thin film transistor array panel is provided with a pixel.
  • the pixel includes a sub-pixel R, a sub-pixel G, and a sub-pixel B, and the method includes the following steps: (A), the scan driving module generates a scan signal and transmits the scan signal to the scan line; (B), The data driving module generates a data signal and transmits the data signal to the data line; (C) the scan line transmits the scan signal to at least one of the pixels, the scan signal pair being in the same row The sub-pixels are sequentially scanned in columns; (D), the data lines transmit the data lines to at least one of the pixels, the data lines before the data signals are input to the sub-pixels The sub-pixel input high voltage is pre-charged, and after pre-charging, a signal for displaying an image is input to the sub-pixel.
  • the method further includes the step of: (E), the common line applies a high voltage or a low voltage to the sub-pixel according to a polarity of the sub-pixel coupled thereto.
  • the invention has the beneficial effects that: compared with the prior art, the invention does not need to use a frame buffer on one hand, which saves cost; on the other hand, it does not need to use complicated timing function to overdrive; the third aspect, if The conventional phenomenon of comparing the front and rear signal look-up tables to overdrive can greatly avoid the phenomenon that the liquid crystal is instantaneously driven and the twist angle is incorrect.
  • FIG. 1 is a schematic diagram of a column drive overdrive mode in the prior art
  • FIG. 2 is a block diagram of a liquid crystal display device of the present invention.
  • FIG. 3 is a partial schematic view showing a first preferred embodiment of a liquid crystal display device of the present invention.
  • FIG. 4 is a schematic diagram showing signal driving of a liquid crystal display device of the present invention.
  • Figure 5 is a partial schematic view showing a second preferred embodiment of the liquid crystal display device of the present invention.
  • Figure 6 is a partial schematic view showing a third preferred embodiment of the liquid crystal display device of the present invention.
  • Figure 7 is a partial schematic view showing a fourth preferred embodiment of the liquid crystal display device of the present invention.
  • the liquid crystal display device of the present invention adopts a pre-charge in a frame and an array common line (Array) Com)
  • Array array common line
  • FIG. 2 is a block diagram of a liquid crystal display device of the present invention.
  • the liquid crystal display device of the present invention includes a scan driving module 204, a data driving module 201, a thin film transistor array panel 202, a common line 205, a scanning line (gate line) 203, and a data line 207.
  • the scanning line 203 and the data line 207 vertical setting.
  • the thin film transistor array panel 102 is provided with a pixel 206, which includes three sub-pixels, and the sub-pixels are not shown in FIG.
  • the scan driving module 204 is configured to generate a scan signal (gate signal), the scan signal is sent by the scan driving module 204 to the scan line 203, and the data driving module 201 is configured to generate a data signal, and the data signal is driven by the data driving module 201 is sent to the data line 207.
  • the scan line 203 is coupled to the pixel 206. Specifically, the scan line 203 is coupled to at least one sub-pixel of the pixel 206, and the data line 207 is coupled to the pixel 206, specifically, at least one of the data line 207 and the pixel 206.
  • the pixels are coupled, and the common line 205 is coupled to the pixel 206. Specifically, the common line 205 is coupled to at least one of the pixels 206.
  • FIG. 3 is a partial schematic view of a first preferred embodiment of a liquid crystal display device of the present invention
  • FIG. 4 is a schematic diagram of signal driving of the liquid crystal display device of the present invention.
  • the tri-gate column driver (Tri-gate) is composed of three inverted sub-pixels (sub-pixel R, sub-pixel G, and sub-pixel B).
  • the sub-pixel R, the sub-pixel G, and the sub-pixel B are vertically arranged in parallel with the scanning direction of the scanning signal.
  • the data line is in accordance with Flip
  • the data lines (including the data line 1 and the data line 2) are arranged in the direction in which the sub-pixel R, the sub-pixel G, and the sub-pixel B are arranged, and the data line is coupled with the first and second sub-pixels in one flip pixel and The sub-pixels in the middle of the adjacent flipped pixels are coupled, specifically, the data line 1 and the sub-pixel R311 of the first flip pixel 310, the sub-pixel G322 of the second flip pixel, the sub-pixel B313 of the first flip pixel, and the fifth The sub-pixel R351 of the flip pixel 350, the sub-pixel G342 of the fourth flip pixel 340, and the sub-pixel B353 of the fifth flip pixel 350 are coupled.
  • the common lines (including the common line 0, the common line 1, the common line 2, and the common line 3) are disposed in a direction perpendicular to the data lines and arranged in an array.
  • the common line is coupled to the sub-pixels of the two flipped pixels adjacent to each other in the horizontal direction
  • the common line 0 is coupled to the sub-pixel R321 of the second flipped pixel 320, the common line.
  • the first flip pixel 310 is adjacent to the second flip pixel 320, and the polarity of the sub-pixel adjacent to the first flip pixel 310 and the second flip pixel 320 is opposite; the first flip pixel 310 is adjacent to the fourth flip pixel 340, first The sub-pixels adjacent to the flip pixel 310 and the fourth flip pixel 340 are opposite in polarity.
  • the liquid crystal display device of the present invention does not require one frame of time to charge the flipped pixels because the flipped pixels have been utilized by the data signals in the same frame before the charging voltage in the flipped pixels is changed from 1 V to 3 V. 8V pre-charge.
  • the inversion pixel in-pixel charging voltage 1V is charged by the data signal 6V and the common line (common electrode) signal 5V or the data signal 4V and the common electrode signal 5V to the inverted pixel.
  • Inverting the in-pixel charging voltage 3V is to charge the inverted pixel by the data signal 8V and the common electrode signal 5V or the data signal 2V and the common electrode signal 5V.
  • Inverting the pixel pre-charge 8V is to charge the flipped pixel by the data signal 8V and the common electrode modulation signal 0V or the data signal 2V and the common electrode modulation signal 10V.
  • the first set of gate signals sends high power to the gates of the first column of sub-pixels (including the sub-pixel R311 of the first flip pixel 310, the sub-pixel R321 of the second flip pixel 320, and the sub-pixel R331 of the third flip pixel 330) Flat signal to open the gate of the first column of sub-pixels, let the first column of sub-pixels (including the sub-pixel R311 of the first flip pixel 310, the sub-pixel R321 of the second flip pixel 320, and the sub-pixel R331 of the third flip pixel 330) Before the charging voltage in the battery is changed from 1V to 3V, the first column of sub-pixels is precharged by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the first group of gate signals sends a high level signal to the gate of the first row of sub-pixels
  • the sub-pixel R311 of the first flip pixel 310 and the sub-pixel R331 of the third flip pixel 330 are both positive polarity data lines 8V
  • the common electrode voltage of the common line 1 is modulated from 5V to a low voltage of 0V, and the sub-pixel R311 of the first flip pixel 310 and the sub-pixel R331 of the third flip pixel 330 are precharged with a high voltage of 8V.
  • the sub-pixel R321 of the second flip pixel 320 is the negative polarity data line 2V, and the sub-pixel R321 of the second flip pixel 320 is precharged with a high voltage of 8V in cooperation with the common electrode high voltage 10V of the common line 0.
  • the first group of gate signals sends a low voltage signal to the first column of sub-pixels to turn off the gate of the first column of sub-pixels; the second group of gate signals to the second column of sub-pixels (including the first inverted pixel 310)
  • the gates of the pixel G312, the sub-pixel G322 of the second flip pixel 320, and the sub-pixel G332 of the third flip pixel 330 transmit a high level signal to turn on the gate of the second column of sub-pixels; likewise, the second column of sub-pixels
  • the charging voltage in the sub-pixel G312 including the first flip pixel 310, the sub-pixel G322 of the second flip pixel 320, and the sub-pixel G332 of the third flip pixel 330 is changed from 1V to 3V, and is adjusted by the data line 8V and the common electrode.
  • the second column of sub-pixels is precharged by changing the signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the second group of gate signals sends a high level signal to the gates of the second row of sub-pixels, since the sub-pixel G312 of the first flip pixel 310 and the sub-pixel G332 of the third flip pixel 330 are both negative data lines 2V
  • the common electrode voltage of the common line 2 is modulated from 5V to a high voltage of 10V, and the sub-pixel G312 of the first flip pixel 310 and the sub-pixel G332 of the third flip pixel 330 are precharged with a high voltage of 8V.
  • the sub-pixel G322 of the second flip pixel 320 is a positive polarity data line 8V, and the common line 1 also maintains the common electrode low voltage 0V when the first group of gate signals is turned on, and the sub-pixel G322 of the second flip pixel 320. Precharge a high voltage of 8V.
  • the second set of gate signals sends a low voltage signal to the second column of sub-pixels to turn off the gates of the second column of sub-pixels; the third set of gate signals to the third column of sub-pixels (including the first flipped pixels 310)
  • the gates of the sub-pixel B313, the sub-pixel B323 of the second flip pixel 320, and the sub-pixel B333 of the third flip pixel 330 transmit a high-level signal to turn on the gate of the third-row sub-pixel; the same, let the third column
  • the charging voltage in the sub-pixel is changed from 1V to 3V, and is shared by the data line 8V.
  • the third modulation sub-pixel is precharged by the electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the third group of gate signals sends a high level signal to the gate of the third row of sub-pixels
  • the sub-pixel B313 of the first flip pixel 310 and the sub-pixel B333 of the third flip pixel 330 are both positive data lines 8V
  • the common electrode voltage of the common line 3 is modulated from 5V to a low voltage of 0V, and the sub-pixel B313 of the first flip pixel 310 and the sub-pixel B333 of the third flip pixel 330 are precharged with a high voltage of 8V.
  • the sub-pixel B323 of the second flip pixel 320 is the negative polarity data line 2V, and the common line 2 also maintains the common electrode high voltage 10V when the second group of gate signals is turned on, and the sub-pixel B323 of the second flip pixel 320. Precharge a high voltage of 8V.
  • the third group of gate signals sends a high level signal to the gate of the third column of sub-pixels
  • the first group of gate signals also sends a high level signal to the gate of the first column of sub-pixels, due to the first
  • the sub-pixel R311 of the flip pixel 310 and the sub-pixel R331 of the third flip pixel 330 are both positive polarity data lines 8V.
  • the first flip pixel 310 is turned on.
  • the sub-pixel R311 and the sub-pixel R331 of the third flip pixel 330 are charged with the correct display target voltage 3V.
  • the sub-pixel R321 of the second flip pixel 320 is the negative polarity data line 2V, and the common electrode 0 voltage returns to the normal common electrode voltage 5V, and the sub-pixel R321 of the second flip pixel 320 is precharged with the correct display target voltage. 3V.
  • the fourth group of gate signals sends a high level signal to the gates of the fourth column of sub-pixels to turn on the gates of the fourth column of sub-pixels; and so on, the overdrive function can be implemented in one frame.
  • FIG. 5 is a partial schematic view showing a second preferred embodiment of the liquid crystal display device of the present invention.
  • the flip pixel is composed of three inverted sub-pixels (sub-pixel R, sub-pixel G, and sub-pixel B).
  • the flip pixel is a three-gate column drive, and the flip pixels are sequentially driven in columns.
  • the three sub-pixels of the flipped pixel are arranged in a longitudinal direction parallel to the scanning direction of the scanning signal.
  • the data line is coupled to all sub-pixels in one flip pixel in a direction in which the sub-pixel R, the sub-pixel G, and the sub-pixel B are arranged, and the data signal is driven by the column.
  • the driving mode is driven, that is, all the sub-pixels have the same polarity in the same row.
  • the data line 1 is coupled to the sub-pixel R511, the sub-pixel G512, and the sub-pixel B513 of the first flip pixel 510.
  • the common electrode 1 is coupled to the sub-pixel R511 and the sub-pixel G512 of the first flip pixel 510 and the sub-pixel R531 and the sub-pixel G532 of the third flip pixel 530.
  • the common line 2 is coupled to the sub-pixel G522 of the second flip pixel 520 and The sub-pixel B523, the common line 3 is coupled to the sub-pixel B513 of the first flip pixel 510 and the sub-pixel R541 of the fourth flip pixel 540 and the sub-pixel B533 of the third flip pixel 530 and the sub-pixel R561 of the sixth flip pixel 560.
  • the common line 1, the common line 2, and the common line 3 are disposed in a direction perpendicular to the data lines and arranged in an array.
  • the first flip pixel 510 and the second flip pixel 520 are adjacent to each other, and the sub-pixels adjacent to the first flip pixel 510 and the second flip pixel 520 have opposite polarities. Referring to FIG.
  • the first group of gate signals are directed to the first column of sub-pixels (including the sub-pixel R511 of the first flip pixel 510, the sub-pixel R521 of the second flip pixel 520, and the sub-pixel R531 of the third flip pixel 530).
  • the gate sends a high level signal to turn on the gate of the first column of sub-pixels, and the first column of sub-pixels (including the sub-pixel R511 of the first flip pixel 510, the sub-pixel R521 of the second flip pixel 520, and the third)
  • the first column sub-pixel is given by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V. Precharge.
  • the first group of gate signals sends a high level signal to the gates of the first row of sub-pixels
  • the sub-pixel R511 of the first flip pixel 510 and the sub-pixel R531 of the third flip pixel 530 are both positive data lines 8V
  • the common electrode voltage of the common line 1 is modulated from 5V to a low voltage of 0V, and the sub-pixel R511 of the first flip pixel 510 and the sub-pixel R531 of the third flip pixel 530 are precharged with a high voltage of 8V.
  • the sub-pixel R521 of the second flip pixel 520 is the negative polarity data line 2V, and the sub-pixel R521 of the second flip pixel 520 is precharged with a high voltage of 8V in cooperation with the common electrode high voltage 10V of the common line 0.
  • the first group of gate signals sends a low voltage signal to the first column of sub-pixels to turn off the gate of the first column of sub-pixels; the second group of gate signals to the second column of sub-pixels (including the first inverted pixel 510)
  • the gates of the pixel G512, the sub-pixel G522 of the second flip pixel 520, and the sub-pixel G532 of the third flip pixel 530 transmit a high level signal to turn on the gate of the second column of sub-pixels, and the second column of sub-pixels (including Before the charging voltage in the sub-pixel G512 of the first flip pixel 510, the sub-pixel G522 of the second flip pixel 520, and the sub-pixel G532 of the third flip pixel 530 is changed from 1V to 3V, the data line 8V and the common electrode modulation signal are used.
  • the second column of sub-pixels is precharged with 0V or data signal 2V and a common voltage of 8V of the common electrode modulation signal 10V.
  • the second group of gate signals sends a high level signal to the gates of the second row of sub-pixels, since the sub-pixel G512 of the first flip pixel 510 and the sub-pixel G532 of the third flip pixel 530 are both positive data lines 8V
  • the common electrode voltage of the common line 1 is maintained at the same time as the common electrode low voltage 0V when the first group of gate signals is turned on, and the sub-pixel G512 of the first flipped pixel 510 and the sub-pixel G532 of the third flipped pixel 530 are precharged by 8V. high voltage.
  • the sub-pixel R522 of the second flip pixel 520 is a negative polarity data line 2V
  • the common electrode voltage of the common line 2 is modulated from 5V to a high voltage of 10V
  • the sub-pixel G522 of the second flip pixel 520 is precharged with a high voltage of 8V. .
  • the second set of gate signals sends a low voltage signal to the second column of sub-pixels to turn off the gates of the second column of sub-pixels; the third set of gate signals to the third column of sub-pixels (including the first flipped pixels 510)
  • the gates of the sub-pixel B513, the sub-pixel G523 of the second flip pixel 520, and the sub-pixel G533 of the third flip pixel 530 transmit a high level signal to turn on the gate of the third column of sub-pixels, and let the third column of sub-pixels (
  • the charging voltage in the sub-pixel B513 including the first flip pixel 510, the sub-pixel B523 of the second flip pixel 520, and the sub-pixel B533) of the third flip pixel 530 is changed from 1V to 3V, and is modulated by the data line 8V and the common electrode.
  • the signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V are used to precharge the third column of sub-pixels.
  • the third group of gate signals sends a high level signal to the gate of the third row of sub-pixels
  • the sub-pixel B513 of the first flip pixel 510 and the sub-pixel B533 of the third flip pixel 530 are both positive data lines 8V
  • the common electrode voltage of the common line 3 is modulated from 5V to a low voltage of 0V, and the sub-pixel B513 of the first flip pixel 510 and the sub-pixel B533 of the third flip pixel 530 are precharged with a high voltage of 8V.
  • the sub-pixel B523 of the second flip pixel 520 is the negative polarity data line 2V, and the common electrode voltage of the common line 2 is maintained at the common electrode high voltage 10V when the second group of gate signals is turned on, and the second flip pixel 520 is The sub-pixel B523 is precharged with an 8V high voltage.
  • the third group of gate signals sends a high level signal to the gate of the third column of sub-pixels
  • the first group of gate signals also sends a high level signal to the gate of the first column of sub-pixels, due to the first
  • the sub-pixel R511 of the flip pixel 510 and the sub-pixel R531 of the third flip pixel 530 are both positive polarity data lines 8V.
  • the first flip pixel 510 is turned on.
  • the sub-pixel R511 and the sub-pixel R531 of the third flip pixel 530 are charged with the correct display target voltage 3V.
  • the sub-pixel R521 of the second flip pixel 520 is the negative polarity data line 2V
  • the common electrode voltage with the common line 0 returns to the normal common electrode voltage 5V
  • the sub-pixel R521 of the second flip pixel 520 is charged with the correct display target voltage. 3V.
  • the fourth group of gate signals starts to send a high level signal to the gate of the fourth column of sub-pixels to open the gate of the fourth column of sub-pixels; and so on, the overdrive function can be realized in one frame. .
  • FIG. 6 is a partial schematic view showing a third preferred embodiment of the liquid crystal display device of the present invention.
  • vertical strips (Vertical Strip) pixels are made up of three vertical strips (Vertical The sub-pixels of the strip (sub-pixel R, sub-pixel G, and sub-pixel B).
  • the sub-pixel R, the sub-pixel G, and the sub-pixel B are sequentially arranged in the horizontal direction.
  • Data signal driven with column The driving mode is driven, that is, all the sub-pixels have the same polarity in the same row.
  • Vertical strip pixels are driven in columns (Vertical Strip with Column Driving).
  • the data lines are arranged in a direction perpendicular to the arrangement direction of the sub-pixel R, the sub-pixel G, and the sub-pixel B.
  • Each of the data lines is coupled to the same polarity sub-pixel in the vertical strip-shaped pixel on the same row, specifically, the data line 1 and the sub-pixel B611 and the third vertical strip-shaped pixel of the first vertical strip-shaped pixel 610
  • the sub-pixel B631 of 630 and the sub-pixel B651 of the fifth vertical strip pixel 650 are coupled.
  • the common line 1, the common line 2, and the common line 3 are arranged in a direction perpendicular to the data lines and arranged in an array.
  • the sub-pixel R633 of the pixel 630 and the sub-pixel G622 of the second vertical strip pixel 620 are coupled to the sub-pixel G642 of the fourth vertical strip pixel 640, and the sub-pixel G632 of the common line 2 and the third vertical strip-shaped pixel 630
  • the sub-pixel R663 of the vertical strip pixel 660 is coupled, and the common line 3 and so on.
  • the first vertical strip pixel 610 is adjacent to the second vertical strip pixel 620, and the first vertical strip pixel 610 is opposite to the second vertical strip pixel 620; the first vertical strip pixel 610 is The third vertical strip pixels 630 are adjacent to each other, and the first vertical strip pixels 610 are opposite in polarity to the sub-pixels adjacent to the third vertical strip pixels 630.
  • the first group of gate signals are to the first column of sub-pixels (including the sub-pixel B611, the sub-pixel G612, the sub-pixel R613, and the second vertical strip pixel 620 of the first vertical strip-shaped pixel 610).
  • the gates of the pixel B621, the sub-pixel G622, and the sub-pixel R623) send a high-level signal to turn on the gate of the first column of sub-pixels, and the first column of sub-pixels (including the sub-pixel B611 of the first vertical strip 610, Before the charging voltage in the pixel G612, the sub-pixel R613, and the second pixel B621 of the second vertical strip 620, the sub-pixel G622, and the sub-pixel R623) is changed from 1V to 3V, the data line 8V and the common electrode modulation signal 0V or the data signal are used.
  • the first column of sub-pixels is precharged by 2V and the common electrode modulation signal 10V with a charging voltage of 8V.
  • the sub-pixels of the sub-pixel B611, the sub-pixel R613, and the second vertical strip-shaped pixel 620 of the first vertical strip-shaped pixel 610 G622 is a positive data line 8V
  • the common electrode voltage of the common line 1 is modulated from 5V to a low voltage of 0V
  • the sub-pixel B611, the sub-pixel R613 and the second vertical strip-shaped pixel 620 of the first vertical strip pixel 610 are 620.
  • the sub-pixel G622 is pre-charged with a high voltage of 8V.
  • the sub-pixel G612 of the first vertical strip pixel 610 and the sub-pixel B621 and the sub-pixel R623 of the second vertical strip pixel 620 are negative polarity data lines 2V, and the common electrode high voltage 10V of the common line 0 is opposite to the first
  • the sub-pixel G612 of the vertical strip pixel 610 and the sub-pixel B621 and the sub-pixel R623 of the second vertical strip pixel 620 are precharged with a high voltage of 8V.
  • the first group of gate signals sends a low voltage signal to the first column of sub-pixels to turn off the gate of the first column of sub-pixels; the second group of gate signals to the second column of sub-pixels (including the third vertical strip of pixels 630)
  • the gates of the sub-pixel B631, the sub-pixel G632, the sub-pixel R633, and the sub-pixel B641, the sub-pixel G642, and the sub-pixel R643 of the fourth vertical strip pixel 640 transmit a high-level signal to turn on the gate of the second column of sub-pixels.
  • the second column of sub-pixels is precharged by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the sub-pixels of the sub-pixel B631, the sub-pixel R633, and the fourth vertical strip-shaped pixel 640 of the third vertical strip-shaped pixel 630 G642 is a positive polarity data line 8V
  • the common electrode voltage with the common line 1 is maintained at the common electrode low voltage 0V when the first group of gate signals is turned on
  • the sub-pixel B631 and the sub-pixel of the third group of vertical strip pixels 630 are
  • the sub-pixel G642 of R633 and the fourth group of vertical strip pixels 640 is precharged with an 8V high voltage.
  • the sub-pixel G632 of the third vertical strip pixel 630 and the sub-pixel B641 and the sub-pixel R643 of the fourth vertical strip pixel 640 are negative polarity data lines 2V, and the common electrode voltage of the common line 2 is modulated from 5V to a high voltage. 10V, the sub-pixel G632 of the third vertical strip pixel 630 and the sub-pixel B641 and the sub-pixel R643 of the fourth vertical strip pixel 640 are precharged with a high voltage of 8V.
  • the second group of gate signals sends a low voltage signal to the second column of sub-pixels to turn off the gate of the second column of sub-pixels; the third group of gate signals to the third column of sub-pixels (including the fifth vertical strip of pixels)
  • the gates of the sub-pixel B651, the sub-pixel G652, the sub-pixel R653, and the sub-pixel B661, the sub-pixel G662, and the sub-pixel R663 of the sixth vertical strip pixel 650 transmit a high-level signal to turn on the third sub-pixel.
  • the gate is disposed in the third column of sub-pixels (including the sub-pixel B651, the sub-pixel G652, the sub-pixel R653, and the sixth vertical strip 660, the sub-pixel B661, the sub-pixel G662, and the sub-pixel R663) of the fifth vertical strip 650
  • the third column of sub-pixels is precharged by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the sub-pixels of the sub-pixel B651, the sub-pixel R653, and the sixth vertical strip-shaped pixel 660 of the fifth vertical strip-shaped pixel 650 G662 is a positive polarity data line 8V
  • the common electrode voltage with the common line 3 is modulated from 5V to a low voltage 0V
  • the sub-pixel G662 is pre-charged with an 8V high voltage.
  • the sub-pixel G652 of the fifth vertical strip pixel 650 and the sub-pixel B661 and the sub-pixel R663 of the sixth vertical strip pixel 660 are negative polarity data lines 2V, and the common electrode of the common line 2 is maintained at the same level as the second set of gates.
  • the pole signal is turned on, the common electrode high voltage is 10V, and the sub-pixel G652 of the fifth vertical strip pixel 650 and the sub-pixel B661 and the sub-pixel R663 of the sixth vertical strip pixel 660 are precharged with a high voltage of 8V.
  • the first group of gate signals When the third group of gate signals sends a high level signal to the gate of the third column of sub-pixels, the first group of gate signals also sends a high level signal to the gate of the first column of sub-pixels, due to the first
  • the sub-pixel B611 of the vertical strip-shaped pixel 610, the sub-pixel R613, and the sub-pixel G622 of the second set of vertical strip-shaped pixels 620 are all positive polarity data lines 8V, and the common electrode voltage of the common line 1 is restored to the normal common electrode at this time.
  • the sub-pixel B611 and the sub-pixel R613 of the first group of vertical strip pixels 610 and the sub-pixel G622 of the second group of vertical strip-shaped pixels 620 are charged with a correct display target voltage of 3V.
  • the sub-pixel G612 of the first group of vertical strip pixels 610 and the sub-pixel B621 and the sub-pixel R623 of the second group of vertical strip-shaped pixels 620 are negative polarity data lines 2V, and the common electrode voltage with the common line 0 returns to the normal total
  • the electrode voltage is 5 V
  • the sub-pixel G612 of the first group of vertical strip pixels 610 and the sub-pixel B621 and the sub-pixel R623 of the second group of vertical strip-shaped pixels 620 are charged with the correct display target voltage 3V.
  • the fourth group of gate signals starts to send a high level signal to the gate of the fourth column of sub-pixels to open the gate of the fourth column of sub-pixels; and so on, the overdrive function can be realized in one frame. .
  • FIG. 7 is a partial schematic view showing a fourth preferred embodiment of the liquid crystal display device of the present invention.
  • Figure 7 is also in the column driver (Column The overdrive function of the liquid crystal display device of the present invention is realized under the conditions of Driving.
  • the vertical strip pixel is composed of three vertical stripe sub-pixels (sub-pixel R, sub-pixel G, and sub-pixel B).
  • the sub-pixel R, the sub-pixel G, and the sub-pixel B are sequentially arranged in the horizontal direction.
  • the first vertical strip pixel 710 and the second vertical strip pixel 720 are arranged in a row
  • the third vertical strip pixel 730 and the fourth vertical strip pixel 740 are arranged in a row, and so on.
  • the same data line is connected to each vertical strip pixel in the vertical direction, the sub-pixels with the same odd-numbered pixels in the vertical direction (one of the sub-pixel R, the sub-pixel G and the sub-pixel B) and the sub-pixels with the same even pixel (sub-pixel) R, one of the sub-pixel G and the sub-pixel B) are connected to the same data line, wherein the polarity of the sub-pixel of the odd-numbered pixel is different from the polarity of the sub-pixel of the even-numbered pixel.
  • the data line 1 is coupled to the sub-pixel B711 of the first vertical strip pixel 710, the sub-pixel G732 of the third vertical strip pixel 730, and the sub-pixel B751 of the fifth vertical strip pixel 750, and the data line 2 and the
  • the sub-pixel G712 of a vertical strip pixel 710, the sub-pixel R733 of the third vertical strip pixel 730, and the sub-pixel G752 of the fifth vertical strip pixel 750 are coupled, and the data line 3 and the first vertical strip pixel 710 are next.
  • the pixel R713, the sub-pixel B741 of the fourth vertical strip pixel 740, and the sub-pixel R753 of the fifth vertical strip pixel 750 are coupled, and so on.
  • the common line 1, the common line 2, and the common line 3 are arranged in a direction perpendicular to the data lines and arranged in an array.
  • the common line is coupled to the mutually offset sub-pixels of the two vertical strip-shaped pixels adjacent in the vertical direction, specifically, the common line 1 and the sub-pixel B711 of the first vertical strip-shaped pixel 710,
  • the sub-pixel R713 and the sub-pixel G722 of the second vertical strip-shaped pixel 720 and the sub-pixel G732 of the third vertical strip-shaped pixel 730 and the sub-pixel B741 and the sub-pixel R743 of the fourth vertical strip-shaped pixel 740 are coupled, and the common line 2 and Sub-pixel B731 of the third vertical strip pixel 730, sub-pixel G742 of the fourth vertical strip-shaped pixel 740, sub-pixel G752 of the fifth vertical strip-shaped pixel 750, and sub-pixel of the sixth vertical strip-shaped pixel 760 B761, sub-pixel R763 are coupled, public
  • the first vertical strip pixel 710 is adjacent to the second vertical strip pixel 720, and the sub-pixels adjacent to the first vertical strip pixel 710 and the second vertical strip pixel 720 have opposite polarities; the first vertical strip pixel 710 is adjacent to the third vertical strip pixel 730, and the sub-pixels adjacent to the first vertical strip pixel 710 and the third vertical strip pixel 730 have opposite polarities.
  • the first group of gate signals are to the first column of sub-pixels (including the sub-pixel B711, the sub-pixel G712, the sub-pixel R713, and the second vertical strip pixel 720 of the first vertical strip-shaped pixel 710).
  • the gates of the pixel B721, the sub-pixel G722, and the sub-pixel R723) send a high-level signal to turn on the gate of the first column of sub-pixels, and the first column of sub-pixels (including the sub-pixel B711 of the first vertical strip 710, Before the charging voltage in the pixel G712, the sub-pixel R713, and the sub-pixel B721, the sub-pixel G722, and the sub-pixel R723 of the second vertical strip 720 is changed from 1V to 3V, the data line 8V and the common electrode modulation signal 0V or the data signal are used.
  • the first column of sub-pixels is precharged by 2V and the common electrode modulation signal 10V with a charging voltage of 8V.
  • the sub-pixels of the sub-pixel B711, the sub-pixel R713, and the second vertical strip-shaped pixel 720 of the first vertical strip-shaped pixel 710 G722 is a positive polarity data line 8V
  • the common electrode voltage of the common line 1 is modulated from 5V to a low voltage of 0V
  • the sub-pixel G722 is pre-charged with an 8V high voltage.
  • the sub-pixel G712 of the first vertical strip pixel 710 and the sub-pixel B721 and the sub-pixel R723 of the second vertical strip pixel 720 are the negative polarity data line 2V, and the common electrode high voltage 10V of the common line 0 is opposite to the first
  • the sub-pixel G712 of the vertical strip pixel 710 and the sub-pixel B721 and the sub-pixel R723 of the second vertical strip pixel 720 are precharged with a high voltage of 8V.
  • the first group of gate signals sends a low voltage signal to the first column of sub-pixels to turn off the gate of the first column of sub-pixels; the second group of gate signals to the second column of sub-pixels (including the third vertical strip of pixels 730)
  • the gates of the sub-pixel B731, the sub-pixel G732, the sub-pixel R733, and the sub-pixel B741, the sub-pixel G742, and the sub-pixel R743 of the fourth vertical strip-shaped pixel 740 transmit a high-level signal to turn on the gate of the second column of sub-pixels.
  • the second column of sub-pixels is precharged by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the sub-pixels G732 of the third vertical strip-shaped pixel 730 and the sub-pixels B741 and sub-pixels of the fourth vertical strip-shaped pixel 740 R743 is a positive data line 8V
  • the common electrode voltage with the common line 1 is maintained at the common electrode low voltage 0V when the first group of gate signals is turned on
  • the sub-pixel G732 and the fourth for the third group of vertical strip pixels 730 are
  • the sub-pixel B741 and the sub-pixel R743 of the vertical strip pixel 740 are precharged with a high voltage of 8V.
  • the sub-pixel B731, the sub-pixel R733, and the sub-pixel G742 of the fourth group of vertical strip-shaped pixels 740 of the third group of vertical strip-shaped pixels 730 are negative polarity data lines 2V, and the common electrode voltage of the common line 2 is modulated by 5V.
  • the sub-pixel B731, the sub-pixel R733 of the third group of vertical strip pixels 730 and the sub-pixel G742 of the fourth group of vertical strip-shaped pixels 740 are precharged with a high voltage of 8V.
  • the second group of gate signals sends a low voltage signal to the second column of sub-pixels to turn off the gate of the second column of sub-pixels; the third group of gate signals to the third column of sub-pixels (including the fifth vertical strip of pixels)
  • the gates of the sub-pixel B751, the sub-pixel G752, the sub-pixel R753, and the sub-pixel B761, the sub-pixel G762, and the sub-pixel R763 of the sixth vertical strip-shaped pixel 750 transmit a high-level signal to turn on the third sub-pixel.
  • the gate is arranged in the third row of sub-pixels (including the sub-pixel B751, the sub-pixel G752, the sub-pixel R753, and the sub-pixel B761, the sub-pixel G762, and the sub-pixel 763 of the sixth vertical strip 760) Before the charging voltage is changed from 1V to 3V, the third column of sub-pixels is precharged by the data line 8V and the common electrode modulation signal 0V or the data signal 2V and the charging voltage 8V of the common electrode modulation signal 10V.
  • the sub-pixels of the sub-pixel B751, the sub-pixel R753, and the sixth vertical strip-shaped pixel 760 of the fifth vertical strip-shaped pixel 750 G762 is a positive polarity data line 8V
  • the common electrode voltage with the common line 3 is modulated from 5V to a low voltage 0V
  • the sub-pixel G762 is pre-charged with an 8V high voltage.
  • the sub-pixel G752 of the fifth vertical strip pixel 750 and the sub-pixel B761 and the sub-pixel R763 of the sixth group of vertical strip pixels 760 are negative polarity data lines 2V, and the common electrode of the common line 2 is maintained as the second group.
  • the gate signal is turned on, the common electrode high voltage is 10V, and the sub-pixel G752 of the fifth vertical strip pixel 750 and the sub-pixel B761 and the sub-pixel R763 of the sixth vertical strip pixel 760 are pre-charged with a high voltage of 8V.
  • the first group of gate signals When the third group of gate signals sends a high level signal to the gate of the third column of sub-pixels, the first group of gate signals also sends a high level signal to the gate of the first column of sub-pixels, due to the first
  • the sub-pixel B711 of the vertical strip-shaped pixel 710, the sub-pixel R713, and the sub-pixel G722 of the second set of vertical strip-shaped pixels 720 are all positive polarity data lines 8V, and the common electrode voltage of the common line 1 is restored to the normal common electrode at this time.
  • the sub-pixel B711 and the sub-pixel R713 of the first group of vertical strip pixels 710 and the sub-pixel G722 of the second group of vertical strip-shaped pixels 720 are charged with a correct display target voltage of 3V.
  • the sub-pixel G712 of the first group of vertical strip pixels 710 and the sub-pixel B721 and the sub-pixel R723 of the second group of vertical strip-shaped pixels 720 are negative polarity data lines 2V, and the common electrode voltage of the common line 0 returns to the normal total The electrode voltage is 5V, and the sub-pixel G712 of the first group of vertical strip pixels 710 and the sub-pixel B721 and the sub-pixel R723 of the second group of vertical strip-shaped pixels 720 are charged with the correct display target voltage 3V. Then, the fourth group of gate signals starts to send a high level signal to the gate of the fourth column of sub-pixels to open the gate of the fourth column of sub-pixels; and so on, the overdrive function can be realized in one frame. .
  • the signal driving method of the liquid crystal display device of the present invention comprises the steps of: the scan driving module generates a scan signal and transmits the scan signal to the scan line; the data drive module generates the data signal and transmits the data signal to the data.
  • a scan line sends the scan signal to at least one sub-pixel in the pixel, the scan signal sequentially scans the sub-pixels in the same row in columns; the data line sends the data line to at least one sub-pixel in the pixel, the data line
  • the sub-pixel is pre-charged prior to inputting the data signal into the sub-pixel.
  • the above method may further include the step of: the common line applies a high voltage or a low voltage to the sub-pixel according to the polarity of the sub-pixel to which it is coupled.

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Abstract

一种液晶显示装置，包括：扫描驱动模块（204），用于产生扫描信号并将所述扫描信号发送给扫描线（203）；数据驱动模块（201），用于产生数据信号并将所述数据信号发送给数据线（207）；薄膜晶体管阵列面板（102），其上设有像素（206），所述像素包括次像素R（311）、次像素G（312）和次像素B（313）；扫描线（203），所述扫描线与所述像素中的至少一个次像素耦接，所述扫描信号对处于同一行的次像素按列依次扫描；数据线（207），所述数据线与所述像素中的至少一个次像素耦接，所述数据线用于在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号。本申请还公开了一种液晶显示装置的信号驱动方法。

Description

液晶显示装置及其信号驱动方法 技术领域
本发明涉及一种显示装置，特别是涉及一种液晶显示装置；
本发明还涉及一种信号驱动方法，特别是涉及一种液晶显示装置的信号驱动方法。
 背景技术
过驱动（Over Driving）技术是一种用于改善液晶显示面板显示效果的技术。传统的过驱动技术一般将前后图像信号作查表比较来找出预先定义的内差电压值以提高响应速度，这种做法需要使用帧缓冲器（Frame Buffer）来存储前一图像，然后再与当前图像作比较，上述预先定义的内差电压值也需要存储在存储器中，此外还需要定时控制器（Time Control Register， TCON）的配合。
一般的以列驱动实现过驱动功能的方式如图1所示，原信号从1V（正负极性电压分别为6V/4V）切换至3V（正负极性电压分别为8V/2V），为提高响应速度，通常会在原信号中插入5V（正负极性电压分别为10V/0V）的信号。当像素内的电压由1V变成3V时需要耗费一帧的时间来充电，使之得到5V的电压。
以PVA来看，如果只做一组内差查表，由于为了达到高穿透率而将像素电极中的条状电极间的间距设计成较大，造成液晶瞬时受到驱动而导致扭转角度不正确，于是，当从低灰阶切换到高灰阶时往往会产生所谓犀牛角现象，降低了显示效果。
故，有必要提供一种液晶显示装置及其信号驱动方法，以解决现有技术所存在的问题。
 技术问题
本发明的一个目的在于提供一种液晶显示装置，其能在一帧内实现过驱动。
本发明的另一个目的在于提供一种液晶显示装置的信号驱动方法。
 技术解决方案
本发明构造了一种液晶显示装置，包括：扫描驱动模块，用于产生扫描信号并将所述扫描信号发送给所述扫描线；数据驱动模块，用于产生数据信号并将所述数据信号发送给所述数据线；薄膜晶体管阵列面板，其上设有像素，所述像素包括次像素R、次像素G和次像素B；扫描线，所述扫描线与所述像素中的至少一个次像素耦接，所述扫描信号对处于同一行的次像素按列依次扫描；数据线，所述数据线与所述像素中的至少一个次像素耦接，所述数据线用于在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号；所述液晶显示装置还包括公共线，所述公共线与所述像素中的至少一个次像素耦接，用于根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压；所述像素的三个所述次像素排列按与所述扫描信号的扫描方向平行或垂直的方向排列；所述公共线与所述扫描信号对次像素进行扫描的方向垂直；两个相邻的所述像素的相邻两个次像素具有相反的极性。
在本发明的液晶显示装置中，每一条所述公共线与极性相同的次像素耦接。
在本发明的液晶显示装置中，每一条所述数据线与极性相同的次像素耦接。
本发明构造了一种液晶显示装置，包括：扫描驱动模块，用于产生扫描信号并将所述扫描信号发送给所述扫描线；数据驱动模块，用于产生数据信号并将所述数据信号发送给所述数据线；薄膜晶体管阵列面板，其上设有像素，所述像素包括次像素R、次像素G和次像素B；扫描线，所述扫描线与所述像素中的至少一个次像素耦接，所述扫描信号对处于同一行的次像素按列依次扫描；数据线，所述数据线与所述像素中的至少一个次像素耦接，所述数据线用于在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号。
在本发明的液晶显示装置中，所述液晶显示装置还包括公共线，所述公共线与所述像素中的至少一个次像素耦接，用于根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压。
在本发明的液晶显示装置中，所述像素的三个所述次像素排列按与所述扫描信号的扫描方向平行的方向排列。
在本发明的液晶显示装置中，所述像素的三个所述次像素排列按与所述扫描信号的扫描方向垂直的方向排列。
在上述的液晶显示装置中，所述公共线与所述扫描信号对次像素进行扫描的方向垂直。
在本发明的液晶显示装置中，两个相邻的所述像素的相邻两个次像素具有相反的极性。
在上述的液晶显示装置中，每一条所述公共线与极性相同的次像素耦接。
在上述的液晶显示装置中，每一条所述数据线与极性相同的次像素耦接。
本发明构造了一种液晶显示装置的信号驱动方法，所述液晶显示装置包括扫描驱动模块、数据驱动模块、薄膜晶体管阵列面板、扫描线和数据线，所述薄膜晶体管阵列面板上设有像素，所述像素包括次像素R、次像素G和次像素B，所述方法包括以下步骤：（A）、扫描驱动模块产生扫描信号并将所述扫描信号发送给所述扫描线；（B）、数据驱动模块产生数据信号并将所述数据信号发送给所述数据线；（C）、扫描线将所述扫描信号发送给所述像素中的至少一个次像素，所述扫描信号对处于同一行的次像素按列依次扫描；（D）、数据线将所述数据线发送给所述像素中的至少一个次像素，所述数据线在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号。
在本发明的液晶显示装置的信号驱动方法中，所述方法还包括以下步骤：（E）、公共线根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压。
 有益效果
本发明的有益效果是：相对于现有技术，本发明一方面不需要使用帧缓冲器，节约了成本；另一方面，不需要使用复杂的定时功能来进行过驱动；第三方面，如果在使用传统的将前后信号查表比较以进行过驱动时能大大避免液晶瞬时受到驱动而造成扭转角度不正确的现象的发生。
 附图说明
图1为现有技术中列驱动的过驱动方式的示意图；
图2为本发明的液晶显示装置的框图；
图3为本发明的液晶显示装置的第一较佳实施例的局部示意图；
图4为本发明的液晶显示装置信号驱动的示意图；
图5为本发明的液晶显示装置的第二较佳实施例的局部示意图；
图6为本发明的液晶显示装置的第三较佳实施例的局部示意图；
图7为本发明的液晶显示装置的第四较佳实施例的局部示意图。
 本发明的最佳实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。本发明所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
在图中，结构相似的单元是以相同标号表示。
本发明的液晶显示装置通过帧（Frame）内预充电（Pre-charge）及阵列公共线（Array com）高低电平信号的配合，在每个正确的数据信号写入到像素前都对像素先行充电一高电压，相当于在正确的数据信号写入到像素前进行过驱动（Over Driving）。
参考图2，图2为本发明的液晶显示装置的框图。本发明的液晶显示装置包括扫描驱动模块204、数据驱动模块201、薄膜晶体管阵列面板202、公共线205、扫描线（栅极线）203和数据线207，图2中，扫描线203与数据线207垂直设置。薄膜晶体管阵列面板102上设有像素206，该像素206包括三个次像素，图2中未示出次像素。扫描驱动模块204用于产生扫描信号（栅极信号），该扫描信号被该扫描驱动模块204发送给所述扫描线203，数据驱动模块201用于产生数据信号，该数据信号被该数据驱动模块201发送给所述数据线207。扫描线203与像素206耦接，具体地，扫描线203与像素206中的至少一个次像素耦接，数据线207与像素206耦接，具体地，数据线207与像素206中的至少一个次像素耦接，公共线205与像素206耦接，具体地，公共线205与像素206中的至少一个次像素耦接。
参考图3和图4，图3为本发明的液晶显示装置的第一较佳实施例的局部示意图，图4为本发明的液晶显示装置信号驱动的示意图。在本实施例中，三栅极列驱动（Tri-gate）是由三个翻转的次像素（次像素R、次像素G和次像素B）组成。次像素R、次像素G和次像素B按与扫描信号的扫描方向平行纵向排列。在本实施例中，数据线依Flip pixel设计，数据线（包括数据线1和数据线2）按次像素R、次像素G和次像素B排列的方向设置，并且数据线与一个翻转像素内的首尾两个次像素耦接以及与相邻的翻转像素的中间的次像素耦接，具体地，数据线1与第一翻转像素310的次像素R311、第二翻转像素的次像素G322、第一翻转像素的次像素B313、第五翻转像素350的次像素R351、第四翻转像素340的次像素G342和第五翻转像素350的次像素B353耦接。公共线（包括公共线0、公共线1、公共线2和公共线3）设置在与数据线垂直的方向上并且以阵列（Array）的形式排列。在本实施例中，公共线与在水平方向上相邻的两个翻转像素的中互相错开的次像素耦接，具体地，公共线0耦接第二翻转像素320的次像素R321，公共线1（com 1）耦接第一翻转像素310的次像素R311、第二翻转像素320的次像素G322和第三翻转像素330的次像素R331，公共线2（com 2）耦接第一翻转像素310的次像素G312、第二翻转像素320的次像素B323和第三翻转像素330的次像素G332，公共线3（com 3）耦接第一翻转像素310的次像素B313、第五翻转像素350的次像素R351和第三翻转像素330的次像素B333。第一翻转像素310与第二翻转像素320相邻，第一翻转像素310与第二翻转像素320相邻的次像素极性相反；第一翻转像素310与第四翻转像素340相邻，第一翻转像素310与第四翻转像素340相邻的次像素极性相反。图4中，本发明的液晶显示装置不需要耗费一帧的时间来给翻转像素充电，因为在翻转像素内的充电电压由1V变成3V之前已经利用了同一帧内的数据信号对翻转像素进行8V预充电。上述翻转像素内充电电压1V是由数据信号6V与公共线（共电极）信号5V或者数据信号4V与共电极信号5V对翻转像素进行充电。翻转像素内充电电压3V是由数据信号8V与共电极信号5V或者数据信号2V与共电极信号5V对翻转像素进行充电。翻转像素预充电8V是由数据信号8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V对翻转像素进行充电。第一组栅极信号向第一列次像素（包括第一翻转像素310的次像素R311、第二翻转像素320的次像素R321和第三翻转像素330的次像素R331）的栅极发送高电平信号以打开第一列次像素的栅极，让第一列次像素（包括第一翻转像素310的次像素R311、第二翻转像素320的次像素R321和第三翻转像素330的次像素R331）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第一列次像素进行预充电。当第一组栅极信号向第一列次像素的栅极发送高电平信号时，由于第一翻转像素310的次像素R311及第三翻转像素330的次像素R331均是正极性数据线8V，配合公共线1的共电极电压由5V调变至低电压0V，对第一翻转像素310的次像素R311及第三翻转像素330的次像素R331预充一8V高电压。同时，第二翻转像素320的次像素R321是负极性数据线2V，配合公共线0的共电极高电压10V，对第二翻转像素320的次像素R321预充一8V高电压。接着，第一组栅极信号向第一列次像素发送低电压信号以关闭第一列次像素的栅极；第二组栅极信号向第二列次像素（包括第一翻转像素310的次像素G312、第二翻转像素320的次像素G322和第三翻转像素330的次像素G332）的栅极发送高电平信号以打开第二列次像素的栅极；同样，让第二列次像素（包括第一翻转像素310的次像素G312、第二翻转像素320的次像素G322和第三翻转像素330的次像素G332）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第二列次像素进行预充电。当第二组栅极信号向第二列次像素的栅极发送高电平信号时，由于第一翻转像素310的次像素G312及第三翻转像素330的次像素G332均是负极性数据线2V，配合公共线2的共电极电压由5V调变至高电压10V，对第一翻转像素310的次像素G312及第三翻转像素330的次像素G332预充一8V高电压。同时，第二翻转像素320的次像素G322是正极性数据线8V，配合公共线1还维持同第一组栅极信号开启时的共电极低电压0V，对第二翻转像素320的次像素G322预充一8V高电压。紧接着，第二组栅极信号向第二列次像素发送低电压信号以关闭第二列次像素的栅极；第三组栅极信号向第三列次像素（包括第一翻转像素310的次像素B313、第二翻转像素320的次像素B323和第三翻转像素330的次像素B333）的栅极发送高电平信号以打开第三列次像素的栅极；相同的，让第三列次像素（包括第一翻转像素310的次像素B313、第二翻转像素320的次像素B323和第三翻转像素330的次像素B333）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第三列次像素进行预充电。当第三组栅极信号向第三列次像素的栅极发送高电平信号时，由于第一翻转像素310的次像素B313及第三翻转像素330的次像素B333均是正极性数据线8V，配合公共线3的共电极电压由5V调变至低电压0V，对第一翻转像素310的次像素B313及第三翻转像素330的次像素B333预充一8V高电压。同时，第二翻转像素320的次像素B323是负极性数据线2V，配合公共线2还维持同第二组栅极信号开启时的共电极高电压10V，对第二翻转像素320的次像素B323预充一8V高电压。当第三组栅极信号向第三列次像素的栅极发送高电平信号的同时，第一组栅极信号也会向第一列次像素的栅极发送高电平信号，由于第一翻转像素310的次像素R311及第三翻转像素330的次像素R331均是正极性数据线8V，配合此时公共线1的共电极电压回复到正常共电极电压5V，便对第一翻转像素310的次像素R311及第三翻转像素330的次像素R331充上正确显示目标电压3V。同时，第二翻转像素320的次像素R321是负极性数据线2V，配合公共线0共电极电压回复到正常共电极电压5V，对第二翻转像素320的次像素R321预充上正确显示目标电压3V。再接着，第四组栅极信号向第四列次像素的栅极发送高电平信号以打开第四列次像素的栅极；依此类推，便可在一帧内实现过驱动功能。
参考图5，图5为本发明的液晶显示装置的第二较佳实施例的局部示意图。在本实施例中，翻转像素由三个翻转的次像素（次像素R、次像素G和次像素B）组成。在本实施例中，翻转像素是三栅极列驱动，翻转像素按列依次驱动。翻转像素的三个次像素按与扫描信号的扫描方向平行的纵向排列。数据线与一个翻转像素内的所有次像素按次像素R、次像素G和次像素B排列的方向耦接，数据信号驱动以column driving方式驱动，即在同一行内所有的次像素的极性相同。具体地，数据线1与第一翻转像素510的次像素R511、次像素G512和次像素B513耦接。共电极公共线1耦接第一翻转像素510的次像素R511和次像素G512以及第三翻转像素530的次像素R531和次像素G532，公共线2耦接第二翻转像素520的次像素G522和次像素B523，公共线3耦接第一翻转像素510的次像素B513和第四翻转像素540的次像素R541以及第三翻转像素530的次像素B533和第六翻转像素560的次像素R561。公共线1、公共线2和公共线3设置在与数据线垂直的方向上并且以阵列的形式排列。第一翻转像素510和第二翻转像素520相邻，第一翻转像素510和第二翻转像素520相邻的次像素极性相反。参考图5和图4，第一组栅极信号向第一列次像素（包括第一翻转像素510的次像素R511、第二翻转像素520的次像素R521和第三翻转像素530的次像素R531）的栅极发送高电平信号以打开第一列次像素的栅极，让第一列次像素（包括第一翻转像素510的次像素R511、第二翻转像素520的次像素R521和第三翻转像素530的次像素R531）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第一列次像素进行预充电。当第一组栅极信号向第一列次像素的栅极发送高电平信号时，由于第一翻转像素510的次像素R511及第三翻转像素530的次像素R531均是正极性数据线8V，配合公共线1的共电极电压由5V调变至低电压0V，对第一翻转像素510的次像素R511及第三翻转像素530的次像素R531预充一8V高电压。同时，第二翻转像素520的次像素R521是负极性数据线2V，配合公共线0的共电极高电压10V，对第二翻转像素520的次像素R521预充一8V高电压。接着，第一组栅极信号向第一列次像素发送低电压信号以关闭第一列次像素的栅极；第二组栅极信号向第二列次像素（包括第一翻转像素510的次像素G512、第二翻转像素520的次像素G522和第三翻转像素530的次像素G532）的栅极发送高电平信号以打开第二列次像素的栅极，让第二列次像素（包括第一翻转像素510的次像素G512、第二翻转像素520的次像素G522和第三翻转像素530的次像素G532）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第二列次像素进行预充电。当第二组栅极信号向第二列次像素的栅极发送高电平信号时，由于第一翻转像素510的次像素G512及第三翻转像素530的次像素G532均是正极性数据线8V，配合公共线1的共电极电压维持同第一组栅极信号开启时的共电极低电压0V，对第一翻转像素510的次像素G512及第三翻转像素530的次像素G532预充一8V高电压。同时，第二翻转像素520的次像素R522是负极性数据线2V，配合公共线2的共电极电压由5V调变至高电压10V，对第二翻转像素520的次像素G522预充一8V高电压。紧接着，第二组栅极信号向第二列次像素发送低电压信号以关闭第二列次像素的栅极；第三组栅极信号向第三列次像素（包括第一翻转像素510的次像素B513、第二翻转像素520的次像素G523和第三翻转像素530的次像素G533）的栅极发送高电平信号以打开第三列次像素的栅极，让第三列次像素（包括第一翻转像素510的次像素B513、第二翻转像素520的次像素B523和第三翻转像素530的次像素B533）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第三列次像素进行预充电。当第三组栅极信号向第三列次像素的栅极发送高电平信号时，由于第一翻转像素510的次像素B513及第三翻转像素530的次像素B533均是正极性数据线8V，配合公共线3的共电极电压由5V调变至低电压0V，对第一翻转像素510的次像素B513及第三翻转像素530的次像素B533预充一8V高电压。同时，第二翻转像素520的次像素B523是负极性数据线2V，配合公共线2的共电极电压维持同第二组栅极信号开启时的共电极高电压10V，对第二翻转像素520的次像素B523预充一8V高电压。当第三组栅极信号向第三列次像素的栅极发送高电平信号的同时，第一组栅极信号也会向第一列次像素的栅极发送高电平信号，由于第一翻转像素510的次像素R511及第三翻转像素530的次像素R531均是正极性数据线8V，配合此时公共线1的共电极电压回复到正常共电极电压5V，便对第一翻转像素510的次像素R511及第三翻转像素530的次像素R531充上正确显示目标电压3V。同时，第二翻转像素520的次像素R521是负极性数据线2V，配合公共线0的共电极电压回复到正常共电极电压5V，对第二翻转像素520的次像素R521充上正确显示目标电压3V。紧接着，第四组栅极信号开始向第四列次像素的栅极发送一高电平信号以打开第四列次像素的栅极；依此类推，便可在一帧内实现过驱动功能。
参考图6，图6为本发明的液晶显示装置的第三较佳实施例的局部示意图。在本实施例中，垂直条状（Vertical Strip）像素由三个垂直条状（Vertical Strip）的次像素（次像素R、次像素G和次像素B）组成。次像素R、次像素G和次像素B在水平方向上依次排列。数据信号驱动以column driving方式驱动，即在同一行内所有的次像素的极性相同。垂直条状像素按列依次驱动（Vertical Strip with Column Driving）。数据线按与次像素R、次像素G和次像素B排列方向成垂直的方向设置。每条数据线与处在同一行上的垂直条状像素中的同一极性次像素耦接，具体地，数据线1与第一垂直条状像素610的次像素B611、第三垂直条状像素630的次像素B631和第五垂直条状像素650的次像素B651耦接。公共线1、公共线2和公共线3按与数据线垂直的方向设置并且以阵列的形式排列。在本实施例中，公共线1与第一垂直条状像素610的次像素B611和第三垂直条状像素630的次像素B631、第一垂直条状像素610的次像素R613和第三垂直条状像素630的次像素R633以及第二垂直条状像素620的次像素G622和第四垂直条状像素640的次像素G642耦接，公共线2与第三垂直条状像素630的次像素G632和第五垂直条状像素650的次像素G652、第四垂直条状像素640的次像素B641和第六垂直条状像素660的次像素B661以及第四垂直条状像素640的次像素R643和第六垂直条状像素660的次像素R663耦接，公共线3依此类推。第一垂直条状像素610与第二垂直条状像素620相邻，第一垂直条状像素610与第二垂直条状像素620相邻的次像素极性相反；第一垂直条状像素610与第三垂直条状像素630相邻，第一垂直条状像素610与第三垂直条状像素630相邻的次像素极性相反。参考图6和图4，第一组栅极信号向第一列次像素（包括第一垂直条状像素610的次像素B611、次像素G612、次像素R613及第二垂直条状像素620的次像素B621、次像素G622、次像素R623）的栅极发送高电平信号以打开第一列次像素的栅极，让第一列次像素（包括第一垂直条状610的次像素B611、次像素G612、次像素R613及第二垂直条状620的次像素B621、次像素G622、次像素R623）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第一列次像素进行预充电。当第一组栅极信号向第一列次像素的栅极发送高电平信号时，由于第一垂直条状像素610的次像素B611、次像素R613及第二垂直条状像素620的次像素G622均是正极性数据线8V，配合公共线1的共电极电压由5V调变至低电压0V，对第一垂直条状像素610的次像素B611、次像素R613及第二垂直条状像素620的次像素G622预充一8V高电压。同时，第一垂直条状像素610的次像素G612与第二垂直条状像素620的次像素B621及次像素R623是负极性数据线2V，配合公共线0的共电极高电压10V，对第一垂直条状像素610的次像素G612与第二垂直条状像素620的次像素B621及次像素R623预充一8V高电压。接着，第一组栅极信号向第一列次像素发送低电压信号以关闭第一列次像素的栅极；第二组栅极信号向第二列次像素（包括第三垂直条状像素630的次像素B631、次像素G632、次像素R633及第四垂直条状像素640的次像素B641、次像素G642、次像素R643）的栅极发送高电平信号以打开第二列次像素的栅极，让第二列次像素（包括第三垂直条状像素630的次像素B631、次像素G632、次像素R633及第四垂直条状像素640的次像素B641、次像素G642、次像素R643）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第二列次像素进行预充电。当第二组栅极信号向第二列次像素的栅极发送高电平信号时，由于第三垂直条状像素630的次像素B631、次像素R633及第四垂直条状像素640的次像素G642均是正极性数据线8V，配合公共线1的共电极电压维持同第一组栅极信号开启时的共电极低电压0V，对第三组垂直条状像素630的次像素B631、次像素R633及第四组垂直条状像素640的次像素G642预充一8V高电压。同时，第三垂直条状像素630的次像素G632与第四垂直条状像素640的次像素B641及次像素R643是负极性数据线2V，配合公共线2的共电极电压由5V调变至高电压10V，对第三垂直条状像素630的次像素G632与第四垂直条状像素640的次像素B641及次像素R643预充一8V高电压。紧接着，第二组栅极信号向第二列次像素发送低电压信号以关闭第二列次像素的栅极；第三组栅极信号向第三列次像素（包括第五垂直条状像素650的次像素B651、次像素G652、次像素R653及第六垂直条状像素660的次像素B661、次像素G662、次像素R663）的栅极发送高电平信号以打开第三列次像素的栅极，让第三列次像素（包括第五垂直条状650的次像素B651、次像素G652、次像素R653及第六垂直条状660的次像素B661、次像素G662、次像素R663）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第三列次像素进行预充电。当第三组栅极信号向第三列次像素的栅极发送高电平信号时，由于第五垂直条状像素650的次像素B651、次像素R653及第六垂直条状像素660的次像素G662均是正极性数据线8V，配合公共线3的共电极电压由5V调变至低电压0V，对第五垂直条状像素650的次像素B651、次像素R653及第六垂直条状像素660的次像素G662预充上一8V高电压。同时，第五垂直条状像素650的次像素G652与第六垂直条状像素660的次像素B661及次像素R663是负极性数据线2V，配合公共线2的共电极电维持同第二组栅极信号开启时的共电极高电压10V，对第五组垂直条状像素650的次像素G652与第六垂直条状像素660的次像素B661及次像素R663预充一8V高电压。当第三组栅极信号向第三列次像素的栅极发送高电平信号的同时，第一组栅极信号也会向第一列次像素的栅极发送高电平信号，由于第一组垂直条状像素610的次像素B611、次像素R613及第二组垂直条状像素620的次像素G622均是正极性数据线8V，配合此时公共线1的共电极电压回复到正常共电极电压5V，便对第一组垂直条状像素610的次像素B611及、次像素R613及第二组垂直条状像素620的次像素G622充上正确显示目标电压3V。同时，第一组垂直条状像素610的次像素G612及第二组垂直条状像素620的次像素B621、次像素R623是负极性数据线2V，配合公共线0的共电极电压回复到正常共电极电压5V，对第一组垂直条状像素610的次像素G612及第二组垂直条状像素620的次像素B621、次像素R623充上正确显示目标电压3V。紧接着，第四组栅极信号开始向第四列次像素的栅极发送一高电平信号以打开第四列次像素的栅极；依此类推，便可在一帧内实现过驱动功能。
参考图7，图7为本发明的液晶显示装置的第四较佳实施例的局部示意图。图7同样是在列驱动（Column Driving）的条件下实现本发明的液晶显示装置的过驱动功能。垂直条状像素由三个垂直条状的次像素（次像素R、次像素G和次像素B）组成。次像素R、次像素G和次像素B在水平方向上依次排列。第一垂直条状像素710和第二垂直条状像素720排成一列，第三垂直条状像素730和第四垂直条状像素740排成一列，依此类推。数据线依Flip pixel设计，同一数据线连接垂直方向各垂直条状像素，垂直方向上奇数像素相同的次像素(次像素R、次像素G和次像素B其中之一)及偶数像素相同的次像素(次像素R、次像素G和次像素B其中之一)连接在同一数据线，其中奇数像素的次像素的极性异于偶数像素的次像素的极性。具体地，数据线1与第一垂直条状像素710的次像素B711、第三垂直条状像素730的次像素G732和第五垂直条状像素750的次像素B751耦接，数据线2与第一垂直条状像素710的次像素G712、第三垂直条状像素730的次像素R733和第五垂直条状像素750的次像素G752耦接，数据线3与第一垂直条状像素710的次像素R713、第四垂直条状像素740的次像素B741和第五垂直条状像素750的次像素R753耦接，依此类推。公共线1、公共线2和公共线3按与数据线垂直的方向设置并以阵列的形式排列。在本实施例中，公共线与在垂直方向上相邻的两个垂直条状像素的互相错开的次像素耦接，具体地，公共线1与第一垂直条状像素710的次像素B711、次像素R713和第二垂直条状像素720的次像素G722和第三垂直条状像素730的次像素G732以及第四垂直条状像素740的次像素B741、次像素R743耦接，公共线2与第三垂直条状像素730的次像素B731、次像素R733和第四垂直条状像素740的次像素G742和第五垂直条状像素750的次像素G752以及第六垂直条状像素760的次像素B761、次像素R763耦接，公共线3依此类推。第一垂直条状像素710和第二垂直条状像素720相邻，第一垂直条状像素710和第二垂直条状像素720相邻的次像素具有相反的极性；第一垂直条状像素710和第三垂直条状像素730相邻，第一垂直条状像素710和第三垂直条状像素730相邻的次像素具有相反的极性。参考图7和图4，第一组栅极信号向第一列次像素（包括第一垂直条状像素710的次像素B711、次像素G712、次像素R713及第二垂直条状像素720的次像素B721、次像素G722、次像素R723）的栅极发送高电平信号以打开第一列次像素的栅极，让第一列次像素（包括第一垂直条状710的次像素B711、次像素G712、次像素R713及第二垂直条状720的次像素B721、次像素G722、次像素R723）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第一列次像素进行预充电。当第一组栅极信号向第一列次像素的栅极发送高电平信号时，由于第一垂直条状像素710的次像素B711、次像素R713及第二垂直条状像素720的次像素G722均是正极性数据线8V，配合公共线1的共电极电压由5V调变至低电压0V，对第一垂直条状像素710的次像素B711、次像素R713及第二垂直条状像素720的次像素G722预充一8V高电压。同时，第一垂直条状像素710的次像素G712与第二垂直条状像素720的次像素B721及次像素R723是负极性数据线2V，配合公共线0的共电极高电压10V，对第一垂直条状像素710的次像素G712与第二垂直条状像素720的次像素B721及次像素R723预充一8V高电压。接着，第一组栅极信号向第一列次像素发送低电压信号以关闭第一列次像素的栅极；第二组栅极信号向第二列次像素（包括第三垂直条状像素730的次像素B731、次像素G732、次像素R733及第四垂直条状像素740的次像素B741、次像素G742、次像素R743）的栅极发送高电平信号以打开第二列次像素的栅极，让第二列次像素（包括第三垂直条状730的次像素B731、次像素G732、次像素R733及第四垂直条状740的次像素B741、次像素G742、次像素R743）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第二列次像素进行预充电。当第二组栅极信号向第二列次像素的栅极发送高电平信号时，由于第三垂直条状像素730的次像素G732及第四垂直条状像素740的次像素B741、次像素R743均是正极性数据线8V，配合公共线1的共电极电压维持同第一组栅极信号开启时的共电极低电压0V，对第三组垂直条状像素730的次像素G732及第四垂直条状像素740的次像素B741、次像素R743预充一8V高电压。同时，第三组垂直条状像素730的次像素B731、次像素R733与第四组垂直条状像素740的次像素G742是负极性数据线2V，配合公共线2的共电极电压由5V调变至高电压10V，对第三组垂直条状像素730的次像素B731、次像素R733与第四组垂直条状像素740的次像素G742预充一8V高电压。紧接着，第二组栅极信号向第二列次像素发送低电压信号以关闭第二列次像素的栅极；第三组栅极信号向第三列次像素（包括第五垂直条状像素750的次像素B751、次像素G752、次像素R753及第六垂直条状像素760的次像素B761、次像素G762、次像素R763）的栅极发送高电平信号以打开第三列次像素的栅极，让第三列次像素（包括第五垂直条状750的次像素B751、次像素G752、次像素R753及第六垂直条状760的次像素B761、次像素G762、次像素763）内的充电电压由1V变成3V前，利用数据线8V与共电极调变信号0V或者数据信号2V与共电极调变信号10V的充电电压8V来给第三列次像素进行预充电。当第三组栅极信号向第三列次像素的栅极发送高电平信号时，由于第五垂直条状像素750的次像素B751、次像素R753及第六垂直条状像素760的次像素G762均是正极性数据线8V，配合公共线3的共电极电压由5V调变至低电压0V，对第五垂直条状像素750的次像素B751、次像素R753及第六垂直条状像素760的次像素G762预充上一8V高电压。同时，第五垂直条状像素750的次像素G752与第六组垂直条状像素760的次像素B761及次像素R763是负极性数据线2V，配合公共线2的共电极电维持同第二组栅极信号开启时的共电极高电压10V，对第五组垂直条状像素750的次像素G752与第六垂直条状像素760的次像素B761及次像素R763预充一8V高电压。当第三组栅极信号向第三列次像素的栅极发送高电平信号的同时，第一组栅极信号也会向第一列次像素的栅极发送高电平信号，由于第一组垂直条状像素710的次像素B711、次像素R713及第二组垂直条状像素720的次像素G722均是正极性数据线8V，配合此时公共线1的共电极电压回复到正常共电极电压5V，便对第一组垂直条状像素710的次像素B711及、次像素R713及第二组垂直条状像素720的次像素G722充上正确显示目标电压3V。同时，第一组垂直条状像素710的次像素G712及第二组垂直条状像素720的次像素B721、次像素R723是负极性数据线2V，配合公共线0的共电极电压回复到正常共电极电压5V，对第一组垂直条状像素710的次像素G712及第二组垂直条状像素720的次像素B721、次像素R723充上正确显示目标电压3V。紧接着，第四组栅极信号开始向第四列次像素的栅极发送一高电平信号以打开第四列次像素的栅极；依此类推，便可在一帧内实现过驱动功能。
统观上述实施例，本发明的液晶显示装置的信号驱动方法包括以下步骤：扫描驱动模块产生扫描信号并将该扫描信号发送给扫描线；数据驱动模块产生数据信号并将该数据信号发送给数据线；扫描线将该扫描信号发送给像素中的至少一个次像素，扫描信号对处于同一行的次像素按列依次扫描；数据线将该数据线发送给像素中的至少一个次像素，数据线在将该数据信号输入到次像素中之前对该次像素进行预充电。另外，上述方法还可以包括以下步骤：公共线根据与其耦接的次像素的极性向该次像素施加高电压或低电压。
综上所述，虽然本发明已以优选实施例揭露如上，但上述优选实施例并非用以限制本发明，本领域的普通技术人员，在不脱离本发明的精神和范围内，均可作各种更动与润饰，因此本发明的保护范围以权利要求界定的范围为准。
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  1. 一种液晶显示装置，其特征在于，包括：
    扫描驱动模块，用于产生扫描信号并将所述扫描信号发送给所述扫描线；
    数据驱动模块，用于产生数据信号并将所述数据信号发送给所述数据线；
    薄膜晶体管阵列面板，其上设有像素，所述像素包括次像素R、次像素G和次像素B；
    扫描线，所述扫描线与所述像素中的至少一个次像素耦接，所述扫描信号对处于同一行的次像素按列依次扫描；
    数据线，所述数据线与所述像素中的至少一个次像素耦接，所述数据线用于在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号；
    所述液晶显示装置还包括公共线，所述公共线与所述像素中的至少一个次像素耦接，用于根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压；
    所述像素的三个所述次像素排列按与所述扫描信号的扫描方向平行或垂直的方向排列；
    所述公共线与所述扫描信号对次像素进行扫描的方向垂直；
    两个相邻的所述像素的相邻两个次像素具有相反的极性。
  2. 根据权利要求1所述的液晶显示装置，其特征在于，每一条所述公共线与极性相同的次像素耦接。
  3. 根据权利要求1所述的液晶显示装置，其特征在于，每一条所述数据线与极性相同的次像素耦接。
  4. 一种液晶显示装置，其特征在于，包括：
    扫描驱动模块，用于产生扫描信号并将所述扫描信号发送给所述扫描线；
    数据驱动模块，用于产生数据信号并将所述数据信号发送给所述数据线；
    薄膜晶体管阵列面板，其上设有像素，所述像素包括次像素R、次像素G和次像素B；
    扫描线，所述扫描线与所述像素中的至少一个次像素耦接，所述扫描信号对处于同一行的次像素按列依次扫描；
    数据线，所述数据线与所述像素中的至少一个次像素耦接，所述数据线用于在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号。
  5. 根据权利要求4所述的液晶显示装置，其特征在于，所述液晶显示装置还包括公共线，所述公共线与所述像素中的至少一个次像素耦接，用于根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压。
  6. 根据权利要求4所述的液晶显示装置，其特征在于，所述像素的三个所述次像素排列按与所述扫描信号的扫描方向平行的方向排列。
  7. 根据权利要求4所述的液晶显示装置，其特征在于，所述像素的三个所述次像素排列按与所述扫描信号的扫描方向垂直的方向排列。
  8. 根据权利要求6或7所述的液晶显示装置，其特征在于，所述公共线与所述扫描信号对次像素进行扫描的方向垂直。
  9. 根据权利要求4所述的液晶显示装置，其特征在于，两个相邻的所述像素的相邻两个次像素具有相反的极性。
  10. 根据权利要求9所述的液晶显示装置，其特征在于，每一条所述公共线与极性相同的次像素耦接。
  11. 根据权利要求9所述的液晶显示装置，其特征在于，每一条所述数据线与极性相同的次像素耦接。
  12. 一种液晶显示装置的信号驱动方法，其特征在于，所述液晶显示装置包括扫描驱动模块、数据驱动模块、薄膜晶体管阵列面板、扫描线和数据线，所述薄膜晶体管阵列面板上设有像素，所述像素包括次像素R、次像素G和次像素B，所述方法包括以下步骤：
    （A）、扫描驱动模块产生扫描信号并将所述扫描信号发送给所述扫描线；
    （B）、数据驱动模块产生数据信号并将所述数据信号发送给所述数据线；
    （C）、扫描线将所述扫描信号发送给所述像素中的至少一个次像素，所述扫描信号对处于同一行的次像素按列依次扫描；
    （D）、数据线将所述数据线发送给所述像素中的至少一个次像素，所述数据线在将所述数据信号输入到所述次像素之前对所述次像素输入高电压进行预充电，预充电后，再对所述次像素输入用于显示图像的信号。
  13. 根据权利要求12所述的液晶显示装置的信号驱动方法，其特征在于，所述方法还包括以下步骤：
    （E）、公共线根据与其耦接的所述次像素的极性向所述次像素施加高电压或低电压。
PCT/CN2011/078958 2011-06-24 2011-08-26 液晶显示装置及其信号驱动方法 Ceased WO2012174792A1 (zh)

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