WO2012174695A1 - 多晶硅假栅移除后的监控方法 - Google Patents

多晶硅假栅移除后的监控方法 Download PDF

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Publication number
WO2012174695A1
WO2012174695A1 PCT/CN2011/001992 CN2011001992W WO2012174695A1 WO 2012174695 A1 WO2012174695 A1 WO 2012174695A1 CN 2011001992 W CN2011001992 W CN 2011001992W WO 2012174695 A1 WO2012174695 A1 WO 2012174695A1
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Prior art keywords
wafer
dummy gate
quality
polysilicon
polysilicon dummy
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English (en)
French (fr)
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杨涛
赵超
李俊峰
闫江
陈大鹏
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to US13/499,288 priority Critical patent/US8501500B2/en
Publication of WO2012174695A1 publication Critical patent/WO2012174695A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H10P74/20—Testing or measuring during manufacture or treatment of wafers, substrates or devices characterised by the properties tested or measured, e.g. structural or electrical properties
    • H10P74/203—Structural properties, e.g. testing or measuring thicknesses, line widths, warpage, bond strengths or physical defects
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of monitoring after removal of a polysilicon dummy gate. Background technique
  • the poly gate is removed and then filled into the metal gate electrode.
  • the process is shown in Figure 1.
  • an insulating layer 2, a polysilicon dummy gate 3, a gate sidewall 4, and an interlayer dielectric layer (ILD) 5 are sequentially formed on the substrate 1.
  • the polysilicon dummy gate 3 is removed, a gate opening 6 is formed, and then the metal gate electrode material is filled.
  • the polysilicon gate sidewall 4 is a spacer of silicon oxide or silicon nitride material, and the insulating layer 2 under the poly gate is a deposited high K or silicon oxide or silicon oxynitride material.
  • there are three process routes in the industry to complete the removal of polycrystalline dummy gates namely dry etching, wet etching, and dry-wet hybrid etching; from the experimental and reported results, the trend is more The latter two methods.
  • the object of the present invention is to provide a monitoring method after the polysilicon dummy gate is removed, so as to quickly and accurately monitor and determine whether the polysilicon dummy gate is completely removed, and the measuring method does not cause damage to the wafer.
  • the invention provides a monitoring method after removing the polysilicon dummy gate, comprising the steps of: forming a polysilicon dummy gate structure on the surface of the wafer; determining a measurement target and an error range of the wafer quality; and using the quality after removing the polysilicon dummy gate
  • the measuring device measures the quality of the wafer and determines whether the polysilicon gate is completely removed.
  • the invention also provides a monitoring method after removing the polysilicon dummy gate, comprising the steps of: forming a polysilicon dummy gate structure on the surface of the wafer; determining a measurement target and an error range of the wafer quality difference; measuring by using a mass measurement device Wafer quality, determine the pre-wafer quality value; After removing the polysilicon dummy gate, measure the quality of the wafer using a mass measurement device to determine the post-wafer quality value and determine whether the polysilicon is completely removed.
  • an insulating layer is included, and the insulating layer is a high-k material, silicon oxide or silicon oxynitride. .
  • the insulating layer is removed simultaneously with the polysilicon dummy gate.
  • the mass measuring device is a mechanical precision balance, an electronic precision balance or a semi-automatic/automatic plus code electro-optical projection damping precision balance.
  • This patent proposes a monitoring route after the removal of two polycrystalline false gates, using wafer quality or poor quality detection to monitor whether the polycrystalline dummy gate removal is completely removed.
  • Amount according to the invention The measurement method can quickly and accurately measure the entire wafer without a specific test structure, thereby effectively monitoring whether the polysilicon dummy gate is completely removed, and the measurement method feedback result is intuitive, fast, accurate, and does not take the wafer. Come to damage.
  • Figure 1 shows a schematic of the back gate process.
  • the present invention monitors the polycrystalline dummy by measuring the quality of the wafer after removing the polycrystalline dummy gate. Whether the gate removal is completely removed, and then the process is judged to be acceptable.
  • the specific measurement method steps can be as shown in the following embodiments.
  • an insulating layer 2, a polysilicon dummy gate 3, a gate sidewall 4, an interlayer dielectric layer (ILD) 5 are sequentially formed on the substrate 1, and then the polysilicon dummy gate 3 is removed to form a gate opening 6. .
  • the quality of the wafer as a thin film that is, the ILD 5 on the wafer surface and the sidewalls of the sidewall 4 and the gate opening 6 interposed therebetween
  • the sum of the masses will be significantly reduced. Therefore, by monitoring the quality of the wafer, it can be judged whether the polycrystalline dummy gate is completely removed.
  • the measurement method will have intuitive test results, no damage to the wafer, and high measurement efficiency.
  • the method for monitoring a polysilicon dummy gate in a back gate process in accordance with an embodiment of the present invention includes the following steps: First, a polysilicon dummy gate structure is formed on the surface of the wafer. As shown in FIG. 1, a polysilicon dummy gate structure is formed on the surface of the wafer, that is, an insulating layer 2, a polysilicon dummy gate 3, a gate sidewall 4, and an interlayer dielectric layer (ILD) 5 are sequentially formed on the substrate 1. The polysilicon dummy gate 3 is then removed to form a gate opening 6.
  • the substrate 1 may be bulk silicon, silicon-on-insulator (SOI), SiGe, 5 GaAs or other semiconductor materials.
  • the material of the insulating layer 2 may be silicon oxide, silicon oxynitride or a high-k material such as Hf0 2 , Ti0 2 , Ta 2 5 5 , HfAlN, barium titanate (BST) or the like.
  • the gate sidewall 4 is made of a material having a larger etching selectivity than the multiple H 3 ⁇ 4 silicon dummy gate 3, such as silicon nitride.
  • ILD5 is typically a low density or low k material such as spin-on borophosphosilicate glass (BPSG), porous silica, and the like.
  • the method of forming the polysilicon dummy gate 3 is generally chemical
  • Vapor deposition which is obtained by controlling the CVD temperature to obtain materials of different crystal states, for example, polycrystalline silicon at 625 °C or higher.
  • the polysilicon dummy gate structure can be formed on the test wafer (ie, the spare wafer not used for the final chip-cut product) to determine the wafer of a certain product type after the polycrystalline dummy gate is removed ( A destructive SEM or TEM test can be performed on the sample, and those wafers in which the polysilicon dummy gate 3 is completely removed are selected as samples. This experimental step can be called DOE) the remaining quality of the wafer, that is, the standard quality of the wafer. At this time, the thickness of the polysilicon dummy gate 3 should be zero.
  • the variation range of the residual quality of the wafer after the polysilicon dummy gate is completely removed is obtained.
  • the measurement target and error range of the residual quality of the wafer are reasonably defined.
  • the DOE obtains a polysilicon false gate 3 on a wafer of a certain product model
  • the quality of the remaining structure is 151.203g
  • the variation range is up and down. 9.751 g
  • the criterion for determining the complete removal of the polysilicon dummy gate without over-etching is that the mass of the remaining structure is 151.203 ⁇ 9.751 g.
  • the purpose of the DOE experiment is to find the variation range of the residual quality of the wafer after the polycrystalline false gate is completely removed (SPEC).
  • the polysilicon in the polysilicon dummy gate is removed and dried.
  • the polysilicon of the polysilicon dummy gate 3 may be removed by dry etching using a fluorocarbon plasma etching, or the polysilicon dummy gate 3 may be removed by wet etching using an etching solution such as KOH or TAMH, or these dry methods may be used. Hybrid etching of wet etching. Reasonable selection of the flow rate or concentration of the etching material, pressure and other parameters to control the etching speed, so that the polysilicon of the polysilicon dummy gate 3 is substantially completely in a given time.
  • the drying process can be high-speed drying at a certain temperature in an N2 environment, or drying the wafer based on the Malangi principle.
  • the mass measuring equipment is preferably a precision instrument such as a mechanical precision balance, an electronic precision balance, a semi-automatic/automatic plus coded electro-optical projection damping precision day equalization, and the like. If the residual quality of the wafer is within the error range (the tolerance range has been determined by step 2, for example, 9.751g), the polycrystalline dummy gate 3 can be considered to be corroded and removed. If the wafer quality is not within the error range, it is considered that the polycrystalline dummy gate 3 is not completely removed and needs to be re-processed, that is, the batch sample is sent back to the process line for secondary etching.
  • a precision instrument such as a mechanical precision balance, an electronic precision balance, a semi-automatic/automatic plus coded electro-optical projection damping precision day equalization, and the like.
  • the above embodiment of the present invention obtains the quality variation range after the polysilicon dummy gate is completely removed by experimental design, and then tests the wafer quality of the actual product through the mass measurement device to determine whether the polysilicon dummy gate 3 is completely removed.
  • This test and the method of removing the polysilicon dummy gate by back gate etching avoid the SEM or TEM damage test for large-scale products, which improves the test efficiency and saves the cost.
  • a method of monitoring a polysilicon dummy gate in a back gate process in accordance with another embodiment of the present invention includes the following steps:
  • a polysilicon dummy gate structure is formed on the surface of the wafer. As shown in FIG. 1, a polysilicon dummy gate structure is formed on the surface of the wafer, that is, an insulating layer 2, a polysilicon dummy gate 3, a gate sidewall 4, and an interlayer dielectric layer are sequentially formed on the substrate 1. (ILD) 5 Then, the polysilicon dummy gate 3 is removed to form a gate opening 6.
  • the polysilicon dummy grid can be formed on the test wafer (ie, the spare wafer not used for the final chip-cut product), and the design of experimental (DOE) and quality testing methods are used to determine
  • DOE experimental
  • a polycrystalline dummy gate is removed from a wafer of a certain product type (destructive SEM or TEM test can be performed on the sample, and those wafers in which the polysilicon dummy gate 3 is completely removed are selected as samples)
  • the quality of the front and back is poor, that is, the wafer quality standard is poor.
  • the thickness of the polysilicon dummy gate 3 should be zero. After measuring the data of multiple batches of multiple batches of wafers, the range of variation in quality is obtained.
  • the wafer quality difference measurement target and the error range are reasonably defined.
  • the polysilicon dummy gate 3 is completely removed, and the wafer front-end quality difference is 12.450 g, and the variation range is 1.017 g.
  • the criterion for determining that the polysilicon dummy gate is completely removed and that there is no overetching is that the mass difference before and after the wafer removal of the polysilicon dummy gate is 12.450 ⁇ 1.017g.
  • the wafer shield is measured using a mass measurement device to obtain a wafer quality pre-value M1.
  • the quality of a batch of wafers before removal Ml is 160.479g.
  • the polysilicon of the polysilicon dummy gate 3 may be removed by dry etching using a fluorocarbon plasma etching, or the polysilicon dummy gate 3 may be removed by wet etching using an etching solution such as KOH or TAMH, or these dry methods may be used. Hybrid etching of wet etching. The etch rate is controlled by a reasonable selection of the flow rate or concentration of the etching material, the gas pressure, and the like, so that the polysilicon of the polysilicon dummy gate 3 is substantially completely etched at a given time.
  • the wafer quality difference M1-M2 is automatically calculated by the device to determine whether the polysilicon is completely removed and/or An etch has occurred. For example, if the measured wafer value M2 of the above batch is 148.762g, the mass difference is 11.1717g. If the wafer quality difference is within the error range (the tolerance range has been determined by step 2), it can be considered that the polycrystalline dummy gate 3 has been cleaned and cleaned without over-corrosion. If the wafer quality is not within the error range, it is considered that the polycrystalline dummy gate 3 is not completely removed and needs to be reprocessed, that is, the batch sample is sent back to the process line for secondary etching.
  • the error range the tolerance range has been determined by step 2
  • the insulating layer 2 is a gate dielectric layer of the back gate process. If the insulating layer 2 is a high-k material for the gate dielectric layer of the back gate process, in the monitoring method of the present invention, the insulating layer 2 is not removed with the polysilicon dummy gate 3, but is retained together, so the monitoring method is not change. However, if the insulating layer 2 is only used for the etch stop layer of the polysilicon dummy gate 3, that is, the material is a common insulating dielectric material, such as silicon dioxide, the insulating layer 2 should be removed along with the polysilicon dummy gate 3, and the present invention is The above two embodiments need to make corresponding changes.
  • the monitoring method of Embodiment 3 for the variant of Embodiment 1 includes:
  • step 3 Using a mass measurement device to measure the wafer quality; if the wafer quality is within tolerance (the tolerance range has been determined by step 1), it can be considered that the polycrystalline dummy gate 3 and the insulating layer 2 have been corroded. Cleaned; If the wafer quality is not within the tolerance, the polycrystalline dummy gate 3 and the insulating layer 2 are considered to be completely removed; the process conditions need to be adjusted.
  • the mass measurement device is used to measure the wafer quality, and the wafer quality pre-value is obtained;
  • a mass measurement device to measure the wafer quality, obtain the post-wafer quality value, and automatically calculate the mass difference by the device; if the wafer quality difference is within the tolerance range (the tolerance range has been determined by step 1) ), it can be considered that the polycrystalline dummy gate 3 and the insulating layer 2 have been etched and removed; if the wafer quality difference is not within the tolerance range, it can be considered that the polycrystalline dummy gate 3 and the insulating layer 2 are not completely removed; Condition adjustment.
  • the destructive test using SEM or TEM for large-scale products is avoided, and the test efficiency is improved and the cost is saved.

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  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

本发明提供了一种多晶硅假栅移除后的监控方法，包括以下步骤：在晶圆表面形成多晶硅假栅结构；确定晶圆质量的量测目标及误差范围；去除多晶硅假栅之后，使用质量量测设备测量晶圆的质量，判断多晶硅假栅是否完全移除。依照本发明的量测方法，可以不需要特定测试结构而快速准确对晶圆整片测量，从而有效监控判断多晶硅假栅是否彻底移除，同时该量测方法反馈结果直观、快速、准确，对晶圆不会带来损伤。

Description

多晶硅假栅移除后的监控方法 优先权要求
本申请要求了 2011年 6月 20日提交的、 申请号为 201110165279.5、 发明名称为 "多晶硅假栅移除后的监控方法" 的中国专利申请的优先 权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件的制造方法， 更具体地讲， 涉及一种 多晶硅假栅移除后的监控方法。 背景技术
随高 K/金属栅工程在 45 纳米技术节点上的成功应用，使其成为亚 30纳米以下技术节点不可缺少的关键模块化工程。 目前只有坚持高 K/ 后金属栅 (gate last)路线的英特尔公司在 45纳米和 32纳米量产上取得 了成功。 近年来紧随 IBM产业联盟的三星、 台积电、 英飞凌等业界巨 头也将之前开发的重点由高 K/先金属栅 (gate first)转向 gate last工程。
Gate last工程中， 在完成离子高温退火后， 需要把多晶栅挖掉， 而 后在填充进金属栅电极， 流程详见图 1。 如图 1A, 衬底 1上依次形成绝 缘层 2、 多晶硅假栅极 3、 栅极侧壁 4、 层间介质层 （ILD ) 5。 如图 1B , 去除多晶硅假栅极 3 , 形成栅极开口 6， 然后填充金属栅电极材料。 多 晶栅侧壁 4为氧化硅或氮化硅材料的侧墙 (spacer),多晶栅下面的绝缘层 2是淀积好的高 K或是氧化硅或是氮氧化硅材料。 目前， 工业界有三条 工艺路线来完成多晶假栅的去除工作， 分别是干法刻蚀， 湿法刻蚀， 以及干法-湿法混合刻蚀； 从实验及报道的结果看， 更倾向于后两种方 法。
多晶假栅 3去除后， 需要进行有效的监控手段来判断多晶硅是否完 全去除掉， 任何多晶的残留都会对器件电性能造成极大的负面影响。 该项工艺属于 32nm及以下的先进工艺，在多晶假栅 3移除后如何有效对 制程进行监控， 尚未见任何报道。 最直观的方法是通过扫描电子显微 镜看多晶假栅 3移除后晶 ¾]的横截面， 但这种方法对晶圓具有破坏性， 并且反馈结果很慢， 无法直接用于量产时对制程的有效监控。 同时， 目前集成电路工业界对工艺制程的监控大部分采用的是光学量测手 段， 而随技术节点的不断缩小， 器件结构越来越复杂， 叠层的薄膜越 来越薄， 传统光学量测方法遇到了很大挑战。 为此， 急需一种直观的， 对晶圆无损伤的快速准确有效的监控方法来判断多晶假栅移除得是否 彻底》 发明内容
因此， 本发明的目的在于提出一种多晶硅假栅移除后的监控方法， 以便快速准确有效监控判断多晶硅假栅是否彻底移除， 同时， 该量测 方法对晶圆不会带来损伤。
本发明提供了一种多晶硅假栅移除后的监控方法， 包括以下步骤： 在晶圓表面形成多晶硅假栅结构； 确定晶圆质量的量测目标及误差范 围； 去除多晶硅假栅之后， 使用质量量测设备测量晶圆的质量， 判断 多晶硅^ _栅是否完全移除。
本发明还提供了一种多晶硅假栅移除后的监控方法， 包括以下步 骤： 在晶圆表面形成多晶硅假栅结构； 确定晶圆质量差的量测目标及 误差范围； 使用质量量测设备测量晶圓的质量， 确定晶圆质量前值； 去除多晶硅假栅之后， 使用质量量测设备测量晶圓的质量以确定晶圆 质量后值， 判断多晶硅是否完全移除。
其中， 多晶硅假栅下方包括绝缘层， 所述绝缘层为高 k材料、 氧化 硅或氮氧化硅。 .
其中， 所述绝缘层与所述多晶硅假栅同时被去除。
其中， 通过实验性设计 （DOE ), 获取多晶硅假栅被完全去除的样 品晶圓的质量或质量差以及误差范围。
其中， 如果晶圆质量超出误差范围， 则判定多晶硅没有完全去除， 需要二次处理。
其中， 如果晶圆质量前值与后值的差超出晶圓质量差的误差范围， 则判定多晶硅没有完全去除， 需要二次处理。
其中， 所述质量量测设备为机械精密天平、 电子精密天平或半自 动 /全自动加码电光投影阻尼精密天平。
本专利提出了两条多晶假栅移除后的监控路线， 采用了晶圓质量 或质量差的检测来监控多晶假栅移除是否移除彻底。 依照本发明的量 测方法， 可以不需要特定测试结构而快速准确对晶圆整片测量， 从而 有效监控判断多晶硅假栅是否彻底移除， 同时该量测方法反馈结果直 观、 快速、 准确， 对晶圓不会带来损伤。
本发明所述目的， 以及在此未列出的其他目的， 在本申请独立权 利要求的范围内得以满足。 本发明的实施例限定在独立权利要求中， 具体特征限定在其从属权利要求中。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1显示了后栅工艺示意图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了提出采用晶圆质量量测技术对后栅工艺 多晶硅假栅移除进行监控， 并给出相应的测试结构。 需要指出的是， 类似的附图标记表示类似的结构。
由附图 1 可以得知， 在多晶硅假栅移除之后， 晶圆质量将明显减 小， 基于此种原理， 本发明将通过测量晶圓去除多晶假栅后的质量， 来监控多晶假栅移除是否移除彻底， 进而判断该工艺是否合格。 具体 的测量方法步骤可以如下实施例所示。 实施例 1
参照附图 1 , 在衬底 1上依次形成绝缘层 2、 多晶硅假栅极 3、 栅 极侧壁 4、 层间介质层 （ILD ) 5， 然后去除多晶硅假栅极 3 , 形成栅极 开口 6。 由图 1可见， 在多晶假栅 3移除后， 晶圓当层薄膜的质量（也 即晶圆表面上 ILD5及其之间所夹设的侧壁 4、 栅极开口 6的各层薄膜 质量之和） 将明显减小， 因此通过对晶圆质量的监控， 即可判断多晶 假栅是否完全去除干净； 采用该方法测量将具有测试结果直观， 对晶 圓无损伤以及测量效率高的特点， 适合多晶假栅移除后对工艺的有效 监控。
具体地， 依照本发明的一个实施例的后栅工艺移除多晶硅假栅的 监控方法包括以下步骤： 首先， 在晶圆表面形成多晶硅假栅结构。 如图 1 所示， 晶圆表面 形成有多晶硅假栅结构， 也即在衬底 1上依次形成绝缘层 2、 多晶硅假 栅极 3、 栅极侧壁 4、 层间介质层（ ILD ) 5， 然后去除多晶硅假栅极 3 , 形成栅极开口 6。 其中， 衬底 1可为体硅、 绝缘体上硅 （SOI )、 SiGe、 5 GaAs或其他半导体材料。 绝缘层 2材质可以是氧化硅、 氮氧化硅， 或 是高 K材料， 例如 Hf02、 Ti02、 Ta205、 HfAlN、 钛酸钡 （ BST )等等。 栅极侧壁 4材质为与多 H¾硅假栅 3具有较大刻蚀选择比的材质， 例如 为氮化硅。 ILD5 —般为低密度或低 k 材料， 例如旋涂的硼磷硅玻璃 ( BPSG )、 多孔二氧化硅等等。 形成多晶硅假栅 3 的方法一般为化学
10 气相沉积， 通过控制 CVD温度得到不同结晶状态的材料， 例如在 625 °C以上得到多晶硅。
其次， 确定去除多晶硅假栅之后晶圓质量的量测目标及误差范围。 可以先在测试用的晶圆 （即不用于最后切割成芯片产品的备用晶圆） 上按流程形成多晶硅假栅结构， 确定某一产品型号的晶圆在多晶假栅 i s 移除干净后 （可以针对样片做破坏性的 SEM或 TEM测试， 选取那些 多晶硅假栅 3 被完全去除的晶圆作为样本， 这种实验性步骤可称为 DOE ) 晶圓的剩余质量， 也即晶圆标准质量， 此时多晶硅假栅 3 的厚 度应为 0。 测量多批次晶圓多片的数据后， 得到多晶硅假栅完全去除之 后晶圆剩余质量的变化范围。 根据上述结果合理定义晶圆剩余质量的 0 量测目标及误差范围， 例如 DOE得到某一产品型号的晶圓上多晶硅假 栅 3 完全去除时剩余结构的质量为 151.203g， 其变化范围为上下浮动 9.751 g，则判定多晶硅假栅完全去除且没有过刻蚀的标准是剩余结构的 质量为 151.203±9.751g。 其中， DOE 实验目的就是找到多晶假栅彻底 去除后， 晶圆剩余质量的变化范围 .（SPEC )。
5 然后， 去除多晶硅假栅中的多晶硅并干燥。 可以采用碳氟基等离 子体刻蚀的干法刻蚀来去除多晶硅假栅 3的多晶硅，也可以采用 KOH、 TAMH等刻蚀液湿法刻蚀去除多晶硅假栅 3， 还可以是这些干法、 湿法 刻蚀的混合刻蚀。 合理选择刻蚀原料的流量或浓度、 气压等等参数来 控制刻蚀速度， 使得在给定时间内多晶硅假栅 3 的多晶硅基本被完全
30 刻蚀。 干燥过程可以是在一定温度 N2环境下的高速甩干， 或是基于马 兰葛尼原理对晶圆进行干燥。
接着， 使用质量量测设备测量晶圆质量， 判断多晶硅是否完全移 除。 质量量测设备优选精密仪器， 例如机械精密天平、 电子精密天平、 半自动 /全自动加码电光投影阻尼精密天平等等。 如果晶圆剩余质量在 误差范围内（容差范围已由第 2 步确定， 例如士 9.751g), 可认为多晶假 栅 3 已经腐蚀去除干净。 如果晶圆质量不在误差范围内， 则认为多晶 假栅 3 没有完全去除干净， 需要重新再处理， 也即将本批次样品送回 工艺线进行二次刻蚀。
以上本发明的实施例通过实验性设计得到多晶硅假栅完全去除后 的质量变化范围， 然后通过质量量测设备测试实际产品的晶圓质量， 从而判定多晶硅假栅 3 是否被完全移除。 这种测试以及后栅刻蚀去除 多晶硅假栅的方法， 避免了对于大规模产品均采用 SEM或 TEM的破 坏性测试， 提高了测试效率节省了成本。
实施例 2
与实施例 1 类似， 依照本发明的另一个实施例的后栅工艺移除多 晶硅假栅的监控方法包括以下步骤： '
首先， 在晶圆表面形成多晶硅假栅结构。 如图 1 所示， 晶圆表面 形成有多晶硅假栅结构， 也即在衬底 1上依次形成绝缘层 2、 多晶硅假 栅极 3、 栅极侧壁 4、 层间介质层.（ILD ) 5 , 然后去除多晶硅假栅极 3 , 形成栅极开口 6。
其次， 确定量测目标及误差范围。 可以先在测试用的晶圓 （即不 用于最后切割成芯片产品的备用晶圆） 上按流程形成多晶硅假栅， 通 过这种实验性设计 （design of experimental, DOE ) 以及采用质量测试 手段， 确定某一产品型号的晶圆在多晶假栅移除干净后 （可以针对样 片做破坏性的 SEM或 TEM测试， 选取那些多晶硅假栅 3被完全去除 的晶圆作为样本） 晶圓去除多晶硅假栅前后的质量差， 也即晶圆质量 标准差， 此时多晶硅假栅 3的厚度应为 0。 测量多批次晶圆多片的数据 后， 得到质量差变化的范围。 根据上述结果合理定义晶圆质量差量测 目标及误差范围， 例如 DOE得到某一产品型号的晶圆上多晶硅假栅 3 完全去除时晶圆前后质量差为 12.450g, 其变化范围为 1.017g， 则判定 多晶硅假栅完全去除且没有过刻蚀的标准是晶圓去除多晶硅假栅前后 质量差为 12.450±1.017g。
再次， 在晶圆多晶硅假栅 3 去除之前， 使用质量量测设备测量晶 圆的盾量， 得到晶圆质量前值 Ml。 例如某批次晶圆去除之前的质量 Ml为 160.479g。
然后， 去除多晶硅假栅并干燥。 可以采用碳氟基等离子体刻蚀的 干法刻蚀来去除多晶硅假栅 3的多晶硅， 也可以采用 KOH、 TAMH等 刻蚀液湿法刻蚀去除多晶硅假栅 3 , 还可以是这些干法、 湿法刻蚀的混 合刻蚀。 合理选择刻蚀原料的流量或浓度、 气压等等参数来控制刻蚀 速度， 使得在给定时间内多晶硅假栅 3的多晶硅基本被完全刻蚀。
接着， 使用质量量测设备测量晶圓去除多晶硅假栅之后的质量， 也即晶圆质量后值 M2， 通过设备自动计算得到晶圆质量差值 M1-M2, 判断多晶硅是否完全移除和 /或发生过刻蚀。 例如对于上述批次的晶圓 测得后值 M2为 148.762g， 则质量差为 11.717g。 如果晶圆质量差在误 差范围内（容差范围已由第 2步确定）， 可认为多晶假栅 3已经腐蚀去除 干净， 且没有过腐蚀发生。 如果晶圆质量差不在误差范围内， 则认为 多晶假栅 3 没有完全去除干净， 需要重新再处理， 也即将本批次样品 送回工艺线进行二次刻蚀。
实施例 3
与实施例 1或 2类似， 区别仅在于绝缘层 2是否是后栅工艺的栅 极介质层。 如果绝缘层 2是高 k材料， 用于后栅工艺的栅极介质层， 则在本发明的监控方法中， 绝缘层 2不随多晶硅假栅 3被去除， 而是 一并保留， 因此监控方法不变。 但是若绝缘层 2 仅用于多晶硅假栅 3 的刻蚀停止层， 也即材质为普通的绝缘介质材料， 例如二氧化硅， 则 绝缘层 2应随多晶硅假栅 3—并去除， 则本发明上述两实施例需要做 出相应的变更。
具体地， 实施例 3对于实施例 1变种的监控方法包括：
1 ) 釆用质量测量监控法， 量测某一产品型号的晶圆在多晶假栅 3 以及绝缘层 2完全移除干净后的质量； 测量多批次晶圆的多片数据后， 得到多晶假栅 3 以及绝缘层 2完全去除后质量的变化范围； 据上述结 果合理定义晶圓在多晶假栅移除后质量的量测目标及容差范围 (SPEC); ^
2 ) 通过干法刻蚀或是湿法刻蚀或是干法-湿法混合刻蚀去除掉多 晶假栅 3以及绝缘层 2， 并将晶圓干燥；
3 )使用质量量测设备测量晶圓质量； 如果晶圆质量在容差范围内 (容差范围已由第 1步确定），可认为多晶假栅 3以及绝缘层 2已经腐蚀 去除干净； 如果晶圆质量不在容差范围内， 可认为多晶假栅 3 以及绝 缘层 2没有完全去除干净； 需要对工艺条件进行调整。
相应地， 对于实施例 2的变种如下：
1 ) .采用质量测量监控法， 量测某一产品型号的同一片晶圓在多晶 假栅 3 以及绝缘层 2完全移除干.净前后的质量差； 测量多批次晶圆的 多片数据后， 得到多晶假栅 3 以及绝缘层 2完全去除前后质量差的变 化范围； 据上述结果合理定义晶圆在多晶假栅 3 以及绝缘层 2移除前 后质量差的量测目标及容差范围（SPEC);
2 )在晶圆多晶假栅 3以及绝缘层 2去除前， 使用质量量测设备测 量晶圓质量， 得到晶圆质量前值；
3) 通过干法刻蚀或是湿法刻蚀或是干法 -湿法混合刻蚀去除掉多 晶假栅 3以及绝缘层 2 , 并将晶圆干燥；
4 )使用质量量测设备测量晶圆质量， 得到晶圓质量后值， 并通过 设备自动计算出质量差值； 如果晶圆质量差值在容差范围内（容差范围 已由第 1步确定），可认为多晶假栅 3以及绝缘层 2已经腐蚀去除干净； 如果晶圆质量差值不在容差范围内， 可认为多晶假栅 3 以及绝缘层 2 没有完全去除千净； 需要对工艺条件进行调整。
依照本发明的量测以及刻蚀方法， 避免了对于大规模产品均采用 SEM或 TEM的破坏性测试， 提高了测试效率节省了成本。 此外， 还能 同时判定是否发生刻蚀不足或过刻蚀， 因此测试更加方便高效， 得到 的产品良率以及可靠性有大幅提升。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种多晶硅假栅移除后的监控方法， 包括以下步骤：
在晶圆表面形成多晶硅假栅结构；
确定晶圓质量的量测目标及误差范围；
去除多晶硅假栅之后， 使用质量量测设备测量晶圆的质量， 判断 多晶硅假栅是否完全移除。
2. 一种多晶硅假栅移除后的监控方法， 包括以下步骤：
在晶圆表面形成多晶硅假栅结构；
确定晶圆质量差的量测目标及误差范围；
使用质量量测设备测量晶圆的质量， 确定晶圆质量前值； 去除多晶硅假栅之后， 使用质量量测设备测量晶圆的质量以确定 晶圆质量后值， 判断多晶硅是否完全移除。
3. 如权利要求 1或 2的方法， 其中， 多晶硅假栅下方包括绝缘层， 所述绝缘层为高 k材料、 氧化硅或氮氧化硅。
4. 如权利要求 3的方法， 其中， 所述绝缘层与所述多晶硅假栅同 时被去除。
5. 如权利要求 1或 2的方法， 其中， 通过实验性设计 （DOE )， 获 取多晶硅假栅被完全去除的样品晶圆的质量或质量差以及误差范围。
6. 如权利要求 1的方法， 其中， 如果晶圆质量超出误差范围， 则 判定多晶硅没有完全去除， 需要二次处理。
7. 如权利要求 2的方法， 其中， 如果晶圆质量前值与后值的差超 出晶圆质量差的误差范围， 则判定多晶硅没有完全去除， 需要二次处 理。
8. 如权利要求 1或 2的方法， 其中， 所述质量量测设备为机械精密 天平、 电子精密天平或半自动 /全自动加码电光投影阻尼精密天平。
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