WO2012154027A1 - Appareil pour applications avec capteurs et procédé de fabrication - Google Patents

Appareil pour applications avec capteurs et procédé de fabrication Download PDF

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Publication number
WO2012154027A1
WO2012154027A1 PCT/MY2012/000086 MY2012000086W WO2012154027A1 WO 2012154027 A1 WO2012154027 A1 WO 2012154027A1 MY 2012000086 W MY2012000086 W MY 2012000086W WO 2012154027 A1 WO2012154027 A1 WO 2012154027A1
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WO
WIPO (PCT)
Prior art keywords
accordance
sensor applications
sensor
substrate
layer
Prior art date
Application number
PCT/MY2012/000086
Other languages
English (en)
Inventor
Daniel Chia Sheng Bien
Masuri Othman
Ali Zaini Abdullah
Original Assignee
Mimos Bhd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mimos Bhd. filed Critical Mimos Bhd.
Publication of WO2012154027A1 publication Critical patent/WO2012154027A1/fr

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
    • G01N27/00—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means
    • G01N27/26—Investigating or analysing materials by the use of electric, electrochemical, or magnetic means by investigating electrochemical variables; by using electrolysis or electrophoresis
    • G01N27/403—Cells and electrode assemblies
    • G01N27/414—Ion-sensitive or chemical field-effect transistors, i.e. ISFETS or CHEMFETS
    • G01N27/4148—Integrated circuits therefor, e.g. fabricated by CMOS processing

Definitions

  • the present invention generally relates to an apparatus for sensor applications and method of manufacturing thereof, more particularly the present invention relates to sensors in a channel of an apparatus and method of manufacturing the apparatus.
  • FET field-effect transistor
  • ISFETs ion-sensitive field-effect transistors
  • Chem-FETs chemical field-effect transistors
  • En-FETs enzyme field-effect transistors
  • US 2006/0272942 Al disclosed an electrochemical sensor and method of its production comprising a microfluidic channel and an electronic sensing device on a first substrate, and a second substrate bonded to the first substrate so as to close the microfluidic channel, wherein a functional part of the electronic sensing device is exposed at the surface of the microfluidic channel and wherein the microfluidic channel is formed by embossing.
  • the electronic device is a vertical-channel field-effect transistor.
  • US 7749905 B2 disclosed a vertical FET structure with nanowire forming the FET channels. The nanowires are formed over a conductive silicide layer, and a surrounding gate gates the nanowires.
  • US 2005/0212531 Al disclosed a fluid sensor for use in an environment having an ambient temperature has a FET comprising a functionalized semiconductor nano- wire, an integral heater disposed proximate to the FET to heat the FET to an elevated temperature relative to the ambient temperature, and integral thermal insulation disposed to maintain the field-effect transistor at the elevated temperature.
  • US 7859029 B2 disclosed a FET-based sensor for detecting an ionic material, an ionic material detecting device including the FET-based sensor ⁇ and a method of detecting an ionic material using the FET-based sensor.
  • the FET-based sensor includes: a sensing chamber including a reference electrode and a plurality of sensing FETs; and a reference chamber including a reference electrode and a plurality of reference FETs.
  • the object of the present invention is to provide an apparatus for sensor applications and method of manufacturing the apparatus, wherein the present invention discloses miniaturised sensors in channelled systems with advantages of portability, higher sensitivity, prompter response with reduced sample volumes, and the ability to detect multiple types of matter over conventional systems.
  • One object of the present invention is to provide an apparatus that comprises a substrate having an insulating layer, at least a channel, at least a sensor including an interface associated with the sidewall of the channel for detecting samples, and at least a contact means attached to the sensor for providing electrical connectivity.
  • Another object of the present invention is to provide at least a sensor in the apparatus, preferably an implementation of field-effect transistor (FET) sensor that the source, gate, and the drain region are stacked vertically on the substrate.
  • FET field-effect transistor
  • LPCVD low-pressure chemical vapor deposition
  • the present invention herein aims to teach a vertical FET based sensor incorporated into the sidewall of the flow channel and accommodates an array of sensors onto the sidewalls of the channel.
  • the sensors as preferred in the present invention can be of the same or different type depending on the type of sensors employed and the types of matter for sensing.
  • Figure 1 illustrates a representation of a perspective view of an array of sensors associated with the sidewalls of the channel in accordance with the present invention.
  • Figure 2 illustrates a representation of a perspective view of an array of sensors associated with the sidewalls of the channel etched into the substrate in accordance with the present invention.
  • Figure 3 illustrates a representation of a perspective view of the present invention being encapsulated with another substrate.
  • Figure 4 illustrates a process flow of basic manufacturing process of the apparatus in accordance with the present invention.
  • Figure 5 illustrates sequential cross-sectional views representing the basic processing steps for fabricating the sensor in accordance with the present invention.
  • Figure 6 illustrates sequential cross-sectional views representing the basic processing steps for fabricating the sensor in accordance with the present invention.
  • FIG. 1 the figures illustrate representation of the apparatus for sensor applications in accordance with the present invention.
  • the apparatus as preferred in the present invention comprises a substrate (1 1 ) having an insulating layer (12), at least a channel (13) for providing flow path, at least a sensor (14) including an interface (15) associated with the sidewall of the channel (13) for detecting samples, and at least a contact means (16) attached to the sensor (14) for electrical connectivity.
  • Figure 1 and Figure 2 depict an array of sensors (14) including interfaces (15) aligned to the sidewalls of the channel (13) where the sensors (14) are separated from the substrate (1 1) by an insulating layer (12) that blankets the substrate (1 1).
  • the arrangement of the sensors (14) on both sidewalls as shown in the figure, essentially maximises contact between the interfaces (15) with samples flowing through the channel (13), thus improving the device sensitivity and response time.
  • the present invention accomplishes that the interface (15) of the sensor (14) is associated with the sidewall of the channel (13) in such a way that the sensor (14) is aligned perpendicularly on the substrate (1 1), hence providing a structure that easily accommodates an array of sensors (14) where miniaturisation of the apparatus made possible.
  • the substrate (1 1) is preferably made of an insulator such as silicon, glass, quartz type substrates or any combination thereof.
  • the insulating layer (12) that blankets the substrate (1 1) however is preferably silicon dioxide with high chemical stability to protect the surface of the substrate ( 1 1) from damages. Another reason is that the insulating layer (12) also functions for controlling and maintaining the electrical properties of the substrate (1 1) from being modified with the introduction of the sensors (14).
  • the channel (13) serves as a flow path for samples that is introduced into the channel (13).
  • the channel (13) that is formed on the substrate (1 1) as shown in Figure 1 to Figure 3, is through any process preferably by etching and provides a flow path with a structure that is not limited to nano- dimension for detecting and sensing samples corresponding to the various matters of chemical solutions, fluids and gases for targeted analysis.
  • the dimension of the channel (13) allows for reduced volumes of samples.
  • Etching into the substrate (11) can be done by plasma etching for example Sulfur Hexafluoride (SF 6 ) and Octafluorocyclobutane (C4F8) for silicon or polyimide; or Octafluorocyclobutane (C 4 Fg) and Argon (Ar) for glass type substrate (1 1).
  • plasma etching for example Sulfur Hexafluoride (SF 6 ) and Octafluorocyclobutane (C4F8) for silicon or polyimide; or Octafluorocyclobutane (C 4 Fg) and Argon (Ar) for glass type substrate (1 1).
  • Wet etching is also possible where Potassium Hydroxide (KOH) and Tetramethylammonium hydroxide (TMAH) solution is typically used to etch silicon and Hydrofluoric Acid (HF) used for glass etching.
  • KOH Potassium Hydroxide
  • TMAH Tetramethylammonium hydroxide
  • the sensor (14) as associated with the sidewalls of the channel (13) in an embodiment preferred in the present invention is a field-effect transistor (FET) and not limited to ion-sensitive field-effect transistors (ISFETs), chemical field-effect transistors (Chem- FETs) and enzyme field-effect transistors (En-FETs), which comprises a source, gate, and a drain region that is incorporated to the sidewalls of the channel (13).
  • FET field-effect transistor
  • ISFETs ion-sensitive field-effect transistors
  • Chem- FETs chemical field-effect transistors
  • En-FETs enzyme field-effect transistors
  • the present invention to all intents and purposes teaches that the sensor (14) associates with the sidewall of the channel (13) in such a way that the sensor (14) is aligned perpendicularly on the substrate (1 1), wherein the source, gate, and the drain region of the sensor (14) characteristically a FET transistor are vertically stacked to the sidewall of the channel (13), hence in essence, the present invention anticipates for a significant reduction in the surface area of the sensors (14).
  • the total quantity of the sensor (14) and the types of sensors (14) as preferably adopted in the present invention are however not limited, wherein a pluralities of the sensor (14) are implemented to detect various samples of chemical solutions, fluids and gases corresponding to the availability of such matters.
  • the present invention anticipates for multiple analytes or ions in the various samples to be detected simultaneously.
  • the sidewall of the channel (13) is typically a thin layer of an insulating material preferably silicon dioxide for protecting the surface of the sensor (14) from damage induced by the different bonding structure of the interface (15), and ultimately for providing a layer of gate oxide or dielectric that separates the interface (15) from the source and drain terminals, and the conductive channel that connects the source and drain regions.
  • an insulating material preferably silicon dioxide for protecting the surface of the sensor (14) from damage induced by the different bonding structure of the interface (15), and ultimately for providing a layer of gate oxide or dielectric that separates the interface (15) from the source and drain terminals, and the conductive channel that connects the source and drain regions.
  • the interface (15) that associates the sensor (14) and the sidewall of the channel (13) as adopted in the present invention is a layer of a sensing element that allows for interaction between the sensor (14) and the samples that flows through the channel
  • the sensing element of the interface (15) is preferably chosen from material types that are not limited to silicon nitride, metal oxides, enzymes, chemical composites, nanotubes or nanowires depending on the types of ions and analytes in the various samples to be detected.
  • the FET based sensors (14) can be fabricated by surface machining of polysilicon and highly doped to form source and drain regions of the FET based sensors (14), or by machining silicon on insulator type stack and highly doped to form source and drain regions of the FET based sensors (14) for devices that requires higher performance.
  • the source and drain regions are preferably connected to the contact means (16) with metal contacts for electrical connectivity, thus forming terminals for the source and drain regions.
  • the contact means (16) are made of any material that conducts electricity that preferably exhibits a good conducting element, which is not limited to metal contacts. Fundamentally, the electrical properties of the FET based sensor (14) are influenced by the value of voltages detected at the interface (15) and it is therefore that the contact means (16) provides electrical connnectivity between the sensor (14) to an auxiliary system of not limited to material testing, analysis, or chemical synthesis for various sensor applications.
  • Figure 3 illustrates the apparatus in accordance with the present invention being encapsulated with a seal (101) of another substrate of silicon, glass or polymer type for sealing the channel (13) and the sensors (14) in the apparatus. This is to ensure that the samples flowing through the channel (13) are prevented from leaking out.
  • the encapsulation more often than not takes place after configuring the interface (15) of the apparatus in accordance with the present invention.
  • the encapsulation also allows for the contact means (16) to protrude from seal (101) so as to provide electrical connectivity to an auxiliary system.
  • FIG 4 the figure illustrates a process flow of basic manufacturing process of the apparatus in accordance with the present invention.
  • the method of manufacturing the apparatus for sensor application is merely summarized in this figure.
  • the process is initiated by providing a substrate (11). Then, an insulating layer (12) is blanketed on the substrate (1 1) before forming the FET based sensors (14) on the insulating layer and structuring a channel (13) within the apparatus of the present invention.
  • a layer of sensing element is deposited on the substrate (11) to form interfaces (15), and followed by encapsulating the channel (13) and the sensors (14) with a seal (101 ) for preventing leakages, as well as the apparatus is provided with electrical contacts for connection with an auxiliary system.
  • the process begins with providing a substrate (1 1), and initially deposited with a layer of an insulating material (30) of preferably a thin film of silicon dioxide on the substrate (1 1) forming a blanket of insulating layer (12) on the substrate (1 1) as shown in Figure 1.
  • the substrate (1 1) is preferably made of an insulator such as silicon, glass, quartz type substrates or any combination thereof.
  • the insulating layer (12) as mentioned previously, is preferably silicon dioxide with high chemical stability to protect the surface of the substrate (11) from damages induced by the different bonding structure of when next a layer of first material (31) is deposited on the insulating material (30), and also functions for controlling and maintaining the electrical properties of the substrate (1 1 ) from being modified with the introduction of the sensors (14).
  • the process is followed by depositing a layer of second material (32) on the first material (31), and depositing a layer of third material (33) on the second material (32), wherein the layer of first material (31) and the third material (33) are preferably highly doped corresponding to source and drain regions of the FET.
  • the layer of the second material (32) however is a material that corresponds with the gate region of the FET.
  • the source and the drain region herein are interchangeable with either the first material (31) or the third material (33).
  • the third material (33) is apparently selected to be the drain region.
  • the third material (33) is apparently selected to be he source region.
  • the layer of the first material (31), the second material (32), and the third material (33) are preferably deposited by means of low-pressure chemical vapor deposition (LPCVD) to produce thin films of high-purity and high-performance solid materials.
  • an opening for exposing the layer of the first material (31) is formed by means of exposing an area (51) of the first material (31) by etching out the corresponding area (51) of the second material (32) and the third material (33). This opening is carried out for later on in the process for enabling formation of electrical contacts to the first material (31).
  • a channel (13) is structured adjacent to said area (51) by etching out the first material (31), the second material (32), and the third material (33), wherein the area etched off the first material (31), the second material (32), and the third material (33) forms a furrow appropriate for the structure of the channel (13) adjacent to said area
  • a layer of an insulating material (30) of silicon dioxide is deposited on the surfaces of the substrate (11) for the provision of the sidewall of the channel (13), and followed by depositing a fourth material (34) layer of a sensing element on the insulating material (30) for providing interface (15).
  • the insulating material is for protecting the surface of the sensor (14) from damage induced by the different bonding structure of the interface
  • the interface (15) as the layer of a sensing element allows for interaction between the sensor (14) and the samples that flows through the channel (13).
  • the sensing element is preferably layers of silicon nitride, metal oxides, enzymes, chemical composites, nanotubes or nanowires depending on the types of ions and analytes in the samples.
  • the apparatus is provided with a contact means (16) for the first material (31 ) and the third material (33) corresponding to a source and a drain contact or vice versa, by etching out the fourth material (34) and the corresponding insulating layer (12) for exposing an area of the first material, and by etching out the fourth material (34) and the corresponding insulating area (30) for exposing an area of the third material.
  • the contact means ( 16) that preferably conducts electricity provides electrical conductivity between the sensor (14) and a preferred embodiment of an auxiliary system of not limited to material testing, analysis, or chemical synthesis for various sensor applications.
  • the contact means (16) are made of any material preferably exhibits a good conducting element, which is not limited to metal contacts.
  • the channel (13) and sensor (14) are rather encapsulated with another substrate of silicon, glass or polymer type for sealing the channel (13) and sensor (14) in order to prevent leakages.
  • FIG 1 , Figure 5 and Figure 6 the figures are sequential cross-sectional views of the basic process for fabricating the apparatus by means of silicon on insulator (SOI) technology in accordance with the present invention hereafter described.
  • SOI silicon on insulator
  • the method for fabricating the apparatus by means of SOI technology favors the fabrication of a higher quality device such as low noise and high sensitivity. This is due to the fact that, single crystal silicon is used in the fabrication of the source and ' drain of the FET via SOI technology, as compared to the polycrystalline silicon used in the thin film deposition technology.
  • the process first begins with providing a substrate (1 1), and initially deposited with a layer of an insulating material (30) of preferably a thin film of silicon dioxide on the substrate (1 1) forming a blanket of insulating material (30) on the substrate (1 1) as shown in Figure 1.
  • the substrate (1 1) is preferably made of an insulator such as silicon, glass, quartz type substrates or any combination thereof.
  • the insulating layer (12) as mentioned previously, is preferably silicon dioxide with high chemical stability.
  • an active silicon substrate (71) is provided and highly doped on one surface for providing a layer of a first material (31) within the active silicon substrate (71).
  • the insulating material (30) of the substrate (1 1) provided earlier that has been oxidized is then bonded with the first material (31) of the active silicon substrate (71) to form a silicon on insulator type substrate.
  • the process is continued with thinning of the active silicon substrate (71) with methods not limited to grinding and polishing, chemical etching or plasma etching, and subsequently doping another surface of the active silicon substrate (71) for providing a layer of a third material (33).
  • the layer of the first material (31) and the third material (33) are preferably highly doped corresponding to source and drain regions of the FET.
  • the layer of the active silicon substrate (71) however corresponds to the gate region of the FET.
  • the source and the drain region herein are interchangeable with either the first material (31) or the third material (33). In other words, in a first option, if the first material (31) is selected as the source region, the third material (33) is apparently selected to be the drain region. Likewise, in a second option, if the first material (31) is selected as the drain region, the third material (33) is apparently selected to be he source region.
  • an opening for exposing the layer of the first material (31) is formed by means of exposing an area (51) of the first material (31) by etching out the corresponding area (51) of the active silicon substrate (71) and the third material (33). This opening is carried out for later on in the process for enabling formation of electrical contacts to the first material (31).
  • a channel (13) is structured adjacent to said area (51) by etching out the first material (31), the second material (32), and the third material (33), wherein the area etched off the first material (31), the active silicon substrate (71), and the third material (33) forms a furrow appropriate for the structure of the channel (13) adjacent to said area (51 ).
  • a layer of an insulating material (30) of silicon dioxide is deposited on the surfaces of the substrate (1 1) for the provision of the sidewall of the channel (13), and followed by depositing a fourth material (34) layer of a sensing element on the insulating material (30) for providing interface (15).
  • the insulating material is for protecting the surface of the sensor (14) from damage induced by the different bonding structure of the interface (15), and ultimately for providing a layer of gate oxide or dielectric that separates the interface (15) from the source and drain terminals, and the conductive channel that connects the source and drain regions.
  • the interface (15) as the layer of a sensing element allows for interaction between the sensor (14) and the samples that flows through the channel (13).
  • the sensing element is preferably layers of silicon nitride, metal oxides, enzymes, chemical composites, nanotubes or nanowires depending on the types of ions and analytes in the samples.
  • the apparatus is provided with a contact means (16) for the first material (31) and the third material (33) corresponding to a source and a drain contact or vice versa, by etching out the fourth material (34) and the corresponding insulating layer (30) for exposing an area of the first material, and by etching out the fourth material (34) and the corresponding insulating material (30) for exposing an area of the third material.
  • the contact means (16) that preferably conducts electricity provides electrical conductivity between the sensor (14) and a preferred embodiment of an auxiliary system of not limited to material testing, analysis, or chemical synthesis for various sensor applications.
  • the contact means (16) are made of any material preferably exhibits a good conducting element, which is not limited to metal contacts. Effectively, the channel (13) and sensor (14) are rather encapsulated with another substrate of silicon, glass or polymer type for sealing the channel (13) and sensor (14) in order to prevent leakages.

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Abstract

L'invention concerne un appareil pour des applications avec capteurs ainsi qu'un procédé de fabrication de celui-ci ; la présente invention concerne plus particulièrement des capteurs dans un canal d'un appareil, et un procédé de fabrication de cet appareil. L'appareil comprend un substrat (11) comportant une couche isolante (12), au moins un canal (13) sur le substrat (11) formant un trajet de circulation, au moins un capteur (14) comprenant une interface (15) associée à la paroi latérale du canal (13) afin de détecter des échantillons, et au moins un moyen de contact (16) fixé au capteur (14) pour la connectivité électrique.
PCT/MY2012/000086 2011-05-12 2012-04-23 Appareil pour applications avec capteurs et procédé de fabrication WO2012154027A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2011002143 2011-05-12
MYPI2011002143 2011-05-12

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WO2012154027A1 true WO2012154027A1 (fr) 2012-11-15

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014098566A1 (fr) * 2012-12-21 2014-06-26 Mimos Berhad Transistor à effet de champ sensible aux ions

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764797A (en) * 1985-09-14 1988-08-16 Thorn Emi Plc Chemical-sensitive semiconductor device
US20070218610A1 (en) * 2001-04-23 2007-09-20 Samsung Electronics Co., Ltd. Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4764797A (en) * 1985-09-14 1988-08-16 Thorn Emi Plc Chemical-sensitive semiconductor device
US20070218610A1 (en) * 2001-04-23 2007-09-20 Samsung Electronics Co., Ltd. Methods of making a molecular detection chip having a metal oxide silicon field effect transistor on sidewalls of a micro-fluid channel

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
JAYANARAYANAN, S.: "Silicon-based vertical MOSFETs", DOCTORAL DISSERTATION, May 2004 (2004-05-01), Retrieved from the Internet <URL:http://hdl.handle.riet/2152/2021> *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014098566A1 (fr) * 2012-12-21 2014-06-26 Mimos Berhad Transistor à effet de champ sensible aux ions

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