WO2012152092A1 - Gate ground nmos unit for anti-static protection and anti-static protection structure thereof - Google Patents

Gate ground nmos unit for anti-static protection and anti-static protection structure thereof Download PDF

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Publication number
WO2012152092A1
WO2012152092A1 PCT/CN2012/070728 CN2012070728W WO2012152092A1 WO 2012152092 A1 WO2012152092 A1 WO 2012152092A1 CN 2012070728 W CN2012070728 W CN 2012070728W WO 2012152092 A1 WO2012152092 A1 WO 2012152092A1
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ggnmos
source
unit
regular
drain
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PCT/CN2012/070728
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French (fr)
Chinese (zh)
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吕宇强
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上海先进半导体制造股份有限公司
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Publication of WO2012152092A1 publication Critical patent/WO2012152092A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to the field of semiconductor manufacturing technology, and in particular, to a GGNMOS unit for antistatic protection and an antistatic protection structure based on the GGNMOS unit. Background technique
  • Electro-Static Discharge (ESD) protection structure In semiconductor chips, the most popular Electro-Static Discharge (ESD) protection structure is usually a gate-grounded GGNMOS (Gate Grounded NMOS) structure.
  • GGNMOS Gate Grounded NMOS
  • the parasitic series resistance between the source (the emitter of the parasitic transistor) and the grounded substrate (the base of the parasitic transistor) is the key to triggering the conduction of the parasitic transistor, but the GGNMOS interdigital structure is common in the prior art.
  • the GGNMOS located at the center of the interdigital structure is the farthest from the ground line in both the length and width directions, so its base parasitic series resistance is also the largest, so the most It is easy to trigger the parasitic triode to open the drain first.
  • the MOS transistors on both sides are generally not turned on, and this uneven conduction causes the current to concentrate in the channel region at the center position, and thus this region is usually most likely to be burnt first.
  • the current high ESD protection capability (eg 8KV) will require the GGNMOS to have a sufficiently large channel width (gate length) and turn-on uniformity to achieve the ability to discharge large currents, if simple additions are used to increase the common interdigital structure.
  • the number of GGNMOS fingers or the increase of the single finger length will make the opening unevenness more obvious. It is more likely that the intermediate protection tube is burned and the protection tubes at both ends are not opened, and it is difficult to effectively improve the ESD protection capability.
  • a GGNMOS-based anti-static protection structure is needed to solve the problem that the ESD protection capability caused by the uneven conduction of the existing GGNMOS protection tube is not high.
  • the technical problem to be solved by the present invention is to provide a GGNMOS unit for antistatic protection and an antistatic protection structure based on the GGNMOS unit, which has a sufficiently large channel width and uniformity of opening to achieve a large current release. ability.
  • the present invention provides a GGNMOS cell for antistatic protection, which has a regular polygonal shape, a drain thereof is closed by a ring-shaped gate, and the annular gate is again a conical polygonal shape concentric therewith.
  • the source is surrounded by a concentric annular polygon substrate grounding area equal to the distance between the source and the field is uniformly spaced apart by the field oxygen region.
  • the source and/or upper drain portions of the GGNMOS cell are covered with a concentric annular metal silicide blocking layer.
  • the source and the drain are both N-type heavily doped, and the grounding area of the substrate is P-type heavily doped.
  • the source and the drain of the GGNMOS cell are added with ESD injection.
  • the source of the GGNMOS unit is a regular quadrangle, a regular hexagon, a regular octagon, a regular decagonal or a regular hexagon.
  • the outer side of the single GGNMOS unit has a length of 20 to 50 ⁇ m.
  • the present invention further provides an antistatic protection structure based on a GGNMOS unit, including a plurality of GGNMOS cells in a regular polygonal shape;
  • the drain thereof is closed by a ring-shaped gate, and the ring-shaped gate is surrounded by a concentric polygonal-shaped source, and the source is disposed at an outer distance equal to the distance a concentric regular polygon ring-shaped substrate grounding region, which is evenly spaced apart by the field oxygen region;
  • the substrate ground regions of the plurality of GGNMOS cells are connected in parallel with each other, and the plurality of GGNMOS cells are connected to form an array.
  • the source and/or upper drain portions of the single GGNMOS cell are covered with a concentric annular metal silicide blocking layer.
  • the source and the drain are both N-type heavily doped, and the grounding area of the substrate is P-type heavily doped.
  • the source and drain of the single GGNMOS cell are added with ESD injection.
  • the GGNMOS unit is a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
  • the outer side of the single GGNMOS unit has a length of 20 to 50 ⁇ m.
  • the array comprises 3 x 5, 4 x 4, 4 x 5 or 5 x 5 GGNMOS cells.
  • the present invention has the following advantages:
  • the invention adjusts the planar layout structure of the GGNMOS cell, uses a ring-shaped gate to close the drain, and the source is surrounded by a concentric substrate ground region to make the parasitic transistor base series resistance (parasitic resistance) Equal.
  • the anti-static protection structure of the invention can realize each ESD protection device unit when static electricity occurs
  • each GGNMOS unit is evenly turned on at the same time, so that the human body model (Human Body Model, ⁇ ) can achieve high ESD protection capability of 8KV or more, effectively solving the problem that the existing GGNMOS device of the parallel interdigital structure has different opening voltages. Increase the number of parallels and the size of the single finger so that the high ESD protection capability cannot be achieved.
  • FIG. 1 is a schematic plan view showing a common layout of an antistatic protection structure of a common GGNMOS interdigital structure in the prior art
  • FIG. 2 is a schematic diagram showing a planar layout structure of a GGNMOS unit for antistatic protection according to an embodiment of the present invention
  • FIG. 3 is a schematic cross-sectional view showing the operation of the GGNMOS cell taken along line A-A of FIG. 2 according to an embodiment of the present invention
  • FIG. 4 is a schematic plan view showing an antistatic protection structure based on a GGNMOS unit according to an embodiment of the present invention. detailed description
  • the GGNMOS cell 200 can have a regular polygonal shape, such as a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal, or a regular hexagon.
  • the drain 201 of the GGNMOS cell 200 is closed by the annular gate 202 to form a circular area.
  • the annular gate 202 is in turn surrounded by a conical polygonal source 203, which may be a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
  • the outer side of the source 203 is provided with a concentric regular polygonal ring-shaped substrate ground region 205 equal to the distance, that is, the outer side of the source 203 is surrounded by the substrate ground region 205 at a uniform distance, and the inner ring of the substrate ground region 205 is
  • the shape is the same as the source 203, and is, for example, a regular quadrangle or a regular octagon.
  • Source The field oxide region 204 is evenly spaced apart from the substrate ground region 205.
  • the source 203 and/or the drain 201 of the GGNMOS cell 200 may be partially covered with a concentric annular metal silicide blocking layer.
  • a concentric annular metal silicide blocking layer may be covered between the small ring drawn by the broken line in the drain 201 and the annular gate 202, and in the small ring It is covered with a metal silicide;
  • a metal silicide barrier layer may be covered between the annular ring 202 and the large ring drawn by the broken line in the source electrode 203, and the remaining region on the source electrode 203 is covered with a metal silicide. This can introduce parasitic series resistance into the GGNMOS to limit current and further improve the ESD protection capability of the device.
  • the source 203 and the drain 201 of the GGNMOS cell 200 are both N-type heavily doped, and the substrate ground region 205 is P-type heavily doped. If the source 203 and the drain 201 increase the ESD injection step, the ESD protection capability of the GGMOS unit can be further improved.
  • FIG. 3 is a schematic cross-sectional view showing the operation of the GGNMOS cell taken along line ⁇ - ⁇ in Figure 2, in accordance with one embodiment of the present invention.
  • the P-well 210 is grounded by a turn of P+ implanted substrate ground region 205, which is the parasitic series resistance of the two source 203 to drain 201 of the GGNMOS cell 200.
  • the antistatic protection structure 400 may include a plurality of regular polygonal GGNMOS cells 200, such as a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
  • a single GGNMOS cell 200 its drain 201 is closed by the annular gate 202 to form a circular region.
  • the annular gate 202 is in turn surrounded by a conical polygonal source 203, which may be a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
  • the outer side of the source 203 is provided with a concentric regular polygonal ring-shaped substrate grounding region 205 equal to the distance, that is, the outer side of the source 203 is surrounded by the substrate grounding region 205 at a uniform distance, and the inner ring of the substrate grounding region 205 is
  • the shape is the same as the source 203, and is, for example, a regular quadrangle or a regular octagon.
  • Source 203 and substrate ground region 205 They are evenly spaced apart by the field oxide region 204.
  • the substrate potential near the source 203 can be increased, and the parasitic transistor can be triggered to achieve a drain effect. Since the base parasitic resistance (parasitic series resistance) of each individual GGNMOS cell 200 is the same, each GGNMOS cell 200 is simultaneously turned on to uniformly discharge, thereby achieving a high (HBM 8K or more) ESD protection capability.
  • the substrate ground regions 205 of the plurality of GGNMOS cells 200 are connected in parallel with each other, and the plurality of GGNMOS cells 200 are connected to form an array.
  • the array size for example, the array is increased to include 3 x 5, With 4 x 4, 4x5, 5 x 5 or more GGNMOS cells, high ESD protection of 8KV or higher can be achieved without GNMOS uneven conduction.
  • the source 203 and/or the drain 201 of the single GGNMOS cell 200 may be partially covered with a concentric annular metal silicide blocking layer.
  • a concentric annular metal silicide blocking layer may be covered between the small ring drawn by the broken line in the drain 201 and the annular gate 202, and the small ring may be The inner layer is covered with a metal silicide; a metal silicide blocking layer may be covered between the annular ring 202 and the large ring drawn by the broken line in the source 203, and the remaining region on the source 203 is covered with the metal silicide. .
  • This can introduce a parasitic series resistor in the GGNMOS to limit current and further improve the ESD protection capability of the device.
  • the source 203 and the drain 201 of the GGNMOS cell are both N-type heavily doped, and the substrate ground region 205 is P-type heavily doped. If the source 203 and the drain 201 further increase the ESD injection step, the ESD protection capability of the GGMOS unit can be further improved.
  • the outer side length of a single GGNMOS unit may be 20 ⁇ 50 ⁇ .
  • the present invention makes the parasitic transistor base series resistance (parasitic resistance) equal by changing the planar layout structure of the GGNMOS cell, using a ring-shaped gate to close the drain, and the source is surrounded by a concentric substrate ground region.
  • the anti-static protection structure of the invention can realize the simultaneous opening of each ESD protection device unit (ie, each GGNMOS unit) when static electricity is generated, thereby achieving high ESD protection capability of 8KV or more of the Human Body Model (HBM), effective
  • each ESD protection device unit ie, each GGNMOS unit
  • HBM Human Body Model

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Provided is a GGNMOS unit for anti-static protection, which has a regular polygon shape. The drain thereof is closed by a ring gate, the ring gate is surrounded by a source with a regular polygon shape concentric therewith, the outside of the source is provided with a concentric substrate ground area with a regular polygon shape with equal distance thereto, and both of them are separated uniformly by a field oxygen area. Correspondingly, also provided is an anti-static protection structure based on a GGNMOS unit. The present invention uses the method wherein the ring gate closes the drain and the source is surrounded by a concentric substrate ground area by changing the plane layout structure of the GGNMOS unit to make the series resistance of the base of the parasitic transistor equal everywhere. The anti-static protection structure in the present invention can start up each ESD protection device unit uniformly and simultaneously when static occurs, thus reaching high ESD protection ability higher than HBM 8 KV.

Description

用于防静电保护的栅极接地的 NMOS单元及其防静电保护结构 技术领域  Gate-grounded NMOS unit for anti-static protection and anti-static protection structure thereof
本发明涉及半导体制造技术领域， 具体来说， 本发明涉及一种用于防静电保 护的 GGNMOS单元以及一种基于该 GGNMOS单元的防静电保护结构。 背景技术  The present invention relates to the field of semiconductor manufacturing technology, and in particular, to a GGNMOS unit for antistatic protection and an antistatic protection structure based on the GGNMOS unit. Background technique
在半导体芯片中， 最流行的静电放电 （Electro-Static Discharge, ESD )保护结 构通常是一种栅极接地的 GGNMOS ( Gate Ground NMOS, 栅极接地的 NMOS ) 结构。 在 ESD发生时， ESD保护器件 GGNMOS的寄生三极管会被触发的导通， 产生击穿 （Snapback )现象， 达到泄流的效果。 而源极（寄生三极管的发射极）与 接地的衬底（寄生三极管的基极 )之间的寄生串联电阻是触发该寄生三极管导通的 关键， 但是在现有技术中常见的 GGNMOS叉指结构的防静电保护结构中， 如图 1 所示， 位于叉指结构中心部位的 GGNMOS由于在长、 宽两个方向上都距离接地线 最远，因而它的基极寄生串联电阻也最大，因而最容易先触发寄生三极管开启泄流。 而此时位于两边的 MOS管一般尚未开启， 则这种不均匀导通就会造成电流集中在 中心位置的沟道区域， 因而通常这一块区域也最容易被最先烧毁。  In semiconductor chips, the most popular Electro-Static Discharge (ESD) protection structure is usually a gate-grounded GGNMOS (Gate Grounded NMOS) structure. When the ESD occurs, the parasitic transistor of the ESD protection device GGNMOS will be triggered to conduct, resulting in a Snapback phenomenon to achieve the effect of discharge. The parasitic series resistance between the source (the emitter of the parasitic transistor) and the grounded substrate (the base of the parasitic transistor) is the key to triggering the conduction of the parasitic transistor, but the GGNMOS interdigital structure is common in the prior art. In the antistatic protection structure, as shown in Figure 1, the GGNMOS located at the center of the interdigital structure is the farthest from the ground line in both the length and width directions, so its base parasitic series resistance is also the largest, so the most It is easy to trigger the parasitic triode to open the drain first. At this time, the MOS transistors on both sides are generally not turned on, and this uneven conduction causes the current to concentrate in the channel region at the center position, and thus this region is usually most likely to be burnt first.
另外， 当前高 ESD的防护能力 （例如 8KV )会要求 GGNMOS具有足够大的 沟道宽度（栅极长度）和开启的均匀性以达到释放大电流的能力， 如果单純采用增 加常见的叉指结构的 GGNMOS 叉指的数量或者增加单指长度却又会使得开启的 不均匀性更加明显， 更容易出现中间保护管烧毁而两端的保护管未开启的现象，难 以实现 ESD保护能力的有效提升。  In addition, the current high ESD protection capability (eg 8KV) will require the GGNMOS to have a sufficiently large channel width (gate length) and turn-on uniformity to achieve the ability to discharge large currents, if simple additions are used to increase the common interdigital structure. The number of GGNMOS fingers or the increase of the single finger length will make the opening unevenness more obvious. It is more likely that the intermediate protection tube is burned and the protection tubes at both ends are not opened, and it is difficult to effectively improve the ESD protection capability.
因此， 需要一种基于 GGNMOS的防静电保护结构， 以解决现有的 GGNMOS 保护管不均匀导通造成的 ESD保护能力不高的问题。 发明内容  Therefore, a GGNMOS-based anti-static protection structure is needed to solve the problem that the ESD protection capability caused by the uneven conduction of the existing GGNMOS protection tube is not high. Summary of the invention
本发明所要解决的技术问题是提供一种用于防静电保护的 GGNMOS 单元以 及一种基于该 GGNMOS单元的防静电保护结构，具有足够大的沟道宽度和开启的 均匀性以达到释放大电流的能力。 为解决上述技术问题，本发明提供一种用于防静电保护的 GGNMOS单元，具 有正多边形状 ,其漏极被环状栅极封闭 ,所述环状栅极又被与其同心的正多边形状 的源极包围，所述源极外侧设置有与之距离处处相等的同心的正多边形环状的衬底 接地区域， 两者之间被场氧区域均匀间隔开。 The technical problem to be solved by the present invention is to provide a GGNMOS unit for antistatic protection and an antistatic protection structure based on the GGNMOS unit, which has a sufficiently large channel width and uniformity of opening to achieve a large current release. ability. In order to solve the above technical problem, the present invention provides a GGNMOS cell for antistatic protection, which has a regular polygonal shape, a drain thereof is closed by a ring-shaped gate, and the annular gate is again a conical polygonal shape concentric therewith. The source is surrounded by a concentric annular polygon substrate grounding area equal to the distance between the source and the field is uniformly spaced apart by the field oxygen region.
可选地， 所述 GGNMOS单元的源极和 /或漏极上部分覆盖有同心环状的金属 硅化物阻挡层。  Optionally, the source and/or upper drain portions of the GGNMOS cell are covered with a concentric annular metal silicide blocking layer.
可选地， 所述源极和漏极均为 N型重掺杂， 所述衬底接地区域为 P型重掺杂。 可选地， 所述 GGNMOS单元的源极和漏极增加有 ESD注入。  Optionally, the source and the drain are both N-type heavily doped, and the grounding area of the substrate is P-type heavily doped. Optionally, the source and the drain of the GGNMOS cell are added with ESD injection.
可选地， 所述 GGNMOS单元的源极呈正四边形、 正六边形、 正八边形、 正十 二边形或正十六边形。  Optionally, the source of the GGNMOS unit is a regular quadrangle, a regular hexagon, a regular octagon, a regular decagonal or a regular hexagon.
可选地， 所述单个 GGNMOS单元的外侧边长为 20~50μηι。  Optionally, the outer side of the single GGNMOS unit has a length of 20 to 50 μm.
相应地，本发明还提供一种基于 GGNMOS单元的防静电保护结构， 包括多个 正多边形状的 GGNMOS单元；  Correspondingly, the present invention further provides an antistatic protection structure based on a GGNMOS unit, including a plurality of GGNMOS cells in a regular polygonal shape;
其中， 在单个 GGNMOS单元中， 其漏极被环状栅极封闭， 所述环状栅极又被 与其同心的正多边形状的源极包围 ,所述源极外侧设置有与之距离处处相等的同心 的正多边形环状的衬底接地区域， 两者之间被场氧区域均匀间隔开；  Wherein, in a single GGNMOS cell, the drain thereof is closed by a ring-shaped gate, and the ring-shaped gate is surrounded by a concentric polygonal-shaped source, and the source is disposed at an outer distance equal to the distance a concentric regular polygon ring-shaped substrate grounding region, which is evenly spaced apart by the field oxygen region;
所述多个 GGNMOS单元的衬底接地区域彼此并联，将所述多个 GGNMOS单 元连接构成阵列。  The substrate ground regions of the plurality of GGNMOS cells are connected in parallel with each other, and the plurality of GGNMOS cells are connected to form an array.
可选地， 所述单个 GGNMOS单元的源极和 /或漏极上部分覆盖有同心环状的 金属硅化物阻挡层。  Optionally, the source and/or upper drain portions of the single GGNMOS cell are covered with a concentric annular metal silicide blocking layer.
可选地， 所述源极和漏极均为 N型重掺杂， 所述衬底接地区域为 P型重掺杂。 可选地， 所述单个 GGNMOS单元的源极和漏极增加有 ESD注入。  Optionally, the source and the drain are both N-type heavily doped, and the grounding area of the substrate is P-type heavily doped. Optionally, the source and drain of the single GGNMOS cell are added with ESD injection.
可选地， 所述 GGNMOS单元呈正四边形、 正六边形、 正八边形、 正十二边形 或正十六边形。  Optionally, the GGNMOS unit is a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
可选地， 所述单个 GGNMOS单元的外侧边长为 20~50μηι。  Optionally, the outer side of the single GGNMOS unit has a length of 20 to 50 μm.
可选地， 所述阵列包括 3 x5个、 4x4个、 4 x5个或者 5 x5个 GGNMOS单元。 与现有技术相比， 本发明具有以下优点：  Optionally, the array comprises 3 x 5, 4 x 4, 4 x 5 or 5 x 5 GGNMOS cells. Compared with the prior art, the present invention has the following advantages:
本发明通过改变 GGNMOS单元的平面布局结构， 使用了环状栅极封闭漏极， 源极由同心的衬底接地区域围绕的方法使寄生三极管基极串联电阻（寄生电阻）处 处相等。 本发明的防静电保护结构可在静电发生时， 实现各个 ESD保护器件单元The invention adjusts the planar layout structure of the GGNMOS cell, uses a ring-shaped gate to close the drain, and the source is surrounded by a concentric substrate ground region to make the parasitic transistor base series resistance (parasitic resistance) Equal. The anti-static protection structure of the invention can realize each ESD protection device unit when static electricity occurs
(即各个 GGNMOS单元） 同时均匀开启， 从而可以达到人体模型 （Human Body Model , ΗΒΜ ) 8KV以上的高 ESD保护能力， 有效地解决了现有的并联叉指结构 的 GGNMOS器件开启电压不一，不能增大并联数量和单指尺寸以至于不能达到高 ESD防护能力的缺陷。 附图说明 (ie, each GGNMOS unit) is evenly turned on at the same time, so that the human body model (Human Body Model, ΗΒΜ) can achieve high ESD protection capability of 8KV or more, effectively solving the problem that the existing GGNMOS device of the parallel interdigital structure has different opening voltages. Increase the number of parallels and the size of the single finger so that the high ESD protection capability cannot be achieved. DRAWINGS
本发明的上述的以及其他的特征、 性质和优势将通过下面结合附图和实施例 的描述而变得更加明显， 其中：  The above and other features, properties and advantages of the present invention will become more apparent from the following description in conjunction with the appended claims
图 1为现有技术中一种常见的 GGNMOS叉指结构的防静电保护结构的平面布 局示意图；  1 is a schematic plan view showing a common layout of an antistatic protection structure of a common GGNMOS interdigital structure in the prior art;
图 2为本发明一个实施例的用于防静电保护的 GGNMOS单元的平面布局结构 示意图；  2 is a schematic diagram showing a planar layout structure of a GGNMOS unit for antistatic protection according to an embodiment of the present invention;
图 3为本发明一个实施例的沿着图 2中 A-A，线看过去的 GGNMOS单元的剖 面工作原理示意图；  3 is a schematic cross-sectional view showing the operation of the GGNMOS cell taken along line A-A of FIG. 2 according to an embodiment of the present invention;
图 4为本发明一个实施例的基于 GGNMOS单元的防静电保护结构的平面布局 示意图。 具体实施方式  4 is a schematic plan view showing an antistatic protection structure based on a GGNMOS unit according to an embodiment of the present invention. detailed description
下面结合具体实施例和附图对本发明作进一步说明， 但不应以此限制本发明 的保护范围。  The present invention is further described in conjunction with the specific embodiments and the accompanying drawings, but should not limit the scope of the invention.
图 2为本发明一个实施例的用于防静电保护的 GGNMOS单元的平面布局结构 示意图。 如图所示， 该 GGNMOS单元 200可具有正多边形状， 例如正四边形、 正 六边形、正八边形、正十二边形或正十六边形皆可。 GGNMOS单元 200的漏极 201 被环状栅极 202封闭，成为一个圓形区域。环状栅极 202又被与其同心的正多边形 状的源极 203包围， 源极 203可以为正四边形、 正六边形、 正八边形、 正十二边形 或正十六边形。源极 203外侧设置有与之距离处处相等的同心的正多边形环状的衬 底接地区域 205, 即源极 203外侧以均匀距离包围有衬底接地区域 205, 而衬底接 地区域 205的内环形状与源极 203相同 ,例如都是正四边形或者正八边形等。 源极 203与衬底接地区域 205之间被场氧区域 204均匀间隔开。 2 is a schematic diagram showing a planar layout structure of a GGNMOS unit for antistatic protection according to an embodiment of the present invention. As shown, the GGNMOS cell 200 can have a regular polygonal shape, such as a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal, or a regular hexagon. The drain 201 of the GGNMOS cell 200 is closed by the annular gate 202 to form a circular area. The annular gate 202 is in turn surrounded by a conical polygonal source 203, which may be a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon. The outer side of the source 203 is provided with a concentric regular polygonal ring-shaped substrate ground region 205 equal to the distance, that is, the outer side of the source 203 is surrounded by the substrate ground region 205 at a uniform distance, and the inner ring of the substrate ground region 205 is The shape is the same as the source 203, and is, for example, a regular quadrangle or a regular octagon. Source The field oxide region 204 is evenly spaced apart from the substrate ground region 205.
在本实施例中， GGNMOS单元 200的源极 203和 /或漏极 201上可以部分覆盖 有同心环状的金属硅化物阻挡层。 具体来说， 继续参考图 2, 可以在漏极 201中的 虚线所绘的小圓环与环状栅极 202之间覆盖有同心环状的金属硅化物阻挡层，而在 该小圓环内覆盖有金属硅化物；可以在环状栅极 202与源极 203中的虚线所绘的大 圓环之间覆盖有金属硅化物阻挡层， 而在源极 203 上的其余区域覆盖有金属硅化 物。 这样做可以在 GGNMOS中引入寄生串联电阻， 起到限流作用， 进一步提高器 件的 ESD防护能力。  In this embodiment, the source 203 and/or the drain 201 of the GGNMOS cell 200 may be partially covered with a concentric annular metal silicide blocking layer. Specifically, with continued reference to FIG. 2, a concentric annular metal silicide blocking layer may be covered between the small ring drawn by the broken line in the drain 201 and the annular gate 202, and in the small ring It is covered with a metal silicide; a metal silicide barrier layer may be covered between the annular ring 202 and the large ring drawn by the broken line in the source electrode 203, and the remaining region on the source electrode 203 is covered with a metal silicide. This can introduce parasitic series resistance into the GGNMOS to limit current and further improve the ESD protection capability of the device.
在本实施例中， GGNMOS单元 200的源极 203和漏极 201均为 N型重掺杂， 衬底接地区域 205为 P型重掺杂。如果源极 203和漏极 201再增加 ESD注入步骤， 则可以进一步提高 GGMOS单元的 ESD防护能力。  In this embodiment, the source 203 and the drain 201 of the GGNMOS cell 200 are both N-type heavily doped, and the substrate ground region 205 is P-type heavily doped. If the source 203 and the drain 201 increase the ESD injection step, the ESD protection capability of the GGMOS unit can be further improved.
另外， 在本实施例中， 单个 GGNMOS单元的外侧边长可以为 20~50μηι。 图 3为本发明一个实施例的沿着图 2中 Α-Α，线看过去的 GGNMOS单元的剖 面工作原理示意图。 如图所示， P阱 210由一圈 P+注入的衬底接地区域 205接地， 208和 209为该 GGNMOS单元 200的两处源极 203到漏极 201的寄生串联电阻。 当 ESD发生时， 漏极 201流向衬底接地区域 205的电流流过寄生串联电阻 208和 209引起源极 203附近 P阱 210电位上升，当该电位使寄生 NPN三极管 206和 207 的发射结正偏时， 寄生 NPN三极管导通， 产生击穿 （Snapback ) 曲线。 由图 2可 知单个环状 GGNMOS单元 200内该寄生串联电阻 208、 209处处相等， 所以寄生 NPN三极管会均匀触发。  In addition, in this embodiment, the outer side length of a single GGNMOS unit may be 20~50μη. Figure 3 is a schematic cross-sectional view showing the operation of the GGNMOS cell taken along line Α-Α in Figure 2, in accordance with one embodiment of the present invention. As shown, the P-well 210 is grounded by a turn of P+ implanted substrate ground region 205, which is the parasitic series resistance of the two source 203 to drain 201 of the GGNMOS cell 200. When ESD occurs, the current flowing from the drain 201 to the substrate ground region 205 flows through the parasitic series resistors 208 and 209 causing the potential of the P well 210 near the source 203 to rise, which causes the emitter junctions of the parasitic NPN transistors 206 and 207 to be forward biased. When the parasitic NPN transistor is turned on, a Snapback curve is generated. It can be seen from Fig. 2 that the parasitic series resistances 208, 209 in the single annular GGNMOS cell 200 are equal everywhere, so the parasitic NPN transistor will be uniformly triggered.
图 4为本发明一个实施例的基于 GGNMOS单元的防静电保护结构的平面布局 示意图。 如图所示， 该防静电保护结构 400可以包括多个正多边形状的 GGNMOS 单元 200, 例如正四边形、 正六边形、 正八边形、 正十二边形或正十六边形皆可。  4 is a schematic plan view showing an antistatic protection structure based on a GGNMOS unit according to an embodiment of the present invention. As shown, the antistatic protection structure 400 may include a plurality of regular polygonal GGNMOS cells 200, such as a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon.
其中， 在单个 GGNMOS单元 200中， 其漏极 201被环状栅极 202封闭， 成为 一个圓形区域。 环状栅极 202又被与其同心的正多边形状的源极 203 包围， 源极 203可以为正四边形、 正六边形、 正八边形、 正十二边形或正十六边形。 源极 203 外侧设置有与之距离处处相等的同心的正多边形环状的衬底接地区域 205, 即源极 203外侧以均匀距离包围有衬底接地区域 205 , 而衬底接地区域 205的内环形状与 源极 203相同 , 例如都是正四边形或者正八边形等。 源极 203与衬底接地区域 205 之间被场氧区域 204均匀间隔开。 这样当有 ESD电流从漏极 201流至衬底接地区 域 205时便可提高源极 203附近的衬底电位， 触发寄生三极管导通达到泄流效果。 由于每个单独的 GGNMOS单元 200的基极寄生电阻（寄生串联电阻）均相同， 所 以各个 GGNMOS单元 200会被同时开启均匀泄流， 从而达到很高的（ HBM 8K以 上） ESD保护能力。 Wherein, in a single GGNMOS cell 200, its drain 201 is closed by the annular gate 202 to form a circular region. The annular gate 202 is in turn surrounded by a conical polygonal source 203, which may be a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagonal or a regular hexagon. The outer side of the source 203 is provided with a concentric regular polygonal ring-shaped substrate grounding region 205 equal to the distance, that is, the outer side of the source 203 is surrounded by the substrate grounding region 205 at a uniform distance, and the inner ring of the substrate grounding region 205 is The shape is the same as the source 203, and is, for example, a regular quadrangle or a regular octagon. Source 203 and substrate ground region 205 They are evenly spaced apart by the field oxide region 204. Thus, when an ESD current flows from the drain 201 to the substrate ground region 205, the substrate potential near the source 203 can be increased, and the parasitic transistor can be triggered to achieve a drain effect. Since the base parasitic resistance (parasitic series resistance) of each individual GGNMOS cell 200 is the same, each GGNMOS cell 200 is simultaneously turned on to uniformly discharge, thereby achieving a high (HBM 8K or more) ESD protection capability.
在该防静电保护结构 400中， 多个 GGNMOS单元 200的衬底接地区域 205 彼此并联， 将多个 GGNMOS单元 200连接构成阵列， 通过增大阵列规模， 例如将 阵列增大到包括 3 x5个、 4 x4个、 4x5个、 5 x5个或者更多个 GGNMOS单元， 就 可以达到 8KV以上的高 ESD防护能力，而且不会出现 GNMOS不均匀导通的现象。  In the antistatic protection structure 400, the substrate ground regions 205 of the plurality of GGNMOS cells 200 are connected in parallel with each other, and the plurality of GGNMOS cells 200 are connected to form an array. By increasing the array size, for example, the array is increased to include 3 x 5, With 4 x 4, 4x5, 5 x 5 or more GGNMOS cells, high ESD protection of 8KV or higher can be achieved without GNMOS uneven conduction.
在本实施例中， 单个 GGNMOS单元 200的源极 203和 /或漏极 201上可以部 分覆盖有同心环状的金属硅化物阻挡层。 具体来说， 如图 2所示， 可以在漏极 201 中的虚线所绘的小圓环与环状栅极 202之间覆盖有同心环状的金属硅化物阻挡层， 而在该小圓环内覆盖有金属硅化物；可以在环状栅极 202与源极 203中的虚线所绘 的大圓环之间覆盖有金属硅化物阻挡层，而在源极 203上的其余区域覆盖有金属硅 化物。 这样做可以在 GGNMOS中引入寄生串联电阻， 起到限流作用， 进一步提高 器件的 ESD防护能力。  In this embodiment, the source 203 and/or the drain 201 of the single GGNMOS cell 200 may be partially covered with a concentric annular metal silicide blocking layer. Specifically, as shown in FIG. 2, a concentric annular metal silicide blocking layer may be covered between the small ring drawn by the broken line in the drain 201 and the annular gate 202, and the small ring may be The inner layer is covered with a metal silicide; a metal silicide blocking layer may be covered between the annular ring 202 and the large ring drawn by the broken line in the source 203, and the remaining region on the source 203 is covered with the metal silicide. . This can introduce a parasitic series resistor in the GGNMOS to limit current and further improve the ESD protection capability of the device.
在本实施例中， GGNMOS单元的源极 203和漏极 201均为 N型重掺杂，衬底 接地区域 205为 P型重掺杂。 如果源极 203和漏极 201再增加 ESD注入步骤， 则 可以进一步提高 GGMOS单元的 ESD防护能力。  In this embodiment, the source 203 and the drain 201 of the GGNMOS cell are both N-type heavily doped, and the substrate ground region 205 is P-type heavily doped. If the source 203 and the drain 201 further increase the ESD injection step, the ESD protection capability of the GGMOS unit can be further improved.
另外， 在本实施例中， 单个 GGNMOS单元的外侧边长可以为 20~50μηι。 本发明通过改变 GGNMOS单元的平面布局结构， 使用了环状栅极封闭漏极， 源极由同心的衬底接地区域围绕的方法使寄生三极管基极串联电阻（寄生电阻）处 处相等。 本发明的防静电保护结构可在静电发生时， 实现各个 ESD保护器件单元 (即各个 GGNMOS单元） 同时均匀开启， 从而可以达到人体模型 （Human Body Model , HBM ) 8KV以上的高 ESD保护能力， 有效地解决了现有的并联叉指结构 的 GGNMOS器件开启电压不一，不能增大并联数量和单指尺寸以至于不能达到高 ESD防护能力的缺陷。  In addition, in this embodiment, the outer side length of a single GGNMOS unit may be 20~50μη. The present invention makes the parasitic transistor base series resistance (parasitic resistance) equal by changing the planar layout structure of the GGNMOS cell, using a ring-shaped gate to close the drain, and the source is surrounded by a concentric substrate ground region. The anti-static protection structure of the invention can realize the simultaneous opening of each ESD protection device unit (ie, each GGNMOS unit) when static electricity is generated, thereby achieving high ESD protection capability of 8KV or more of the Human Body Model (HBM), effective The problem that the GGNMOS devices of the existing parallel interdigital structure have different turn-on voltages and cannot increase the number of parallel connections and single-finger size so as to fail to achieve high ESD protection capability is solved.
本发明虽然以较佳实施例公开如上， 但其并不是用来限定本发明， 任何本领 域技术人员在不脱离本发明的精神和范围内，都可以做出可能的变动和修改， 因此 本发明的保护范围应当以本发明权利要求所界定的范围为准。 The present invention is disclosed in the above preferred embodiments, but it is not intended to limit the invention, and any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of the invention. The scope of the invention should be determined by the scope defined by the claims of the invention.

Claims

权 利 要 求 Rights request
1、一种用于防静电保护的 GGNMOS单元， 具有正多边形状， 其漏极被环 状栅极封闭 , 所述环状栅极又被与其同心的正多边形状的源极包围， 所述源极 外侧设置有与之距离处处相等的同心的正多边形环状的衬底接地区域， 两者之 间被场氧区域均匀间隔开。 A GGNMOS cell for antistatic protection having a regular polygonal shape, a drain of which is closed by a ring-shaped gate, which is in turn surrounded by a conical, normally polygonal source thereof, said source The outer side of the pole is provided with a concentric regular polygonal ring-shaped substrate grounding area equal to the distance therebetween, and the two are evenly spaced apart by the field oxygen region.
2、 根据权利要求 1所述的 GGNMOS 单元， 其特征在于， 所述 GGNMOS 单元的源极和 /或漏极上部分覆盖有同心环状的金属硅化物阻挡层。 2. The GGNMOS unit according to claim 1, wherein the source and/or the upper portion of the drain of the GGNMOS unit are covered with a concentric annular metal silicide blocking layer.
3、 根据权利要求 1或 2所述的 GGNMOS单元， 其特征在于， 所述源极和漏 极均为 N型重掺杂， 所述衬底接地区域为 P型重掺杂。 The GGNMOS cell according to claim 1 or 2, wherein the source and the drain are both N-type heavily doped, and the substrate ground region is P-type heavily doped.
4、 根据权利要求 3所述的 GGNMOS 单元， 其特征在于， 所述 GGNMOS 单元的源极和漏极增加有 ESD注入。 4. The GGNMOS unit according to claim 3, wherein the source and the drain of the GGNMOS unit are added with ESD injection.
5、 根据权利要求 1所述的 GGNMOS 单元， 其特征在于， 所述 GGNMOS 单元的源极呈正四边形、 正六边形、 正八边形、 正十二边形或正十六边形。 The GGNMOS unit according to claim 1, wherein the source of the GGNMOS unit has a regular quadrangle, a regular hexagon, a regular octagon, a regular dodecagon or a regular hexagon.
6、根据权利要求 5所述的 GGNMOS单元，其特征在于，所述单个 GGNMOS 单元的外侧边长为 20~50μηι。 The GGNMOS unit according to claim 5, wherein the outer side of the single GGNMOS unit has a length of 20 to 50 μm.
7、 一种基于 GGNMOS 单元的防静电保护结构， 包括多个正多边形状的 GGNMOS单元； 7. An antistatic protection structure based on a GGNMOS unit, comprising a plurality of regular polygonal GGNMOS cells;
其中， 在单个 GGNMOS单元中， 其漏极被环状栅极封闭， 所述环状栅极 又被与其同心的正多边形状的源极包围， 所述源极外侧设置有与之距离处处相 等的同心的正多边形环状的衬底接地区域， 两者之间被场氧区域均匀间隔开； 所述多个 GGNMOS单元的衬底接地区域彼此并联，将所述多个 GGNMOS 单元连接构成阵列。 Wherein, in a single GGNMOS cell, the drain thereof is closed by a ring-shaped gate, and the ring-shaped gate is surrounded by a concentric polygonal-shaped source, and the source is disposed at an outer distance equal to the distance A concentric regular polygon ring-shaped substrate ground region is evenly spaced between the field oxide regions; the substrate ground regions of the plurality of GGNMOS cells are connected in parallel with each other, and the plurality of GGNMOS cells are connected to form an array.
8、 根据权利要求 7所述的防静电保护结构， 其特征在于， 所述单个8. The antistatic protection structure according to claim 7, wherein said single
GGNMOS单元的源极和 /或漏极上部分覆盖有同心环状的金属硅化物阻挡层。 The source and/or drain upper portions of the GGNMOS cell are covered with a concentric annular metal silicide blocking layer.
9、 根据权利要求 7或 8所述的防静电保护结构， 其特征在于， 所述源极和 漏极均为 N型重掺杂， 所述衬底接地区域为 P型重掺杂。 9. The antistatic protection structure according to claim 7 or 8, wherein the source and the drain are both N-type heavily doped, and the substrate ground region is P-type heavily doped.
10、 根据权利要求 9所述的防静电保护结构， 其特征在于， 所述单个 GGNMOS单元的源极和漏极增加有 ESD注入。 10. The antistatic protection structure according to claim 9, wherein the source and the drain of the single GGNMOS unit are added with ESD injection.
11、 根据权利要求 7所述的防静电保护结构， 其特征在于， 所述 GGNMOS 单元呈正四边形、 正六边形、 正八边形、 正十二边形或正十六边形。 The antistatic protection structure according to claim 7, wherein the GGNMOS unit has a regularogram, a regular hexagon, a regular octagon, a regular dodecagon or a regular hexagon.
12、 根据权利要求 11所述的防静电保护结构， 其特征在于， 所述单个 GGNMOS单元的外侧边长为 20~50μηι。 12. The antistatic protection structure according to claim 11, wherein an outer side length of the single GGNMOS unit is 20 to 50 μm.
13、 根据权利要求 7或 12所述的防静电保护结构， 其特征在于， 所述阵列 包括 3 x5个、 4 x4个、 4 x 5个或者 5 x 5个 GGNMOS单元。 13. The antistatic protection structure according to claim 7 or 12, wherein the array comprises 3 x 5, 4 x 4, 4 x 5 or 5 x 5 GGNMOS cells.
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