CN110071104B - Electrostatic discharge protection structure and manufacturing method thereof - Google Patents
Electrostatic discharge protection structure and manufacturing method thereof Download PDFInfo
- Publication number
- CN110071104B CN110071104B CN201910299308.3A CN201910299308A CN110071104B CN 110071104 B CN110071104 B CN 110071104B CN 201910299308 A CN201910299308 A CN 201910299308A CN 110071104 B CN110071104 B CN 110071104B
- Authority
- CN
- China
- Prior art keywords
- nmos transistors
- area
- protection structure
- discharge element
- discharge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The invention provides an electrostatic discharge protection structure and a manufacturing method thereof, wherein the electrostatic discharge protection structure comprises an idle area, a discharge element area and a substrate contact part, wherein the discharge element area surrounds the periphery of the idle area, a plurality of NMOS transistors connected in parallel are arranged in the discharge element area, and the substrate contact part surrounds the periphery of the discharge element area. The electrostatic discharge protection structure provided by the invention deletes the NMOS transistor with the largest central substrate resistance, only retains the surrounding NMOS transistors, and the substrate resistances of the retained NMOS transistors are not different, so that uniform conduction discharge of all NMOS transistors in the electrostatic discharge protection structure can be realized, and the overall protection capability of the electrostatic discharge protection structure is greatly improved.
Description
Technical Field
The invention belongs to the field of semiconductor integrated circuits, and relates to an Electro-static discharge (ESD) protection structure and a manufacturing method thereof.
Background
At present, an input/output PAD (IO PAD) of a high-voltage device is usually protected by a high-voltage NMOS, and a Grounded-Gate NMOS (GGNMOS) or a Gate-coupled NMOS (GCNMOS) structure is adopted. In the existing layout design, the middle of the ESD device is a high voltage NMOS device, which completely occupies the inner area, and the outer surface is connected to a ring of P-type substrate, and the outermost surface is a ring of N-type guard ring (guard ring).
ESD devices are typically very large in area and now commonly use a multi-finger cross-parallel structure (multi-finger). As the number of fingers (typically corresponding to the number of NMOS transistors) increases, it becomes difficult to turn on each finger uniformly. Since the center finger is very far from the outer substrate contact, the other fingers are relatively close to the outer substrate contact, which results in the inner center finger having the greatest substrate resistance, while the other fingers have a lesser substrate resistance, especially the fingers near the substrate contact have very little substrate resistance. Since the larger the substrate resistance is, the easier it is to turn on the discharge for the NMOS ESD device (according to V ═ I × R, the larger R is, the easier it is to reach the turn-on voltage), as a result, only the central finger is turned on to discharge, while the other fingers are hard to turn on the discharge, and finally the central finger is burned out, resulting in the failure of the ESD device.
Therefore, how to provide a new esd protection structure and a method for fabricating the same to overcome the above problems is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide an esd protection structure and a method for manufacturing the esd protection structure, so as to solve the problem that the esd protection structure in the prior art cannot achieve uniform on-state discharge.
To achieve the above and other related objects, the present invention provides an electrostatic discharge protection structure, including:
an idle area;
the discharge element area surrounds the periphery of the idle area, and a plurality of NMOS transistors connected in parallel are arranged in the discharge element area;
and a substrate contact part surrounding the discharge element region.
Optionally, the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
Optionally, the free region comprises a shallow trench isolation structure.
Optionally, the esd protection structure further comprises a guard ring surrounding the discharge element region and located at the periphery of the substrate contact.
Optionally, the NMOS transistors comprise at least one of grounded-gate NMOS transistors and gate-coupled NMOS transistors.
Optionally, a plurality of the NMOS transistors adopt a multi-finger cross parallel structure.
Optionally, at least two of the NMOS transistors share a source and at least two of the NMOS transistors share a drain.
The invention also provides a manufacturing method of the electrostatic discharge protection structure, which comprises the following steps:
providing a semiconductor substrate;
defining an idle area and a discharge element area in the semiconductor substrate, wherein the discharge element area surrounds the periphery of the idle area;
forming a plurality of NMOS transistors connected in parallel in the discharge element region;
and forming a substrate contact part, wherein the substrate contact part surrounds the periphery of the discharge element area.
Optionally, the method further includes a step of forming a shallow trench isolation structure in the idle region.
Optionally, the method further comprises a step of forming a guard ring, wherein the guard ring surrounds the discharge element region and is positioned at the periphery of the substrate contact part.
Optionally, the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
Optionally, the NMOS transistors comprise at least one of grounded-gate NMOS transistors and gate-coupled NMOS transistors.
Optionally, a plurality of the NMOS transistors adopt a multi-finger cross parallel structure.
Optionally, at least two of the NMOS transistors share a source and at least two of the NMOS transistors share a drain.
As described above, the esd protection structure of the present invention includes the idle region and the discharge device region surrounding the idle region, wherein the NMOS transistor is only disposed in the discharge device region. Because the NMOS transistor with the largest central substrate resistance is deleted, only the surrounding NMOS transistors are reserved, the substrate resistances of the reserved NMOS transistors are not different, and uniform conduction and discharge of all the NMOS transistors in the electrostatic discharge protection structure can be realized. Through experimental verification, by adopting the scheme of the invention, the discharge level of a Human Body Model (HBM for short) can be improved from 1000V to 2000V, and the overall protection capability of the electrostatic discharge protection structure is greatly improved.
Drawings
FIG. 1 is a plan view of an ESD structure.
FIG. 2 is a plan view of the ESD structure of the present invention.
FIG. 3 is a process flow chart of the method for fabricating an ESD structure according to the present invention.
Description of the element reference numerals
100. 200 electrostatic discharge protection structure
201 free area
101. 202 discharge element region
102. 203 grid electrode
103. 204 source electrode
104. 205 drain stage
105. 206 substrate contact
106. 207 guard ring
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 3. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
As shown in fig. 1, an esd protection structure 100 is shown for protecting an IO PAD of a high voltage device, the esd protection structure 100 includes a discharge element region 101, an inner space of the discharge element region 101 is fully occupied by a plurality of high voltage NMOS devices, each of the NMOS devices includes a gate 102 and a source 103 and a drain 104 located at two sides of the gate 102. The discharge element region 101 is first surrounded by a substrate contact 105 and an outermost ring is an N-type guard ring 106. Because the central NMOS is far away from the substrate contact part outside, and the other NMOSs are close to the substrate contact part outside, the internal central NMOS has the maximum substrate resistance, while the substrate resistances of the other NMOSs are small, especially the substrate resistance of the NMOS close to the substrate contact part is very small, so that the NMOS only in the center is easy to conduct and discharge, the other NMOSs are difficult to conduct and discharge, and finally the central NMOS is burnt out, so that the ESD device is invalid. Therefore, the substrate resistance uniformity of the electrostatic discharge protection structure is improved by the following new design scheme.
Example one
Referring to fig. 2, a plan layout view of an esd protection structure 200 is shown in the present embodiment, which includes an idle region 201, a discharge device region 202 and a substrate contact 206, wherein the discharge device region 202 surrounds the idle region 201, and the substrate contact 206 surrounds the discharge device region 202.
As an example, a plurality of NMOS transistors connected in parallel are disposed in the discharge element region 202, and each NMOS transistor includes a gate 203, and a source 204 and a drain 205 located on both sides of the gate 203. In this embodiment, at least two of the NMOS transistors share a source, and at least two of the NMOS transistors share a drain, so as to save layout space.
As an example, a plurality of the NMOS transistors may adopt a multi-finger cross parallel structure (not shown) to realize a sufficient substrate current, wherein sources of the plurality of NMOS transistors are connected and fingered, drains of the plurality of NMOS transistors are connected and fingered, the fingered of the sources and the fingered of the drains are isolated from each other and arranged to cross, and the gates are located between the fingered of the sources and the fingered of the drains.
As an example, the NMOS transistor may be a grounded-gate NMOS transistor (GGNMOS), or a gate-coupled NMOS transistor (GCNMOS), where a drain terminal of the GGNMOS is connected to the PAD and a gate terminal thereof is connected to a power ground, and the ESD protection utilizes a parasitic NPN transistor thereof to form a low-impedance discharge path, thereby protecting an internal circuit of the IC. In the GCNMOS structure, electrostatic charges are quickly coupled to the grid end of an NMOS tube by using a capacitor and a small resistor, and the NMOS tube is quickly started to discharge the charges.
Specifically, the discharge element is not provided in the empty region 201. In this embodiment, the free region includes a shallow trench isolation structure.
Specifically, the idle region 201 is relatively located in the central region of the discharge element region 202, so as to remove the NMOS transistor with the largest substrate resistance and the NMOS transistor with a relatively larger substrate resistance. The area of the idle region 201 can be set as required, and under the condition that the uniformity of the substrate resistance is ensured to be not large, the smaller the area of the idle region 201 is, the better the area is, so that the substrate area utilization rate is improved. By way of example, the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
As an example, the esd protection structure 200 further comprises a guard ring 207, wherein the guard ring 207 surrounds the discharge device region 202 and is located at the periphery of the substrate contact 206.
The electrostatic discharge protection structure comprises an idle area and a discharge element area surrounding the idle area, wherein the NMOS transistor is only arranged in the discharge element area. Because the NMOS transistor with the largest central substrate resistance is deleted, only the surrounding NMOS transistors are reserved, the substrate resistances of the reserved NMOS transistors are not different, and uniform conduction and discharge of all the NMOS transistors in the electrostatic discharge protection structure can be realized. Through experimental verification, by adopting the scheme of the invention, the discharge level of a Human Body Model (HBM for short) can be improved from 1000V to 2000V, and the overall protection capability of the electrostatic discharge protection structure is greatly improved.
Example two
Referring to fig. 3, a process flow diagram of the manufacturing method is shown, which includes the following steps:
s1: providing a semiconductor substrate;
s2: defining an idle area and a discharge element area in the semiconductor substrate, wherein the discharge element area surrounds the periphery of the idle area;
s3: forming a plurality of NMOS transistors connected in parallel in the discharge element region;
s4: and forming a substrate contact part, wherein the substrate contact part surrounds the periphery of the discharge element area.
Specifically, the semiconductor substrate may be a P-type substrate, or may be an N-type substrate provided with a P-well.
Specifically, the discharge element is not provided in the vacant region. In this embodiment, the method further includes forming a shallow trench isolation structure in the idle region.
Specifically, the idle region is relatively located in the central region of the discharge element region to remove the NMOS transistor with the largest substrate resistance and the NMOS transistor with a relatively large substrate resistance. The area of the idle area can be set as required, and the smaller the area of the idle area is, the better the area of the idle area is, so that the area utilization rate of the substrate is improved under the condition that the difference of the resistance uniformity of the substrate is not large. By way of example, the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
As an example, the method further includes forming a guard ring surrounding the discharge element region and located at a periphery of the substrate contact.
As an example, the NMOS transistor includes a gate, and a source and a drain 205 located at two sides of the gate. In this embodiment, at least two of the NMOS transistors share a source, and at least two of the NMOS transistors share a drain, so as to save layout space.
As an example, a plurality of the NMOS transistors may adopt a multi-finger cross parallel structure (not shown) to realize a sufficient substrate current, wherein sources of the plurality of NMOS transistors are connected and fingered, drains of the plurality of NMOS transistors are connected and fingered, the fingered of the sources and the fingered of the drains are isolated from each other and arranged to cross, and the gates are located between the fingered of the sources and the fingered of the drains.
As an example, the NMOS transistor may be a grounded-gate NMOS transistor (GGNMOS), or a gate-coupled NMOS transistor (GCNMOS), where a drain terminal of the GGNMOS is connected to the PAD and a gate terminal thereof is connected to a power ground, and the ESD protection utilizes a parasitic NPN transistor thereof to form a low-impedance discharge path, thereby protecting an internal circuit of the IC. In the GCNMOS structure, electrostatic charges are quickly coupled to the grid end of an NMOS tube by using a capacitor and a small resistor, and the NMOS tube is quickly started to discharge the charges.
In the manufacturing method of the electrostatic discharge protection structure of this embodiment, the idle region and the discharge element region are defined in the semiconductor substrate, the NMOS transistor is only disposed in the discharge element region, and the NMOS transistor with the largest central substrate resistance is deleted, so that the substrate resistance uniformity of each NMOS transistor in the discharge element region can be improved, and uniform conduction and discharge of all NMOS transistors in the electrostatic discharge protection structure are realized.
In summary, the esd protection structure of the present invention includes an idle region and a discharge device region surrounding the idle region, wherein the NMOS transistor is only disposed in the discharge device region. Because the NMOS transistor with the largest central substrate resistance is deleted, only the surrounding NMOS transistors are reserved, the substrate resistances of the reserved NMOS transistors are not different, and uniform conduction and discharge of all the NMOS transistors in the electrostatic discharge protection structure can be realized. Through experimental verification, by adopting the scheme of the invention, the discharge level of a Human Body Model (HBM for short) can be improved from 1000V to 2000V, and the overall protection capability of the electrostatic discharge protection structure is greatly improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (12)
1. An electrostatic discharge protection structure, comprising:
an idle region comprising a shallow trench isolation structure;
the discharge element area surrounds the periphery of the idle area, and a plurality of NMOS transistors connected in parallel are arranged in the discharge element area;
and a substrate contact part surrounding the discharge element region.
2. The esd-protection structure of claim 1, wherein: the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
3. The esd-protection structure of claim 1, wherein: the electrostatic discharge protection structure further comprises a guard ring, wherein the guard ring surrounds the periphery of the discharge element region and is positioned on the periphery of the substrate contact part.
4. The esd-protection structure of claim 1, wherein: the NMOS transistors include at least one of grounded-gate NMOS transistors and gate-coupled NMOS transistors.
5. The esd-protection structure of claim 1, wherein: and a plurality of NMOS transistors adopt a multi-finger cross parallel structure.
6. The esd-protection structure of claim 1, wherein: at least two of the NMOS transistors share a source and at least two of the NMOS transistors share a drain.
7. A manufacturing method of an electrostatic discharge protection structure is characterized by comprising the following steps:
providing a semiconductor substrate;
defining an idle area and a discharge element area in the semiconductor substrate, wherein the discharge element area surrounds the periphery of the idle area;
forming a plurality of NMOS transistors connected in parallel in the discharge element region;
forming a substrate contact portion, wherein the substrate contact portion surrounds the periphery of the discharge element area;
and forming a shallow trench isolation structure in the idle area.
8. The method of claim 7, wherein: the method also comprises a step of forming a guard ring, wherein the guard ring surrounds the periphery of the discharge element region and is positioned at the periphery of the substrate contact part.
9. The method of claim 7, wherein: the ratio of the area of the idle region to the area of the discharge element region ranges from 1:9 to 3: 2.
10. The method of claim 7, wherein: the NMOS transistors include at least one of grounded-gate NMOS transistors and gate-coupled NMOS transistors.
11. The method of claim 7, wherein: and a plurality of NMOS transistors adopt a multi-finger cross parallel structure.
12. The method of claim 7, wherein: at least two of the NMOS transistors share a source and at least two of the NMOS transistors share a drain.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910299308.3A CN110071104B (en) | 2019-04-15 | 2019-04-15 | Electrostatic discharge protection structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910299308.3A CN110071104B (en) | 2019-04-15 | 2019-04-15 | Electrostatic discharge protection structure and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110071104A CN110071104A (en) | 2019-07-30 |
| CN110071104B true CN110071104B (en) | 2020-05-19 |
Family
ID=67367623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910299308.3A Active CN110071104B (en) | 2019-04-15 | 2019-04-15 | Electrostatic discharge protection structure and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110071104B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112366202A (en) * | 2020-10-23 | 2021-02-12 | 长江存储科技有限责任公司 | Electrostatic discharge protection structure and manufacturing method thereof |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010059987A (en) * | 1999-12-31 | 2001-07-06 | 박종섭 | Elector static discharge protection circuit |
| CN101442045A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Multi-fork syconoid MOSFET structure |
| CN102983130A (en) * | 2011-09-05 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6833568B2 (en) * | 2003-03-13 | 2004-12-21 | Texas Instruments Incorporated | Geometry-controllable design blocks of MOS transistors for improved ESD protection |
| KR101056201B1 (en) * | 2004-07-27 | 2011-08-11 | 동부일렉트로닉스 주식회사 | Semiconductor device for electrostatic discharge protection |
| CN102034809B (en) * | 2009-09-27 | 2012-07-04 | 上海宏力半导体制造有限公司 | ESD (Electrostatic Discharge) protective circuit |
-
2019
- 2019-04-15 CN CN201910299308.3A patent/CN110071104B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20010059987A (en) * | 1999-12-31 | 2001-07-06 | 박종섭 | Elector static discharge protection circuit |
| CN101442045A (en) * | 2007-11-23 | 2009-05-27 | 上海华虹Nec电子有限公司 | Multi-fork syconoid MOSFET structure |
| CN102983130A (en) * | 2011-09-05 | 2013-03-20 | 中芯国际集成电路制造(上海)有限公司 | An electro-static discharge protection circuit for an integrated circuit and a manufacturing method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110071104A (en) | 2019-07-30 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6621133B1 (en) | Electrostatic discharge protection device | |
| EP2140491B1 (en) | Stacked esd protection circuit having reduced trigger voltage | |
| US6858902B1 (en) | Efficient ESD protection with application for low capacitance I/O pads | |
| WO2006001990A1 (en) | Fast turn-on and low-capacitance scr esd protection | |
| US20050254189A1 (en) | ESD protection circuit with low parasitic capacitance | |
| US8614489B2 (en) | Vertical NPNP structure in a triple well CMOS process | |
| US20060215337A1 (en) | ESD protection circuit with low parasitic capacitance | |
| TWI664709B (en) | Electrostatic discharge protection semiconductor device | |
| WO2004075370A2 (en) | Minimum-dimension, fully-silicided mos driver and esd protection design for optimized inter-finger coupling | |
| US8703547B2 (en) | Thyristor comprising a special doped region characterized by an LDD region and a halo implant | |
| US6777721B1 (en) | SCR device for ESD protection | |
| CN1360347A (en) | Electrostatic discharge protecting circuit | |
| US9673189B2 (en) | ESD unit | |
| TW201633492A (en) | Electrostatic discharge protection semiconductor device | |
| US9530768B1 (en) | Gate-coupled NMOS device for electro-static discharge protection | |
| CN110071104B (en) | Electrostatic discharge protection structure and manufacturing method thereof | |
| TW201640646A (en) | Connection pad electrostatic protection element of integrated circuit | |
| US20220310589A1 (en) | Integrated circuit device and method for esd protection | |
| TWI697092B (en) | Semiconductor electrostatic discharge protection circuit, esd protection semiconductor device, and layout structure of esd protection semiconductor device | |
| CN110060997B (en) | Electrostatic discharge protection structure and manufacturing method thereof | |
| CN101202279A (en) | Electrostatic discharge protection circuit and integrated circuit | |
| CN114783996A (en) | Multi-finger structure for promoting uniform triggering of electrostatic discharge device | |
| CN100338770C (en) | Electrostatic discharge protecting circuit | |
| US20050082619A1 (en) | Electrostatic discharge protection structure for deep sub-micron gate oxide | |
| US6236086B1 (en) | ESD protection with buried diffusion |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |