CN102034809B - ESD (Electrostatic Discharge) protective circuit - Google Patents

ESD (Electrostatic Discharge) protective circuit Download PDF

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Publication number
CN102034809B
CN102034809B CN2009101968697A CN200910196869A CN102034809B CN 102034809 B CN102034809 B CN 102034809B CN 2009101968697 A CN2009101968697 A CN 2009101968697A CN 200910196869 A CN200910196869 A CN 200910196869A CN 102034809 B CN102034809 B CN 102034809B
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CN
China
Prior art keywords
scr
well contact
pipe
esd
well
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CN2009101968697A
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Chinese (zh)
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CN102034809A (en
Inventor
单毅
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上海宏力半导体制造有限公司
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Priority to CN2009101968697A priority Critical patent/CN102034809B/en
Publication of CN102034809A publication Critical patent/CN102034809A/en
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Publication of CN102034809B publication Critical patent/CN102034809B/en

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Abstract

The invention relates to an ESD (Electrostatic Discharge) protective circuit, which comprises an N-well contact arranged around a PMOS (P-channel Metal Oxide Semiconductor) tube and a P-well contact arranged around an NMOS (N-channel Metal Oxide Semiconductor) tube. A P+ and an N+ are inserted respectively between the N-well and P-well contacts. The N-well contact, P+, N+ and P-well contact form an SCR tube. The ESD protective capacity in unit size of the SCR is greater than that of the MOS tube. The reverse breakdown voltage of a grid diode at the junction of a drain and a grid of the NMOS tube of the circuit is lower so the drain with ESD impulse can generate drain current by means of reverse breakdown under lower voltage so that the base-emitter of a T2 of the SCR is positively biased, the T2 is conducted and finally the whole SCR structure is conducted. The triggering voltage of the ESD protective circuit is low and the protective capacity is far stronger than that of the single MOS tube once the SCR can be triggered and conducted.

Description

A kind of ESD protection circuit

Technical field

The present invention relates to the electrostatic discharge (ESD) protection technical field, design a kind of ESD protection circuit especially.

Background technology

Referring to Fig. 1, this figure is the output driving circuit and static discharge (ESD, Electro Static Discharge) the protective circuit structure chart of a kind of input-output unit in the prior art.

P1 and P2 are the PMOS pipes, and N1 and N2 are the NMOS pipes.The circuit that P1 and N1 form both can be used as esd protection circuit, can be used as the output driving circuit of input-output unit again, and as can beappreciated from fig. 1, the circuit that the P1 on the left side and N1 form is as esd protection circuit.The circuit that the P2 on the right and N2 form is the output driving circuit as input-output unit.

The difference of the output driving circuit of esd protection circuit and input-output unit only is the position difference that the grid of PMOS pipe and NMOS pipe is connected.

Because the esd protection circuit of this structure is the protection of being done by simple metal-oxide-semiconductor, because the protective capability of metal-oxide-semiconductor unit sizes is relatively poor.Therefore, generally adopt the SCR pipe to do esd protection.Because the unit sizes protective capability of SCR pipe is better than metal-oxide-semiconductor.But, do esd protection circuit with the SCR pipe merely and also have shortcoming.Specify below in conjunction with Fig. 2.

Referring to Fig. 2, the structural representation of the esd protection circuit of managing for SCR in this figure prior art.

When anode adds positive esd pulse, have only ESD voltage high to certain value, reverse breakdown could take place in the PN junction that PWELL and NWELL form, and produces a leakage current that flows to PWELL.This leakage current flows through resistance R pwell, makes the base-emitter positively biased of T2, the T2 conducting.Thereby the collector electrode of T2 has electric current to flow through, and this current flowing resistance Rnwell makes the base-emitter positively biased of T1, the T1 conducting.Therefore whole SCR just can conducting.It is thus clear that SCR needs to trigger, the PN junction generation reverse breakdown that just needs PWELL and NWELL to form, this puncture voltage is very high, so the trigger voltage of SCR is very high.

When anode added negative esd pulse, PWELL and NWELL formed the diode of a positively biased, and electric current directly flows to anode through diode from negative electrode, and diode turn-on voltage is very low, does not have the high problem of similar SCR trigger voltage.

In sum, the trigger voltage of SCR is added in the voltage of anode when depending on the PN junction generation reverse breakdown that PWELL and NWELL form, and this voltage needs very high, can not effective esd protection be provided for internal circuit.

Summary of the invention

The problem that the present invention solves provides a kind of esd protection circuit, can improve the protective capability of esd protection circuit, reduces trigger voltage simultaneously.

For addressing the above problem; The present invention provides a kind of ESD protection circuit; Comprise: the N-well contact is set around the PMOS pipe; The P-well contact is set around the NMOS pipe, between said N-well contact and said P-well contact, inserts a P+ and a N+ successively, said N-well contact, a P+, a N+ contact with P-well and form the SCR pipe.

Preferably, the source electrode of said PMOS pipe connects VDD, and drain electrode connects the PAD pad; The drain electrode of said NMOS pipe connects the PAD pad, and source electrode connects GND; The N-well contact of said SCR pipe connects VDD, and P+ connects VDD, and N+ connects GND, and the P-well contact connects GND.

Preferably, the grid of said PMOS pipe connects VDD, and the grid of said NMOS pipe connects GND.

Compared with prior art, the present invention has the following advantages:

The esd protection circuit that the embodiment of the invention provides; Through in the middle of the structure of existing P metal-oxide-semiconductor and NMOS pipe, inserting a P+ and a N+ successively; Just in time contact with P-well and form SCR, because the esd protection of SCR unit sizes ability force rate metal-oxide-semiconductor is good according to the N-well contact.And the reverse breakdown voltage of the grid diode of the drain electrode-grid intersection of the NMOS of this circuit structure pipe is lower; When so drain electrode has esd pulse; Can be under low voltage produce leakage current, make the base-emitter positively biased of T2 of SCR, the T2 conducting with regard to reverse breakdown.Compared with prior art; The esd protection circuit that the embodiment of the invention provides can just provide enough SCR trigger currents when low voltage; Therefore the trigger voltage of the esd protection circuit in the embodiment of the invention is low; In case and SCR can trigger, its protective capability is eager to excel a lot than the protective capability of simple metal-oxide-semiconductor.

Description of drawings

Fig. 1 is the output driving circuit and the esd protection circuit sketch map of a kind of input-output unit in the prior art;

Fig. 2 is the sectional view of the esd protection circuit of SCR pipe in the prior art;

Fig. 3 is the domain of esd protection circuit of the present invention;

Fig. 4 is the corresponding structural representation of Fig. 3 esd protection circuit of the present invention;

Fig. 5 is the output driving circuit sketch map of a kind of esd protection circuit provided by the invention and input-output unit.

Embodiment

For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.

A kind of ESD protection circuit that the embodiment of the invention provides comprises PMOS pipe, NMOS pipe and SCR pipe.Be specially: the N-well contact is set around the PMOS pipe; The P-well contact is set around the NMOS pipe; Between said N-well contact and said P-well contact, insert a P+ and a N+ successively, said N-well contact, a P+, a N+ contact with P-well and form at least two SCR pipes.

Referring to Fig. 3, this figure is the domain of esd protection circuit of the present invention.

The esd protection circuit that the embodiment of the invention provides comprises PMOS pipe, NMOS pipe and SCR pipe.

From domain shown in Figure 3, can find out; It in the top N-well contact ring PMOS pipe of a plurality of parallel connections; It in the following P-well contact ring NMOS pipe of a plurality of parallel connections; Between N-well contact ring and P-well contact ring, insert a P+ and a N+ successively, so positive good utilisation N-well contact, P+, N+ and P-well contacting structure form the SCR pipe.

Need to prove; The esd protection circuit that the embodiment of the invention provides does not limit the concrete number of PMOS pipe, NMOS pipe and SCR pipe; Can find out from domain structure figure shown in Figure 3, comprise the NMOS pipe of the PMOS pipe of a lot of parallel connections, a plurality of parallel connections and the SCR pipe of a plurality of parallel connections.

Because the esd protection of SCR pipe unit sizes can be eager to excel by the force rate metal-oxide-semiconductor, therefore possibly improve the esd protection ability, why the structure of introducing esd protection circuit provided by the invention below in detail can reduce the trigger voltage of SCR pipe simultaneously.

Referring to Fig. 4, this figure is the corresponding structural representation of Fig. 3 esd protection circuit of the present invention.

As can be seen from Figure 4, the left side be PMOS pipe, the right be the NMOS pipe, middle is the SCR pipe.

Present embodiment does not limit the grid of PMOS pipe and what the grid of NMOS pipe specifically connects.

Such just as Fig. 1 when this structure is used as esd protection circuit, the grid of PMOS pipe connects VDD, the grid connection GND of NMOS pipe.

When this structure was used as the output driving circuit of input-output unit, the grid of the grid of PMOS pipe and NMOS pipe all connect the front wheel driving circuit.

As can be seen from Figure 4, the source electrode of PMOS pipe connects VDD, and drain electrode connects the PAD pad.

The drain electrode of NMOS pipe connects the PAD pad, and source electrode connects GND.

The N-well contact of SCR pipe all is connected VDD with P+, and contact all is connected GND to N+ with P-well.

At this moment, when the PAD pad added positive esd pulse, when ESD voltage was low, drain electrode place of NMOS just can provide a bigger leakage current to flow into PWELL.

As shown in Figure 4, the drain electrode of NMOS-grid intersection has a grid diode D; The reverse breakdown voltage of this diode D is lower, so drain when esd pulse is arranged, can under low voltage, produce leakage current with regard to reverse breakdown; Make the base-emitter positively biased of T2, the T2 conducting.

The collector electrode of T2 has electric current to flow through, and this electric current flows through Rnwell, makes the base-emitter positively biased of T1, the T1 conducting.Therefore whole SCR just can conducting.Compared with prior art; The esd protection circuit that the embodiment of the invention provides can just provide enough SCR trigger currents when low voltage; Therefore the trigger voltage of the esd protection circuit in the embodiment of the invention is low; In case and SCR can trigger, the protective capability of the ratio metal-oxide-semiconductor that its protective capability is simple is eager to excel a lot.

Referring to Fig. 5, this figure is the sketch map of the output driving circuit of a kind of esd protection circuit provided by the invention and input-output unit.

Need to prove that the basic composition circuit among this embodiment is the structure that NMOS pipe, PMOS pipe and the SCR pipe in the foregoing description formed.

Different with prior art Fig. 1 is that the present invention has embedded the SCR pipe in the middle of PMOS pipe and NMOS pipe.The structure of being made up of metal-oxide-semiconductor and the mixing of SCR pipe provided by the invention had both solved the problem of simple metal-oxide-semiconductor unit sizes protective capability difference, had solved the problem that simple SCR pipe needs high trigger voltage again.

The above only is preferred embodiment of the present invention, is not the present invention is done any pro forma restriction.Though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention.Any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the method for above-mentioned announcement capable of using and technology contents are made many possible changes and modification to technical scheme of the present invention, or are revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.

Claims (1)

1. an ESD protection circuit is characterized in that, comprising: in the N trap, form the PMOS pipe, in the P trap, form the NMOS pipe; Around the PMOS pipe,, N-well contacts around being set; Around the NMOS pipe,, P-well contacts around being set; Between said N-well contact and said P-well contact, insert a row P+ doped region and a row N+ doped region successively, said N-well contact, a row P+ doped region, a row N+ doped region contact with P-well and form the SCR pipe; A said N-well contact and a said row P+ doped region are formed in the said N trap, and a said P-well contact and a said row N+ doped region are formed in the said P trap, and wherein said N trap is adjacent with said P trap; The source electrode of said PMOS pipe connects VDD, and drain electrode connects the PAD pad; The drain electrode of said NMOS pipe connects the PAD pad, and source electrode connects GND; The N-well contact of said SCR pipe connects VDD, and a row P+ doped region connects VDD, and a row N+ doped region connects GND, and the P-well contact connects GND; The grid of said PMOS pipe connects VDD, and the grid of said NMOS pipe connects GND.
CN2009101968697A 2009-09-27 2009-09-27 ESD (Electrostatic Discharge) protective circuit CN102034809B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009101968697A CN102034809B (en) 2009-09-27 2009-09-27 ESD (Electrostatic Discharge) protective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009101968697A CN102034809B (en) 2009-09-27 2009-09-27 ESD (Electrostatic Discharge) protective circuit

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CN102034809A CN102034809A (en) 2011-04-27
CN102034809B true CN102034809B (en) 2012-07-04

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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104241277B (en) * 2014-09-28 2017-10-13 江南大学 A kind of SCR device that GDPMOS is embedded with high maintenance voltage
CN110071104B (en) * 2019-04-15 2020-05-19 长江存储科技有限责任公司 Electrostatic discharge protection structure and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6271999B1 (en) * 1998-11-20 2001-08-07 Taiwan Semiconductor Manufacturing Company ESD protection circuit for different power supplies
US6433392B1 (en) * 1998-04-08 2002-08-13 Texas Instruments Incorporated Electrostatic discharge device and method
CN1494146A (en) * 2002-10-31 2004-05-05 中芯国际集成电路制造(上海)有限公 Electro static discharging protective circuit and its designing method
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6433392B1 (en) * 1998-04-08 2002-08-13 Texas Instruments Incorporated Electrostatic discharge device and method
US6271999B1 (en) * 1998-11-20 2001-08-07 Taiwan Semiconductor Manufacturing Company ESD protection circuit for different power supplies
CN1494146A (en) * 2002-10-31 2004-05-05 中芯国际集成电路制造(上海)有限公 Electro static discharging protective circuit and its designing method
CN1658388A (en) * 2004-02-18 2005-08-24 富士通株式会社 Electrostatic discharge protection circuit

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Inventor after: Yang Guang

Inventor after: Wu Junsheng

Inventor after: Xu Li

Inventor after: Dan Yi

Inventor before: Dan Yi

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Effective date of registration: 20121205

Address after: 100031 Xicheng District West Chang'an Avenue, No. 86, Beijing

Patentee after: State Grid Corporation of China

Patentee after: Shanghai Electric Power Corporation

Patentee after: Shanghai Zihe Communication Technology Co., Ltd.

Address before: 201203 Shanghai city Zuchongzhi road Pudong Zhangjiang hi tech Park No. 1399

Patentee before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai

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Free format text: CORRECT: ADDRESS; FROM: 201203 PUDONG NEW AREA, SHANGHAI TO: 100031 XICHENG, BEIJING

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Owner name: SHANGHAI MUNICIPAL ELECTRIC POWER COMPANY SHANGHAI

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