CN101452851A

CN101452851A - Manufacturing method for ESD gate grounding NMOS transistor

Info

Publication number: CN101452851A
Application number: CNA2007100943848A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-12-06
Filing date: 2007-12-06
Publication date: 2009-06-10

Abstract

The invention discloses a method for manufacturing an ESD gate grounded NMOS transistor. Through photoetching, the drain end and the edge of the grid electrode of the ESD transistor are in certain distance; a region (a drift region) between the drain end and the grid electrode is only provided with a lightly-doped source drain (LDD) region and no high-dosage drain adulteration; as square resistance of the LDD region is much larger relative to the high doped drain end, the method can ensure that larger series resistance is obtained under the condition of shorter length of the drift region without increasing area occupied by the transistor, thereby saving the area of the transistor; moreover, as the breakdown voltage of an LDD junction is lower than the drain end, the transistor decides the trigger voltage through the LDD junction, well achieves the aim of reducing the trigger voltage, does not need any extra ESD photoetching and ESD ion injection, thereby simplifying a process and saving cost.

Description

ESD gate grounding NMOS transistor manufacture method

Technical field

The present invention relates to field of manufacturing semiconductor devices, relate in particular to a kind of ESD gate grounding NMOS transistor manufacture method.

Background technology

Electrostatic protection (ESD) gate grounding NMOS (GGNMOS) is the junction breakdown by drain terminal, makes Lou/raceway groove/source parasitic bipolar transistor conducting, gets the effect of bleed off static.For ESD has the better protect effect, it leaks trigger voltage (trigger voltage) needs suitably to reduce, and needs bigger series resistance at drain terminal in addition, in order to regulate the size of ESD transistor thermal breakdown voltage.Conventional ESD gate grounding NMOS transistor is general to adopt self aligned source to leak technology, promptly utilize grid and side wall to carry out the source earlier and leak the ion injection, then in order to realize bigger drain terminal series resistance, need between grid and drain terminal, stay bigger space to make silicide barrier layer, as the drift region, and at position injection N type or the p type impurity of transistor drain terminal apart from the described pore size at grid edge, form the ESD knot, to reach the purpose of suitable reduction trigger voltage, the cross-section structure of the ESD gate grounding NMOS transistor of finally making and planar structure are respectively as depicted in figs. 1 and 2.Because leak in the source is heavily doped region, square resistance is very little, need stay bigger space just can reach the series resistance requirement so make nmos pass transistor by above-mentioned conventional method, therefore wastes very much the device area occupied.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of ESD gate grounding NMOS transistor manufacture method, can reduce trigger voltage, can also dwindle the shared area of transistor simultaneously.

For solving the problems of the technologies described above, the invention provides a kind of ESD gate grounding NMOS transistor manufacture method, comprising:

Form the operation of grid;

Carry out selective N type ion on the silicon substrate and inject the operation that forms the LDD zone;

Form the operation of side wall in described grid both sides;

Leak ion in the N+ source and inject the position that reticle defines the drift region, utilize photoresist to block described drift region then, silicon chip is carried out the N+ source leak the operation that ion injects.

The present invention is owing to adopted technique scheme, has such beneficial effect, promptly make transistorized drain terminal of ESD and gate edge at intervals by reticle, and make the zone (being the drift region) between drain terminal and grid have only lightly-doped source to leak (LDD) zone, and do not have the leakage of high dose to mix, because the square resistance in LDD zone is much bigger with respect to highly doped drain terminal, therefore having guaranteed can be under the short situation of drift region length, obtain bigger series resistance, and need not to increase the shared area of transistor, according to experimental result as can be known, for realizing onesize series resistance, the drift region length of definition required for the present invention is the over half of existing technology, so the method for the invention is from having saved transistorized area to a great extent; In addition, because the puncture voltage of LDD knot is lower than drain terminal, and transistor of the present invention makes trigger voltage by the decision of LDD knot, therefore played the purpose that reduces trigger voltage well, and need not any extra ESD reticle and the injection of ESD ion, and simplified technology thus, saved cost.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the sectional structure chart of the ESD gate grounding NMOS transistor made by existing technology;

Fig. 2 is the plane structure chart of the ESD gate grounding NMOS transistor made by existing technology;

Fig. 3 is the schematic flow sheet according to an embodiment of ESD gate grounding NMOS transistor manufacture method of the present invention;

Fig. 4 a-4e is for making the sectional structure chart in the ESD gate grounding NMOS transistor process according to Fig. 3;

Fig. 5 is the plane structure chart of the ESD gate grounding NMOS transistor made according to the method for the invention.

Embodiment

In one embodiment, as shown in Figure 3, ESD gate grounding NMOS transistor manufacture method of the present invention may further comprise the steps:

The first step is carried out selectivity P type channel ion and is injected on silicon substrate.

Second step, at silicon substrate grown on top one deck gate oxide, deposit one deck polysilicon gate on described gate oxide then.

The 3rd step, use known photoetching technique, described polysilicon gate is carried out etching, form the grid of device, cross-section structure at this moment is shown in Fig. 4 a.

The 4th step, on silicon substrate, carry out selectivity low dosage LDD (Lightly Doped Drain, slight doped-drain) N type ion and inject, form light dope LDD zone, wherein the dosage range of the ion that is injected is E13～E14cm ^-2

In the 5th step, form the silicon nitride side wall in the both sides of described grid.

Above-mentioned steps all belongs to common process to those skilled in the art, therefore is not described in detail herein.

The 6th step, according to the transistor series resistance that will realize and the size of puncture voltage, leak ion in the N+ source and inject the position that reticle defines the drift region, then shown in Fig. 4 b, utilize photoresist to block the drift region, then silicon chip is carried out the N+ source and leaks ion and inject, inject ion dosage range be 2E15～5E15cm ^-2Thereby, forming transistorized source and drain areas, the zone between at this moment formed transistor drain terminal and the gate edge is the drift region, removes photoresist then, and cross-section structure at this moment is shown in Fig. 4 c.By this step, make the zone between transistor drain terminal and gate edge have only lightly doped drain (LDD) zone, and do not have the leakage of high dose to mix, because the square resistance in LDD zone is much bigger with respect to highly doped drain terminal, therefore having guaranteed can be under the short situation of drift region length, obtain bigger series resistance, and need not to increase the shared area of transistor, therefore saved transistorized area to a certain extent (as can be known according to experimental result, for realizing onesize series resistance, the drift region length of definition required for the present invention is the over half of existing technology); In addition,, therefore can play the purpose that reduces trigger voltage well, thereby no longer need any extra ESD reticle and ESD ion to inject, thereby simplify technology, save cost because the puncture voltage of LDD knot is lower than drain terminal.

The 7th step, deposit layer of metal silicide barrier layer on silicon chip, for example when described metal silicide is silica, the thickness range of institute's deposit is 300～1000 dusts, use known photoetching technique that described blocking layer of metal silicide is carried out etching then, thereby make only to remain with blocking layer of metal silicide on described drift region, cross-section structure at this moment is shown in Fig. 4 d.

The 8th step, deposit layer of metal silicide (as the cobalt of 50～150 dusts) on silicon chip, and described silicide carried out alloying, and the cross-section structure of final formed nmos pass transistor is shown in Fig. 4 e, and its planar structure is then as shown in Figure 5.

Certainly; the method of manufacturing high voltage PMOS transistor of the present invention is not limited in the foregoing description; as long as follow following basic principle: promptly realize the drift region with lightly doped LDD zone; persons skilled in the art should realize other alternatives, and can't exceed claimed scope of the present invention.

Claims

1, a kind of ESD gate grounding NMOS transistor manufacture method is characterized in that, comprising:

Form the operation of grid;

Form the operation of side wall in described grid both sides;

According to the described ESD gate grounding NMOS transistor of claim 1 manufacture method, it is characterized in that 2, the dosage range that injects ion in the operation in described formation LDD zone is E13～E14cm ^-2

3, according to claim 1 or 2 described ESD gate grounding NMOS transistor manufacture methods, it is characterized in that, silicon chip is carried out the N+ source leak the operation that ion injects described, inject ion dosage range be 2E15～5E15cm ^-2