CN101770985B - Forming method for MOS device for ESD protection - Google Patents

Forming method for MOS device for ESD protection Download PDF

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CN101770985B
CN101770985B CN 200910247747 CN200910247747A CN101770985B CN 101770985 B CN101770985 B CN 101770985B CN 200910247747 CN200910247747 CN 200910247747 CN 200910247747 A CN200910247747 A CN 200910247747A CN 101770985 B CN101770985 B CN 101770985B
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device
mos
mos device
esd protection
source
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CN 200910247747
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CN101770985A (en )
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俞柳江
王全
曹永峰
周伟
顾学强
肖慧敏
陈立山
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上海集成电路研发中心有限公司
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Abstract

本发明公开了一种用于ESD防护的MOS器件的形成方法,通过与该MOS器件类型相反的另一MOS器件的源/漏区的离子注入工艺,对形成该MOS器件的镇流电阻的区域进行反向注入,从而最终降低该区域的离子注入浓度,进而在不增加工艺步骤的基础上增加了该MOS器件的镇流电阻的阻值。 The present invention discloses a method of forming a MOS device for ESD protection, by an ion implantation process of the source / drain regions of the MOS device opposite to the other type MOS device, ballast resistance region of the MOS device is formed reverse injection, thereby reducing the final concentration of the ion implantation region, and further increased without increasing the resistance of the ballast resistor MOS device on the basis of process steps. 另外,由于镇流电阻的阻值增大,在需要相同ESD防护性能的MOS器件时,可以减小其漏区与栅极之间的间隔,从而减小MOS器件的尺寸,降低成本。 Further, due to the resistance of the ballast resistance is increased, the same device need MOS ESD protection performance, it is possible to reduce the interval between the drain region and the gate, thereby reducing the size of MOS devices, cost reduction.

Description

用于ESD防护的MOS器件的形成方法 A method for forming an ESD protection MOS device

技术领域 FIELD

[0001] 本发明涉及硅半导体器件技术领域,特别涉及一种用于ESD防护的MOS器件的形成方法。 [0001] The present invention relates to the field of semiconductor silicon devices, and more particularly to a method of forming a MOS device for ESD protection.

背景技术 Background technique

[0002] 在制造工艺和最终系统应用过程中,集成电路可能出现静电放电(Electrostatics Discharge,ESD)现象。 [0002] In the manufacturing process and the final system application process, the integrated circuit electrostatic discharge (Electrostatics Discharge, ESD) phenomenon may occur. ESD现象通常引起高电压电位的放电(一般几千伏)而导致短期(一般100ns)的高电流(几安培)脉冲,这会破坏在当前集成电路中存在的脆弱器件,造成系统的功能失效。 ESD discharge phenomenon usually caused a high voltage potential (typically several kilovolts) and leads to short-term (typically 100ns) high current (several amperes) pulses, which will destroy the fragile integrated circuit device is present in the current, resulting in failure of function of the system. 因而,对集成电路来说ESD防护是必不可少的。 Thus, the integrated circuit for ESD protection is a must.

[0003] MOS器件是一种重要的ESD防护器件,被广泛地用于集成电路I/O 口的ESD防护。 [0003] MOS device is an important ESD protection devices, ESD protection is widely used in integrated circuit I / O port. 当MOS器件用于ESD防护时,利用的是MOS器件的雪崩击穿特性,需要将栅极、源极以及衬底接地,同时漏极和I/O 口接同一电平。 When the ESD protection for MOS devices by using the avalanche breakdown characteristics of MOS devices, it is necessary to gate, source and substrate grounded, while the drain and I / O port access the same level. 当MOS器件的外加偏压在一定值(触发电压)以下时,漏电流很小。 When the applied bias voltage of the MOS device to a constant value (the trigger voltage) or less, the leakage current is very small. 而当外加偏压超过这个值后,MOS器件由于雪崩击穿导通放大电流,同时MOS器件两端电压会回滞到某个电压值(维持电压),由此能够保护集成电路I/O 口抵御静电冲击。 When the applied bias voltage exceeds this value, the avalanche breakdown of the MOS device since the amplified current conduction while the voltage across the MOS device will return to a hysteresis voltage value (sustain voltage), it is possible to protect the integrated circuit I / O port against static shock.

[0004] 镇流是一种提高MOS器件的ESD防护作用的方法,其主要通过对MOS器件的漏端增加镇流电阻来避免电流集聚(微观镇流)和改进多点出点(宏观镇流)。 [0004] The ballast is an effect to improve the ESD protection MOS device process, mainly by increasing the drain terminal of the MOS device to avoid ballast resistance current crowding (micro ballast) and improved multi-point (macro-ballasted ). 形成镇流电阻的最常用方法是通过硅化物掩膜层在漏区与栅极之间形成一层非硅化物电阻。 The most common method of forming the ballast resistance layer is formed in a non-silicide resistance between the drain region and the gate by the silicide mask layer. 图1显示了形成有镇流电阻的NMOS器件的剖面图,其中,在源区12、漏区13以及栅极11上形成有硅化物15,而在漏区13与栅极11之间的一部分区域没有形成硅化物,这便形成了镇流电阻14。 Figure 1 shows a cross-sectional view is formed with a ballast resistance of the NMOS device, wherein 12, the drain region 13 and a gate 11 is formed on the source region has a silicide 15, and a portion between the drain region 13 and the gate 11 silicide region is not formed, which will form the ballast resistor 14.

[0005] 镇流电阻的阻值大小与MOS器件的源/漏区的离子注入浓度和深度有着密切的关系。 [0005] The size of the resistance of the MOS devices resistor town source / drain ion implantation concentration and depth are closely related. NMOS器件和PMOS器件通常在同一衬底上一起形成,图2和图3分别显示了现有工艺中用于ESD防护的NMOS器件和PMOS器件的源/漏区的离子注入过程。 NMOS and PMOS devices are typically formed on the same substrate together, Figures 2 and 3 show a conventional ion implantation process for ESD protection NMOS and PMOS devices of the source / drain regions. 其中,NMOS器件和PMOS器件的源/漏区的离子注入工艺的顺序由工艺本身决定。 Wherein the ion source / drain regions of the NMOS and PMOS devices of sequential injection process is determined by the process itself. 在图2中,对NMOS器件进行源/漏区的N+注入工艺时,PMOS器件完全被光阻I覆盖,所以PMOS器件的源/漏区不会被N+注入。 In FIG. 2, N of the NMOS devices for the source / drain region implantation process time +, PMOS devices are completely covered with resist I, the source / drain regions of the PMOS device is not N + implantation. 同样,在图3中,对PMOS器件进行源/漏区的P+注入工艺时,NMOS器件也是完全被光阻I覆盖,NMOS器件的源/漏区也不会被P+注入。 Similarly, in FIG. 3, the source of the PMOS device of the P / drain regions of the + implantation process, the NMOS device is completely covered by the photoresist I, the source / drain regions of the NMOS device will not be a P + implantation. 然而,由此,镇流电阻的阻值大小完全由MOS器件的源/漏区的离子注入浓度和深度决定,这使得镇流电阻的阻值无法得到进一步的增加。 However, thereby, the size of the resistance of resistor town completely injected ion concentration and depth is determined by the source / drain regions of the MOS device, which makes the resistance of the ballast resistance can not be further increased.

发明内容 SUMMARY

[0006] 本发明的目的在于提供一种用于ESD防护的MOS器件的形成方法,在不增加工艺步骤的基础上增加MOS器件的镇流电阻的阻值。 [0006] The object of the present invention is to provide a method for forming an ESD protection MOS device for increasing the resistance of the ballast resistance of the MOS device without increasing the process steps.

[0007] 本发明提供一种用于ESD防护的MOS器件的形成方法,所述MOS器件和与其类型相反的另一MOS器件在同一衬底上形成,所述MOS器件在其漏区与栅极之间形成有第一镇流电阻,且所述MOS器件的源/漏区的离子注入浓度和深度均大于所述另一MOS器件,其中,对所述另一MOS器件进行源/漏区的离子注入工艺时,用光阻覆盖所述MOS器件并通过曝光露出所述第一镇流电阻,以同时对形成所述第一镇流电阻的区域进行离子注入。 [0007] The present invention provides a method of forming a MOS device for ESD protection, the MOS device and opposite thereto a further type MOS device is formed on the same substrate, the MOS device with a gate at the drain region is formed between a first ballast resistor, and the ion source / drain regions of the MOS device and implant concentration greater than the depth of said further MOS device, wherein the device further MOS source / drain regions when the ion implantation process a resist covering the MOS device is exposed by the exposure of the first ballast resistor to the first region is formed simultaneously ballast resistor is ion implantation.

[0008] 优选的,对所述MOS器件进行源/漏区的离子注入工艺时,用光阻完全覆盖住所述另一MOS器件。 [0008] Preferably, the MOS device is an ion source / drain regions during the injection process, with the photoresist completely covers the MOS device further.

[0009] 优选的,所述另一MOS器件在其漏区与栅极之间形成有第二镇流电阻。 [0009] Preferably, the other MOS devices between the drain region and the gate electrode is formed with a second ballast resistor.

[0010] 优选的,所述MOS器件为NMOS器件,而所述另一MOS器件为PMOS器件。 [0010] Preferably, the MOS device is an NMOS device, while the other MOS device is a PMOS device.

[0011] 优选的,所述NMOS器件的源/漏区的离子注入工艺为N+注入工艺,所述PMOS器件的源/漏区的离子注入工艺为P+注入工艺。 [0011] Preferably, the ion source / drain regions of the NMOS device N + implantation process is implantation process, the ion source / drain regions of the PMOS device implantation process of P + implantation process.

[0012] 与现有技术相比,本发明提供的一种用于ESD防护的MOS器件的形成方法,通过与该MOS器件类型相反的另一MOS器件的源/漏区的离子注入工艺,对形成该MOS器件的镇流电阻的区域进行反向注入,从而最终降低该区域的离子注入浓度,进而在不增加工艺步骤的基础上增加了该MOS器件的镇流电阻的阻值。 [0012] Compared with the prior art, the present invention provides a method of forming a MOS device for ESD protection, by an ion implantation process with the opposite type of MOS device to another device MOS source / drain regions of town forming the MOS device reverse flow region of the injection resistance, thereby reducing the final concentration of the ion implantation region, and further increased without increasing the resistance of the ballast resistor MOS device on the basis of process steps. 另外,由于镇流电阻的阻值增大,在需要相同ESD防护性能的MOS器件时,可以减小其漏区与栅极之间的间隔,从而减小MOS器件的尺寸,降低成本。 Further, due to the resistance of the ballast resistance is increased, the same device need MOS ESD protection performance, it is possible to reduce the interval between the drain region and the gate, thereby reducing the size of MOS devices, cost reduction.

附图说明 BRIEF DESCRIPTION

[0013] 图1显示了形成有镇流电阻的NMOS器件的剖面图; [0013] Figure 1 shows a cross-sectional view is formed with a ballast resistance of NMOS device;

[0014] 图2和图3分别显示了现有工艺中用于ESD防护的NMOS器件和PMOS器件的源/漏区的离子注入过程; [0014] Figures 2 and 3 show the prior art ion ESD protection for the NMOS and PMOS devices of a source / drain region implantation process;

[0015] 图4和图5分别显示了根据本发明的方法中用于ESD防护的NMOS器件和PMOS器件的源/漏区的离子注入过程。 [0015] Figures 4 and 5 show the implanted ion source / drain regions of the NMOS and PMOS devices of the present invention a method for ESD protection process.

具体实施方式 detailed description

[0016] 为使本发明的目的、特征更明显易懂,下面结合附图对本发明的具体实施方式作进一步的说明。 [0016] For purposes of the present invention, features more fully understood in conjunction with the following drawings of specific embodiments of the present invention will be further described.

[0017] 本发明的核心思想在于,通过与该MOS器件类型相反的另一MOS器件的源/漏区的离子注入工艺,对形成该MOS器件的镇流电阻的区域进行反向注入。 [0017] The core idea of ​​the present invention, by an ion implantation process of the source / drain regions of the MOS device opposite to the other type MOS device, the MOS device is formed of town that the flow resistance of the reverse injection.

[0018] 在本发明中,用于ESD防护的MOS器件和与其类型相反的另一MOS器件在同一衬底上形成。 [0018] In the present invention, for the reverse ESD protection MOS device and its other type MOS device is formed on the same substrate. 具体地,所述MOS器件可以为NMOS器件,而所述另一MOS器件为PMOS器件。 In particular, the MOS device may be an NMOS device, while the other MOS device is a PMOS device. 请综合参阅图4和图5,图4和图5分别显示了根据本发明的方法中用于ESD防护的NMOS器件和PMOS器件的源/漏区的离子注入过程。 Please refer to FIG. 4 and FIG. Comprehensive 5, Figures 4 and 5 show the implanted ion source / drain regions of the NMOS and PMOS devices ESD protection method of the present invention a process. 在图4和图5中,NMOS器件20在其漏区与栅极之间形成有第一镇流电阻24,而PMOS器件30在其漏区与栅极之间也可以形成有第二镇流电阻34。 4 and 5, the NMOS device 20 is formed with a first ballast resistor 24 between the drain region and the gate, and the PMOS device 30 between the drain region and the gate may be formed with a second ballast resistor 34. NMOS器件20的源/漏区的离子注入工艺为N+注入工艺,PMOS器件30的源/漏区的离子注入工艺为P+注入工艺。 The ion source / drain regions of the NMOS device 20 for the N + implantation process implantation process, the ion source / drain regions of the PMOS device 30 for the P + implantation process implantation process. 而且,NMOS器件20的源/漏区的N+注入浓度和深度均大于PMOS器件30的源/漏区的P+注入浓度和深度。 Further, the source / drain regions of the NMOS device 20 and an N + implant concentration greater than the depth P of the source / drain regions of the PMOS device 30 and the depth of implant concentration +. 例如,在本实施例中,采用了 For example, in the present embodiment, using

0.13um工艺。 0.13um process. 对NMOS器件20的源/漏区注入砷离子,能量为40KeV,深度约为0.027um,注入剂量为6*1015/cm2,在后续退火工艺之后,被激活的载流子(砷)的浓度约为5.8*1019/cm3。 Injection of the source / drain regions of the NMOS device 20 arsenic ions with an energy of 40 KeV, a depth of about 0.027um, an implantation dose of 6 * 1015 / cm2, after the subsequent annealing process, the concentration of the activated carrier (arsenic) about to 5.8 * 1019 / cm3. 对PMOS器件30的源/漏区注入硼离子,能量为5KeV,深度约为0.017um,注入剂量为 Injection of the source / drain region of the PMOS device 30 boron ions, 5KeV energy, a depth of about 0.017um, an implantation dose of

2.5*1015/cm2,在后续退火工艺之后,被激活的载流子(硼)的浓度约为1.8*1019/cm3。 2.5 * 1015 / cm2, after the subsequent annealing process, the concentration of the activated carrier (B) is about 1.8 * 1019 / cm3. 由此,砷离子的分布完全覆盖了硼离子的分布,砷离子在局部的浓度均要比硼离子高。 Thus, the distribution of arsenic ions completely covers the distribution of boron ions, arsenic ions in a concentration of boron ions are locally higher than that.

[0019] 下面,具体描述NMOS器件20和PMOS器件30的源/漏区的离子注入过程。 [0019] The following detailed description of the ion source / drain regions 20 of the NMOS and PMOS devices 30 of device implantation process. 其中,对PMOS器件30进行源/漏区的离子注入工艺时,用光阻覆盖NMOS器件20并通过曝光露出第一镇流电阻24,以同时对形成第一镇流电阻24的区域进行离子注入。 Wherein the PMOS device 30 of the ion source / drain regions during the injection process, the resist 20 covers the NMOS device is exposed by an exposure and a first ballast resistor 24, to simultaneously form a first ballast resistor region 24 by ion implantation . 需要注意的是,NMOS器件20和PMOS器件30的源/漏区的离子注入工艺的顺序不影响本方法的实施。 Note that the ion source / drain regions of the NMOS device 20 and PMOS device 30 of the sequential injection process does not affect the method of the present embodiment. 例如,可以先对NMOS器件20进行源/漏区的N+注入工艺,此时用光阻完全覆盖住PMOS器件30,如图4所示,因此PMOS器件30的源/漏区不会被N+注入。 For example, for an NMOS device 20 first N source / drain regions + implantation process, this time with a photoresist 30 completely covers the PMOS device shown in Figure 4, the PMOS device the source / drain regions 30 of N + implantation is not . 之后,如图5所示,在NMOS器件20上涂覆光阻并通过曝光露出第一镇流电阻24,然后同时对PMOS器件30的源/漏区和形成第一镇流电阻24的区域进行P+注入工艺。 Thereafter, as shown in FIG. 5, a photoresist 20 is coated on the NMOS device is exposed by an exposure and a first ballast resistor 24, and while the region of the first ballast resistor 24 to the source / drain regions 30 and PMOS devices are formed P + implantation process. 由此,在对PMOS器件30进行源/漏区的P+注入工艺的同时,实现对形成第一镇流电阻24的区域的P+注入,这相当于进行反向注入,会中和掉该区域中的一部分N+离子,从而最终降低该区域的离子注入浓度,进而在不增加工艺步骤的基础上增加第一镇流电阻24的阻值。 Thus, the P of the PMOS device 30 source / drain region implantation process + Also, to achieve the formation of a first region of the ballast resistor 24 to the P + implantation, which is equivalent to the reverse injection will be in and out of the region portion of N + ions, thereby reducing the final concentration of the ion implantation region, thereby increasing the resistance value without increasing a first ballast resistor 24 on the basis of the process steps. 此外,也可以先对PMOS器件30的源/漏区和形成第一镇流电阻24的区域进行P+注入工艺,然后对NMOS器件20进行源/漏区的N+注入工艺。 It is also possible for the first source / drain regions 30 and PMOS devices forming a first N region ballast resistor 24 is P + implantation process, the NMOS device 20 and then a source / drain region implantation process +.

[0020] 当然,在本发明的其它实施例中,所述MOS器件可以为PMOS器件,而所述另一MOS器件为NMOS器件,原理与上述实施例类似。 [0020] Of course, in other embodiments of the present invention, the MOS device may be a PMOS device, while the other MOS device is an NMOS device, the principles of the above-mentioned embodiment.

[0021] 此外,由于镇流电阻的阻值增大,在需要相同ESD防护性能的MOS器件时,可以减小其漏区与栅极之间的间隔,从而减小MOS器件的尺寸,降低成本。 When [0021] Further, since the resistance of the ballast resistance is increased, the same device need MOS ESD protection performance, it is possible to reduce the interval between the drain region and the gate, thereby reducing the size of MOS devices, cost reduction .

[0022] 综上所述,本发明提供的一种用于ESD防护的MOS器件的形成方法,在对该MOS器件进行源/漏区的离子注入工艺之后,通过与该MOS器件类型相反的另一MOS器件的源/漏区的离子注入工艺,对形成该MOS器件的镇流电阻的区域进行反向注入,中和掉该区域中的一部分原有离子,从而降低了该区域的离子注入浓度,进而在不增加工艺步骤的基础上增加了该MOS器件的镇流电阻的阻值。 The method of forming [0022] In summary, the present invention provides a MOS device for ESD protection, an ion implantation process after a source / drain region of the MOS device, the MOS device by another type opposite the ion source / drain regions of a MOS device implantation process for forming the ballast resistance region of the MOS device is reverse injection, a portion of these ions in and out of the region, thereby reducing the concentration of ions in the implanted region and further without increasing the process steps to increase the resistance of the ballast resistor MOS device. 另外,由于镇流电阻的阻值增大,在需要相同ESD防护性能的MOS器件时,可以减小其漏区与栅极之间的间隔,从而减小MOS器件的尺寸,降低成本。 Further, due to the resistance of the ballast resistance is increased, the same device need MOS ESD protection performance, it is possible to reduce the interval between the drain region and the gate, thereby reducing the size of MOS devices, cost reduction.

[0023] 显然,本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。 [0023] Obviously, those skilled in the art can make various modifications and variations to the invention without departing from the spirit and scope of the invention. 这样,倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内,则本发明也意图包含这些改动和变型在内。 Thus, if these modifications and variations of the present invention fall within the claims of the invention and the scope of equivalents thereof, the present invention intends to include these modifications and variations.

Claims (4)

  1. 1.一种用于ESD防护的MOS器件的形成方法,所述MOS器件和与其类型相反的另一MOS器件在同一衬底上形成,所述MOS器件在其漏区与栅极之间形成有第一镇流电阻,且所述MOS器件的源/漏区的离子注入浓度和深度均大于所述另一MOS器件,其特征在于,对所述另一MOS器件进行源/漏区的离子注入工艺时,用光阻覆盖所述MOS器件并通过曝光露出所述第一镇流电阻,以同时对形成所述第一镇流电阻的区域进行离子注入;其中,对所述MOS器件进行源/漏区的离子注入工艺时,用光阻完全覆盖住所述另一MOS器件。 1. A method of forming a MOS ESD protection device for the opposite type of MOS device and its other MOS devices formed on the same substrate, the MOS device is formed between the drain region and the gate has a first ballast resistor, and the ion source / drain regions of the MOS device and a depth of implant concentration greater than the other MOS devices, wherein the MOS device further ion source / drain implantation when the process of the MOS device covered with photoresist and exposed through the first ballast resistor is exposed, while the regions to form the first resistor town of ion implantation; wherein the MOS device is a source / drain region ion implantation process while using the photoresist completely covers the MOS device further.
  2. 2.如权利要求1所述的用于ESD防护的MOS器件的形成方法,其特征在于,所述另一MOS器件在其漏区与栅极之间形成有第二镇流电阻。 2. The method for forming a MOS device. 1 for ESD protection of claim, wherein the MOS device further formed with a second ballast resistor between the drain region and the gate.
  3. 3.如权利要求1所述的用于ESD防护的MOS器件的形成方法,其特征在于,所述MOS器件为NMOS器件,而所述另一MOS器件为PMOS器件。 A method as claimed in claim a MOS ESD protection device for the 1, wherein the MOS device is an NMOS device, while the other MOS device is a PMOS device.
  4. 4.如权利要求3所述的用于ESD防护的MOS器件的形成方法,其特征在于,所述NMOS器件的源/漏区的离子注入工艺为N+注入工艺,所述PMOS器件的源/漏区的离子注入工艺为P+注入工艺。 4. The method of forming the 3 MOS ESD protection device according to claim, wherein said ion NMOS source / drain region of the device for the N + implantation process implantation process, the source / drain of the PMOS device ion implantation region for the P + implantation process technology.
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Citations (3)

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Publication number Priority date Publication date Assignee Title
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6222236B1 (en) * 1999-04-30 2001-04-24 Motorola, Inc. Protection circuit and method for protecting a semiconductor device
CN101452851A (en) * 2007-12-06 2009-06-10 上海华虹Nec电子有限公司 Manufacturing method for ESD gate grounding NMOS transistor

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5920774A (en) * 1998-02-17 1999-07-06 Texas Instruments - Acer Incorporate Method to fabricate short-channel MOSFETS with an improvement in ESD resistance
US6222236B1 (en) * 1999-04-30 2001-04-24 Motorola, Inc. Protection circuit and method for protecting a semiconductor device
CN101452851A (en) * 2007-12-06 2009-06-10 上海华虹Nec电子有限公司 Manufacturing method for ESD gate grounding NMOS transistor

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