CN101807599B - Semiconductor device and method of manufacturing the same - Google Patents
Semiconductor device and method of manufacturing the same Download PDFInfo
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- CN101807599B CN101807599B CN201010121457XA CN201010121457A CN101807599B CN 101807599 B CN101807599 B CN 101807599B CN 201010121457X A CN201010121457X A CN 201010121457XA CN 201010121457 A CN201010121457 A CN 201010121457A CN 101807599 B CN101807599 B CN 101807599B
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- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
In the semiconductor device according to the present invention, a P type diffusion layer and an N type diffusion layer as a drain lead region are formed on an N type diffusion layer as a drain region. The P type diffusion layer is disposed between a source region and the drain region of the MOS transistor. When a positive ESD surge is applied to a drain electrode, causing an on-current of a parasite transistor to flow, this structure allows the on-current of the parasite transistor to take a path flowing through a deep portion of an epitaxial layer. Thus, the heat breakdown of the MOS transistor is prevented.
Description
Technical field
The present invention relates to a kind of preventing because of the overvoltage of static discharge (Electrostatic Discharge below is called ESD) etc. and the semiconductor device and the manufacturing approach thereof that are damaged.
Background technology
As an embodiment of existing semiconductor devices, the known structure that following MOS (metal-oxide semiconductor (MOS)) transistor 31 is arranged.
As shown in Figure 8, on P type semiconductor substrate 32, be formed with N type epitaxial loayer 33.Be formed with p type diffused layer 34,35 at epitaxial loayer 33 as back gate region.Be formed with n type diffused layer 36 at p type diffused layer 34 as the source region.And, be formed with n type diffused layer 37,38 at epitaxial loayer 33 as the drain region.On epitaxial loayer 33, be formed with grid oxidation film 39, gate electrode 40 and dielectric film 41 (for example, with reference to patent documentation 1).
Patent documentation 1: (Japan) spy opens 2003-303961 communique (3-4 page or leaf, 1-2 figure)
In MOS transistor 31, be provided with the parasitic transistor Tr2 that constitutes by n type diffused layer 37,38 (comprising epitaxial loayer 33), p type diffused layer 34,35 and n type diffused layer 36 (below be called parasitic Tr2).And the drain electrode 42 as if to MOS transistor 31 for example applies positive ESD surge, then shown in dotted line, generates the conducting electric current I 2 of parasitic Tr2, and parasitic Tr2 carries out turn-on action.At this moment, because the conducting electric current I 2 of the parasitic Tr2 of electrode 42 side flow that drain certainly flows in little epitaxial loayer 33 face side of resistance value, therefore, in the zone shown in the circle 43, the conducting electric current I 2 of parasitic Tr2 is assembled.And, because on epitaxial loayer 33, dispose thermal conductivity than the grid oxidation film 39 of silicon difference, dielectric film 41 etc., therefore, the face side of epitaxial loayer 33 becomes the zone of poor radiation.Consequently, in the zone shown in the arrow 43,, cause producing the problem that epitaxial loayer 33 face side receive heat damage according to the heat that the conducting electric current I 2 because of parasitic Tr2 produces.For example, become the structure of 1000 μ m and carry out electrostatic breakdown when experiment at grid length (W), for the conducting electric current I 2 (break current) of parasitic Tr2 with respect to MOS transistor 31; Below 1A, produce above-mentioned heat damage; For machine mould (MM), become the ESD tolerance below the 200V, for manikin (HBM); Becoming the ESD tolerance below the 1000V, is not the structure that can realize desirable ESD tolerance.
Summary of the invention
The present invention makes in view of above-mentioned each situation; In semiconductor device of the present invention; It is characterized in that; Have: a conductive-type semiconductor layer, a conductivity type drain diffusion layer that is formed at said semiconductor layer, the opposite conductivity type back of the body grid diffusion layer that is formed at said semiconductor layer and a conductivity type source electrode diffusion layer that forms overlappingly with said back of the body grid diffusion layer; Be formed with the opposite conductivity type diffusion layer overlappingly in said drain diffusion layer, said opposite conductivity type diffusion layer is compared the contact area to said drain diffusion layer contact at least, more to said back of the body grid diffusion layer side configuration.Therefore, in the present invention, the conducting electric current of avoiding parasitic Tr flows at semiconductor surface, and prevents the heat damage that the conducting electric current because of parasitic Tr causes.
In addition; In the manufacturing approach of semiconductor device of the present invention; Form a conductivity type drain diffusion layer, opposite conductivity type back of the body grid diffusion layer, a conductivity type source electrode diffusion layer at semiconductor layer; On said semiconductor layer, form gate electrode, at the sidewall formation insulating cell film of said gate electrode, the manufacturing approach of this semiconductor device is characterised in that; Said gate electrode is used as the part of mask and forms after the opposite conductivity type diffusion layer with the mode with said drain diffusion ply, form the insulating cell film at the sidewall of said gate electrode.Therefore, in the present invention, positional precision highland configuration prevents the diffusion layer of the heat damage that the conducting electric current because of parasitic Tr causes in drain diffusion layer.
In the present invention, through in the drain region, forming PN junction, the current path of the conducting electric current of parasitic Tr is in semiconductor layer deep side.According to this structure, heat dissipation region enlarges, and prevents that element from receiving heat damage.
In addition, in the present invention,,, prevent to cause element to be destroyed because of the conducting electric current of parasitic Tr so current capacity improves because parasitic transistor moves in element.
In addition, in the present invention, through gate electrode and insulating cell film are used as the part of mask respectively, thereby can form the diffusion layer of protection usefulness on drain diffusion layer positional precision highland.
Description of drawings
Fig. 1 (A), (B) are the profiles that is used to explain the semiconductor device of execution mode of the present invention;
Fig. 2 (A), (B) are used to explain that (A) of execution mode of the present invention reaches the figure of the characteristic of semiconductor device (B);
Fig. 3 (A), (B) are the circuit diagrams that is used to explain (A) of execution mode of the present invention and semiconductor device (B);
Fig. 4 is the profile of manufacturing approach that is used to explain the semiconductor device of execution mode of the present invention;
Fig. 5 is the profile of manufacturing approach that is used to explain the semiconductor device of execution mode of the present invention;
Fig. 6 is the profile of manufacturing approach that is used to explain the semiconductor device of execution mode of the present invention;
Fig. 7 is the profile of manufacturing approach that is used to explain the semiconductor device of execution mode of the present invention;
Fig. 8 is the profile that is used to explain the semiconductor device of existing execution mode.
Description of reference numerals
1 N channel type MOS transistor
2 p type single crystal silicon substrates
3 epitaxial loayers
10 n type diffused layers
14 p type diffused layers
15 PN junctions zone
Embodiment
Below, specify the semiconductor device of first execution mode of the present invention with reference to Fig. 1～Fig. 3.Fig. 1 (A) and (B) be the profile that is used to explain the MOS transistor of this execution mode.Fig. 2 (A) and (B) be the figure of ESD tolerance that is used to explain the MOS transistor of this execution mode.Fig. 3 (A) and (B) be the figure that utilizes form that is used to explain the MOS transistor of this execution mode.
Shown in Fig. 1 (A), N channel type MOS transistor (below be called N-MOS) 1 has the superpotential protection structure of reply ESD etc. at its element internal.As shown in the figure, on p type single crystal silicon substrate 2, form N type epitaxial loayer 3.In addition, in this execution mode,, be not limited to this situation though illustrate the situation that on substrate 2, forms one deck epitaxial loayer 3.For example, also can be the situation of range upon range of multilayer epitaxial layer on substrate.In addition, epitaxial loayer 3 utilizes separated region 4 to be divided into a plurality of element-forming region.And separated region 4 is made up of P type embedding layer 4A and p type diffused layer 4B.Diffusion layer 4B from the epitaxial layer 3, the surface of a diffusion depth (down crawl amplitude (which Kei the bittern width)) than the buried layer 4A from the substrate second surface a diffusion depth (up crawl amplitude (which Kei the bittern width)) shallow, whereby , the separation zone 4 can be formed narrower region.
N type embedding layer 5 is across being formed on substrate 2 and epitaxial loayer 3 these two zones.And p type diffused layer 6 is formed at epitaxial loayer 3 and as the back gate region of N-MOS 1 and use.In addition, be formed with p type diffused layer 7 overlappingly at p type diffused layer 6, this p type diffused layer 7 is derived the zone as the back of the body grid of N-MOS1 and is used.
N type diffused layer 8 is formed at p type diffused layer 6, and as the source region of N-MOS1 and use.And n type diffused layer 9 is formed at epitaxial loayer 3 and as the drain region of N-MOS1 and use.In addition, be formed with n type diffused layer 10 overlappingly at n type diffused layer 9, this n type diffused layer 10 is derived the zone as the drain electrode of N-MOS1 and is used.
P type diffused layer 14 is formed at the n type diffused layer 9,10 as the drain region overlappingly.P type diffused layer 14 and is compared contact hole 26 (with reference to Fig. 7) and more is positioned at p type diffused layer 6 sides as back gate region between source electrode-drain region of N-MOS1.P type diffused layer 14 for example is positioned at the end of gate electrode 11 and the below of insulating cell film 13, and is formed at the face side of n type diffused layer 9.And the impurity concentration of p type diffused layer 14 is compared n type diffused layer 9 becomes high concentration, and compares n type diffused layer 10 and become low concentration.In addition, p type diffused layer 14 is as drift diffusion layer and using, and with the drain electrode, the drain electrode wiring layer capacitive coupling that are disposed on the p type diffused layer 14.
Shown in Fig. 1 (B), shown in thick line, form the PN junction zone 15 that constitutes by n type diffused layer 10 and p type diffused layer 14 in the drain region of N-MOS 1.And for example, the impurity concentration of N type epitaxial loayer 3 is 1.0 * 10
15(/cm
2), the impurity concentration of p type diffused layer 6 is 1.0 * 10
17～1.0 * 10
18(/cm
2), the impurity concentration of p type diffused layer 14 is 1.0 * 10
17(/cm
2), the impurity concentration of n type diffused layer 10 is 1.0 * 10
20(/cm
2).According to this structure, the knot in PN junction zone 15 is withstand voltage, and is withstand voltage lower than the knot in the zone of the PN junction between source electrode-drain region of N-MOS1 16.And when the drain electrode to N-MOS1 for example applied positive overvoltage such as ESD surge, PN junction zone 15 punctured earlier than PN junction zone 16, constituted the structure that protection N-MOS1 does not receive over-voltage protection.
At this, in N-MOS 1, has parasitic transistor Tr1 (below be called parasitic Tr1).Particularly, parasitic Tr1 comprises: as the n type diffused layer 8 of emitter region, as the p type diffused layer 6,7 of base region, as the n type diffused layer 9,10 (comprising N type epitaxial loayer 3) of collector region.And; When the drain electrode 28 (with reference to Fig. 7) to N-MOS 1 applied positive ESD surge (overvoltage), PN junction zone 15 punctured, and the hole is injected to n type diffused layer 9, N type epitaxial loayer 3 at p type diffused layer 14; Shown in the arrow of dotted line, generate the conducting electric current I 1 of parasitic Tr1.Because the conducting electric current I 1 of this parasitism Tr1 flows into to p type diffused layer 6, therefore, the current potential of the base region of parasitic Tr1 rises, and parasitic Tr1 carries out turn-on action.Because parasitic Tr1 carries out turn-on action, therefore, in the collector region of above-mentioned parasitic Tr1, causes that conductivity is unusual, resistance value significantly reduces, and current capacity improves.
On the other hand, because the conducting electric current I 1 of the parasitic Tr1 of the big electric current of conduct is mobile, so also might cause N-MOS1 to receive heat damage.So in this execution mode, p type diffused layer 14 is disposed at the side of the n type diffused layer 10 between source electrode-drain region of N-MOS1.And the conducting electric current I 1 of parasitic Tr1 is via the bottom surface side of n type diffused layer 10, and side direction p type diffused layer 6 flows into from the deep of epitaxial loayer 3.According to this structure, shown in oval mark 17, because of configuration p type diffused layer 14, so the current path of the conducting electric current I 1 of parasitic Tr1 is avoided epitaxial loayer 3 face side of gate electrode 11 and insulating cell film 13 belows.Consequently, because the conducting electric current I 1 of parasitic Tr1 so the good heat dissipation region of thermal conductivity also increases, prevents that N-MOS1 from receiving heat damage in the deep side flow of the good epitaxial loayer 3 of thermal conductivity.
Particularly, when not disposing p type diffused layer 14, the zone shown in the oval mark 17 is the zone that the conducting electric current I 1 as the parasitic Tr1 of big electric current flows, and becomes the zone of the countermeasure that need take to tackle heat damage.Why be like this because, because that silicon (epitaxial loayer) is compared its thermal conductivity of insulating barrier (silicon oxide film etc.) is good, so in the face side of epitaxial loayer 3, because of silicon oxide film 12 grades cause the thermal diffusivity variation.That is, the side in the deep of epitaxial loayer 3, its entire circumference become the good epitaxial loayer of thermal conductivity 3, and become the face side of comparing epitaxial loayer 3 and the good zone of thermal diffusivity.
In addition, in N-MOS1, p type diffused layer 6 face side below gate electrode 11 form channel region, and the principal current of N-MOS1 flows in the face side of epitaxial loayer 3.And in the drain region, the principal current of N-MOS1 is walked around p type diffused layer 14, and flows into to drain electrode.But owing to around p type diffused layer 14, dispose n type diffused layer 9, so have bigger advantage, i.e. the increase of resistance value is also relaxed, and prevents the heat damage that the conducting electric current I 1 by parasitic Tr1 causes.In addition, though also there is the problem that electric field is concentrated in gate electrode 11 ends of side in the drain region,, relax so also can realize electric field owing to dispose n type diffused layer 9 as low concentration region.
Particularly, in Fig. 2 (A), solid line representes to have this execution mode of p type diffused layer 14, and dotted line representes not have the existing execution mode of p type diffused layer 14.In addition, for other component structures and experiment condition, this execution mode and existing homomorphosis.In addition, for the ease of explanation, use the structure shown in Fig. 1 (B) to describe.
In this execution mode, shown in solid line, for example,, generate break current through applying the electrostatic breakdown voltage about 9.0V.And electrostatic breakdown voltage is fixed on the scope about 9～10V, and break current generally perpendicularly rises.On the other hand, in existing form, shown in dotted line, for example, apply the voltage about 11V, thereby generate break current, and the burst after producing punctures (ス Na Star プ Star Network) phenomenon as electrostatic breakdown voltage.
In the N-MOS1 shown in the solid line, because of p type diffused layer 14 hinders the expansion from the depletion layer of PN junction zone 15 expansions, so electrostatic breakdown voltage (puncture voltage) reduces.And, in the N-MOS1 shown in the solid line,, do not make big electric current flow to the hole of this degree of parasitic Tr1 from p type diffused layer 14 so can not produce because of electrostatic breakdown voltage reduces.Consequently, continue to flow, need high voltage, will produce the rise phenomenon of above-mentioned break current thus in order to make break current (the conducting electric current I 1 of parasitic Tr1).On the other hand.In the structure shown in the dotted line, do not form PN junction zone 15, electrostatic breakdown voltage (puncture voltage) increases because of PN junction zone 16.And the break current of generation (the conducting electric current I 1 of parasitic Tr1) also becomes big electric current, because of this big electric current produces a large amount of holes.Consequently, the hole of generation flows into to p type diffused layer 6, and parasitic Tr1 carries out turn-on action, produces the burst punch-through.
Also can know according to this experimental result, in the N-MOS1 of this execution mode,, can utilize low-voltage to puncture PN junction zone 15 through forming p type diffused layer 14.Consequently, become following structure, that is, also can reduce the magnitude of current of the conducting electric current 11 of parasitic Tr1, and be difficult to produce the conducting electric current I 1 that is accompanied by parasitic Tr1 and the heat damage that causes.In addition, as after shown in Fig. 3 (B) of stating, can utilize the structure of N-MOS1 to constitute protection component.At this moment, the puncture voltage of protection component is for example fixing within the specific limits shown in the scope about 9～10V, thus, becomes easy with respect to the setting of the protection voltage of protected element.And, can protect protected element reliably and superpotential influence that do not receive ESD etc.
In addition, in Fig. 2 (B), with Fig. 2 (A) likewise, solid line representes to have this execution mode of p type diffused layer 14, dotted line representes not have the existing execution mode of p type diffused layer 14.In addition, for other component structures and experiment condition, this execution mode and existing homomorphosis.
In this execution mode, shown in solid line, before the electric current that flows between source electrode-drain region arrived 0.6A, component temperature also rose at leisure gently.Afterwards, rise to stage of 0.7A at drain current, the rising of component temperature becomes significantly, and reaches about 1300K.On the other hand, in existing form, shown in dotted line, before the electric current that flows between source electrode-drain region arrived 0.4A, component temperature also rose at leisure gently.Afterwards, rise to stage of 0.6A at drain current, component temperature sharply rises, and reaches about 1700K.
Also can know according to this experimental result, through forming p type diffused layer 14 and the deep side of epitaxial loayer 3 is made as current path, thereby become following structure, be i.e. the heat damage that improves and prevent easily to cause of thermal diffusivity in element because of electric current
In addition, in this execution mode, shown in Fig. 3 (A), in N-MOS1, have the PN junction zone 15 that overvoltage protection is used, for N-MOS1, constitute the structure that principal current flows usually between source electrode-drain region.And, though following structure is illustrated, promptly for example; When applying positive ESD surge to drain electrode; The conducting electric current I 1 of parasitic Tr1 from the electrode side that drains in the deep of epitaxial loayer 3 side direction source electrode side flow, thereby protection N-MOS1 but is not limited to this structure.For example, shown in Fig. 3 (B),, thereby also can be used as protection diode and using through gate electrode and the source electrode short circuit that makes N-MOS1.When constituting this structure, be connected with the protected element distribution through protecting diode, thereby can protect protected element and do not receive positive superpotential influences such as ESD surge.
In addition, though N-MOS 1 is described, for P channel type MOS transistor (below be called P-MOS), because of have the superpotential structure that influences that is not received ESD etc. by protection at its element internal, so also can obtain same effect.Particularly, in the drain region of P-MOS, also between source electrode-drain region, dispose n type diffused layer, and form the PN junction zone.According to this structure, the conducting electric current that can avoid parasitic Tr flows in the face side of epitaxial loayer, and protection P-MOS, makes the influence of its heat damage that does not receive to cause because of the conducting electric current of the parasitic Tr of electric current greatly.
In addition, on P type substrate 2, form N type epitaxial loayer 3, and on N type epitaxial loayer 3, form the situation of N-MOS1, but be not limited to this situation although understand.It for example also can be the situation that forms N-MOS1 with respect to the N type diffusion zone that forms at P type substrate 2.About P-MOS, too.In addition, in the scope that does not break away from main idea of the present invention, can carry out various changes.
Then, specify the manufacturing approach of the semiconductor device of second execution mode of the present invention with reference to Fig. 4～Fig. 7.Fig. 4～Fig. 7 is the profile of manufacturing approach that is used to explain the semiconductor device of this execution mode.In addition, in following explanation, for the inscape mark same Reference numeral identical with each inscape of utilizing N channel type MOS transistor shown in Figure 1 (below be called N-MOS1) to explain.
At first, as shown in Figure 4, prepare p type single crystal silicon substrate 2, on substrate 2, form N type epitaxial loayer 3.Then, at substrate 2 and epitaxial loayer 3, form the P type embedding layer 4A and the N type epitaxial loayer 5 that constitute separated region 4.In addition, form p type diffused layer 4B that constitutes separated region 4 and the p type diffused layer 6 that becomes the back gate region of N-MOS1 at epitaxial loayer 3.In addition, in the desirable zone of epitaxial loayer 3, form LOCOS (local oxidation of silicon) oxide-film 21.
Then, as shown in Figure 5, on epitaxial loayer 3, form after the silicon oxide film 12, use photoresist (not shown) from the surface of epitaxial loayer 3 with accelerating voltage 30～300 (keV), import volume 1.0 * 10
12～1.0 * 10
14(/cm
2) ion injects for example phosphorus (P) of N type impurity.Then, remove after the photoresist, heat-treat and form n type diffused layer 9.Next, on silicon oxide film 12, form polysilicon film,, form gate electrode 11 through removing selectively.Then, gate electrode 11 is used as a part of mask, and form the n type diffused layer 8 of the source region that constitutes N-MOS1.Afterwards, on silicon oxide film 12, form photoresist 22, on the photoresist on the zone that is formed with p type diffused layer 14 22, form peristome.Then, from the surface of epitaxial loayer 3 with accelerating voltage 30～100 (keV), import volume 1.0 * 10
13～1.0 * 10
15(/cm
2) ion injects for example boron (B) of p type impurity.At this moment, use gate electrode 11 to utilize self-aligned technology (Japanese: own integration technology) carry out ion and inject, thereby p type diffused layer 14 is formed with respect to gate electrode 11 positional precision highlands.In addition, p type diffused layer 14 and n type diffused layer 9 are overlapping and form, but p type diffused layer 14 is compared the extrinsic region that n type diffused layer 9 becomes high concentration, so that its overlapping region constitutes p type diffused layer 14.
Then, as shown in Figure 6, remove photoresist 22 (with reference to Fig. 5), after heat-treating, on epitaxial loayer 3, for example utilize the CVD method to pile up silicon oxide film.Then, through this silicon oxide film is carried out etching, thereby form insulating cell film 13 at the sidewall of gate electrode 11.Afterwards, on silicon oxide film 12, form photoresist 23, and on the photoresist on the zone that is formed with n type diffused layer 10 23, form peristome.Then, from the surface of epitaxial loayer 3 with accelerating voltage 30～200 (keV), import volume 1.0 * 10
15～1.0 * 10
17(/cm
2) ion injects for example arsenic (As) of N type impurity.At this moment, use insulating cell film 13 to utilize self-aligned technology to carry out ion and inject, thereby n type diffused layer 10 is formed with respect to insulating cell film 13 positional precision highlands.Utilizing this manufacturing approach, when drain electrode 28 (with reference to Fig. 7) is connected with n type diffused layer 10, can the distance between gate electrode 11 and the drain electrode 28 be made as the shortest spacing distance, and can dwindles the component size of N-MOS1.In addition, n type diffused layer 10 and p type diffused layer 14 are overlapping and form, but n type diffused layer 10 is compared the extrinsic region that p type diffused layer 14 becomes high concentration, so that its overlapping region constitutes n type diffused layer 10.
Utilize this manufacturing approach, when forming p type diffused layer 14 with n type diffused layer 10, need not consider that mask departs from amplitude, p type diffused layer 14 positional precision highlands are disposed at the below of gate electrode 11 and insulating cell film 13.Therefore, can not increase the component size of N-MOS1,, between source electrode-drain region, form the PN junction zone, thereby can obtain the effect of utilizing first execution mode to explain in the drain region of N-MOS1.
At last, as shown in Figure 7, after epitaxial loayer 3 forms p type diffused layer 7, on epitaxial loayer 3, form dielectric film 24.The for example range upon range of TEOS of having of dielectric film 24 (Tetra-Ethyl-Ortho-Silicate: film, BPSG (Boron Phospho Silicate Glass: film, SOG (Spin On Glass: be spun on glass) film etc. and constituting boron-phosphorosilicate glass) tetraethyl orthosilicate).And, form contact hole 25,26 at dielectric film 24, form source electrode 27, drain electrode 28 via contact hole 25,26.
In addition, in this execution mode, use gate electrode 11, insulating cell film 13 have been described, the positional precision highland forms the situation of n type diffused layer 10 and p type diffused layer 14, but is not limited to this.In the drain region of N-MOS1, current path between source electrode-drain region configuration p type diffused layer 14, and form PN junction zone 15 (with reference to Fig. 1 (A)) and get final product, its manufacturing approach can be carried out design alteration arbitrarily.In addition, in the scope that does not break away from main idea of the present invention, can carry out various changes.
Claims (7)
1. semiconductor device is characterized in that having:
One conductive-type semiconductor layer,
Be formed at said semiconductor layer a conductivity type drain diffusion layer,
Be formed at said semiconductor layer opposite conductivity type back of the body grid diffusion layer and
A conductivity type source electrode diffusion layer that forms overlappingly with said back of the body grid diffusion layer,
Be formed with the opposite conductivity type diffusion layer overlappingly in said drain diffusion layer, said opposite conductivity type diffusion layer is compared the contact area to said drain diffusion layer contact at least, more to said back of the body grid diffusion layer side configuration.
2. semiconductor device as claimed in claim 1; It is characterized in that, on first diffusion layer of the low concentration that constitutes said drain diffusion layer, be formed with second diffusion layer of the high concentration that constitutes said drain diffusion layer overlappingly; Said contact area is formed on second diffusion layer of said high concentration
Said opposite conductivity type diffusion layer is the area with high mercury of the first diffusion floor height of the said low concentration of concentration ratio, and compares second diffusion layer of said high concentration, more to said back of the body grid diffusion layer side configuration.
3. semiconductor device as claimed in claim 2 is characterized in that, second diffusion layer of said opposite conductivity type diffusion layer and said high concentration forms the PN junction zone.
4. like each described semiconductor device in the claim 1～3, it is characterized in that, on said semiconductor layer, be formed with gate electrode, be formed with the insulating cell film at the sidewall of said gate electrode,
Said opposite conductivity type diffusion layer is configured in the end that is positioned at the said gate electrode on the said drain diffusion layer and the below of said insulating cell film at least.
5. according to claim 1 or claim 2 semiconductor device is characterized in that a said conductive-type semiconductor layer is formed at the opposite conductivity type semiconductor substrate.
6. the manufacturing approach of a semiconductor device; Form a conductivity type drain diffusion layer, opposite conductivity type back of the body grid diffusion layer, a conductivity type source electrode diffusion layer at semiconductor layer; On said semiconductor layer, form gate electrode; Sidewall at said gate electrode forms the insulating cell film, and the manufacturing approach of this semiconductor device is characterised in that
Said gate electrode is used as the part of mask and forms after the opposite conductivity type diffusion layer with the mode with said drain diffusion ply, form the insulating cell film at the sidewall of said gate electrode.
7. the manufacturing approach of semiconductor device as claimed in claim 6; It is characterized in that; Form first diffusion layer of the low concentration that constitutes said drain diffusion layer at said semiconductor layer; On said semiconductor layer, form gate electrode, with said gate electrode as the part of mask and use and to form after the opposite conductivity type diffusion layer with the overlapping mode of first diffusion layer of said low concentration
Form the insulating cell film at the sidewall of said gate electrode, said insulating cell film is used as the part of mask and to form second diffusion layer of the high concentration that constitutes said drain diffusion layer with the overlapping mode of first diffusion layer of said low concentration.
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| JP2013008715A (en) * | 2011-06-22 | 2013-01-10 | Semiconductor Components Industries Llc | Semiconductor device |
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| US9236472B2 (en) | 2012-04-17 | 2016-01-12 | Freescale Semiconductor, Inc. | Semiconductor device with integrated breakdown protection |
| JP5978031B2 (en) * | 2012-07-03 | 2016-08-24 | 株式会社日立製作所 | Semiconductor device |
| DE112013006080T5 (en) * | 2012-12-19 | 2015-08-27 | Knowles Electronics, Llc | Apparatus and method for high voltage I / O electrostatic discharge protection |
| JP6656968B2 (en) * | 2016-03-18 | 2020-03-04 | エイブリック株式会社 | Semiconductor device having an ESD protection element |
| CN106847809B (en) * | 2017-02-23 | 2018-09-04 | 无锡新硅微电子有限公司 | The rectifier bridge structure integrated on piece |
| CN116387363B (en) * | 2023-05-08 | 2024-01-09 | 上海晶岳电子有限公司 | LDMOS (laterally diffused metal oxide semiconductor) process TVS (transient voltage suppressor) device and manufacturing method thereof |
| CN116525609B (en) * | 2023-05-15 | 2024-09-03 | 上海晶岳电子有限公司 | LDMOS process TVS device and method for manufacturing the same |
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| CN101807599A (en) | 2010-08-18 |
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