WO2012142804A1 - 非易失性电荷捕获型存储器件、其制备方法及应用 - Google Patents

非易失性电荷捕获型存储器件、其制备方法及应用 Download PDF

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WO2012142804A1
WO2012142804A1 PCT/CN2011/078223 CN2011078223W WO2012142804A1 WO 2012142804 A1 WO2012142804 A1 WO 2012142804A1 CN 2011078223 W CN2011078223 W CN 2011078223W WO 2012142804 A1 WO2012142804 A1 WO 2012142804A1
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layer
memory device
storage
type memory
charge trap
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French (fr)
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汤振杰
夏奕东
殷江
刘治国
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Nanjing University
Nanjing Tech University
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Nanjing University
Nanjing Tech University
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    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
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    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • C23C16/40—Oxides
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    • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
    • C23C28/04—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material
    • C23C28/042—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D only coatings of inorganic non-metallic material including a refractory ceramic layer, e.g. refractory metal oxides, ZrO2, rare earth oxides
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G11C16/0475—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] comprising two or more independent storage sites which store independent data
    • H—ELECTRICITY
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    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
    • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
    • H—ELECTRICITY
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    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures

Definitions

  • the present invention relates to a nonvolatile charge trap type memory device, a method of fabricating the same, and an application thereof.
  • Moore's Law which was predicted by Dr. Gordon E. Moore, one of the founders of Intel Corporation, in 1964: the number of components integrated on a single chip of an integrated circuit, that is, the integration of integrated circuits. Every 12 to
  • CMOS process gate dielectric layers have been widely studied as CMOS process gate dielectric layers, and pseudo-diode oxides are also a hot research topic.
  • the dielectric properties are improved by mixing two high dielectric constant materials. Based on this idea, it is possible to mix one of the two high dielectric constant materials with different crystallization temperatures to benefit the difference in crystallization temperature.
  • One of the materials is crystallized by high temperature annealing, and the other material remains non-ferrous. In the crystalline state, the crystallized nanocrystallites are surrounded by an amorphous matrix phase.
  • A1 2 0 3 has a high dielectric constant (9) and a wide forbidden band width (8.8 eV), so A1 2 0 3 is used as a tunneling layer and a barrier layer instead of the conventional device.
  • Si0 2 can reduce leakage current and improve device storage performance.
  • Zr0 2 has proven to have the potential to replace sio 2 as a gate dielectric material as a high dielectric constant material.
  • the crystallization temperature is relatively lower than the crystallization temperatures above sio 2 and AI 2 O 3 loocrc.
  • pulsed laser deposition PLD
  • ALD atomic layer chemical vapor deposition
  • the pulsed laser deposition method is a new type of thin film preparation technology developed in the late 1980s.
  • the basic principle is to use a UV pulsed laser that is focused and has a high energy flow density to illuminate the target, generate a laser plasma, and finally on the substrate.
  • the film is deposited on the film.
  • the biggest advantage is that the chemical composition of the membrane is close to the chemical composition of the target, so that it is easy to obtain a membrane with tightly controlled composition.
  • Atomic layer chemical vapor deposition is a challenging preparation technique in the field of high-fc material preparation.
  • the principle is to realize the layer by layer growth by the self-saturation of the gas phase source adsorbing or reacting on the surface of the substrate, and the thickness of the formed film does not depend on the substrate temperature, vapor pressure, source flow and other growth parameters in the working window. , only related to the number of cycles.
  • Atomic Layer Deposition Film Due to its unique self-limiting growth process, Atomic Layer Deposition Film has the advantages of precise thickness control, excellent three-dimensional conformability and large-area film formation uniformity, and has unique advantages in the preparation of ultra-thin films and nanostructures.
  • the present invention provides a method for fabricating a nonvolatile charge trap type memory device which is simple in operation and easy to control, and has a uniform distribution of nanocrystallites as a storage medium.
  • the present invention also provides a nonvolatile charge trap type memory device obtained by the above production method.
  • the present invention also provides the use of the above-described preparation method for a nonvolatile charge trap type memory device in an information storage and nonvolatile semiconductor memory device.
  • the method for preparing the nonvolatile charge trap type memory device includes the following steps:
  • the sample prepared above is annealed at a temperature lower than the melting point of M, and Zr0 2 nanocrystallites are precipitated from the storage layer and surrounded by an amorphous mother phase, and the ZrO 2 nanocrystallite is used as a storage medium.
  • the invention is based on the difference in crystallization temperature of the two substances in the mixture, and the supersaturated component in the mixture is crystallized by means of high temperature annealing treatment, that is, Zr0 2 nanocrystallites are precipitated from the mother layer of the storage layer, and are amorphous mother phase. Surrounded by, thereby achieving the effect of nanocrystal storage.
  • the nanocrystallites obtained as a storage medium by this method are uniformly distributed in the amorphous mother phase. Obviously, this would result in a composition of the final amorphous mother phase that is different from the memory layer film originally formed on the tunneling layer, but the overall composition of the memory layer does not change.
  • the annealing time should be limited.
  • the annealing time in step d) is 10 ⁇ 60s.
  • the annealing atmosphere is prior art, either an oxygen atmosphere or a nitrogen atmosphere. Those skilled in the art can select suitable annealing conditions according to the specific conditions.
  • the method of forming a ZrCK Mh- x film on the tunneling layer is preferably: (ZrC ⁇ MMh- x is used as a target, and is deposited by a pulsed laser deposition method on the tunneling layer (ZrCK M ⁇ x film. Pulsed laser deposition conditions) Preferably, the energy is 150-400 mJ, and the frequency is l ⁇ 10 Hz.
  • the preparation method of the ZrC ⁇ Mh- x target adopts the prior art, for example, the Zr0 2 and the SiO 2 (or Zr0 2 and A1 2 0 3 ) powders are uniformly mixed.
  • the tunneling layer and the barrier layer are both A1 2 0 3 , and further preferably, the tunneling layer, the storage layer and the barrier layer have thicknesses of 2 to 4 nm, 5 nm, and 7 to 12 nm, respectively.
  • the substrate is preferably Si.
  • the nonvolatile charge trap type memory device obtained by the above preparation method comprises a tunneling layer, a memory layer and a barrier layer which are sequentially connected, and the Zr0 2 nanocrystallite obtained by annealing treatment is used (ZrCK SiO ⁇ -x is a storage layer)
  • ZrCK SiO ⁇ -x is a storage layer
  • FIG. 2 The application of the above non-volatile charge trap type memory device in the information storage and non-volatile semiconductor memory device is as shown in FIG. 2:
  • the platinum electrode When the platinum electrode is applied with a positive voltage relative to the Si substrate, the electric field is directed from the upper electrode to the substrate. As the applied voltage increases, the electric field strength increases. The surface of the Si substrate reaches an inversion, forms a surface electron channel, and tunnels through the A1 2 0 3 tunneling layer under the electric field to enter the (ZrC ⁇ Mh- x memory layer, and then the electrons on the surface of the Zr0 2 nanocrystallite The trap state captures the effect of storage, which is the writing process of the nonvolatile charge trap type memory device.
  • FIG. 3 shows that when the scan voltage is ⁇ 1V, the memory window is 0.3V.
  • the scan voltage is ⁇ 5V and ⁇ 14V, there are already obvious hysteresis windows, which are 4.0V and 7.5V, respectively.
  • Figure 4 shows that the device after annealing has a large memory window compared to before annealing, indicating that Zr0 2 nanocrystallites play a crucial role in the memory performance of the device. Zr0 2 nanocrystallites increase the density of trap states in the film, allowing the device to have a high charge storage.
  • Figure 6 is: Anti-fatigue properties of Zr0 2 nm microcrystalline based nonvolatile charge trap type memory devices at different temperatures. As can be seen from the figure, as the temperature increases, the fatigue resistance of the device decreases slightly. At 15 CTC, the memory window is only reduced by 0.15V. It is shown that Zr0 2 nanocrystallites can be used as a storage medium to significantly improve the fatigue resistance of the device.
  • DRAWINGS Figure 1 High resolution projection electron micrograph of a Zr0 2 nanocrystallite nonvolatile charge trap type memory device.
  • Figure 2 Schematic diagram of the structure and principle of a Zr0 2 nanocrystalline microcrystalline nonvolatile charge trap type memory device.
  • A1 2 0 3 adjacent to the Si sinking bottom serves as a tunneling layer
  • A1 2 0 3 of the platinum electrode is used as a barrier layer
  • x is used as a storage layer, and Zr0 2 obtained by annealing treatment is obtained.
  • Nanocrystallites act as a storage medium.
  • Figure 3 Capacitance-voltage characteristics of Zr0 2 nm microcrystalline based nonvolatile charge trap type memory devices at different scan voltages at high frequencies (1 MHz).
  • the X axis represents the voltage applied to the platinum electrode (in volts) and the y axis represents the normalized storage capacitor.
  • Figure 4 Device memory window before and after annealing as the scan voltage of the platinum electrode changes.
  • the X-axis represents the scan voltage (in volts) applied to the platinum electrode and the y-axis represents the memory window (in volts).
  • Figure 5 Maintainability of Zr0 2 nm microcrystalline based non-volatile charge trapping memory devices at different test temperatures.
  • the X axis represents the hold time (in seconds) and the y axis represents the amount of charge loss.
  • the hollow curve is a device that has not undergone 10 5 write/erase operations; the solid curve is a device subjected to 10 5 write/erase operations.
  • Figure 6 Fatigue resistance of ZrO A-meter microcrystalline based nonvolatile charge trap type memory devices.
  • the X axis represents the number of write/erase times, and the y axis represents the flat band voltage (in volts).
  • the hollow curve is an erase operation; the solid curve is a write operation.
  • DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Based on a Si substrate, a preparation process of a Zr0 2 nanocrystal-based nonvolatile charge trap type memory device is as follows:
  • the Si substrate was placed in an appropriate amount of acetone, ultrasonically cleaned, and ultrasonically cleaned with deionized water to rinse off impurities remaining on the surface of the substrate.
  • the substrate is then immersed in hydrofluoric acid to remove surface oxides, ultrasonically cleaned with deionized water, blown dry with high purity nitrogen, and placed in an atomic layer chemical vapor deposition chamber for deposition of the film.
  • A1(CH 3 ) 3 is used as the metal source during the deposition process, and ozone is the oxygen source.
  • A1(CH 3 ) 3 enters the cavity with nitrogen, reacts with the surface of the silicon substrate at the hydroxyl end and saturates, and then the oxygen source is brought into the cavity by nitrogen to form a surface reaction with the metal source to form A1 2 0 3 to form a tunneling layer.
  • A1 2 0 3 with a thickness of 3 nm is deposited as a tunneling layer.
  • the sample is placed in a pulsed laser deposition chamber, and the prepared (ZrC ⁇ WSiO ⁇ -x target is deposited on the surface of the sample (ZrC ⁇ SiO ⁇ -x film for storage).
  • the (Zr0 2 ) x (Si0 2 ) i_ x target is prepared by mixing Zr0 2 and SiO 2 powders in a molar ratio; and then in a planetary ball mill.
  • test method for maintaining performance is as follows: A voltage pulse of 10 V, lms is applied to the upper electrode, and electrons enter the storage layer under the action of an electric field and are captured by the Zr0 2 nanocrystallite. The amount of charge loss after different times was tested to obtain the amount of charge loss at different retention times.
  • the test method for the fatigue resistance of the device is as follows: First, a voltage pulse of 10 V, lms is applied to the upper electrode, and electrons enter the storage layer under the action of an electric field and are captured by the Zr0 2 nanocrystallite. A voltage pulse of -10 V, lms is then applied to the upper electrode, and the electrons return to the substrate under the action of an electric field. This is repeated 10 5 times.

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Description

说明书 非易失性电荷捕获型存储器件、 其制备方法及应用 技术领域 本发明涉及一种非易失性电荷捕获型存储器件、 其制备方法及应用。 背景技术 几十年来，集成电路的发展基本遵循了 Intel公司创始人之一的 Gordon E. Moore博士 1964 年预言的摩尔定律： 在集成电路的单个芯片上集成的元件数， 即集成电路的集成度， 每 12至
18 个月增加一倍， 特征尺寸縮小 倍。 随着器件的特征尺寸越来越小， 传统的浮栅型非易 失性半导体存储器件面临严重的漏电问题。 浮栅型存储器件中隧穿层尺寸的不断减小， 以至 于一个缺陷就会导致多晶硅浮栅中存储的电荷全部损失。 为了解决这一难题， 多晶硅-氧化物 -氮化物 -氧化物-硅 (SONOS)型半导体存储器件被广泛地研究。 在这类器件中， 电子被 Si3N4 存储层中分立的陷阱捕获， 起到存储的效果。 由于， 这些陷阱彼此分离， 所以隧穿层中的缺 陷不能泄露全部的存储电子， 器件的保持性能得到改善， 从而克服了传统浮栅型存储器件的 弊端。 近年来， 采用纳米微晶作为电荷存储介质成为研究的热点。 但是， 许多研究工作者将 大部分精力花费在制备金属纳米微晶和半导体纳米微晶存储器件中， 对其他形式纳米微晶研 究较少。
近年来， 高介电常数材料作为 CMOS工艺栅介质层已经被广泛研究， 同时伪二元氧化物 也是其中研究的热点。 通过混合两种高介电常数材料， 实现介电性能的提高。 正是基于这点 想法， 可以通过混合两种结晶温度不同的高介电常数材料， 利于两者结晶温度的差别， 通过 高温退火处理， 使其中一种材料结晶， 而另一种材料依旧保持非晶态， 结晶出的纳米微晶被 非晶母相所包围。 利用将这一工艺特点与传统 SONOS型半导体电荷存储工艺相结合， 实现 高介电常数材料纳米微晶基电荷捕获型存储器件。 另一方面， 相比 Si02， A1203 具有高的介 电常数 (9)和宽的禁带宽度 (8.8eV)， 所以采用 A1203 作为隧穿层和阻挡层代替传统器件中的 Si02， 能很好的减小漏电流和提高器件的存储性能。 Zr02作为高介电常数材料已经被证明具 有代替 sio2 作为栅介质材料的潜力。 同时相比于 sio2和 AI2O3 loocrc以上的结晶温度， 其 结晶温度相对较低。
作为薄膜生长工艺中的主要制备方法， 脉冲激光沉积法 (PLD)和原子层化学气相沉积 (ALD)不仅对薄膜的生长起到关键的作用， 而且对器件的性能也起着举足轻重的作用。 脉冲 激光沉积法方法是 20世纪 80年代后期发展起来的一种新型薄膜制备技术。 其基本原理是利 用经过聚焦而具有很高能流密度的紫外脉冲激光照射靶材， 产生激光等离子体， 最终在衬底 上沉积成膜。 其最大优点是膜的化学成分和靶的化学成分很接近， 因而易于获得成分可严格 控制的膜。 它特别适合于制备高熔点、 多组分的氧化物薄膜和异质结构。 原子层化学气相沉 积 (ALD) 是 high-fc材料制备领域正在发展中的极具挑战性的一种制备技术。其原理是利用气 相源在衬底表面吸附或反应的自饱和性实现逐层 (layer by layer)生长， 生成薄膜的厚度在工作 窗口内不依赖于衬底温度、 蒸气压、 源流量等生长参数,只与循环周期的数目有关。 由于其独 特的自限制生长过程， 原子层沉积成膜具有精确的厚度控制、 优异的三维贴合性和大面积成 膜均匀性等优点， 在制备超薄薄膜、 纳米结构方面独具优势。 发明内容 本发明提供一种非易失性电荷捕获型存储器件的制备方法， 操作简单、 易于控制， 作为 存储介质的纳米微晶分布均匀。
本发明还提供上述制备方法得到的非易失性电荷捕获型存储器件。
本发明还提供上述制备方法得到的非易失性电荷捕获型存储器件在信息存储和不挥发半 导体存储器件中的应用。
所述非易失性电荷捕获型存储器件的制备方法包括以下步骤：
a) 在衬底表面形成隧穿层；
b) 在隧穿层上形成组成均匀的 (ZrCK Mh— x薄膜作为存储层， 其中 l〉x〉0.5， 所述 M为 Si02或 A1203， 优选 0.6 x 0.9， 进一步优选 0.7 x 0.9。
c) 在存储层上形成阻挡层；
d) 将以上制备的试样在低于 M熔点的温度下退火， 使 Zr02纳米微晶从存储层中析出， 并被非晶母相包围， 所述 Zr02纳米微晶作为存储介质。
本发明基于混合物中两种物质结晶温度的差别， 经过高温退火处理的手段， 使混合物中 的过饱和成分结晶析出， 即 Zr02纳米微晶从存储层母相中析出， 并且被非晶母相所包围， 从 而实现纳米微晶存储的效果。这种方法所得作为存储介质的纳米微晶均匀分布在非晶母相中。 显然， 这会导致最后的非晶母相与最初在隧穿层上形成的存储层薄膜的组成不一样， 但存储 层整体的组成不变。 作为常识， 为了避免对器件结构造成不利影响， 退火的时间应有一定限 制， 优选步骤 d) 中退火时间为 10~60s。 退火气氛为现有技术， 氧气气氛或氮气气氛均可。 本领域技术人员可根据具体情况， 选择合适的退火条件。
在隧穿层上形成 (ZrCK Mh— x薄膜的方法优选为： 以 (ZrC^MMh— x为靶材， 在隧穿层上用 脉冲激光沉积方法沉积 (ZrCK M^ x薄膜。脉冲激光沉积条件优选为能量为 150~400mJ，频率 l~10Hzo (ZrC^ Mh— x靶材的制备方法采用现有技术， 如将 Zr02和 Si02 (或者 Zr02和 A1203) 粉体混合均匀， 然后在 10~15MPa 的压力下压成圆片， 最后在 125CTC下烧制 6小时， 制成 (ZrC^MMh— x陶瓷靶材。 作为现有技术， 通常为了使 Zr02和 Si02 (或者 Zr02和 A1203)粉体 混合均匀， 需要在球磨机中湿磨， 然后将粉体烘干后再压制圆片。
优选所述隧穿层和阻挡层均为 A1203，进一步优选所述隧穿层、存储层和阻挡层的厚度分 别为 2~4nm、 5nm禾口 7~12nm。 衬底优选采用 Si。
当然， 本发明还应在阻挡层上面沉积铂、 铝、 TaN或者 Hf 等公知材料作为上电极。 上述制备方法所得非易失性电荷捕获型存储器件， 包含顺序连接的隧穿层、 存储层和阻 挡层， 利用 （ZrCK SiO^— x 为存储层， 通过退火处理得到的 Zr02纳米微晶起到存储介质的 作用。 结构如图 1所示。
上述制备方法所得非易失性电荷捕获型存储器件在信息存储和不挥发半导体存储器件中 的应用， 原理图如图 2所示：
a) 当铂电极相对与 Si衬底施加一个正电压， 电场由上电极指向衬底。随着施加电压的增 加， 电场强度不断增加。 Si衬底表面达到反型， 形成表面电子通道， 并且在电场作用下隧穿 过 A1203隧穿层， 进入到 (ZrC^ Mh— x存储层， 进而被 Zr02纳米微晶表面的电子陷阱态捕获， 达到存储的效果， 该过程就是该非易失性电荷捕获型存储器件的写入过程。
c) 当切断电源， 电子被存储在 Zr02纳米微晶中， 而不会泄漏， 从而起到电荷存储的效 果。
d) 当铂金电极相对与 Si衬底施加一个负电压， 电场由衬底指向上电极。 存储在 Zr02纳 米微晶中的电子在电场力的作用下， 穿过隧穿层重新回到衬底， 从而实现对器件的擦除操作。
本发明具有以下有益效果：
a) 该器件结构能获得大的存储信息量。图 3 显示当扫描电压为 ±1V时，存储窗口为 0.3V。 当扫描电压为 ±5V和 ±14V时， 已经具有明显的滞回窗口， 分别为 4.0V和 7.5V。
b) 图 4 显示， 相比于退火之前， 退火之后的器件具有大的存储窗口， 说明 Zr02纳米微 晶对器件的存储性能起着至关重要的作用。 Zr02纳米微晶能提高薄膜中的陷阱态密度， 从使 器件具有高电荷存储量。
c) 由图 5可以看出， 随着测试温度的升高， 器件的电荷损失量增大； 且经过 105次擦除 写入后的器件电荷损失较大。但是， 在 15CTC下 (测试时间为 4x l04 )， Zr02纳米微晶基非易失 性电荷捕获型存储器件在经过 105次擦除写入后的电荷损失量仅为 12%。
d) 图 6为： Zr02纳米微晶基非易失性电荷捕获型存储器件不同温度下的抗疲劳特性。 从图中可以看出， 随着温度的升高， 器件的抗疲劳性能稍有下降， 15CTC下， 存储窗口仅仅减 小了 0.15V。 表明以 Zr02纳米微晶作为存储介质能够显著提高器件的抗疲劳性能。 附图说明 图 1 : Zr02纳米微晶基非易失性电荷捕获型存储器件的高分辨投射电子显微图。 图 2: Zr02纳米微晶基非易失性电荷捕获型存储器件的结构及其原理示意图。 其中， 紧 邻 Si沉底的 A1203作为隧穿层，紧邻铂电极的 A1203作为阻挡层， (Zr02)x(Si02)!.x作为存储层， 退火处理得到的 Zr02纳米微晶作为存储介质。
图 3: 高频情况下 (lMHz)， Zr02纳米微晶基非易失性电荷捕获型存储器件在不同扫描电 压下的电容 -电压特性。 其中 X轴表示施加在铂电极上的电压 (单位为伏特)， y轴表示归一化 的存储电容。
图 4: 退火前后器件存储窗口随着铂电极扫描电压的变化情况。 其中 X轴表示施加在铂 电极上的扫描电压 (单位为伏特)， y轴表示存储窗口 (单位为伏特)。
图 5: 不同测试温度下， Zr02纳米微晶基非易失性电荷捕获型存储器件的保持性能。 其 中 X轴表示保持时间 (单位为秒)， y轴表示电荷损失量。 图中， 空心曲线为未经过 105次写入 /擦除操作的器件； 实心曲线为经受 105次写入 /擦除操作的器件。 图 6: ZrO A米微晶基非易失性电荷捕获型存储器件的抗疲劳性能。其中 X轴表示写入 /擦除次数， y轴表示平带电压 (单位为伏特)。 图中， 空心曲线为擦除操作； 实心曲线为写入 操作。 具体实施方式 实施例 1 : 基于 Si衬底， Zr02纳米微晶基非易失性电荷捕获型存储器件的制备过程具体 如下：
(a) 将 Si衬底将衬底放入适量丙酮中， 超声清洗后， 用去离子水超声清洗， 漂洗掉衬底 表面残留的杂质。然后衬底放入氢氟酸中浸泡， 去除表面氧化物， 再使用去离子水超声清洗， 用高纯氮气吹干后放入原子层化学气相沉积腔体内以备沉积薄膜。
(b) 沉积过程中采用 A1(CH3)3作为金属源， 臭氧为氧源。 A1(CH3)3伴随氮气进入腔体， 与羟基终端的硅衬底表面反应并达到饱和， 之后氧源由氮气带入腔体与金属源发生表面反应 生成 A1203， 形成隧穿层， 通过控制原子层沉积循环系数， 沉积厚度为 3 nm的 A1203作为隧 穿层。
(c) 当隧穿层沉积结束， 将试样放入脉冲激光沉积腔中， 利用制备的 （ZrC^WSiO^— x靶 材， 在试样表面沉积 (ZrC^ SiO^— x 薄膜， 作为存储层， 控制薄膜厚度为 5nm。其中， x=0.8。 (Zr02)x(Si02)i_x靶材的制备方法为： 将 Zr02和 Si02粉体按照摩尔比混合； 而后在行星球磨 机中湿磨 12小时， 将粉体烘干， 然后在 10~15MPa的压力下压成厚度为 5mm， 直径 20mm 的圆片， 最后在 125CTC下烧制 6小时， 制成 (ZrC^MSiO^— x陶瓷靶材。
(d ZrCK SiO^— x存储层沉积结束，在其表面沉积一层 7 nm厚的 A1203介质层，作为阻 挡层， 形成过程如步骤 (b)。 (e) 上述制备过程结束后， 将器件置于快速退火炉中， 在 800°C， 氧气气氛中退火 30秒。
(f) 铂 (Pt)作为上电极， 通过磁控溅射的方法沉积在经过退火处理的器件上面。 在 Si沉底 侧面涂覆上一层导电银胶作为下电极。 实验中对 Zr02纳米微晶基非易失性电荷捕获型存储器件存储窗口以及保持性能的测量 均使用 Keithley4200半导体参数分析仪完成。 高频扫描情况下， 上电极接正电压， 下电极接 负电压，扫描过程中电子在电场作用下进入存储层被 Zr02纳米微晶所捕获，相当于写入操作; 相反， 上电极接负电压， 下电极接正电压， 在扫描过程中， 被 Zr02纳米微晶所捕获的电子在 电场力的作用下重新回到衬底， 相当于擦除操作。
保持性能的测试方法为： 在上电极施加 10V， lms的电压脉冲， 电子在电场作用下进入 存储层被 Zr02纳米微晶所捕获。测试不同时间以后电荷的损失量， 从而获得不同保持时间下 的电荷损失量。
器件抗疲劳性能的的测试方法为： 首先在上电极施加 10V， lms的电压脉冲， 电子在电 场作用下进入存储层被 Zr02纳米微晶所捕获。 然后在上电极施加 -10V， lms的电压脉冲， 电 子在电场作用下回到衬底。 如此反复 105次。
所述测试结果如图 3-6所示。

Claims

权利要求书
1. 一种非易失性电荷捕获型存储器件的制备方法， 其特征在于包括以下步骤： a) 在衬底表面形成隧穿层；
b) 在隧穿层上形成组成均匀的 (ZrCK Mh— x薄膜作为存储层， 其中 l〉x〉0.5， 所述 M为 Si02或 A1203;
c) 在存储层上形成阻挡层；
d) 将以上制备的试样在低于 M熔点的温度下退火， 使 Zr02纳米微晶从存储层中析出， 并被非晶母相包围， 所述 Zr02纳米微晶作为存储介质。
2. 如权利要求 1 所述的非易失性电荷捕获型存储器件的制备方法， 其特征在于 0.6 x 0.9。
3. 如权利要求 2所述的非易失性电荷捕获型存储器件的制备方法， 其特征在于 x=0.8。
4. 如权利要求 1-3中任一项所述的非易失性电荷捕获型存储器件的制备方法， 其特征在 于所述 M为 Si02。
5. 如权利要求 1-3中任一项所述的非易失性电荷捕获型存储器件的制备方法， 其特征在 于步骤 d) 中退火时间为 10~60s。
6. 如权利要求 1-3中任一项所述的非易失性电荷捕获型存储器件的制备方法， 其特征在 于所述隧穿层和阻挡层均为 A1203。
7. 如权利要求 6所述的非易失性电荷捕获型存储器件的制备方法，其特征在于所述隧穿 层、 存储层和阻挡层的厚度分别为 2~4nm、 5~8nm和 7~12nm。
8. 如权利要求 1-3中任一项所述的非易失性电荷捕获型存储器件的制备方法， 其特征在 于在隧穿层上形成 (ZrCK Mh— x薄膜的方法为： 以 (ZrCK Mh— x为靶材， 在隧穿层上用脉冲激 光沉积方法沉积 （ZrCK Mh— x薄膜。
9. 权利要求 1-8中任一项制备方法所得非易失性电荷捕获型存储器件。
10.权利要求 1-8中任一项制备方法所得非易失性电荷捕获型存储器件在信息存储和不挥 发半导体存储器件中的应用。
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