WO2012142735A1 - 一种半导体存储器结构及其制造方法 - Google Patents

一种半导体存储器结构及其制造方法 Download PDF

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Publication number
WO2012142735A1
WO2012142735A1 PCT/CN2011/001352 CN2011001352W WO2012142735A1 WO 2012142735 A1 WO2012142735 A1 WO 2012142735A1 CN 2011001352 W CN2011001352 W CN 2011001352W WO 2012142735 A1 WO2012142735 A1 WO 2012142735A1
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WIPO (PCT)
Prior art keywords
field effect
effect transistor
semiconductor memory
tunneling field
gate
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Ceased
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PCT/CN2011/001352
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English (en)
French (fr)
Inventor
王鹏飞
林曦
孙清清
张卫
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Fudan University
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Fudan University
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Priority to US13/376,994 priority Critical patent/US20140034891A1/en
Publication of WO2012142735A1 publication Critical patent/WO2012142735A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H10B63/32—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors of the bipolar type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/82—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays the switching components having a common active material layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
    • H10D12/211—Gated diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Shaping switching materials
    • H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8833—Binary metal oxides, e.g. TaOx

Definitions

  • the present invention relates to the field of microelectronic device technologies, and in particular, to a semiconductor memory structure and a method of fabricating the same, and more particularly to a semiconductor memory structure and a manufacturing method thereof for controlling a phase change memory and a resistive memory using a tunneling field effect transistor method.
  • Background technique
  • Flash floating gate memory is a kind of semiconductor memory device that can save power and save information.
  • 1 is an equivalent circuit diagram of a semiconductor memory device of the prior art. As shown in FIG. 1, the memory device is composed of a transistor 313 and a memory cell 314, and a transistor 313 and a memory cell 314 are connected in series between a bit line 315 and a source potential 312, and a word line 311 is used for switching control of the transistor 313.
  • word line 311 applies a voltage to transistor 313 and turns on transistor 313, while bit line 315 applies a voltage to memory cell 314 such that a read current passes through memory cell 314 and the transistor. 313. Based on the magnitude of the output current, the data stored in the storage unit 314 is read.
  • phase change memory stores data by utilizing the large difference in conductivity between the gram-based compound in the crystalline and amorphous states.
  • phase change chalcogenide exhibits a reversible phase transition when it is turned from the amorphous phase to the crystalline phase.
  • the material In the amorphous phase, the material is highly disordered and there is no lattice structure of the crystal. In this state, the material has high impedance and high reflectivity.
  • the material Conversely, in the crystalline phase, the material has a regular crystal structure with low impedance and low reflectivity.
  • Phase change memory utilizes the impedance difference between the two phases.
  • the intense heat generated by current injection can initiate a phase change in the material.
  • the material properties after phase change are determined by the current, voltage and operating time of the injection. Phase change memories offer faster write and erase speeds and better scaling than traditional Flash floating gate memories.
  • the reading and writing of information of the resistive memory is realized by reading or changing the resistance of the resistive material.
  • a typical resistive material has two states of high resistance and low resistance.
  • resistive memory does not rely on the amount of charge stored in the capacitive structure to store information, but instead relies on changes in the resistivity of the material itself to store information. Since the resistivity of the material itself is independent of the size of the material, the storage performance of the resistive memory is theoretically not degraded as the device size shrinks. This determines the potential integration capability of the resistive memory is much higher than the current mainstream Flash floating gate memory.
  • the resistive memory device has a simple structure and can be easily integrated with existing CMOS production processes.
  • An object of the present invention is to provide a semiconductor memory structure in which a semiconductor memory can be read, written, or the like with a small current.
  • the semiconductor memory structure of the present invention includes at least one variable resistance memory cell and a tunneling field effect transistor structure for operating a semiconductor memory; wherein the tunneling field effect transistor includes at least one source, a drain, a low doped channel region and a gate, the gate of the tunneling field effect transistor is connected to the word line, the source is connected to the source line, and the two ends of the variable resistor are respectively connected to the bit line and The tunneling of the drain of the field effect transistor.
  • the drain of the tunneling field effect transistor is at the top of a platform structure perpendicular to a horizontal surface, the platform structure is a semiconductor substrate material, and the source is at a portion extending outward from the bottom of the platform structure.
  • the low doped channel region is between the drain and the source, and the gate covers a portion below the low doped region of the platform structure to control a source passing through the channel region The amount of current between the drain and the drain.
  • the variable resistance memory cell is connected to a source drain of the tunneling field effect transistor, and a gate of the tunneling field effect transistor can control a current through the memory cell, thereby A read and write operation to the memory unit is implemented.
  • the semiconductor substrate is monocrystalline silicon, polycrystalline silicon or silicon on insulator (SOI).
  • the gate is a stacked structure comprising at least one conductive layer and an insulating layer separating the conductive layer from the semiconductor substrate, the conductive layer being polysilicon, amorphous silicon, tungsten metal, Titanium nitride, tantalum nitride or metal silicide, the insulating layer being Si0 2 , Hf0 2 , HfSiO, HfSiON, SiON or Al 2 0 3 , or a mixture of several of them.
  • the gate conductive layer surrounds A sidewall structure is formed around the vertical germanium doped channel region.
  • the tunneling field effect transistor is a gate-controlled diode structure, when the pn junction of the tunneling field effect transistor is forward biased, the device can pass a large current, thereby satisfying the large writing of the resistive memory and the phase change memory. Current requirements.
  • the present invention also provides a method of fabricating the above semiconductor memory structure, the method comprising the steps of: providing a semiconductor substrate; implanting ions on the substrate to form a first doping type region; forming a first layer of insulation a thin film; etching the first insulating film and the semiconductor substrate to form a columnar active region; sequentially depositing a high-k material dielectric layer, a conductive layer, and a polysilicon layer; etching the polysilicon layer to form a sidewall and for An ion implantation opening; performing ion implantation to form a second doping type region; etching the high K material dielectric layer, the conductive layer, and the polysilicon layer, and etching away the remaining first insulating film; depositing An oxide layer is shielded and etched to form a via structure; a resistive material film and a metal layer are sequentially deposited, and the resistive material film and the metal layer are etched to form a bit line.
  • the semiconductor substrate is monocrystalline silicon, polycrystalline silicon or silicon-on-insulator (SOI), the first doping type is n-type, the second doping type is p-type, or doping type Intermodulation.
  • the first insulating film is Si ⁇ 2 , Si 3 N 4 or an insulating material mixed therebetween, and the resistive material film is Zn0 2 , CuO, low-k material or GeSbTe material, and the metal layer is TiN. Ti, Ta, or TaN.
  • the gate, drain and source are self-aligned.
  • the gate length of the tunneling field effect transistor can be controlled by changing the etching conditions.
  • FIG. 1 is an equivalent circuit diagram of a semiconductor memory device of the prior art.
  • 2, 4, 5, 7, 8, 8, 10, 13, and 15 are cross-sectional views showing an implementation process of a semiconductor memory device according to the present invention.
  • 3 is a plan view showing a state in which a first insulating film and a semiconductor substrate are etched to form a columnar active region structure.
  • Fig. 6 is a plan view showing a state in which a polysilicon layer is etched.
  • Fig. 9 is a plan view showing the etching of the gate dielectric layer and the first insulating film.
  • Figure 11 is a plan view showing the etching of the oxide dielectric layer.
  • Fig. 14 is a plan view showing a state in which a resistive material film and a metal layer are etched.
  • Figure 16 is an equivalent circuit diagram of the semiconductor memory device shown in Figure 15. BEST MODE FOR CARRYING OUT THE INVENTION
  • the thickness of layers and regions are exaggerated for convenience of explanation, and the illustrated sizes do not represent actual dimensions. Although these figures do not fully reflect the actual dimensions of the device, they completely reflect the mutual position between the regions and the constituent structures, especially the upper and lower and adjacent relationships between the constituent structures.
  • Fig. 16 is a circuit diagram showing four semiconductor memories in accordance with the present invention in parallel.
  • the semiconductor memory structure proposed by the present invention includes at least one variable resistance memory cell and a tunneling field effect transistor structure for operating the semiconductor memory.
  • the tunneling field effect transistor includes at least one source, one drain, one low doped channel region, and one gate.
  • the gate of the tunneling field effect transistor is connected to the word line 303a.
  • the source is connected to the source line 302, and both ends of the variable resistor 304a are connected to the drain of the tunneling field effect transistor 305a and the bit line 301, respectively.
  • FIG. 15 is a cross-sectional view along bit line 112 of Figure 14. It can be seen that the drain 101 of the tunneling field effect transistor is on top of a platform structure perpendicular to the horizontal surface.
  • the platform structure is made of the same material as the semiconductor substrate 100, and the source 109 is in the In the bottom of the substrate structure extending outwardly from the bottom of the platform structure, the low doped channel region is between the drain 101 and the source 109, which may be equivalent to the doping of the original substrate, and the gate 107 is A portion below the low doped region of the platform structure is covered to control the amount of current between the source and drain through the channel region.
  • the variable resistance memory cell 111 is composed of a phase change material or a resistive material, and the variable resistance memory cell is connected to the drain of the tunneling field effect transistor. As shown in FIG. 15, the variable resistance memory cell is 111 and the drain of the tunneling field effect transistor is between the bit lines 112. When there is a voltage difference between the drain 101 and the bit line 112, a current in the variable resistance memory cell 111 is passed. The gate 107 of the tunneling field effect transistor can control the current through the memory cell 111 to effect read and write operations on the memory cell.
  • the semiconductor substrate is monocrystalline silicon, polycrystalline silicon or silicon on insulator (SOI).
  • the gate is a stacked structure including at least one conductive layer and one of the conductive layer and the semiconductor
  • the insulating layer of the bulk substrate is: the conductive layer is polysilicon, amorphous silicon, tungsten metal, titanium nitride, tantalum nitride or metal silicide, and the insulating layer is Si0 2 , Hf0 2 , HfSiO, HfSiON , SiON, Al 2 0 3 or a mixture between them.
  • the gate conductive layer forms a sidewall structure around the vertical germanium doped channel region.
  • the variable resistance memory cell is connected to the source or drain of the field effect transistor.
  • the gate of the tunneling field effect transistor can control the current through the memory cell.
  • the tunneling field effect transistor is a gate-controlled diode structure, when the pn junction of the tunneling field effect transistor is forward biased, the device can pass a large current, thereby satisfying the large writing of the resistive memory and the phase change memory. Current requirements. If a conventional device of the same size MOSFET (metal-oxide-semiconductor field effect transistor) is used, it is difficult to achieve this large current.
  • MOSFET metal-oxide-semiconductor field effect transistor
  • the drawings are schematic illustrations of idealized embodiments of the present invention, and the illustrated embodiments of the present invention should not be considered limited to the particular shapes of the regions shown in the figures, but rather to the resulting shapes, such as manufacturing variations.
  • the curves obtained by etching are generally characterized by being curved or rounded, but in the embodiments of the present invention, they are all represented by rectangles, and the representations in the figures are schematic, but this should not be construed as limiting the scope of the invention.
  • the term substrate as used may be understood to include a semiconductor substrate being processed, possibly including other thin film layers prepared thereon. Referring to FIG. 2, a semiconductor substrate 100 is provided, and then n-type ion implantation is performed to form a doped region 101.
  • a thin film 102 and a thin film 103 are sequentially deposited on the provided semiconductor substrate, and then the partial thin film 103, the thin film 102, and the semiconductor substrate are etched to form openings 201 and openings 202, as shown in FIG. It is possible to form a columnar active region.
  • the film 102 is an insulating material which is Si0 2 , Si 3 N 4 or a mixture thereof, and the film 103 is a photoresist layer. It should be noted that in the above etching process, the previously formed doped region 101 is also partially etched away. Therefore, the gate length of the tunneling field effect transistor can be controlled by changing the etching conditions. Fig.
  • FIG. 3 is a plan view showing the etching.
  • the film 103 is removed, and then the film 104, the film 105, the film 106, the film 107, and the film 108 are sequentially deposited.
  • the film 104 is, for example, SiO 2
  • the film 105 is a high-k dielectric layer, such as TiN or TaN.
  • the film 107 is, for example, polysilicon
  • the film 108 is a photoresist layer, as shown in FIG.
  • the film 107 is etched, and then the remaining film 108 is removed.
  • Fig. 6 is a plan view of the etching step in this step.
  • a doped region 109 As shown in FIG.
  • the film 104, the film 105, and the film 106 are etched, and Fig. 9 is a plan view at the time of etching.
  • a thin film 110 is formed, for example, a SiO 2 layer, and then the thin film 110 is etched into a groove structure, as shown in Fig. 12, which is a plan view at the time of etching.
  • a film 111 and a film 112 are sequentially formed, as shown in FIG.
  • the film 111 is, for example, a Zn0 2 , CuO or low-k material
  • the film 112 is a metal which may be TiN, Ti, Ta, or TaN.
  • the film 111 and the film 112 are etched to form a structure as shown in Fig. 15, and Fig. 14 is a plan view when the structure shown in Fig. 15 is formed.
  • Figure 16 is an equivalent circuit diagram of the semiconductor memory device shown in Figure 15. As shown in FIG. 16, the memory cells 304a, 304b, 304c, and 304d formed by the thin film 111 in FIG.
  • tunneling field effect transistors 305a, 305b, 305c, and 305d are respectively associated with the memory cells 304a, 304b, 304c and 304d are connected in series, and the other ends of the tunneling field effect transistors 305a, 305b, 305c, and 305d are connected to the reference voltage wiring 302, and the bit lines 303a, 303b, 303c, and 303d are used for the field effect transistors 305a, 305b, 305c, and 305d, respectively.
  • Switch control Such a semiconductor memory structure in which a semiconductor memory is subjected to operations such as erasing, reading, etc., using a tunneling field effect transistor is formed.
  • a semiconductor memory uses a tunneling field effect transistor to control a phase change memory or a resistive memory such as an erase operation and a read operation, and on the other hand, a forward bias pn junction current of a tunneling field effect transistor It can meet the characteristics that the phase change memory or the resistive memory requires a large current for the erase operation; on the other hand, the vertical structure of the field effect transistor can greatly increase the density of the memory device array.
  • the present invention also discloses a method of fabricating the semiconductor memory structure using a self-aligned process, which is well suited for the fabrication of memory chips. As described above, many widely differing embodiments can be constructed without departing from the spirit and scope of the invention. It is to be understood that the invention is not limited to the specific embodiments described in the specification, unless the scope of the claims.

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Description

技术领域 本发明属于微电子器件技术领域， 具体涉及一种半导体存储器结构及其 制造方法， 特别涉及一种采用隧穿场效应晶体管对相变存储器和阻变存储器 进行控制的半导体存储器结构及其制造方法。 背景技术
Flash 浮栅存储器是能实现断电保存信息的一种半导体存储器件。 图 1 为现有技术一个半导体存储器器件的等效电路图。 如图 1所示， 存储器件由 晶体管 313和存储单元 314组成， 并且晶体管 313和存储单元 314被串联 连接在位线 315和源电位 312之间， 字线 311用于晶体管 313的开关控制。 要存取存储单元 314中的储存的数据时， 字线 311施加电压于晶体管 313, 且开启晶体管 313， 同时， 位线 315施加电压于存储单元 314, 使得一读取 电流经过存储单元 314及晶体管 313。 基于输出电流的大小， 储存在存储单 元 314中的数据得以被读取。 随着集成电路器件技术的不断发展， 半导体器件的尺寸不断缩小， 使得 集成电路的设计朝着片上系统集成（SOC ) 的方向发展， 而实现 SOC的一 个关键技术就是低功耗、 高密度、 存取速度快的片上存储器的集成。 如今的 集成电路器件技术已经处于 30nm左右， 但是传统 Flash浮栅存储器由于耦 合比和电压较高等问题， 很难缩小到 30nm以下， 因此新型的 Flash浮栅存 储器的开发成为了当前研究的热点。 相变存储器和阻变存储器都可以作为新 型的存储器。 相变存储器（ phase change memory )是利用石克族化合物在晶态和非晶 态时的巨大导电性差异来存储数据的。 相变硫族化物在由无定形相转向结晶 相时会表现出可逆的相变现象， 在无定形相时， 材料是高度无序的状态， 不 存在结晶体的网格结构。 在此种状态下， 材料具有高阻抗和高反射率。 相反 地， 在结晶相， 材料具有规律的晶体结构， 具有低阻抗和低反射率。 相变存 储器利用的就是两相间的阻抗差。 由电流注入产生的剧烈的热量可以引发材 料的相变。 相变后的材料性质由注入的电流、 电压及操作时间决定。 与传统 的 Flash浮栅存储器相比， 相变存储器具有更快的写入和擦除速度和更好的 缩放比例。 阻变存储器的信息读写是依靠读取或者改变阻变材料的电阻来实现的。 通常的阻变材料具有高阻和低阻两种状态。 与当前大多数半导体存储器的存 储原理相同，阻变存储器并不依靠电容式结构中所存储的电荷量来存储信息， 而是依靠材料本身的电阻率的改变来存储信息。 由于材料本身的电阻率与材 料的尺度无关， 因此理论上阻变存储器的存储性能并不会随着器件尺寸的缩 小而退化。 这就决定了阻变存储器潜在的集成能力远远高于当前主流的 Flash 浮栅存储器。 另一方面， 阻变存储器的器件结构简单， 可以非常容易 地实现与现有的 CMOS生产工艺的集成。 但是相变存储器和阻变存储器都需要较大的擦写电流， 因此需要特殊的 阵列存取器件对其进行擦写。 发明的公开 本发明的目的在于提出一种可以用较小的电流对半导体存储器进行读、 写等操作的半导体存储器结构。 本发明提出的半导体存储器结构， 包括至少一个电阻可变的存储单元和 一个用于对半导体存储器进行操作的隧穿场效应晶体管结构； 其中， 所述的 隧穿场效应晶体管包括至少一个源极、 一个漏极， 一个低掺杂沟道区和一个 栅极， 所述隧穿场效应晶体管的栅极连至字线， 源极连至源线， 可变电阻的 两端分别连至位线和所述隧穿场效应晶体管的漏极。 所述的隧穿场效应晶体管的漏极处于一个垂直于水平表面的平台结构的 顶部， 该平台结构采用的是半导体村底材料， 所述的源极处于所述平台结构 底部向外延伸的村底内， 所述的低掺杂沟道区处于所述漏极与源极之间， 所 述的栅极将该平台结构的低掺杂区以下的部位覆盖以控制通过沟道区域的 源极与漏极之间的电流大小。 所述的电阻可变的存储器单 与所述隧穿场效应^曰体管的源极 ^者漏极相 连， 所述隧穿场效应晶体管的栅极可以控制通过所述存储器单元的电流， 从 而实现对该存储器单元的读写操作。 所述的半导体衬底为单晶硅、 多晶硅或者绝缘体上的硅 (SOI)。 所述的栅 极是一个叠层结构， 其包括至少一个导电层和一个将所述导电层与所述半导 体衬底隔离的绝缘层， 所述的导电层为多晶硅、 无定形硅、 钨金属、 氮化钛、 氮化钽或者金属硅化物， 所述的绝缘层为 Si02、 Hf02、 HfSiO、 HfSiON、 SiON或 Al203， 或者它们之中几种的混合物。 并且， 所述的栅极导电层环绕 在垂直的氐掺杂沟道区周围形成边墙结构。 由于隧穿场效应晶体管是栅控的二极管结构， 当隧穿场效应晶体管的 p-n 结正向偏置时该器件可以通过大电流， 从而可以满足对阻变存储器和相 变存储器进行写入的大电流要求。 本发明还提供了一种上述半导体存储器结构的制造方法， 该方法包括下 列步骤： 提供一个半导体衬底； 在所述衬底上注入离子形成第一种掺杂类型 的区域； 形成第一层绝缘薄膜； 对第一层绝缘薄膜和半导体衬底进行刻蚀形 成柱状的有源区； 依次淀积形成高 K材料介质层、 导电层和多晶硅层； 对多 晶硅层进行刻蚀形成边墙以及用于进行离子注入的开口； 进行离子注入形成 第二种掺杂类型的区域； 对高 K材料介质层、 导电层和多晶硅层进行刻蚀， 并刻蚀掉剩余的第一层绝缘薄膜； 淀积形成一层氧化物介盾层， 并对其进行 刻蚀形成通孔结构； 依次淀积形成阻变材料薄膜和金属层， 再对阻变材料薄 膜和金属层进行刻蚀形成位线。 所述的半导体衬底为单晶硅、 多晶硅或者绝缘体上的硅 (SOI), 所述第一 种掺杂类型为 n型， 所述的第二种掺杂类型为 p型， 或者掺杂类型互调。 所述的第一层绝缘薄膜为 Si〇2、 Si3N4或者它们之间相混合的绝缘材料， 阻变材料薄膜为 Zn02、 CuO、 low-k材料或者 GeSbTe材料，金属层为 TiN、 Ti、 Ta、 或者 TaN。 采用本发明提出的制造方法后， 栅极、 漏极和源极是自对准的。 而且， 由于所述第一种掺杂的深度小于柱状有源区的高度， 隧穿场效应晶体管的栅 长可以由改变刻蚀的条件来控制。 这种方法使存储器器件制造工序简化， 并 且制程更加稳定。 附图的简要说明 图 1为当前技术一个半导体存储器器件的等效电路图。 图 2、 图 4、 图 5、 图 7、 图 8、 图 10、 图 12、 图 13和图 15为本发明 所提供的一种半导体存储器器件的实施工艺的截面图。 图 3为对第一层绝缘薄膜和半导体衬底进行刻蚀形成柱状有源区结构时 的俯视图。 图 6为对多晶硅层进行刻蚀时的俯视图。 图 9为对栅介质层和第一层绝缘薄膜进行刻蚀时的俯视图。 图 11为对氧化物介质层进行刻蚀时的俯视图。 图 14为对阻变材料薄膜和金属层进行刻蚀时的俯视图。 图 16为图 15所示半导体存储器器件的等效电路图。 实现本发明的最佳方式 下面将参照附图对本发明的一个示例性实施方式作详细说明。 在图中， 为了方便说明， 放大了层和区域的厚度， 所示大小并不代表实际尺寸。 尽管 这些图并不是完全准确的反映出器件的实际尺寸， 但是它们还是完整的反映 了区域和组成结构之间的相互位置，特别是组成结构之间的上下和相邻关系。 图 16为 4个本发明提出的半导体存储器并联时的电路图。 可以看到本 发明提出的半导体存储器结构包括至少一个电阻可变的存储单元和一个用于 对半导体存储器进行操作的隧穿场效应晶体管结构。 所述的隧穿场效应晶体 管包括至少一个源极、 一个漏极， 一个低掺杂沟道区和一个栅极。 以图 16 最左边的隧穿场效应晶体管 305a与可变电阻 304a组成的半导体存储器结构 为例， 通常组成半导体芯片进行操作时， 所述隧穿场效应晶体管的栅极会连 至字线 303a， 源极连至源线 302， 可变电阻 304a的两端分别连至隧穿场效 应晶体管 305a 的漏极与位线 301。 这样可以通过控制隧穿场效应晶体管 305a来控制通过可变电阻 304a的电流并进行控制。 图 15为沿着图 14中位线 112的剖面图。可以看到所述的隧穿场效应晶 体管的漏极 101处于一个垂直于水平表面的平台结构的顶部， 该平台结构采 用的是与半导体衬底 100相同的材料，所述的源极 109处于所述平台结构底 部向外延伸的村底内，所述的低掺杂沟道区处于所述漏极 101与源极 109之 间， 可以等同于原衬底的掺杂， 所述的栅极 107将该平台结构的低掺杂区以 下的部位覆盖以控制通过沟道区域的源极与漏极之间的电流大小。 所述的电阻可变的存储器单元 111由相变材料构成或者阻变材料构成， 并且所述的电阻可变的存储器单元与所述隧穿场效应晶体管的漏极相连。 如 图 15所示， 电阻可变的存储器单元为 111 , 处于隧穿场效应晶体管的漏极于 位线 112之间。 当漏极 101与位线 112之间有电压差时， 会导致电阻可变的 存储器单元 111 中有电流通过。 所述隧穿场效应晶体管的栅极 107可以控制 通过所述存储器单元 111的电流， 从而实现对该存储器单元的读写操作。 所述的半导体衬底为单晶硅、 多晶硅或者绝缘体上的硅 (SOI)。所述的栅 极是一个叠层结构， 其包括至少一个导电层和一个将所述导电层与所述半导 体衬底隔离的绝缘层， 所述的导电层为多晶硅、 无定形硅、钨金属、 氮化钛、 氮化钽或者金属硅化物， 所述的绝缘层为 Si02、 Hf02、 HfSiO、 HfSiON, SiON、 Al203或者它们之间的混合物。 并且， 所述的栅极导电层环绕在垂直 的氐掺杂沟道区周围形成边墙结构。 的电阻可变的存 器单元与 述随穿场效应晶 管^ j源极或者漏^相连。 这 样， 隧穿场效应晶体管的栅极可以控制通过所述存储器单元的电流。 由于隧穿场效应晶体管是栅控的二极管结构， 当隧穿场效应晶体管的 p-n 结正向偏置时该器件可以通过大电流， 从而可以满足对阻变存储器和相 变存储器进行写入的大电流要求。如果是用相同大小的 MOSFET (金属-氧 化物 -半导体场效应晶体管）这种传统器件是很难达到这个大电流的。
参考图是本发明的理想化实施例的示意图， 本发明所示的实施例不应该 被认为仅限于图中所示区域的特定形状， 而是包括所得到的形状， 比如制造 引起的偏差。 例如刻蚀得到的曲线通常具有弯曲或圆润的特点， 但在本发明 实施例中， 均以矩形表示， 图中的表示是示意性的， 但这不应该被认为是限 制本发明的范围。 同时在下面的描述中， 所使用的术语衬底可以理解为包括 正在工艺加工中的半导体村底， 可能包括在其上所制备的其它薄膜层。 请参照图 2， 提供一个半导体衬底 100， 然后进行 n型离子注入形成掺 杂的区域 101。 接下来， 在提供的半导体衬底上依次淀积形成薄膜 102和薄膜 103, 比 如光阻层， 然后刻蚀部分薄膜 103、 薄膜 102和半导体衬底形成开口 201和 开口 202,如图 4,这样就可以形成柱状的有源区。薄膜 102为为 Si02、Si3N4 或者它们之间相混合的绝缘材料， 薄膜 103为光阻层。 需要注意的是， 在上述刻蚀过程中， 之前形成的掺杂区域 101也会部分 被刻蚀掉， 因此， 隧穿场效应晶体管的栅长可以由改变刻蚀的条件来控制。 图 3为进行此次刻蚀时的俯视图。 接下来， 去除薄膜 103, 然后依次淀积形成薄膜 104、 薄膜 105、 薄膜 106、薄膜 107和薄膜 108，薄膜 104比如为 Si02，薄膜 105为高 k介质层， 薄膜 106比如为 TiN 或者 TaN, 薄膜 107比如为多晶硅， 薄膜 108为光阻 层， 如图 5。 如图 7， 对薄膜 107进行刻蚀， 然后去除剩余的薄膜 108, 图 6为本步 骤进行刻蚀时的俯视图。 接下来进行 p型离子注入形成掺杂的区域 109， 如图 8。 接下来， 按如图 10所示， 对薄膜 104、 薄膜 105和膜 106进行刻蚀， 图 9为进行刻蚀时的俯视图。 接下来， 淀积形成一层薄膜 110比如为 Si02层， 然后将薄膜 110刻蚀 成槽结构， 如图 12， 图 11为进行刻蚀时的俯视图。 再接下来， 依次淀积形成薄膜 111和薄膜 112, 如图 13。 薄膜 111比如 为 Zn02、 CuO或者 low-k材料， 薄膜 112为金属可以为 TiN、 Ti、 Ta、 或者 TaN。 最后对薄膜 111和薄膜 112进行刻蚀形成如图 15所示的结构，图 14为 形成如图 15所示结构时的俯视图。 图 16为图 15所示半导体存储器器件的等效电路图。 如图 16所示， 图 15中薄膜 111形成的存储单元 304a、304b、304c和 304d与位线 301相连， 隧穿场效应晶体管 305a、 305b, 305c和 305d分别与存储单元 304a、 304b, 304c和 304d相串联， 并且隧穿场效应晶体管 305a、 305b, 305c和 305d 的另一端与基准电压布线 302相连， 位线 303a、 303b, 303c和 303d分别 用于场效应晶体管 305a、 305b, 305c和 305d的开关控制。 这样一个釆用隧穿场效应晶体管对半导体存储器进行比如擦写、 读等操 作的半导体存储器结构就形成了。 工业应用性 根据本发明， 半导体存储器采用隧穿场效应晶体管对相变存储器或阻变 存储器进行比如擦写操作和读操作的控制， 一方面， 隧穿场效应晶体管的正 向偏置 p-n结电流可以满足相变存储器或阻变存储器需要较大的电流来进行 擦写操作的特点； 另一方面， 垂直结构的场效应晶体管可以大大提高存储器 件阵列的密度。 本发明还公开了一种使用自对准工艺来制造所述半导体存储 器结构的方法， 非常适用于存储器芯片的制造。 如上所述， 在不偏离本发明精神和范围的情况下， 还可以构成许多有很 大差别的实施例。 应当理解， 除了如所附的权利要求所限定的， 本发明不限 于在说明书中所述的具体实例。

Claims

权 利 要求
1 > 一种半导体存储器结构， 其特征在于， 该结构包括至少一个电阻可 变的存储单元和一个用于对半导体存储器进行操作的隧穿场效应晶体管结 构；
其中， 所述的隧穿场效应晶体管包括至少一个源极、 一个漏极， 一个低 掺杂沟道区和一个栅极； 所述隧穿场效应晶体管的栅极连至字线， 源极连至源线， 所述可变电阻 的两端分别连至位线和所述隧穿场效应晶体管的漏极； 所述的隧穿场效应晶体管的漏极处于一个垂直于水平表面的平台结构的 顶部， 该平台结构采用的是半导体衬底材料， 所述的源极处于所述平台结构 底部向外延伸的衬底内， 所述的低摻杂沟道区处于所述漏极与源极之间， 所 述的栅极将该平台结构的低掺杂区以下的部位覆盖以控制通过沟道区域的源 极与漏极之间的电流大小。
2、 根据权利要求 1 所述的半导体存储器结构， 所述的半导体衬底为单 晶硅、 多晶硅或者绝缘体上的硅。
3、 根据权利要求 1 所述的半导体存储器结构， 其特征在于， 所述的栅 极是一个叠层结构， 其包括至少一个导电层和一个将所述导电层与所述半导 体衬底隔离的绝缘层； 所述的导电层为多晶硅、 无定形硅、 钨金属、 氮化钛、 氮化钽或者金属硅化物， 所述的绝缘层为 Si02、 Hf02、 HfSiO、 HfSiON, SiON或 Al203， 或者它们之中几种的混合物。
4、 根据权利要求 3所述的半导体存储器结构， 其特征在于， 所述的栅 极导电层环绕在垂直的低掺杂沟道区周围形成边墙结构。
5、 根据权利要求 1或 4所述的半导体存储器结构， 其特征在于， 所述 的电阻可变的存储器单元由相变材料构成或者阻变材料构成。
6、 根据权利要求 1或 4所述的半导体存储器结构， 其特征在于， 所述 的电阻可变的存储器单元与所述隧穿场效应晶体管的源极或者漏极相连， 所 述隧穿场效应晶体管的栅极可以控制通过所述存储器单元的电流。
7、 一种半导体存储器结构的制造方法， 其特征在于， 该方法包括下列 步骤： 提供一个半导体衬底； 在所述衬底上注入离子形成第一种掺杂类型的区域； 形成第一层绝缘薄膜； 对第一层绝缘薄膜和半导体衬底进行刻蚀， 形成多个柱状的硅有源区； 依次淀积形成高 K材料介质层、 导电层和多晶硅层； 对多晶硅层进行各向异性刻蚀， 形成围绕垂直的沟道的边墙结构； 进行离子注入形成第二种掺杂类型的区域； 对高 K材料介质层、 导电层和多晶硅层进行刻蚀， 并刻蚀掉剩余的第一 层绝缘薄膜； 淀积形成一层氧化物介质层， 并对其进行刻蚀形成通孔结构； 依次淀积形成阻变材料薄膜和金属层， 再对阻变材料薄膜和金属层进行 刻蚀形成位线。
8、 根据权利要求 7 所述的方法， 其特征在于， 所述的半导体衬底为单 晶硅、 多晶硅或者绝缘体上的硅。
9、根据权利要求 7所述的方法， 其特征在于， 所述第一种掺杂类型为 n 型， 所述的第二种掺杂类型为 p型； 或者所述第一种掺杂类型为 p型， 所述 的第二种掺杂类型为 n型。
10、 根据权利要求 7所述的方法， 其特征在于， 所述的第一层绝缘薄膜 为 Si02、 Si3N4或者它们之间相混合的绝缘材料； 所述的阻变材料薄膜为 Zn02、 CuO、 low-k材料或者 GeSbTe材料； 所述的金属层为 TiN、 Ti、 Ta、 或者 TaN。
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