WO2012130115A1 - 一种倒装发光二极管及其制作方法 - Google Patents

一种倒装发光二极管及其制作方法 Download PDF

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WO2012130115A1
WO2012130115A1 PCT/CN2012/073024 CN2012073024W WO2012130115A1 WO 2012130115 A1 WO2012130115 A1 WO 2012130115A1 CN 2012073024 W CN2012073024 W CN 2012073024W WO 2012130115 A1 WO2012130115 A1 WO 2012130115A1
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layer
light
epitaxial layer
type epitaxial
electrode
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PCT/CN2012/073024
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English (en)
French (fr)
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潘群峰
吴志强
林科闯
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厦门市三安光电科技有限公司
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Priority to US14/004,081 priority Critical patent/US9006768B2/en
Publication of WO2012130115A1 publication Critical patent/WO2012130115A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/10—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a light reflecting structure, e.g. semiconductor Bragg reflector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/382—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending partially in or entirely through the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40—Materials therefor
    • H01L33/42—Transparent materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/44—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the coatings, e.g. passivation layer or anti-reflective coating
    • H01L33/46—Reflective coating, e.g. dielectric Bragg reflector

Definitions

  • the present invention relates to a light emitting diode and a method of fabricating the same, and more particularly to a flip-chip emitting diode and a method of fabricating the same, which can improve the light extraction efficiency of the LED chip. Background technique
  • gallium nitride-based light-emitting diodes has gradually expanded from the fields of display, indication, and key backlight to the field of liquid crystal backlight and illumination, and the luminous efficiency has also increased year by year.
  • some manufacturers have developed thin-film chip structures based on substrate transfer technology, the most representative of which is vertical structure chips, which are generally grown in sapphire.
  • the nitrogen-polar n-GaN has a pyramid shape to greatly improve the light extraction efficiency.
  • the downwardly-reflected reflection can be more easily taken out from the front side.
  • the thin film chip of the vertical structure can obtain a pyramid-like roughened surface, it uses a reflective substrate structure, so that there is almost only a front side light-emitting surface, and the light-emitting ratio of the side surface of the thinner chip of the epitaxial layer is almost negligible.
  • the conventional horizontal structure chip is a transparent substrate structure, which includes at least a front side and four side light-emitting surfaces, and the side light output accounts for a large proportion. If the advantages of both can be combined, the transparent substrate structure and the pyramidal roughened surface can be obtained, and the light extraction efficiency can be maximized.
  • the conventional horizontal structure chip based on the transparent substrate structure generally uses a transparent conductive layer such as indium tin oxide (ITO) as a p-type conductive window, and the resistivity of the transparent conductive layer is higher than that of the metal, and the lateral transmission resistance is large and large.
  • ITO indium tin oxide
  • the current expansion is limited under current operating conditions, so it is necessary to erect a metal extension electrode thereon.
  • the metal extension electrode is disposed on the light-emitting region, which inevitably has the problem of blocking illumination, thereby reducing the light extraction efficiency. Summary of the invention
  • the main object of the present invention is to provide a flip-chip light emitting diode and a manufacturing method thereof, which use a thin film chip based on a substrate transfer technology and a transparent substrate structure, and is disposed by isolating a metal P electrode in a non-light emitting region, thereby maximizing The degree of light extraction efficiency is improved.
  • a flip-chip LED structure includes: a flip-chip thin-film light-emitting element and a transparent permanent substrate, wherein the flip-chip thin-film light-emitting element comprises a light-emitting epitaxial layer, a transparent conductive layer, an isolation layer, a P electrode, and an N electrode;
  • the P-type epitaxial layer, the active layer, and the n-type epitaxial layer are sequentially included, and the luminescent epitaxial layer includes two main surfaces of a p-end surface and an n-end surface, and the luminescent epitaxial layer includes a light-emitting mesa region and a non-light-emitting region;
  • the n-type epitaxial layer has two main surfaces, the first main surface is a light-emitting surface, the second main surface is in contact with the active layer, and the N-electrode is formed on the second main surface of the n-type epitaxial layer of the non-light-emitting region, and the isolation layer is formed on Above the N electrode and the n-type epitaxial layer, a transparent conductive layer is formed over the p-type epitaxial layer of the light-emitting mesa region and over the isolation layer and electrically insulated from the N-electrode and the n-type epitaxial layer by the isolation layer, the P electrode Formed on the transparent conductive layer and disposed within the non-light emitting region;
  • the transparent permanent substrate and the p-end surface of the flip-chip light-emitting element are bonded by a transparent connecting layer.
  • the manufacturing method of the flip-chip LED, the steps thereof include:
  • a light-emitting epitaxial layer on the temporary substrate including a buffer layer, an n-type epitaxial layer, an active layer, and a p-type epitaxial layer;
  • the main feature of the present invention is that the metal extension electrode is isolated and embedded in the non-light-emitting area of the chip on the basis of the integrated structure design of the thin film chip and the transparent substrate, thereby avoiding electrode absorption, and maximally exerting both the thin film chip and the transparent substrate.
  • the structure has the advantage of improving chip light extraction.
  • a part of the P-electrode and the N-electrode may be exposed by etching a portion of the light-emitting epitaxial layer and the transparent conductive layer for the purpose of providing a soldering region for electrically contacting the flip-chip thin-film light-emitting element from the n-end surface.
  • the n-type epitaxial layer may be subjected to wet surface roughening after removing the temporary substrate and the buffer layer.
  • a reflective layer may be plated on the back surface of the transparent permanent substrate to reduce back side light absorption and improve front side light output.
  • FIG. 1 is a cross-sectional structural view of a flip-chip light emitting diode according to an example of the present invention
  • FIG. 2 is a cross-sectional structural view showing a flip-chip light-emitting device of an example of the present invention
  • 3 to 8 are schematic cross-sectional views showing a process of fabricating a flip-chip light emitting diode according to an example of the present invention.
  • a schematic cross-sectional view of a preferred flip-chip LED structure of the present invention includes a flip-chip light-emitting device 100 (Fig. 2) and a sapphire permanent substrate 30, and a flip-chip light-emitting device 1 00 and the sapphire permanent substrate 30 are bonded by a benzocyclobutene (BCB resin) layer 31.
  • BCB resin benzocyclobutene
  • the flip-chip light-emitting device 100 includes: a light-emitting epitaxial layer 101, which is sequentially formed by stacking an n-GaN layer 12, a multiple quantum well active layer 13 and a p-GaN layer 14, and an n-GaN layer 12 and The p-GaN layer 14 is disposed at both ends of the light-emitting epitaxial layer 101, and the light-emitting epitaxial layer 101 includes a light-emitting mesa region 110 and a non-light-emitting region 120.
  • the N electrode 21 is formed on the n-GaN layer 12 of the non-light emitting region 120, and the Si 2 layer 24 is formed as an isolation layer on the N electrode 21 and the n-GaN layer 12; the IT0 layer 23 is formed as a transparent conductive layer in the light emitting layer.
  • the P electrode 22 is formed over the IT0 layer 23 in the range of the non-light emitting region 120.
  • the sapphire permanent substrate 30 is bonded to the p end surface of the flip chip light-emitting element 100 through the benzocyclobutene (BCB resin) layer 31.
  • a mirror layer 32 is formed on the back side of the sapphire permanent substrate 30.
  • a method of fabricating a flip-chip light emitting diode according to the preferred embodiment shown in FIG. 1 is as follows:
  • the epitaxial light-emitting layer is grown, that is, the sapphire substrate 10 is used as a growth substrate, and the buffer layer 11 and the n-GaN layer 12 are sequentially grown thereon by a metal organic chemical vapor deposition (M0CVD) method.
  • M0CVD metal organic chemical vapor deposition
  • a light-emitting mesa is defined, that is, a multi-quantum well active layer 13 and a p-GaN layer 14 are removed by partial reactive ion etching (RIE) to expose a non-light-emitting region of the n-GaN layer 12,
  • RIE partial reactive ion etching
  • the unique region is a non-light-emitting region
  • an N-electrode 21 is formed on the n-GaN layer 12 of the non-light-emitting region, and the material is Cr/Pt/Au.
  • a Si0 2 layer 24 is deposited by plasma enhanced chemical vapor deposition (PECVD) to a thickness of about 500 nm, and the Si0 2 on the light-emitting mesa is removed by etching, so that the remaining Si0 2 layer 14 is covered as an isolation layer.
  • PECVD plasma enhanced chemical vapor deposition
  • indium tin oxide (IT0) was deposited as a transparent conductive layer 23 on the p-GaN layer 14 of the light-emitting mesa region and on the Si0 2 spacer layer 24 by electron beam evaporation, and the thickness was 250 nm.
  • a P electrode 22 is formed over the IT0 layer 23 located in the non-light-emitting region, and the material is Cr/Pt/Au.
  • the light-emitting epitaxial layer is bonded to a sapphire permanent substrate 30 through a benzocyclobutene (BCB resin) layer 31, and a mirror 32 is plated on the back surface of the sapphire permanent substrate 30.
  • the material is A1 and has a thickness of 300 nm.
  • the sapphire growth substrate 10 is removed by laser lift, the buffer layer 11 is removed by reactive ion etching (RIE), and the n-GaN layer 12 of a partial region is etched by photolithography and RIE to expose a portion.
  • the N electrode 21 is for providing a wire portion; the n-GaN layer 12, the multiple quantum well active layer 13, the p-GaN layer 14, and the IT0 layer 23 are partially exposed by photolithography, RIE, and wet etching, and the exposed portion is exposed.
  • the P electrode 22 is used to provide a wire portion.
  • the n-GaN layer 12 may be wet-roughened to form a pyramid surface microstructure, such a structure size and a light-emitting wavelength. Closer, the light extraction efficiency of the LED can be greatly improved.

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Description

一种倒装发光二极管及其制作方法
本申请要求于 2011年 4月 1日提交中国专利局、 申请号为 201110080882.3、 发明名称为 "一种倒装发光二极管及其制作方法" 的中国专利申请的优先权， 其全部内容通过 ^ ]用结合在本申请中。 技术领域
本发明涉及一种发光二极管及其制作方法， 更为具体地， 涉及一种倒装发 光二极管及其制作方法， 可以提高发光二极管芯片的取光效率。 背景技术
近年来， 氮化镓基发光二极管的应用已从显示、 指示、按键背光等领域逐 步扩大到液晶背光和照明领域，发光效率也逐年攀升。 为了提高发光二极管的 驱动功率和发光效率， 一些厂商研发设计出基于衬底转移技术的薄膜 ( Thin-film )芯片结构， 其中最有代表性就是垂直结构芯片， 其做法一般是在 蓝宝石等生长衬底上外延沉积氮化镓基发光材料 ,然后把发光材料层通过键合 技术或电镀倒装黏结到半导体或金属基板等永久衬底上， 再将生长衬底去除， 随后可以通过湿法粗化氮极性的 n-GaN呈金字塔状以大幅提高取光效率。 另 外，通过在发光材料层与永久衬底之间插入一反射镜， 可以将向下发射的反射 从而更容易从正面取出。
然而，垂直结构的薄膜芯片虽然可以获得金字塔状粗化表面，但其釆用了 反射衬底结构， 所以几乎仅有正面一出光面， 因外延层较薄芯片侧面的出光比 例几乎可以忽略。 相比于垂直芯片， 传统的水平结构芯片为透明衬底结构， 其 至少包含正面和四个侧面出光面， 而且侧面的出光占较大的比例。如果能结合 两者的优点， 既是透明衬底结构， 又能获得金字塔状的粗化表面， 就能最大程 度提高取光效率。 然而，传统的基于透明衬底架构的水平结构芯片一般釆用氧 化铟锡（ITO )等透明导电层作为 p型导电窗口， 透明导电层的电阻率相对金 属较高， 横向传输电阻较大， 大电流工作条件下电流扩展受限， 因此需要在其 上架设金属扩展电极，然而在发光区上架设金属扩展电极必然存在遮挡发光的 问题， 从而降低取光效率。 发明内容
本发明的主要目的是提供一种倒装发光二极管及其制作方法，其釆用基于 衬底转移技术的薄膜芯片加透明衬底架构，并且通过将金属 P电极隔离布置于 非发光区， 从而最大程度提高取光效率。 根据实现上述目的的倒装发光二极管结构包括：倒装薄膜发光元件和透明 永久衬底， 其中倒装薄膜发光元件包括发光外延层、 透明导电层、 隔离层、 P 电极和 N电极； 发光外延层依次包括 P型外延层、有源层和 n型外延层， 并且发光外延层 包含 p端面和 n端面两个主表面， 以 p端面为参考，发光外延层包括发光台面 区域和非发光区域；
n型外延层具有两个主表面， 第一主表面为出光面， 第二主表面与有源层 接触， N电极形成于非发光区域的 n型外延层第二主表面上， 隔离层形成于 N 电极和 n型外延层之上，透明导电层形成于发光台面区域的 p型外延层之上以 及隔离层之上并且通过隔离层与 N电极和 n型外延层之间相互电绝缘， P电极 形成于透明导电层之上并且被布置在非发光区域范围内；
透明永久衬底与倒装薄膜发光元件的 p端面通过透明连接层形成粘合。 倒装发光二极管的制作方法， 其步骤包括：
1) 在临时衬底上生长发光外延层， 依次包括緩冲层、 n 型外延层、 有源 层和 p型外延层；
2 )定义发光台面区域： 蚀刻部分区域的 p型外延层和有源层， 暴露出 n 型外延层， 被独刻区域即为非发光区域；
3 )在非发光区域的 n型外延层之上制作 N电极；
4 )制作隔离层， 覆盖非发光区域的 N电极和 n型外延层；
5 )在发光台面区域的 p型外延层之上和隔离层之上制作透明导电层；
6 )在位于非发光区域范围内的透明导电层之上制作 P电极； 7 )将发光外延层与透明永久衬底通过透明连接层形成粘合；
8 )去除临时衬底以及緩冲层， 暴露出 n型外延层表面。 本发明的主要特征是在整合薄膜芯片和透明衬底两种结构设计的基础上， 将金属扩展电极隔离嵌入芯片的非发光区域，从而避免电极吸光， 最大程度发 挥薄膜芯片和透明衬底两种结构在提高芯片取光方面的优势。 在本发明中， 出于器件封装焊线的考虑， 可以通过蚀刻部分发光外延层以 及透明导电层，暴露出部分 P电极和 N电极， 以提供从 n端面电接触倒装薄膜 发光元件的焊接区。 为了提高取光效率， 可以在去除临时衬底和緩冲层后， 针 对 n型外延层进行湿法表面粗化。 另夕卜， 考虑到封装基板的反射率可能不够理 想，可以在透明永久衬底背面加镀一反射层，以减少背面吸光，提高正面出光。
附图说明
通过附图所示， 本发明的上述及其它目的、 特征和优势将更加清晰。 在全 部附图中相同的附图标记指示相同的部分。并未刻意按实际尺寸等比例缩放绘 制附图， 重点在于示出本发明的主旨。
图 1为本发明实例的倒装发光二极管的截面结构图；
图 2为本发明实例的倒装薄膜发光元件的截面结构图；
图 3 至图 8为本发明实例的倒装发光二极管制作过程的截面示意图。 图中各组件符号说明：
10 蓝宝石生长衬底
11 緩冲层
12 n_GnN层
13 多量子阱有源层
14 p-GnN层
21 N电极
22 P电极
23 IT0层
24 S i02层 30 蓝宝石永久^ "底
31 反射镜
100 倒装薄膜发光元件
101 发光外延层
110 发光台面区域
120 非发光区域。 具体实施方式
为使本发明的上述目的、特征和优点能够更加明显易懂， 下面结合附图对 本发明的具体实施方式做详细的说明。
如图 1所示， 为本发明优选的一种倒装发光二极管结构的截面示意图， 其 结构包含倒装薄膜发光元件 100 (如图 2 )和蓝宝石永久衬底 30 , 并且倒装薄 膜发光元件 1 00和蓝宝石永久衬底 30通过苯并环丁烯（ BCB树脂）层 31形成 粘合。 其中， 倒装薄膜发光元件 100包括： 发光外延层 101 , 发光外延层依次 由 n-GaN层 12、 多量子阱有源层 1 3和 p-GaN层 14堆叠而成， n-GaN层 12和 p-GaN层 14居发光外延层 101 两端， 以 p端表面为参考面， 发光外延层 101 包括发光台面区域 110和非发光区域 120。
N电极 21形成于非发光区域 120的 n-GaN层 12之上， S i02层 24作为隔 离层形成于 N电极 21和 n-GaN层 12之上； IT0层 23作为透明导电层形成于 发光台面区域 110的 p-GaN层 14之上以及 S i02隔离层 24之上，并且通过 S i 02 隔离层 24与非发光区域 120的 n-GaN层 12和 N电极 21之间相互电绝缘； P 电极 22形成于非发光区域 120范围内的 IT0层 23之上。
蓝宝石永久衬底 30通过苯并环丁烯 ( BCB树脂 )层 31与倒装薄膜发光元 件 100的 p端面形成粘合。
一反射镜层 32形成于蓝宝石永久衬底 30的背面。
按照图 1所示的优选实施例的倒装发光二极管的制作方法为：
如图 3所示， 生长外延发光层， 即以蓝宝石衬底 10为生长衬底， 釆用金属有 机化学气相沉积（M0CVD )方法在其上依次生长緩冲层 11、 n-GaN层 12、 多量 子阱有源层 1 3和 p-GaN层 14。 如图 4所示， 定义发光台面， 即釆用反应离子蚀刻 （RIE)去除部分区域 的多量子阱有源层 13和 p-GaN层 14,暴露出非发光区域的 n-GaN层 12 ,被独 刻区域即为非发光区域， 在非发光区域的 n-GaN层 12之上制作 N电极 21, 材 料为 Cr/Pt/Au。
如图 5所示，釆用等离子体增强化学气相沉积（PECVD)沉积一 Si02层 24, 厚度约 500nm, 蚀刻去除发光台面上的 Si02, 使得余下的 Si02层 14则作为隔 离层覆盖非发光区域的 N电极 21和 n型外延层 12。
如图 6所示， 釆用电子束蒸发在发光台面区域的 p-GaN层 14之上和 Si02 隔离层 24之上蒸镀一氧化铟锡（IT0)作为透明导电层 23, 厚度 250nm。 在位 于非发光区域范围内的 IT0层 23之上制作 P电极 22, 材料为 Cr/Pt/Au。
如图 7所示， 将发光外延层通过一苯并环丁烯（BCB树脂）层 31粘合到 一蓝宝石永久衬底 30之上， 在蓝宝石永久衬底 30的背面镀一反射镜 32, 其 材料为 A1, 厚度 300nm。
如图 8所示， 釆用激光剥离去除蓝宝石生长衬底 10, 釆用反应离子蚀刻 (RIE)去除緩冲层 11, 釆用光刻和 RIE蚀刻部分区域的 n-GaN层 12, 暴露出 部分 N电极 21用于提供焊线部分；釆用光刻、 RIE和湿法蚀刻部分区域的 n-GaN 层 12、 多量子阱有源层 13、 p-GaN层 14和 IT0层 23, 暴露出部分 P电极 22 用于提供焊线部分。
为了更进一步提高取光效率， 还可以在蓝宝石生长衬底 10 和緩冲层 11 去除后， 针对 n-GaN层 12做湿法粗化， 可以形成金字塔表面微结构， 这样的 结构尺寸与出光的波长较为接近， 可以大幅度提高发光二极管的取光效率。
以上公开的仅为本发明的几个具体实施例， 但是， 本发明并非局限于此， 任何本领域的技术人员能思之的变化都应落入本发明的保护范围。

Claims

权 利 要 求
1. 一种倒装发光二极管， 其特征在于包括： 倒装薄膜发光元件和透明永 久衬底；
所述倒装薄膜发光元件包括发光外延层、 透明导电层、 隔离层、 P电极和 N电极；
所述发光外延层依次包括 P型外延层、有源层和 n型外延层， 并且所述发 光外延层包含 p端面和 n端面两个主表面， 以所述 p端面为参考， 所述发光外 延层包括发光台面区域和非发光区域；
所述 n型外延层具有两个主表面， 第一主表面为出光面， 第二主表面与所 述有源层接触，所述 N电极形成于所述非发光区域的所述 n型外延层的所述第 二主表面上；
所述隔离层形成于所述 N电极和所述 n型外延层之上；
所述透明导电层形成于所述发光台面区域的所述 P型外延层之上和所述 隔离层之上并且通过所述隔离层与所述 N电极和所述 n型外延层之间相互电绝 所述 P电极形成于所述透明导电层之上并且被布置在所述非发光区域范 围内；
所述透明永久衬底与所述倒装薄膜发光元件的所述 P端面通过透明连接 层形成粘合。
2. 根据权利要求 1所述的倒装发光二极管， 其特征在于： 所述 P电极和 所述 N电极分别具有用于从所述 n端面电接触所述倒装薄膜发光元件的焊接 区。
3. 根据权利要求 1所述的倒装发光二极管， 其特征在于： 所述透明永久 衬底背面还包含一反射层。
4. 根据权利要求 1所述的倒装发光二极管， 其特征在于： 所述 n型外延 层的表面为粗化表面。
5. 一种倒装发光二极管的制作方法， 其步骤包括：
1 )在临时衬底上生长发光外延层， 依次包括緩冲层、 n型外延层、 有源 层和 P型外延层；
2 )定义发光台面区域， 蚀刻部分区域的所述 p型外延层和所述有源层， 暴露出所述 n型外延层， 被独刻区域即为非发光区域；
3 )在所述非发光区域的所述 n型外延层之上制作 N电极；
4 )制作隔离层， 覆盖所述非发光区域的所述 N电极和所述 n型外延层；
5 )在所述发光台面区域的所述 p型外延层之上和所述的隔离层之上制作 透明导电层；
6 )在位于所述非发光区域范围内的所述透明导电层之上制作 P电极；
7 )将所述发光外延层与透明永久衬底通过透明连接层形成粘合；
8 )去除所述临时衬底以及所述緩冲层， 暴露出所述 n型外延层表面。
6、 根据权利要求 5所述的制作方法， 其特征在于， 还包括：
9 )蚀刻部分区域的所述 n型外延层， 暴露出部分所述 N电极；
10 )蚀刻部分区域的所述发光外延层和透明导电层， 暴露出部分所述 P 电极。
7、 根据权利要求 5所述的制作方法， 其特征在于： 还包括在去除临时衬 底及緩冲层后釆用湿法蚀刻所述 n型外延层以形成粗化表面。
8、 根据权利要求 5所述的制作方法， 其特征在于： 还包括在所述永久透 明衬底的背面镀一反射层。
9、 根据权利要求 5所述的制作方法， 其特征在于：
所述透明永久衬底为蓝宝石永久衬底。
10、 根据权利要求 5所述的制作方法， 其特征在于：
所述透明连接层为苯并环丁烯层。
PCT/CN2012/073024 2011-04-01 2012-03-26 一种倒装发光二极管及其制作方法 WO2012130115A1 (zh)

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