WO2012129823A1 - Boost级联升压电路 - Google Patents

Boost级联升压电路 Download PDF

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Publication number
WO2012129823A1
WO2012129823A1 PCT/CN2011/072789 CN2011072789W WO2012129823A1 WO 2012129823 A1 WO2012129823 A1 WO 2012129823A1 CN 2011072789 W CN2011072789 W CN 2011072789W WO 2012129823 A1 WO2012129823 A1 WO 2012129823A1
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Prior art keywords
boost
diode
inductor
stage
circuit
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PCT/CN2011/072789
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English (en)
French (fr)
Inventor
郭东胜
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TCL China Star Optoelectronics Technology Co Ltd
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Shenzhen China Star Optoelectronics Technology Co Ltd
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Priority to US13/131,096 priority Critical patent/US8493039B2/en
Priority to CN201180009520.3A priority patent/CN102893506B/zh
Publication of WO2012129823A1 publication Critical patent/WO2012129823A1/zh
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
    • H02M1/007—Plural converter units in cascade

Definitions

  • the invention relates to a Boost cascade boost circuit.
  • Boost boost circuit In the DC-DC circuit, the Boost boost circuit and the Buck step-down circuit are used in various fields.
  • a well-known Boost boost circuit is shown in FIG. 1 , which includes an input terminal Vin, an inductor L, and a A diode D, a switching transistor Q, a voltage stabilizing filter capacitor C, a pulse width modulation (PWM) generator (not shown) and an output terminal Vout.
  • the working principle of the Boost boosting circuit 100 is as follows: when the PWM signal is in the high level period Ton, the switching transistor Q is turned on, and the diode D is turned off. At this time, the power source charges the inductor L through the path 14; when the PWM signal is During the low-level period Toff, the switching transistor Q is turned off, and the diode D is turned on, at which time the inductor L releases energy through the path 12.
  • VL is related to the duty cycle D, and is considered by the energy conservation law in the inductor current continuous mode (CCM mode).
  • the switching transistor Q when the known Boost booster circuit 100 is raised to a higher voltage, the switching transistor Q is capable of withstanding the voltage of Vout, and thus faces the problem of the withstand voltage limitation of the switching transistor Q. Further, from the above formula, it is understood that the duty ratio D needs to be increased (i.e., the high-level period Ton is extended) when it is raised to a higher voltage. However, when the high-level period Ton approaches the period T, the switching transistor Q may not be turned off in such a short time, thus causing a limitation that the duty ratio D cannot be too close to 1, causing the well-known Boost boosting circuit to fail. Achieve the desired results.
  • a Boost cascade boost circuit includes a first stage boost boost circuit, an output terminal and a voltage stabilizing filter capacitor, wherein the stabilized filter capacitor is grounded at one end and the other end is connected to the output terminal
  • the primary Boost boost circuit includes an input terminal, a PWM generator, a first inductor, a first diode and a first switch transistor, the first inductor being connected to the input end at one end, and the other end Connecting the anode of the first diode, the control end of the first switch tube is connected to the PWM generator, the first conductive end is grounded, and the second conductive end is connected to the anode of the first diode
  • the Boost cascade boost circuit further includes a second-stage boost boost circuit, and the second-stage boost boost circuit includes a second inductor, a second switch, a first series diode, and a second a first parallel diode, one end of the second inductor is connected to the cath
  • the PWM generator controls the two switching tubes to be turned on or off at the same time.
  • the two switching transistors are field effect transistors.
  • the two switching transistors are all N-type field effect transistors.
  • the field effect transistor is a metal oxide semiconductor field effect transistor.
  • control end of each of the switching tubes is a gate
  • the first conducting end is a source
  • the second conducting end is a drain
  • a Boost cascade boost circuit includes a first stage boost boost circuit, an output terminal and a voltage stabilizing filter capacitor, wherein the stabilized filter capacitor is grounded at one end and the other end is connected to the output terminal,
  • the first-stage Boost boosting circuit includes an input terminal, a PWM generator, a first inductor and a first switching transistor, wherein the Boost cascade boosting circuit further comprises a second-stage boost boosting circuit.
  • the second stage boost boosting circuit includes a second inductor and a second switching transistor, and the PWM generator controls the first switching transistor and the second switching transistor to be simultaneously turned on or simultaneously turned off when two
  • the input power supply charges the two inductors through two paths respectively; when the two switches are turned off, the input power is connected to the output through the first inductor and the second inductor.
  • the two inductors release energy; the two switches together share the voltage at the output.
  • a Boost cascade boost circuit includes a first stage boost boost circuit, an output terminal and a voltage stabilizing filter capacitor, wherein the stabilized filter capacitor is grounded at one end and the other end is connected to the output terminal,
  • the first-stage Boost boosting circuit includes an input terminal, a PWM generator, a first inductor and a first switching transistor, wherein the Boost cascade boosting circuit further comprises a second-stage boost boosting circuit.
  • the second stage boost boosting circuit includes a second inductor and a second switching transistor, and the PWM generator controls the first switching transistor and the second switching transistor to be simultaneously turned on or simultaneously turned off when two
  • the input end power is grounded via the first inductor and the first switch tube, and is also grounded via the second inductor, the second switch tube, and the first switch tube; when the two switch tubes are turned off, the input end
  • the power supply is sequentially connected to the output terminal via the first inductor and the second inductor.
  • the first switch tube and the second switch tube are field effect transistors.
  • the first switch tube and the second switch tube are both N-type field effect transistors.
  • the Boost cascade boost circuit further includes a third stage boost boost circuit
  • the third stage boost boost circuit includes a third inductor and a third switch
  • the PWM generator controls The three switching tubes are simultaneously turned on or off at the same time.
  • the input terminal power is grounded via the first inductor and the first switching tube, and also via the second inductor, the second switching tube, and
  • the first switch is grounded, and is also grounded via the third inductor, the third switch, the second switch, and the first switch; when the two switches are turned off, the input power is sequentially passed through the first inductor,
  • the second inductor and the third inductor are connected to the output.
  • the first stage boost boost circuit further includes a first diode, the first inductor is connected to the input end at one end, and the anode of the first diode is connected to the other end, the first switch tube
  • the control terminal is connected to the PWM generator, the first conductive terminal is grounded, the second conductive terminal is connected to the anode of the first diode
  • the second-stage boost boost circuit further includes a first series diode and a first a parallel diode, one end of the second inductor is connected to the cathode of the first diode, the other end is connected to the anode of the first series diode, and the control end of the second switch is connected to the PWM generator, a conductive connection is connected to the second conductive end of the first switching transistor, a second conductive end of the second switching transistor is connected to an anode of the first series diode, and an anode connection of the first parallel diode At the input end, the cathode is connected to the cathode
  • the three switching transistors are all field effect transistors.
  • the three switching transistors are all N-type field effect transistors.
  • control ends of the three switch tubes are gates, the first conductive terminal is a source, and the second conductive terminal is a drain.
  • the first stage boost boost circuit further includes a first diode, the first inductor is connected to the input end at one end, and the anode of the first diode is connected to the other end, the first switch tube
  • the control terminal is connected to the PWM generator, the first conduction end is grounded, and the second conduction end is connected to the anode of the first diode.
  • the Boost cascade boost circuit further comprises a third stage boost boost circuit, ...
  • an Nth-stage Boost boost circuit N is a positive integer greater than 3, except for the first-stage boost boost circuit, other levels of boost boost circuits include an inductor, a parallel diode, a series diode, and a switching transistor, one end of the inductor is connected to the cathode of the series diode of the upper stage, the other end is connected to the anode of the series diode of the current stage, the anode of the parallel diode is connected to the input end, and the cathode is connected to the series diode of the upper stage a cathode, the control end of the switch tube is electrically connected to the PWM generator, the first conductive end is connected to the second conductive end of the switch tube of the upper stage, and the second conductive end of the current switch tube is connected To this level United anode of the diode, the series diode circuit stage N of Boost cathode connected to the output terminal.
  • the PWM generator controls each of the switching tubes to be turned on or off at the same time.
  • each of the switching transistors is an N-type field effect transistor.
  • control end of each of the switch tubes is a gate
  • the first conductive end is a source
  • the second conductive end is a drain
  • the Boost cascade boost circuit of the present invention includes a second stage, a third stage, or an Nth stage boost boost circuit, and multiple inductors are realized by turning on and off of a plurality of switching tubes.
  • the device can charge and store energy and release energy, and utilizes multiple switch tubes to share the voltage at the output end, solving the problem of single switch tube withstand voltage and duty cycle D limitation. Therefore, a general-purpose switch tube can be selected to achieve high voltage output. Requirements.
  • Figure 1 is a diagram of a known Boost boost circuit.
  • FIG. 2 is a circuit diagram of a first embodiment of a Boost cascade boost circuit of the present invention.
  • FIG. 3 is a circuit diagram of a second embodiment of a Boost cascade boost circuit of the present invention.
  • FIG. 4 is a circuit diagram of a third embodiment of a Boost cascade boost circuit of the present invention.
  • the Boost cascade boost circuit 200 includes a first stage boost boost circuit and a second stage boost boost circuit.
  • the regulator filter capacitor C is grounded at one end and connected to the output terminal Vout at the other end.
  • the first stage boost boosting circuit includes an input terminal Vin, a first inductor L1, a first diode D1, a first switching transistor Q1, and a PWM generator (not shown).
  • One end of the first inductor L1 is connected to the input terminal Vin, and the other end is connected to the anode of the first diode D1.
  • the control terminal G1 of the first switch transistor Q1 is connected to the PWM generator, the first conductive terminal is grounded, and the second conductive terminal is connected to the anode of the first diode D1.
  • the signal output by the PWM generator has a high-level period Ton and a low-level period Toff in the period T, wherein the ratio of the high-level period Ton to the period T is referred to as the duty ratio D.
  • the second stage boost boost circuit includes a second inductor L2, a first parallel diode Dp1, a first series diode Ds1, and a second switch tube Q2.
  • the second inductor L2 has one end connected to the cathode of the first diode D1 and the other end connected to the anode of the first series diode Ds1.
  • the cathode of the first series diode Ds1 is connected to the output terminal Vout.
  • the anode of the first parallel diode Dp1 is connected to the input terminal Vin, and the cathode is connected to the cathode of the first diode D1.
  • the control terminal G2 of the second switching transistor Q2 is connected to the PWM generator, the first conducting terminal 202 is connected to the second conducting end of the first switching transistor Q1, and the second conducting end of the second switching transistor Q2
  • the terminal 204 is connected to the anode of the first series diode Ds1.
  • the first switch transistor Q1 and the second switch transistor Q2 are N-type field effect transistors (field effect) Transistor, FET), more preferably a metal oxide semiconductor field effect transistor (MOSFET). Further, the control terminals G1 and G2 of the two switching transistors Q1 and Q2 are gates, the first conduction terminal is a source, and the second conduction terminal is a drain.
  • field effect field effect
  • MOSFET metal oxide semiconductor field effect transistor
  • the PWM generator controls the first switch tube Q1 and the second switch tube Q2 to be turned on or off at the same time.
  • the operating principle of the Boost dual-cascade boosting circuit is as follows: when the PWM signal is a high level Ton, the first switching transistor Q1 and the second switching transistor Q2 are turned on, and the first parallel diode Dp1 is turned on. And the first diode D1 and the first series diode Ds1 are turned off. At this time, the power source charges the first inductor L1 through the path 22, and the power source charges the second inductor L2 through the path 24.
  • the first switch transistor Q1 and the second switch transistor Q2 are turned off, the first diode D1 and the first series diode Ds1 are turned on, and the first The parallel diode Dp1 is turned off.
  • the first switch tube Q1 The voltage that Q1 is subjected to is Vin+VL1
  • the voltage that the second switching transistor Q2 is subjected to is the voltage value VL2 across the inductor L2.
  • the first switch tube Q1 and the second switch tube Q2 jointly bear the voltage of the output terminal Vout, which solves the problem of the single switch tube withstand voltage and the duty ratio D limit, and can be achieved by using a general-purpose switch tube. High voltage output requirements.
  • Boost cascade boost circuit 300 further includes a second-stage Boost cascade boost circuit and a third portion, in addition to the first-stage Boost cascade boost circuit, the regulated filter capacitor C and the output terminal Vout.
  • Level Boost boost circuit includes a second inductor L2, a first parallel diode Dp1, a first series diode Ds2, and a second switching transistor Q2.
  • the third stage boost boosting circuit includes a third inductor L3, a second parallel diode Dp2, a second series diode Ds2, and a third switching transistor Q3.
  • the second inductor L2 has one end connected to the cathode of the first diode D1 and the other end connected to the anode of the first series diode Ds1.
  • the anode of the first parallel diode Dp1 is connected to the input terminal Vin, and the cathode is connected to the cathode of the first diode D1.
  • the control terminal G2 of the second switching transistor Q2 is connected to the PWM generator, the first conducting end is connected to the second conducting end of the first switching transistor Q1, and the second conducting end of the second switching transistor Q2 is connected. The terminal is connected to the anode of the first series diode Ds1.
  • the third inductor L3 is connected to the cathode of the first series diode Ds1, and the other end is connected to the anode of the second series diode Ds2.
  • the cathode of the second series diode Ds2 is connected to the output terminal Vout.
  • the anode of the second parallel diode Dp2 is connected to the input terminal Vin, and the cathode is connected to the cathode of the first series diode Ds1.
  • the control terminal G3 of the third switch transistor Q3 is electrically connected to the PWM generator, the first conductive terminal is connected to the drain of the second switch transistor Q2, and the second conductive terminal of the third switch transistor Q3 is connected to The anode of the second series diode Ds2.
  • the PWM generator controls the first switch tube Q1, the second switch tube Q2, and the third switch tube Q3 to be turned on or off at the same time.
  • the operating principle of the Boost three-cascade booster circuit is as follows: when the PWM generator signal is at a high level Ton, the first switch transistor Q1, the second switch transistor Q2, and the third switch transistor Q3 are turned on. The first parallel diode Dp1 and the second parallel diode Dp2 are turned on, and the first diode D1, the first series diode Ds1, and the second series diode Ds2 are turned off.
  • the power source charges the first inductor L1 through the path 32; the power source charges the second inductor L2 through the path 34; the power source charges the third inductor L3 through the path 36 to store energy.
  • the first switch transistor Q1, the second switch transistor Q2, and the third switch transistor Q3 are turned off, the first diode D1 and the first series diode Ds1 And the second series diode Ds2 is turned on, and the first parallel diode Dp1 and the second parallel diode Dp2 are turned off.
  • the first switch tube The voltage that Q1 receives is Vin+VL1
  • the voltage that the second switch Q2 receives is the voltage value VL2 across the inductor L2
  • the voltage that the third switch Q2 receives is the voltage value VL3 across the inductor L3.
  • Boost cascade boost circuit 400 can be analogized in the above manner, except that the first, second, and third stages of the Boost cascade boost circuit, the regulated filter capacitor C, and the output terminal Vout are included.
  • the method further includes a fourth stage boosting circuit (not shown), a fifth stage boosting circuit (not shown), ..., an N-1th stage boosting circuit, and an Nth stage boosting circuit.
  • N is a positive integer greater than three, and each stage of the boosting circuit comprises an inductor, a parallel diode, a series diode and a switching tube.
  • One end of the inductor is connected to the cathode of the series diode of the upper stage, the other end is connected to the anode of the series diode of the current stage, the anode of the parallel diode is connected to the input end, and the cathode is connected to the cathode of the series diode of the upper stage.
  • the control end of the switch tube is electrically connected to the PWM generator, the first conduction end is connected to the second conduction end of the switch tube of the upper stage, and the second conduction end of the current switch tube is connected to the series diode of the current stage
  • the anode, the cathode of the series diode of the Nth stage boost boost circuit is connected to the output.
  • the N-cascade boosting circuit includes an inductor LN, a parallel diode DpN-1, a series diode DsN-1, and a switching transistor QN.
  • One end of the inductor LN is connected to the cathode of the series diode DsN-2 of the N-1th stage, and the other end is connected to the anode of the series diode DsN-1 of the present stage.
  • the anode of the parallel diode DpN-1 is connected to the input terminal Vin, and the cathode is connected to the cathode of the series diode DsN-2 of the N-1th stage.
  • the control terminal GN of the switch transistor QN is electrically connected to the PWM generator, and the first conductive terminal is connected to the second conductive terminal of the N-1th switching transistor QN-1, and the second switching transistor QN is The conductive terminal is connected to the anode of the series diode DsN-1 of the present stage.
  • the cathode of the series diode DsN-1 of the Nth stage Boost cascade boost circuit is connected to the output terminal Vout.
  • Vin+VL1 the voltage that Q1 is subjected to
  • the voltages of the other switches Q2, Q3, ..., QN are only the voltage values VL2, VL3, ... VLN across the respective inductors L2, L3, ... LN.
  • the boost voltage will not be limited by the withstand voltage of the switch tube (such as MOSFET).
  • the output terminal Vout can rise to a very high voltage, and it is not necessary to open the duty ratio D to a large value.

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Description

Boost级联升压电路 技术领域
本发明是有关于一种Boost级联升压电路。
 背景技术
在DC-DC的电路中，Boost升压电路和Buck降压电路应用在多个领域，一种公知的Boost升压电路如图1所示，其包括一输入端Vin、一电感器L、一二极管D、一开关管Q、一稳压滤波电容C、一脉冲宽度调制(PWM)发生器(图未示)及一输出端Vout。上述PWM发生器输出的PWM信号在一周期T中具有高电平期间Ton及低电平期间Toff，其中高电平期间Ton占周期T的比例称为占空比D（D＝Ton/T）。
上述Boost升压电路100的工作原理如下：当PWM信号为高电平期间Ton时，开关管Q导通、二极管D截止，此时电源通过路径14对电感器L充电储能；当PWM信号为低电平期间Toff时，开关管Q截止，二极管D导通，此时电感器L通过路径12释放能量。假设此时的电感器L产生的感应电动势为VL，则Vout=Vin+VL，从而达到升压的效果。而VL与Vin以及占空比D相关，通过能量守恒定律，以电感电流连续模式（CCM模式）来考量，最终可以推导出Vout=Vin/（1-D）。
然而，要通过公知的Boost升压电路100升到更高的电压时，开关管Q要能够承受Vout的电压，因此就会面临到开关管Q的耐压限制问题。此外，由上述公式可知，要升到更高电压时，占空比D需要增大（即延长高电平期间Ton）。然而，当，高电平期间Ton接近周期T时，开关管Q可能无法在这么短的时间关断，因此产生了占空比D不能太接近1的限制，而导致公知的Boost升压电路不能达到预期的效果。
 技术问题
本发明的目的在于提供一种Boost级联升压电路，其通过串联若干个电感器及配合的开关管，解决了上述场开关管耐压不足以及占空比D限制的问题。
 技术解决方案
为达上述的目的，本发明采取以下技术方案。一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器、一第一二极管和一第一开关管，所述第一电感器一端连接所述输入端，另一端连接所述第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器、一第二开关管、一第一串联二极管和一第一并联二极管，上述第二电感器一端连接所述第一二极管的阴极，另一端连接所述第一串联二极管的阳极，所述第一串联二极管的阴极连接所述输出端，所述第二开关管的控制端连接至所述PWM发生器，第一导通端连接至所述第一开关管的第二导通端，第二开关管的第二导通端连接至所述第一串联二极管的阳极，所述第一并联二极管的阳极连接所述输入端，阴极连接所述第一二极管的阴极。
优选地，所述PWM发生器控制所述两个开关管同时导通或同时关断。
优选地，所述两个开关管都是场效应晶体管。
优选地，所述两个开关管都是N型场效应晶体管。
优选地，所述场效应晶体管是金属氧化物半导体场效应管。
优选地，所述各級开关管之控制端为栅极，第一导通端为源极，第二导通端为漏极。
一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器和一第一开关管，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器和一第二开关管，所述PWM发生器控制所述第一开关管及第二开关管同时导通或同时关断，当两个开关管导通时，输入端电源通过两条路径分别对两个电感器充电储能；当两个开关管关断时，输入端电源经由第一电感器、第二电感器连接到输出端，两个电感器释放能量；上述两个开关管共同承担输出端的电压。
一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器和一第一开关管，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器和一第二开关管，所述PWM发生器控制所述第一开关管及第二开关管同时导通或同时关断，当两个开关管导通时，输入端电源经由第一电感器和第一开关管接地，也经由第二电感器、第二开关管和第一开关管接地；当两个开关管关断时，输入端电源依序经由第一电感器、第二电感器连接到输出端。
优选地，所述第一开关管及第二开关管都是场效应晶体管。
优选地，所述第一开关管及第二开关管都是N型场效应晶体管。
优选地，所述Boost级联升压电路进一步包括一第三级Boost升压电路，所述第三级Boost升压电路包括一第三电感器和一第三开关管，所述PWM发生器控制所述三个开关管同时导通或同时关断，当三个开关管导通时，输入端电源经由第一电感器和第一开关管接地，也经由第二电感器、第二开关管和第一开关管接地，还经由第三电感器、第三开关管、第二开关管和第一开关管接地；当两个开关管关断时，输入端电源依序经由第一电感器、第二电感器、第三电感器连接到输出端。
优选地，所述第一级Boost升压电路进一步包括一第一二极管，所述第一电感器一端连接输入端，另一端连接第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，上述第二级Boost升压电路进一步包括一第一串联二极管和一第一并联二极管，上述第二电感器一端连接所述第一二极管的阴极，另一端连接所述第一串联二极管的阳极，所述第二开关管的控制端连接至所述PWM发生器，第一导通端连接至所述第一开关管的第二导通端，第二开关管的第二导通端连接至所述第一串联二极管的阳极，所述第一并联二极管的阳极连接所述输入端，阴极连接所述第一二极管的阴极，上述第三级Boost升压电路进一步包括一第二串联二极管和一第二并联二极管，所述第三电感器的一端连接第一串联二极管的阴极，另一端连接第二串联二极管的阳极，所述第二串联二极管的阴极连接所述输出端，所述第三开关管的控制端电性连接至所述PWM发生器，第一导通端连接至第二开关管的第二导通端，第三开关管的第二导通端连接至所述第二串联二极管的阳极，所述第二并联二极管的阳极连接所述输入端，阴极连接所述第一串联二极管的阴极。
优选地，所述三个开关管都是场效应晶体管。
优选地，所述三个开关管都是N型场效应晶体管。
优选地，所述三个开关管的控制端为栅极，第一导通端为源极，第二导通端为漏极。
优选地，所述第一级Boost升压电路进一步包括一第一二极管，所述第一电感器一端连接输入端，另一端连接第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，上述Boost级联升压电路进一步包括一第三级Boost升压电路，……，一第N级Boost升压电路，N为大于3的正整数，除了第一级Boost升压电路以外，其它各级Boost升压电路都包括一电感器、一并联二极管、一串联二极管以及一开关管，所述电感器的一端连接上一级的串联二极管的阴极，另一端连接本级串联二极管的阳极，所述并联二极管的阳极连接所述输入端，阴极连接上一级的串联二极管的阴极，所述开关管的控制端电性连接至所述PWM发生器，第一导通端连接至上一级的开关管的第二导通端，本级开关管的第二导通端连接至本级串联二极管的阳极，第N级Boost升压电路的串联二极管的阴极连接到输出端。
优选地，所述PWM发生器控制每个开关管同时导通或同时关断。
优选地，所述每个开关管都是N型场效应晶体管。
优选地，所述每个开关管的控制端为栅极，第一导通端为源极，第二导通端为漏极。
 有益效果
相较于现有技术，本发明Boost级联升压电路一步包括第二级、第三级、或第N级Boost升压电路，通过多个开关管的导通与关断来实现多个电感器的充电储能与释放能量，并利用多个开关管共同承担输出端的电压，解决了单一开关管耐压以及占空比D限制的问题，因此可选用一般规格的开关管来达到高电压输出的要求。
附图说明
图1为公知的Boost升压电路图。
图2为本发明Boost级联升压电路的第一实施方式的电路图。
图3为本发明Boost级联升压电路的第二实施方式的电路图。
图4为本发明Boost级联升压电路的第三实施方式的电路图。
 本发明的最佳实施方式
请参照图2，是本发明Boost级联升压电路的第一实施方式的电路图，所述Boost级联升压电路200包括一第一级Boost升压电路、一第二级Boost升压电路、一稳压滤波电容C和一输出端Vout。上述稳压滤波电容C一端接地，另一端连接至输出端Vout。所述第一级Boost升压电路包括一输入端Vin、一第一电感器L1、一第一二极管D1、一第一开关管Q1和一PWM发生器(图未示)。所述第一电感器L1的一端连接所述输入端Vin，另一端连接所述第一二极管D1的阳极。所述第一开关管Q1的控制端G1连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管D1的阳极。
所述PWM发生器输出的信号在周期T中具有高电平期间Ton及低电平期间Toff，其中高电平期间Ton占周期T的比例称为占空比D。
所述第二级Boost升压电路包括一第二电感器L2、一第一并联二极管Dp1、一第一串联二极管Ds1及一第二开关管Q2。所述第二电感器L2一端连接所述第一二极管D1的阴极，另一端连接所述第一串联二极管Ds1的阳极。所述第一串联二极管Ds1的阴极连接输出端Vout。所述第一并联二极管Dp1的阳极连接所述输入端Vin，阴极连接所述第一二极管D1的阴极。所述第二开关管Q2的控制端G2连接至所述PWM发生器，第一导通端202连接至所述第一开关管Q1的第二导通端，第二开关管Q2的第二导通端204连接至所述第一串联二极管Ds1的阳极。
具体而言,所述第一开关管Q1及第二开关管Q2是N型场效应晶体管(field effect transistor, FET)，更优选的为金属氧化物半导体场效应管(MOSFET)。进一步地说，所述两个开关管Q1、Q2的控制端G1、G2为栅极，第一导通端为源极、第二导通端为漏极。
所述PWM发生器控制所述第一开关管Q1及第二开关管Q2同时导通或同时关断。所述Boost双级联升压电路的工作原理如下：所述PWM信号为高电平Ton时，所述第一开关管Q1及第二开关管Q2导通，所述第一并联二极管Dp1导通，且所述第一二极管D1及第一串联二极管Ds1截止。此时电源通过路径22对所述第一电感器L1充电储能、电源通过路径24对所述第二电感器L2充电储能。
所述PWM信号为低电平Toff时，所述第一开关管Q1及第二开关管Q2关断，所述第一二极管D1及第一串联二极管Ds1为导通，且所述第一并联二极管Dp1截止。此时所述第一电感器L1及第二电感器L2通过路径26释放能量。设此时的第一电感器L1和第二电感器L2产生的感应电动势为VL1和VL2，则Vout=Vin+VL1+VL2。
相较于现有技术，第一开关管 Q1承受的电压为Vin+VL1，第二开关管Q2承受的电压为电感器L2两端的电压值VL2。这样在升高压时，第一开关管Q1和第二开关管Q2共同承担输出端Vout的电压，解决了单一开关管耐压以及占空比D限制的问题，可选用一般规格的开关管来达到高电压输出的要求。
参照图3，是本发明Boost级联升压电路的第二实施方式的电路图。除了上述具有二级的Boost级联升压电路200之外，本发明还提供了一种具有三级的Boost级联升压电路300。所述Boost级联升压电路300除了包括上述第一级Boost级联升压电路、稳压滤波电容C和输出端Vout外，还进一步包括一第二级Boost级联升压电路和一第三级Boost升压电路。所述第二级Boost级联升压电路包括一第二电感器L2、一第一并联二极管Dp1、一第一串联二极管Ds2及一第二开关管Q2。所述第三级Boost升压电路包括一第三电感器L3、一第二并联二极管Dp2、一第二串联二极管Ds2及一第三开关管Q3。
上述第二电感器L2一端连接所述第一二极管D1的阴极，另一端连接所述第一串联二极管Ds1的阳极。所述第一并联二极管Dp1的阳极连接所述输入端Vin，阴极连接所述第一二极管D1的阴极。所述第二开关管Q2的控制端G2连接至所述PWM发生器，第一导通端连接至所述第一开关管Q1的第二导通端，第二开关管Q2的第二导通端连接至所述第一串联二极管Ds1的阳极。
所述第三电感器L3的一端连接到第一串联二极管Ds1的阴极，另一端连接第二串联二极管Ds2的阳极。所述第二串联二极管Ds2的阴极连接输出端Vout。所述第二并联二极管Dp2的阳极连接所述输入端Vin，阴极连接所述第一串联二极管Ds1的阴极。所述第三开关管Q3的控制端G3电性连接至所述PWM发生器，第一导通端连接至第二开关管Q2的漏极，第三开关管Q3的第二导通端连接至所述第二串联二极管Ds2的阳极。
同样地，所述PWM发生器控制所述第一开关管Q1、第二开关管Q2及第三开关管Q3同时导通或同时关断。上述Boost三级联升压电路的工作原理如下：当所述PWM发生器信号为高电平Ton时，所述第一开关管Q1、第二开关管Q2及第三开关管Q3为导通，所述第一并联二极管Dp1及第二并联二极管Dp2导通，且所述第一二极管D1、第一串联二极管Ds1及第二串联二极管Ds2截止。此时电源通过路径32对所述第一电感器L1充电储能；电源通过路径34对所述第二电感器L2充电储能；电源通过路径36对所述第三电感器L3充电储能。
当所述PWM发生器信号为低电平Toff时，所述第一开关管Q1、第二开关管Q2及第三开关管Q3关断，所述第一二极管D1、第一串联二极管Ds1及第二串联二极管Ds2为导通，且所述第一并联二极管Dp1及第二并联二极管Dp2截止。此时所述第一电感器L1、第二电感器L2及第三电感器L3通过路径38释放能量。设此时的第一电感器L1、第二电感器L2和第三电感器L3产生的感应电动势为VL1 、VL2和VL3，则Vout=Vin+VL1+VL2+VL3。此时，第一开关管 Q1承受的电压为Vin+VL1，第二开关管Q2承受的电压为电感器L2两端的电压值VL2，第三开关管Q2承受的电压为电感器L3两端的电压值VL3。这样在升高压时，第一、第二、第三开关管Q1、Q2、Q3共同承担输出端Vout的电压。
参照图4，是本发明Boost级联升压电路的第三实施方式的电路图。同样地，所述Boost级联升压电路400可依上述方式类推，其除了包括上述第一、第二、第三级的Boost级联升压电路、稳压滤波电容C和输出端Vout之外，还进一步包括一第四级升压电路(图未示)、一第五级升压电路(图未示)、……、一第N-1级升压电路、一第N级升压电路。其中，N为大于三的正整数，各级联升压电路都包括一电感器、一并联二极管、一串联二极管以及一开关管。
所述电感器一端连接上一级的串联二极管的阴极，另一端连接本级串联二极管的阳极，所述并联二极管的阳极连接所述输入端，阴极连接上一级的串联二极管的阴极，所述开关管的控制端电性连接至所述PWM发生器，第一导通端连接至上一级的开关管的第二导通端，本级开关管的第二导通端连接至本级串联二极管的阳极，第N级Boost升压电路的串联二极管的阴极连接到输出端。
举最后一级升压电路，即第 N级联升压电路为例，第 N级联升压电路包括一电感器LN、一并联二极管DpN-1、一串联二极管DsN-1以及一开关管QN。
所述电感器LN的一端连接第N-1级的串联二极管DsN-2的阴极，另一端连接本级串联二极管DsN-1的阳极。所述并联二极管DpN-1的阳极连接所述输入端Vin，阴极连接第N-1级的串联二极管DsN-2的阴极。所述开关管QN的控制端GN电性连接至所述PWM发生器，第一导通端连接至第N-1级的开关管QN-1的第二导通端，开关管QN的第二导通端连接至本级串联二极管DsN-1的阳极。第N级Boost级联升压电路的串联二极管DsN-1的阴极连接到输出端Vout。
参考前述工作原理，可推得Vout=Vin+VL1+VL2+…+VLn。此时，除了第一开关管 Q1承受的电压为Vin+VL1外，其它每个开关管Q2、Q3、……QN的承受的电压只为相应电感器L2、L3、……LN两端的电压值VL2、VL3、……VLN。这样在升高压时，不会有任何一颗开关管承担输出端Vout全部的电压，升高压不会受到开关管（如MOSFET）耐压的限制。另外，在相同的占空比D的情况下，输出端Vout可以升到很高的电压，也就不需要将占空比D开到很大。
虽然本发明已用优选实施例揭露如上，然其并非用以限定本发明，本发明所属技术领域的技术人员，在不脱离本发明的精神和范围内，当可作各种的更动与润饰，因此本发明的保护范围当视后附的权利要求书所界定的为准。
 本发明的实施方式
工业实用性
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Claims (19)

  1. 一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器、一第一二极管和一第一开关管，所述第一电感器一端连接所述输入端，另一端连接所述第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器、一第二开关管、一第一串联二极管和一第一并联二极管，上述第二电感器一端连接所述第一二极管的阴极，另一端连接所述第一串联二极管的阳极，所述第一串联二极管的阴极连接所述输出端，所述第二开关管的控制端连接至所述PWM发生器，第一导通端连接至所述第一开关管的第二导通端，第二开关管的第二导通端连接至所述第一串联二极管的阳极，所述第一并联二极管的阳极连接所述输入端，阴极连接所述第一二极管的阴极。
  2. 根据权利要求1所述的Boost级联升压电路，其特征在于：所述PWM发生器控制所述两个开关管同时导通或同时关断。
  3. 根据权利要求2所述的Boost级联升压电路，其特征在于：所述两个开关管都是场效应晶体管。
  4. 根据权利要求3所述的Boost级联升压电路，其特征在于：所述两个开关管都是N型场效应晶体管。
  5. 根据权利要求3所述的Boost级联升压电路，其特征在于：所述场效应晶体管是金属氧化物半导体场效应管。
  6. 根据权利要求3所述的Boost级联升压电路，其特征在于：所述各級开关管之控制端为栅极，第一导通端为源极，第二导通端为漏极。
  7. 一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器和一第一开关管，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器和一第二开关管，所述PWM发生器控制所述第一开关管及第二开关管同时导通或同时关断，当两个开关管导通时，输入端电源通过两条路径分别对两个电感器充电储能；当两个开关管关断时，输入端电源经由第一电感器、第二电感器连接到输出端，两个电感器释放能量；上述两个开关管共同承担输出端的电压。
  8. 一种Boost级联升压电路，其包括一第一级Boost升压电路、一输出端和一稳压滤波电容，上述稳压滤波电容一端接地，另一端连接至所述输出端，所述第一级Boost升压电路包括一输入端、一PWM发生器、一第一电感器和一第一开关管，其特征在于：上述Boost级联升压电路进一步包括一第二级Boost升压电路，所述第二级Boost升压电路包括一第二电感器和一第二开关管，所述PWM发生器控制所述第一开关管及第二开关管同时导通或同时关断，当两个开关管导通时，输入端电源经由第一电感器和第一开关管接地，也经由第二电感器、第二开关管和第一开关管接地；当两个开关管关断时，输入端电源依序经由第一电感器、第二电感器连接到输出端。
  9. 根据权利要求8所述的Boost级联升压电路，其特征在于：所述第一开关管及第二开关管都是场效应晶体管。
  10. 根据权利要求8所述的Boost级联升压电路，其特征在于，所述第一开关管及第二开关管都是N型场效应晶体管。
  11. 根据权利要求8所述的Boost级联升压电路，其特征在于：所述Boost级联升压电路进一步包括一第三级Boost升压电路，所述第三级Boost升压电路包括一第三电感器和一第三开关管，所述PWM发生器控制所述三个开关管同时导通或同时关断，当三个开关管导通时，输入端电源经由第一电感器和第一开关管接地，也经由第二电感器、第二开关管和第一开关管接地，还经由第三电感器、第三开关管、第二开关管和第一开关管接地；当两个开关管关断时，输入端电源依序经由第一电感器、第二电感器、第三电感器连接到输出端。
  12. 根据权利要求11所述的Boost级联升压电路，其特征在于：所述第一级Boost升压电路进一步包括一第一二极管，所述第一电感器一端连接输入端，另一端连接第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，上述第二级Boost升压电路进一步包括一第一串联二极管和一第一并联二极管，上述第二电感器一端连接所述第一二极管的阴极，另一端连接所述第一串联二极管的阳极，所述第二开关管的控制端连接至所述PWM发生器，第一导通端连接至所述第一开关管的第二导通端，第二开关管的第二导通端连接至所述第一串联二极管的阳极，所述第一并联二极管的阳极连接所述输入端，阴极连接所述第一二极管的阴极，上述第三级Boost升压电路进一步包括一第二串联二极管和一第二并联二极管，所述第三电感器的一端连接第一串联二极管的阴极，另一端连接第二串联二极管的阳极，所述第二串联二极管的阴极连接所述输出端，所述第三开关管的控制端电性连接至所述PWM发生器，第一导通端连接至第二开关管的第二导通端，第三开关管的第二导通端连接至所述第二串联二极管的阳极，所述第二并联二极管的阳极连接所述输入端，阴极连接所述第一串联二极管的阴极。
  13. 根据权利要求12所述的Boost级联升压电路，其特征在于：所述三个开关管都是场效应晶体管。
  14. 根据权利要求13所述的Boost级联升压电路，其特征在于：所述三个开关管都是N型场效应晶体管。
  15. 根据权利要求13所述的Boost级联升压电路，其特征在于：所述三个开关管的控制端为栅极，第一导通端为源极，第二导通端为漏极。
  16. 根据权利要求8所述的Boost级联升压电路，其特征在于：所述第一级Boost升压电路进一步包括一第一二极管，所述第一电感器一端连接输入端，另一端连接第一二极管的阳极，所述第一开关管的控制端连接至PWM发生器，第一导通端接地，第二导通端连接至上述第一二极管的阳极，上述Boost级联升压电路进一步包括一第三级Boost升压电路，……，一第N级Boost升压电路，N为大于3的正整数，除了第一级Boost升压电路以外，其它各级Boost升压电路都包括一电感器、一并联二极管、一串联二极管以及一开关管，所述电感器的一端连接上一级的串联二极管的阴极，另一端连接本级串联二极管的阳极，所述并联二极管的阳极连接所述输入端，阴极连接上一级的串联二极管的阴极，所述开关管的控制端电性连接至所述PWM发生器，第一导通端连接至上一级的开关管的第二导通端，本级开关管的第二导通端连接至本级串联二极管的阳极，第N级Boost升压电路的串联二极管的阴极连接到输出端。
  17. 根据权利要求16所述的Boost级联升压电路，其特征在于：所述PWM发生器控制每个开关管同时导通或同时关断。
  18. 根据权利要求16所述的Boost级联升压电路，其特征在于：所述每个开关管都是N型场效应晶体管。
  19. 根据权利要求18所述的Boost级联升压电路，其特征在于，所述每个开关管的控制端为栅极，第一导通端为源极，第二导通端为漏极。
PCT/CN2011/072789 2011-03-30 2011-04-14 Boost级联升压电路 Ceased WO2012129823A1 (zh)

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