WO2012100562A1 - 阻变随机存储单元及存储器 - Google Patents

阻变随机存储单元及存储器 Download PDF

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Publication number
WO2012100562A1
WO2012100562A1 PCT/CN2011/080728 CN2011080728W WO2012100562A1 WO 2012100562 A1 WO2012100562 A1 WO 2012100562A1 CN 2011080728 W CN2011080728 W CN 2011080728W WO 2012100562 A1 WO2012100562 A1 WO 2012100562A1
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Prior art keywords
resistive
state
random access
voltage
resistive random
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PCT/CN2011/080728
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English (en)
French (fr)
Inventor
刘琦
刘明
龙世兵
吕杭炳
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中国科学院微电子研究所
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Priority to US13/512,797 priority Critical patent/US8642989B2/en
Publication of WO2012100562A1 publication Critical patent/WO2012100562A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/003—Cell access
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/75—Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Definitions

  • the invention belongs to the field of storage technology of the microelectronics industry, and in particular relates to a resistive random storage unit and a memory suitable for the cross array integration mode. Background technique
  • Resistive Random Access Memory is an emerging non-volatile memory technology that combines cell area, device density, power consumption, program/erase speed, 3D integration, and multi-value implementation. Compared with FLASH memory, it has great advantages and is highly concerned by large companies and research institutes at home and abroad. The continuous advancement of resistive random access technology has made it one of the most powerful competitors in the future market for non-volatile memory technology.
  • the resistive random access memory has a vertical device structure of Metal/Insulator/Metal (MIM). Therefore, the resistive random access memory can adopt a cross array structure to realize high-density storage.
  • MIM Metal/Insulator/Metal
  • the cross-array structure memory cells are arranged at parallel intersections perpendicular to each other, and each memory cell can strobe and read and write the device.
  • FIG. 1 is a schematic diagram of a current-voltage curve of a read operation of a prior art resistive random access memory cell in a low resistance state.
  • the resistive memory cell when the resistive memory cell is in the high-impedance state and the low-impedance state, when the DC scan is -V read ⁇ 1 ⁇ 4 ead , the device exhibits a symmetrical current-voltage curve under the polarity of the positive and negative voltages. .
  • the memory cells in the low-resistance state will provide additional leakage channels that will affect the information reading of the memory cells and cause serious problems in the cross-array. Read the crosstalk problem.
  • FIG. 2 is a schematic diagram of a read crosstalk problem in a prior art resistive random access memory array structure. As shown in Figure 2 , in the adjacent four memory cells, the cells with coordinates (1, 1) are in a high-impedance state, and the remaining three adjacent cells (1, 2), (2, 2), and (2, 1) are in a low resistance state, at this time
  • bipolar resistive memory memories mostly use transistors as gates to form a 1T1R cell structure to eliminate read crosstalk in the array.
  • the cell area corresponding to the 1T1R cell structure is larger than the cell area corresponding to the 1D1R or 1R cell structure, which is disadvantageous for the increase in device memory density.
  • the present invention provides a resistive random access memory cell and a memory suitable for cross-array integration to avoid crosstalk and improve the memory density of the device.
  • a resistive random access memory cell comprises: a resistive memory and a two-state resistor connected in series with each other; the two-state resistor comprises: a lower conductive electrode, a two-state resistive functional layer and an intermediate conductive electrode from bottom to top; the two-state resistive functional layer is in the following materials At least one npn-type junction or pnp-type junction formed by doping modification: Si, Ge, GaAs, LnP or SiGe.
  • the doping concentration of the npn-type junction or the pnp-type junction in the two-state resistive functional layer is l xlO 12 cm - 2 ⁇ l xl0 22 cm - 2 .
  • the n-p-n type junction is an n-p-n type Si nanowire.
  • the thickness is 10 ira! ⁇ 500 nm; it is doped by thermal diffusion or ion implantation; it is deposited by chemical vapor deposition, atomic layer deposition or molecular beam epitaxy.
  • the two-state resistor when the forward scan voltage reaches the forward voltage 1 ⁇ 4, the two-state resistor changes from a high resistance state to a low resistance state, and the positive state is maintained Low resistance state; when the scan voltage is retraced by ⁇ , the two-state resistor maintains a low resistance state.
  • the two-state resistor When the scan voltage is less than V 2 , the two-state resistor returns from a low resistance state to a high resistance state, where VV ⁇ is reversed.
  • the scan voltage reaches the negative conduction voltage v 3 , the two-state resistor changes from a high-resistance state to a low-resistance state, and maintains the low-resistance state in a negative direction; when the scan voltage is retraced by the ⁇ , the two-state resistor maintains a low resistance State, when the scan voltage is less than v 4 , the two-state resistor returns from a low resistance state to a high resistance state, where I v 3 1 > I 1 ⁇ 4 I .
  • the programming voltage V 8 thereof satisfies: V 3 ⁇ 48 >V set >V i ; Except for the voltage V plane, it satisfies:
  • v set is a threshold voltage of the bipolar resistive memory transitioning from a high impedance state to a low resistance state.
  • the programming voltage V satisfies: V as >V set >V i ;
  • the voltage V is satisfied: Difficult to ⁇ V set ; its read voltage V read satisfies: ⁇ ! ⁇ ⁇ 63£ ⁇ ⁇ ⁇ 68 ⁇ and I v read I ⁇ I v 3 1;
  • v set is a unipolar resistive memory transition from high impedance state to The low-resistance threshold voltage;
  • v reset is the threshold voltage of the unipolar resistive memory that transitions from a low-resistance state to a high-impedance state.
  • the resistive memory includes: an intermediate conductive electrode, a resistive memory layer and an upper conductive electrode from bottom to top; the two-state resistor and the resistive memory share a common conductive electrode.
  • the thickness of the resistive memory layer is 5 nm to 500 nm; the resistive memory layer is deposited by one of the following methods: electron beam evaporation, chemical vapor deposition, pulsed laser deposition, Atomic layer deposition, spin coating or magnetron sputtering; the resistive memory layer consists of at least one of the following materials or at least one material that has been doped and modified:
  • the conductive electrode is an upper conductive electrode, an intermediate conductive electrode or a lower conductive electrode, and for the conductive electrode: the thickness is 1 ⁇ ! ⁇ 500 nm;
  • the crucible is deposited by one of the following methods: electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition or magnetron sputtering; it consists of at least one of the following materials: W, Al , Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir, M, window, TaN, Ir0 2 , ITO or IZO.
  • a resistive random access memory comprises a resistor read/write unit, an address selection unit and a plurality of the above-mentioned resistive random storage units, wherein: the address selection unit is connected to the plurality of resistive random storage units for selecting a resistive random storage unit for operation, and operating
  • the method includes: setting, resetting or programming; and a resistor reading and writing unit connected to the address selecting unit and the plurality of resistive random access memory units for operating the selected resistive random access memory unit.
  • the resistive variable memory cell formed by the resistive memory of the present invention and the two-state resistor in series has a high and low resistance state, that is, a bidirectional rectification characteristic, because the two-state resistor has both positive and negative voltage polarities.
  • the device can provide a large operating current after applying a large voltage in the polarity of the positive and negative voltages. Therefore, it can be used as a strobe device in series with the bipolar and unipolar resistive memory to reduce the leakage path in the cross array and eliminate Read crosstalk.
  • FIG. 1 is a schematic diagram of a read operation current-voltage curve of a prior art resistive random access memory cell in a low resistance state
  • FIG. 2 is a schematic diagram of a prior art resistive random access memory read crosstalk problem
  • FIG. 3 is a schematic structural diagram of a resistive random access memory unit according to an embodiment of the present invention.
  • FIG. 4 is a graph showing current-voltage characteristics of a two-state resistor in a resistive random access memory cell in a DC scan mode according to an embodiment of the present invention
  • FIG. 5 is a graph showing current-voltage characteristics of a unipolar resistive memory in a DC scan mode in a resistive random access memory cell according to an embodiment of the present invention.
  • FIG. 6 is a graph showing a current-voltage characteristic of a read operation of a resistive random access memory cell in a low resistance state according to an embodiment of the present invention
  • 7 is a graph showing current-voltage characteristics of a bipolar resistive memory in a DC scan mode in a resistive random access memory cell according to an embodiment of the present invention
  • FIG. 8 is a schematic structural diagram of a resistive random access memory according to an embodiment of the present invention. detailed description
  • FIG. 3 is a schematic structural diagram of a resistive random access memory unit according to an embodiment of the present invention.
  • the memory cell includes: a two-state resistor 11 and a resistive memory 12 connected in series.
  • the dual-state resistor 11 has a bidirectional rectifying function, and includes a lower conductive electrode 101, a double-state resistive functional layer and an intermediate conductive electrode 105 from bottom to top.
  • the resistive memory 12 can be a unipolar or bipolar resistive memory including an intermediate conductive electrode 105, a resistive memory layer 106 and an upper conductive electrode 107 from bottom to top.
  • the two-state resistor 11 and the resistive memory 12 share the intermediate conductive electrode 105 in FIG.
  • the two-state resistor 11 and the resistive memory 12 may also have respective intermediate conductive electrodes.
  • the double-state resistor in FIG. 3 is located below the resistive memory, but the relative positional relationship between the two-state resistor and the resistive memory is not limited in the present invention, and the two-state resistor may be located above or below the resistive memory. .
  • the two-state resistance functional layer is composed of an n-type semiconductor 102, a p-type semiconductor 103, and an n-type semiconductor 104.
  • the two-state resistive functional layer may be an npn-type or pnp-type junction formed by doping one or more of the following materials: Si, Ge, GaAs, LnP or SiGe.
  • the two-state resistive functional layer is an npn-type Si nanowire.
  • the deposition method of the two-state resistive functional layer is chemical vapor deposition, atomic layer deposition or molecular beam epitaxy; the doping method for forming the above npn-type junction or pnp-type junction is thermal diffusion or ion implantation, and the doping concentration is I xl 0 12 Cm _2 ⁇ lx l0 22 cm -2 , preferably ⁇ ⁇ ⁇ 15 cm - 2 ⁇ l > ⁇ 10 17 cn 2 .
  • the thickness of the two-state resistor is from 10 nm to 500 nm, preferably from 50 nm to 200 nm.
  • FIG. 4 is a graph showing current-voltage characteristics of a two-state resistor in a resistive random memory cell in a DC scan mode according to an embodiment of the present invention.
  • the two-state resistor of this embodiment starts to be in a high-resistance state, and when the forward-scan voltage reaches the forward-going voltage 1 ⁇ 4, the two-state resistor is turned on, and the two-state resistor is in a high-resistance state.
  • the two-state resistor changes to a low resistance state and maintain the low resistance state in the forward direction; when the scan voltage is retraced by ⁇ , the low resistance state of the two-state resistor can be maintained, but when the device voltage is less than V 2 ( ⁇ > ⁇ 2 ), The two-state resistor returns from a low impedance state to a high resistance state.
  • the two-state resistor also has similar electrical characteristics, that is, when the scan voltage is greater than the forward voltage V 3 voltage, the two-state resistor changes from a high-resistance state to a low-resistance state, and maintains the negative direction.
  • the two-state resistor returns to the high-resistance state, where "II" represents the mathematics Absolute value.
  • the absolute value of the forward voltage of the two-state resistor is less than the absolute value of the negative conduction voltage, that is, I Vj I ⁇
  • the positive and negative conduction voltages of the two-state resistor are controlled by the doping concentration or junction depth of the npn-type or pnp-type junction of the above-mentioned two-state resistance functional layer, that is, for the n-type doping, the on-voltage is inconsistent with the n -type
  • the turn-on voltage increases with the increase of p type.
  • V 2 is between 1V and 2V
  • V 3 is between 3V and 4V
  • V 4 is between 1V and 3V. .
  • the two-state resistor can exhibit two resistance states in the V r V 2 and V 3 -V 4 intervals. And as shown in FIG. 4, in the region where the operating voltages are >V1 and >3, the two-state resistor remains in a low-resistance state, thereby providing a large operating current in both positive and negative voltage polarities.
  • the read/write mode setting of the resistive memory cell including the unipolar resistive memory and the bipolar resistive memory will be described below.
  • FIG. 5 is a current-voltage characteristic diagram of a unipolar resistive memory in a DC scan mode in a resistive random access memory cell according to an embodiment of the present invention.
  • the unipolar resistive memory in this embodiment starts to be in a high resistance state. Under a forward sweep voltage with a finite current, when the voltage reaches Vset , the resistive memory changes from a high resistance state.
  • the low resistance state when the voltage is removed, the resistive memory can still remain in the low resistance state; in the erase operation, a forward scan voltage with no current limit is applied across the resistive memory, when the voltage reaches V
  • the read voltage V read of the unipolar resistive memory satisfies the following relationship: V read ⁇ V reS et ⁇ V
  • V set is between 5V and 8V
  • V reset is between 3V and 5V
  • V read is approximately equal to 2.2V.
  • the read/write operation mode of the resistive random access memory unit formed by the unipolar resistive resistor and the double-state resistor is set as follows:
  • the initial state unipolar resistive resistor and the double-state resistor are in a high-resistance state, when A programming voltage V is applied to the series structure, and the programming voltage satisfies the condition of V > ⁇ >, when the unipolar resistive memory is programmed to a low resistance state; and when an erase voltage V » is applied to the series structure, the erase is performed.
  • Voltage satisfaction when the unipolar resistive memory is programmed from the low resistance state back to the high impedance state.
  • FIG. 6 is a graph showing a current-voltage characteristic of a read operation of a resistive random access memory cell in a low resistance state according to an embodiment of the present invention. As shown in FIG. 6, the resistive random access memory cell exhibits an asymmetrical current-voltage characteristic under a forward-reverse voltage scan.
  • the memory cell formed by the unipolar resistive memory and the two-state resistor in series can reduce the crossover by properly designing the forward and reverse turn-on voltage of the two-state resistor and the read/write voltage of the unipolar resistor. Leakage channels in the array to eliminate read crosstalk.
  • FIG. 7 is a graph showing current-voltage characteristics of a bipolar resistive memory in a DC scan mode in a resistive random access memory cell according to an embodiment of the present invention.
  • the bipolar resistive memory in the embodiment of the present invention starts to be in a high impedance state, and under the forward scan voltage (using the current limiting mode), when the voltage reaches Vset , the resistive memory is high.
  • the resistance state becomes a low resistance state, and when the voltage is removed, the resistive memory can remain in a low resistance state; unlike the unipolar resistive memory, the erase operation of the bipolar resistive memory must be at the opposite pole Under the condition, a negative scan voltage is applied across the device. When the scan voltage reaches V reset , the current value of the device suddenly decreases, and the device returns to the high-impedance state from the low-resistance state. Underneath, the device is still able to maintain a high-impedance state.
  • V set is between 3V and 5V; V reset is between -3V and -5V; V read is approximately equal to 2.2V.
  • the two-state resistor Since the two-state resistor has rectification characteristics in both the positive and negative directions, the two-state resistance is under the premise of properly designing the forward and reverse conduction voltage of the two-state resistor and the read/write voltage of the bipolar resistive memory.
  • the device can also be used as a strobe for bipolar resistive memory.
  • the read and write operations of the bipolar resistive memory in series with the two-state resistor are as follows:
  • the bipolar resistive memory and the two-state resistor are in a high-impedance state.
  • V ⁇ When a programming voltage V ⁇ is applied to the series structure, the programming voltage satisfies the V ⁇ i ⁇ Vse ⁇ Vi condition, and the bipolar resistive memory Is programmed to a low-impedance state; and when an erase voltage V « is applied to the series structure, the erase voltage satisfies the condition I v « I > v 3 , at which time the bipolar resistive memory is programmed from a low-resistance state to a high Resistance state.
  • the read voltage accommodated is used to read the state of the device, and the read voltage satisfies ⁇ ⁇ and I v read I ⁇ I v 3 1 .
  • the device exhibits a current-voltage curve with rectification characteristics under the forward-reverse voltage scan, as shown in FIG.
  • the memory cell formed by the bipolar resistive memory and the two-state resistor in series can be reduced by rationally designing the forward and reverse turn-on voltage of the two-state resistor and the read/write voltage of the unipolar resistor.
  • Leakage channels in the cross array eliminate crosstalk.
  • the thickness of the resistive memory layer is 5 im! ⁇ 500 nm, preferably 50 nm to 500 nm.
  • the resistive memory layer is composed of at least one of or at least one of the following materials: CuS, AgS, AgGeSe, CuI x S 1-x (0.1 ⁇ x ⁇ l), Zr0 2 , Hf0 2 , Ti0 2 , Si0 2 , WO x ( l ⁇ x ⁇ 3 ), NiO, CuO x (0.5 ⁇ x ⁇ 1 ), ZnO, TaO x ( 1 ⁇ 2 ⁇ 5 ), CoO, Y 2 0 3 , Si, PCMO (PrCaMnO), SZO (SrZr.
  • the deposition of the resistive memory layer is one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, spin coating or magnetron sputtering.
  • the thickness of the conductive electrode is from 1 nm to 500 nm, preferably from 20 nm to 100 nm.
  • the material of the conductive electrode is composed of at least one of the following materials: W, Al, Cu, Au, Ag, Pt, Ru, Ti, Ta, Pb, Co, Mo, Ir, M, TiN, TaN, Ir0 2 , ITO Or IZO.
  • the deposition of the conductive electrode is one of electron beam evaporation, chemical vapor deposition, pulsed laser deposition, atomic layer deposition, or magnetron sputtering.
  • FIG. 8 is a schematic structural diagram of a resistive random access memory unit according to an embodiment of the present invention.
  • the resistive memory includes a plurality of the above-mentioned resistive random access cells, an address selecting unit and a resistor read/write unit (not shown in the figure). show).
  • the address selection unit is composed of n bit lines (804) and m word lines (803).
  • the bit lines and word lines are connected to the peripheral decoding circuit for selecting a resistive random access memory unit and programming the same. Erase and read operations.
  • a resistive random access memory cell is disposed at the intersection of the bit line and the word line, and the resistive random access memory cell includes a two-state resistor (801) and a resistive memory (802).
  • the memory unit includes a resistive memory and a two-state memory.
  • the two-state memory includes a lower conductive electrode, a two-state resistive functional layer and an intermediate conductive electrode from bottom to top, and the resistive memory includes an intermediate conductive layer from bottom to top.
  • the electrode, the resistive memory layer and the upper conductive electrode, the two-state resistor and the resistive memory share the intermediate conductive electrode.
  • the two-state resistive functional layer is an npn-type junction formed by doping modification of Si, and the npn-type junction has a viscous concentration of 1 > ⁇ 10 12 cm - 2
  • the thickness of the two-state resistive functional layer is 1 Onm
  • the resistive memory layer is 5 nm CuS
  • the upper conductive electrode, the intermediate conductive electrode or the lower conductive electrode are all 1 nm of Au.
  • the two-state resistive functional layer is a pnp-type junction formed by doping modification of GaAs, and the doping concentration of the pnp-type junction is lxlO 17 cm- 2 ;
  • the thickness of the resistive functional layer is 100 nm, and the resistive memory layer is 50 nm AgGeSe; the upper conductive electrode, the intermediate conductive electrode or the lower conductive electrode are all 10 nm Ag.
  • the two-state resistive functional layer is an npn-type junction formed by doping modification of SiGe, and the doping concentration of the npn-type junction is lxlO 19 cm' 2 ;
  • the thickness of the resistive functional layer is 200 nm, and the resistive memory layer is PCMO of 100 nm; the upper conductive electrode, the intermediate conductive electrode or the lower conductive electrode are both 50 nm Au.
  • the two-state resistive functional layer is a pnp-type junction formed by doping modification of LnP, and the doping concentration of the pnp-type junction is l xlO 22 cm' 2 ;
  • the thickness of the state resistance functional layer is 500 nm
  • the resistive memory layer is W0 2 of 500 nm
  • the upper conductive electrode, the intermediate conductive electrode or the lower conductive electrode are both A1 of 500 nm.
  • the above four memory cells can meet the design requirements, which can reduce the leakage channel in the cross array and eliminate the phenomenon of reading crosstalk.
  • the two-state resistor has rectification characteristics under both positive and negative voltage polarities. At the same time, when the voltage exceeds the conduction voltage, the two-state resistor can provide both positive and negative voltage polarities. Large working current. Therefore, the two-state resistor can be used as a strobe of a unipolar resistive memory or as a strobe of a bipolar resistive memory. Using the above two-state resistor The memory cell can eliminate the misreading and crosstalk of the resistive random memory cell cross array.

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Description

阻变随机存储单元及存储器
技术领域
本发明属于微电子行业存储技术领域， 尤其涉及一种适用于交叉阵 列集成方式的阻变随机存储单元及存储器。 背景技术
阻变随机存储器 （Resistive Random Access Memory, 简称 RRAM) 作为一种新兴的非易失性存储技术， 在单元面积、 器件密度、 功耗、 编 程 /擦除速度、三维集成和多值实现等诸多方面相对 FLASH存储器都具有 极大的优势， 受到国内外大公司和科研院所的高度关注。 阻变随机存储 技术的不断进步使之成为未来非易失性存储技术市场主流产品的最有力 竞争者之一。
阻变随机存储器具有金属 /绝缘层 /金属 （Metal/Insulator/Metal， 简称 MIM) 的垂直器件结构， 因此， 阻变随机存储器可以采用交叉阵列结构 来实现高密度存储。 在交叉阵列结构中， 上下相互垂直的平行交叉点处 设置存储单元， 每一个存储单元都可以实现器件的选通并进行读写。
图 1为现有技术阻变随机存储单元在低阻态下的读操作电流-电压曲 线示意图。 如图 1 所示， 当阻变存储单元分别处于高阻态和低阻态时， 采用直流扫描 -Vread→¼ead时， 器件在正反电压极性下， 表现出对称的电 流 -电压曲线。 当采取交叉阵列存储架构时， 由于存储单元对称的读电学 特性， 处于低阻态的存储单元将提供额外的漏电通道， 这些漏电通道将 影响存储单元的信息读取， 在交叉阵列中产生严重的读串扰问题。 图 2 为现有技术阻变随机存储器阵列结构中读串扰问题的示意图。 如图 2所 示， 在相邻的四个存储单元， 坐标为 （1 , 1 ) 的单元处于高阻状态， 其 余三个相邻单元 （1， 2)、 （2， 2) 和 （2, 1 ) 都处于低阻状态， 这时在
( 1， 1 ) 单元上加读电压时， 预想的电流为沿通道 （1， 1 ) ― (2， 1 ) 进行传输 （如白色箭头所示）， 而实际情况下电流可以沿着低阻通道 （1， 2) ― (2， 2) — (2， 1 ) 进行传输 （如黑色虚线箭头所示）， 使得 （1， 1 ) 单元被误读成低阻状态 （导通状态）。 在图 2 中， 问号代表这种情况 下无法获得 （1， 1 ) 单元的真实状态。
对于单极和双极性阻变随机存储器， 为了达到防止串扰的目的， 在 低阻状态下， 正、 负读电压下流过器件的电流值不能相等， 也就需要存 储单元具有整流特性。 对于单极性阻变存储器来讲， 其编程和擦除电压 极性相同， 采用普通的整流二级管就能实现消除串扰的目的。 而由于双 极性阻变存储器的编程和擦除操作必须在相反的极性下实现，在较大（编 程或擦除） 电压下， 正负方向都需要提供较大的电流。 而普通的单向整 流的二级管根本无法为擦除过程提供足够的操作电流。
目前， 双极性的阻变存储器大多釆用晶体管作为选通管， 组成 1T1R 的单元结构来消除阵列中的读串扰问题。但是 1T1R单元结构对应的单元 面积要比 1D1R或 1R单元结构对应的单元面积大， 因此不利于器件存储 密度的提高。 发明内容
(一） 要解决的技术问题
为解决上述缺陷， 本发明提供了一种适用于交叉阵列集成方式的阻 变随机存储单元及存储器， 以避免读串扰现象， 提高器件的存储密度。
(二） 技术方案
根据本发明的一个方面， 提供了一种阻变随机存储单元。 该存储单 元包括： 相互串联的阻变存储器和双态电阻器； 双态电阻器自下至上包 括： 下导电电极、 双态电阻功能层和中间导电电极； 双态电阻功能层为 以下材料中的至少一种经过掺杂改性后所形成的 n-p-n型结或 p-n-p型结： Si、 Ge、 GaAs, LnP或 SiGe。
优选地， 本发明阻变随机存储单元中， 双态电阻功能层中， n-p-n型 结或 p-n-p型结的掺杂浓度为 l xlO12 cm-2~l xl022 cm— 2。
优选地， 本发明阻变随机存储单元中， n-p-n型结为 n-p- n型 Si纳米 线。
优选地， 本发明阻变随机存储单元中， 对于双态电阻功能层： 其厚 度为 10 ira！〜 500 nm; 其是采用热扩散或离子注入进行掺杂； 其是采用化 学气相沉积、 原子层沉积或分子束外延方法进行沉积。 优选地， 本发明阻变随机存储单元中， 对于双态电阻器： 当正向扫 描电压到达正向导通电压 ¼时， 双态电阻器由高阻态变到低阻态， 并正 向保持该低阻态； 当扫描电压由 ^回扫时， 双态电阻器保持低阻状态， 当扫描电压小于 V2时， 双态电阻器由低阻态回到高阻态， 其中 V V^ 当反向扫描电压到达负向导通电压 v3时， 双态电阻器由高阻态变到低阻 态， 并负向保持该低阻态； 当扫描电压由 ^回扫时， 双态电阻器保持低 阻状态， 当扫描电压小于 v4时， 双态电阻器由低阻态回到高阻态， 其中 I v3 1 > I ¼ I 。
优选地， 本发明阻变随机存储单元中， 当阻变存储器为双极性阻变 存储器时，对于阻变随机存储单元：其编程电压 V 8满足： V ¾8>Vset>Vi ; 其擦除电压 V麵满足： | V擦除 | >V3 ; 其读电压 Vread满足：
Figure imgf000005_0001
和 I vread I < I v3 1； 其中， vset为双极性阻变存储器由高阻态转变到低 阻态的阈值电压。
优选地， 本发明阻变随机存储单元中， 当阻变存储器为单极性阻变 存储器时，对于阻变随机存储单元：其编程电压 V 满足： V as>Vset>Vi ; 其擦除电压 V 議满足：
Figure imgf000005_0002
難 <Vset ; 其读电压 Vread满足： ν!<νΓ63£ΐ<νΓ68ει和 I vread I < I v3 1； 其中， vset为单极性阻变存储器由高 阻态转变到低阻态的阈值电压； vreset为单极性阻变存储器的由低阻态转 变到高阻态的阈值电压。
优选地， 本发明阻变随机存储单元中， 阻变存储器自下至上包括： 中间导电电极、 阻变存储层和上导电电极； 双态电阻器和阻变存储器共 用中间导电电极。
优选地， 本发明阻变随机存储单元中， 阻变存储层的厚度为 5 nm〜 500 nm; 阻变存储层采用以下方法中的一种沉积： 电子束蒸发、 化学气 相沉积、 脉冲激光沉积、 原子层沉积、 旋涂或磁控溅射； 阻变存储层由 以下材料中的至少一种或至少一种经掺杂改性后所形成的材料组成：
CuS; AgS; AgGeSe; CuIxS1-x， 其中 0·1<χ<1 ; Zr02; Hf02; Ti02; Si02; WOx,其中 l<x<3 ; MO; CuOx,其中 0.5<χ<1 ; ZnO; TaOx,其中 1<χ<2.5; CoO; Y203; Si; PrCaMnO; SrZr03; SrTi03; 铜的四氰基苯醌对二甲烷 Cu-TCNQ; 8-羟基喹啉铝 A1Q3或聚乙撑二氧噻吩 PEDOT。 优选地， 本发明阻变随机存储单元中， 导电电极为上导电电极、 中 间导电电极或下导电电极， 对于导电电极： 其厚度为 1 ηπ！〜 500 nm; 其 釆用以下方法中的一种沉积： 电子束蒸发、 化学气相沉积、 脉冲激光沉 积、 原子层沉积或磁控溅射； 其由以下材料中的至少一种组成： W、 Al、 Cu、 Au、 Ag、 Pt、 Ru、 Ti、 Ta、 Pb、 Co、 Mo、 Ir、 M、 窗、 TaN、 Ir02、 ITO或 IZO。
根据本发明的另一个方面， 还提供了一种阻变随机存储器。 该存储 器包括电阻读写单元、 地址选择单元和若干个上述的阻变随机存储单元， 其中： 地址选择单元， 与若干阻变随机存储单元相连， 用于选择进行操 作的阻变随机存储单元， 操作包括： 置位、 复位或编程； 电阻读写单元， 与地址选择单元和若干阻变随机存储单元相连， 用于对所选择的阻变随 机存储单元进行操作。
(三） 有益效果
本发明的阻变存储器与双态电阻器串联后所形成的阻变随机存储单 元， 由于双态电阻器在正反两个电压极性下都具有高、 低电阻状态， 即 双向整流特性， 器件在正反电压极性方向施加较大电压后器件可以提供 较大的工作电流， 因此可作为选通器件与双极和单极阻变存储器进行串 联， 实现减小交叉阵列中的漏电通道， 消除读串扰现象。 附图说明
图 1为现有技术阻变随机存储单元在低阻态下的读操作电流-电压曲 线示意图；
图 2为现有技术阻变随机存储器读串扰问题的示意图；
图 3为本发明实施例阻变随机存储单元的结构示意图；
图 4 为本发明实施例阻变随机存储单元中双态电阻器在直流扫描模 式下的电流 -电压特性曲线图；
图 5 为本发明实施例阻变随机存储单元中单极性阻变存储器在直流 扫描模式下的电流-电压特性曲线图。
图 6为本发明实施例阻变随机存储单元在低阻态下的读操作电流-电 压特征曲线图； 图 7 为本发明实施例阻变随机存储单元中双极性阻变存储器在直流 扫描模式下的电流-电压特性曲线图；
图 8为本发明实施例阻变随机存储器的结构示意图。 具体实施方式
为使本发明的目的、 技术方案和优点更加清楚明白， 以下结合具体 实施例， 并参照附图， 对本发明进一步详细说明。
在本发明的一个示例性实施例中， 提供了一种阻变随机存储单元。 图 3为本发明实施例阻变随机存储单元的结构示意图。 如图 3所示， 该 存储单元包括： 相互串联的双态电阻器 11和阻变存储器 12。 其中， 该双 态电阻器 11具有双向整流功能， 其自下而上包括： 下导电电极 101、 双 态电阻功能层和中间导电电极 105。 阻变存储器 12可以为单极性或双极 性阻变存储器， 其自下而上包括中间导电电极 105、 阻变存储层 106和上 导电电极 107。
需要说明的是， 图 3中双态电阻器 11和阻变存储器 12共用中间导 电电极 105。 当然， 双态电阻器 11和阻变存储器 12也可以有各自的中间 导电电极。 此外,' 图 3 中双态电阻器位于阻变存储器的下方， 但本发明 中双态电阻器和阻变存储器的相对位置关系并没有限制， 双态电阻器可 以位于阻变存储器的上方或下方。
如图 3所示， 双态电阻功能层由 n型半导体 102、 p型半导体 103和 n型半导体 104构成。而双态电阻功能层可以为以下材料中的一种或多种 经过掺杂改性后， 所形成的 n-p-n型或 p-n-p型结： Si、 Ge、 GaAs, LnP 或 SiGe。 优选地， 该双态电阻功能层为 n-p-n型 Si纳米线。 该双态电阻 功能层的沉积方法为化学气相沉积、 原子层沉积或分子束外延； 形成上 述 n-p-n型结或 p-n-p型结的掺杂方法为热扩散或离子注入， 掺杂浓度为 I x l 012 cm_2~l x l022 cm-2, 优选为 Ι χ ΙΟ15 cm-2〜l >< 1017 cn 2。 一般情况下， 双态电阻器的厚度为 10 nm〜500 nm， 优选为 50nm〜200 nm。
对于如图 3所示的阻变随机存储单元， 可以根据双态电阻器 11和阻 变存储器 12的电压-电流特性设置其编程电压、擦除电压、读电压， 从而 避免读串扰问题。 以下将对具体设置方法进行详细说明。 图 4 为本发明实施例阻变随机存储单元中双态电阻器在直流扫描模 式下的电流 -电压特性曲线图。 如图 4所示， 本实施例的双态电阻器开始 处于高阻态，当正向扫描电压到达正向导通电压 ¼时，双态电阻器导通， 这时双态电阻器由高阻态变到低阻态， 并正向保持该低阻态； 当扫描电 压由 ^回扫时， 双态电阻器的低阻状态可以保持， 但是当器件电压小于 V2 (Υ >Υ2) 时， 双态电阻器由低阻态回到高阻态。 在反向扫描电压下， 双态电阻器也有类似的电学特性， 即当扫描电压大于正向导通电压 V3电 压时， 双态电阻器由高阻态变到低阻态， 并负向保持该低阻态， 而在回 扫过程中， 当扫描电压小于 v4 ( I v3 1 > I ¼ I )时， 双态电阻器重新回 到高阻态， 其中， " I I "表示数学中的取绝对值。 在本发明中， 双态 电阻器的正向导通电压的绝对值小于负向导通电压的绝对值， 即 I Vj I <
I V3 I。双态电阻器的正、 负导通电压由上述双态电阻功能层的 n-p-n型 或 p-n-p型结的掺杂浓度或结深来控制， 即对于 n型掺杂， 导通电压随 n 型惨杂的增加而减小； 对于 p型掺杂， 导通电压随 p型惨杂的增加而增 大。 举例来讲， 对于一般的双态存储器来讲， 介于 2V〜3V 之间， V2 介于 1V~2V之间； V3介于 3V~4V之间， V4介于 1V〜3V之间。
可见， 双态电阻器在 VrV2和 V3-V4区间能够表现出两种电阻状态。 并且如图 4所示， 在操作电压 >V1和> 3的区域， 双态电阻器保持在低 阻状态， 从而在正反两个电压极性都可以提供较大的工作电流。 以下将 分别对包含单极性阻变存储器和双极性阻变存储器的阻变存储单元的读 写方式设置进行说明。
首先， 对于包含单极性阻变存储器的阻变随机存储单元， 图 5 为本 发明实施例阻变随机存储单元中单极性阻变存储器在直流扫描模式下的 电流 -电压特性曲线图。 如图 5所示， 本实施例中的单极性阻变存储器开 始处于高阻态， 在一个带有限流的正向扫描电压下， 当电压到达 Vset时， 阻变存储器由高阻态变为低阻态， 而当撤掉电压时， 阻变存储器仍然可 以保持在低阻状态； 在擦除操作中， 在阻变存储器两端加一个没有限流 的正向扫描电压， 当电压到达 Vreset时， 这时阻变存储器回到高阻状态， 在撤掉电压的情况下， 阻变存储器仍然保持在高阻态。 而单极性阻变存 储器的读电压 Vread满足以下关系： Vread<VreSet<V 举例来讲， 对于一般 的单极性阻变存储器来讲， Vset介于 5V〜8V之间； Vreset介于 3V〜5V之间； Vread约等于 2.2V。
单极性阻变电阻器与双态电阻器串联构成的阻变随机存储单元的读 写操作方式设置如下： 初始态单极性阻变电阻器与双态电阻器均处于高 阻状态， 当在串联结构上加一个编程电压 V , 编程电压满足 V >ν^> 条件， 这时单极性阻变存储器被编程到低阻状态； 而当在串联结 构上加一个擦除电压 V », 擦除电压满足
Figure imgf000009_0001
Vset条件， 这时 单极性阻变存储器从低阻状态被编程回到高阻状态。 当单极性阻变存储 器处于低阻状态时， 采用读电压 Vread来读取器件的状态， 读电压满足 V V^c^V^t和 I Vread I < I V3 I 。 图 6为本发明实施例阻变随机存储单 元在低阻态下的读操作电流 -电压特征曲线图。 如图 6所示， 阻变随机存 储单元在正反读电压扫描下， 表现出非对称的电流电压特性。
由上述说明可知， 单极性阻变存储器与双态电阻器串联后构成的存 储单元， 通过合理设计双态电阻器的正反导通电压和单极电阻器的读写 电压， 可以减小交叉阵列中的漏电通道， 从而消除读串扰现象。
其次， 对于包含双极性阻变存储器的阻变存储单元， 图 7 为本发明 实施例阻变随机存储单元中双极性阻变存储器在直流扫描模式下的电流- 电压特性曲线图。 如图 7所示， 本发明实施例中的双极性阻变存储器开 始处于高阻态， 在正向扫描电压下（釆用限流模式）， 当电压到达 Vset时， 阻变存储器由高阻态变为低阻态， 而当撤掉电压时， 阻变存储器仍然可 以保持在低阻状态； 与单极性阻变存储器不同， 双极性阻变存储器的擦 除操作必须在相反的极性下实现， 在器件两端加一个负向扫描电压， 当 扫描电压到达 Vreset时， 这时器件的电流值突然降低， 器件由低阻态重新 回到高阻状态， 在撤掉电压的情况下， 器件仍然能够保持高阻状态。 举 例来讲，对于一般的双极性阻变存储器来讲， Vset介于 3V〜5V之间； Vreset 介于 -3V〜- 5V之间； Vread约等于 2.2V。
由于双态电阻器在正反两个方向上都有整流特性， 因此在合理的设 计双态电阻器的正反导通电压和双极性阻变存储器的读写电压的前提 下， 双态电阻器也可以作为双极性阻变存储器的选通管。
双极性阻变存储器与双态电阻器串联后的读写操作方式如下： 初始 态双极性阻变存储器与双态电阻器均处于高阻状态， 当在串联结构上加 一个编程电压 V 翩， 编程电压满足 V ^i^Vse^Vi条件， 这时双极性阻变 存储器被编程到低阻状态； 而当在串联结构上加一个擦除电压 V «， 擦 除电压满足 I v« I >v3条件，这时双极性阻变存储器从低阻状态被编程 到高阻状态。 当双极性阻变存储器处于低阻状态时， 采用读电压 vread来 读取器件的状态， 读电压满足 ν ν^^ν^和 I vread I < I v3 1 。 这时器 件在正反读电压扫描下， 表现出具有整流特性的电流 -电压曲线， 如图 6 所示。
由上述说明可知， 双极性阻变存储器与双态电阻器串联后构成的存 储单元， 通过合理设计双态电阻器的正反导通电压和单极电阻器的读写 电压后， 可以减小交叉阵列中的漏电通道， 从而消除读串扰现象。
本发明中， 阻变存储层的厚度为 5 im！〜 500 nm, 优选为 50nm〜500 nm。 阻变存储层由以下材料中的至少一种或至少一种经惨杂改性后形成 的材料组成： CuS、 AgS、 AgGeSe、 CuIxS1-x (0.1<x<l ), Zr02、 Hf02、 Ti02、 Si02、 WOx ( l<x<3 )、 NiO、 CuOx (0.5<x<l )、 ZnO、 TaOx ( 1<χ<2·5 )、 CoO、 Y203、 Si、 PCMO (PrCaMnO), SZO (SrZr。3 )、 STO ( SrTi03 )、 有机材料等， 其中有机材料可以 Cu-TCNQ (铜的四氰基苯醌对二甲垸）、 A1Q3 ( 8-羟基喹啉铝）或 PEDOT (聚乙撑二氧噻吩）。 阻变存储层的沉积 是采用电子束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积、 旋涂 或磁控溅射方法中的一种。
本发明中， 对于上导电电极、 中间导电电极、 下导电电极， 导电电 极的厚度为 l nm〜500 nm,优选为 20nm〜： 100 nm。导电电极的材料由以 下材料中的至少一种组成： W、 Al、 Cu、 Au、 Ag、 Pt、 Ru、 Ti、 Ta、 Pb、 Co、 Mo、 Ir、 M、 TiN、 TaN、 Ir02、 ITO或 IZO。 导电电极的淀积是采 用电子束蒸发、 化学气相沉积、 脉冲激光沉积、 原子层沉积或磁控溅射 方法中的一种。
根据本发明的另一个方面， 还提供了采用双态电阻器作为选通单元 的阻变随机存储单元的阵列结构 -阻变随机存储器。 图 8为本发明实施例 阻变随机存储单元器的结构示意图。 如图 8所示， 该阻变存储器包括若 干上述的阻变随机存储单元， 地址选择单元和电阻读写单元 （未在图中 示出）。 其中， 地址选择单元由 n条位线 （804) 以及 m条字线 （803 ) 组 成， 位线和字线与外围译码电路相连， 用于选择阻变随机存储单元， 并 对其进行编程、 擦除和读操作。 位线与字线的交叉处设置阻变随机存储 单元， 该阻变随机存储单元包括双态电阻器（801 )和阻变存储器（802)。
在本发明优选的实施例中， 存储单元包括阻变存储器和双态存储器， 双态存储器自下至上包括下导电电极、 双态电阻功能层和中间导电电极， 阻变存储器自下至上包括中间导电电极、 阻变存储层和上导电电极， 双 态电阻器和阻变存储器共用中间导电电极。
在根据本发明制备的第一种存储单元中， 双态电阻功能层为 Si经过 掺杂改性后所形成的 n-p-n型结，该 n-p-n型结的惨杂浓度为 1 ><1012 cm—2; 双态电阻功能层的厚度为 1 Onm，阻变存储层为 5nm的 CuS；上导电电极、、 中间导电电极或下导电电极均为 lnm的 Au。
在根据本发明制备的第二种存储单元中， 双态电阻功能层为 GaAs 经过掺杂改性后所形成的 p-n-p型结， 该 p-n-p型结的掺杂浓度为 lxlO17 cm—2; 双态电阻功能层的厚度为 lOOnm, 阻变存储层为 50nm的 AgGeSe; 上导电电极、、 中间导电电极或下导电电极均为 10nm的 Ag。
在根据本发明制备的第三种存储单元中， 双态电阻功能层为 SiGe经 过掺杂改性后所形成的 n-p-n型结， 该 n-p-n型结的掺杂浓度为 lxlO19 cm'2; 双态电阻功能层的厚度为 200nm， 阻变存储层为 lOOnm的 PCMO; 上导电电极、、 中间导电电极或下导电电极均为 50nm的 Au。
在根据本发明制备的第四种存储单元中， 双态电阻功能层为 LnP经 过掺杂改性后所形成的 p-n-p 型结， 该 p-n-p型结的掺杂浓度为 l xlO22 cm'2; 双态电阻功能层的厚度为 500nm， 阻变存储层为 500nm的 W02; 上导电电极、 中间导电电极或下导电电极均为 500nm的 A1。
经过测试， 上述四种存储单元均能够达到设计要求， 可以实现减小 交叉阵列中的漏电通道， 消除读串扰现象的目的。
综上所述， 双态电阻器在正、 反两个电压极性下都具有整流的特性， 同时在电压超过导通电压时， 双态电阻器在正反两个电压极性都可以提 供较大的工作电流。 因此， 该双态电阻器既可以作为单极性阻变存储器 的选通管， 也可作为双极性阻变存储器的选通管。 采用上述双态电阻器 的存储单元， 可以消除阻变随机存储器单元交叉阵列的误读与串扰现象。 以上所述的具体实施例， 对本发明的目的、 技术方案和有益效果进 行了进一步详细说明， 所应理解的是， 以上所述仅为本发明的具体实施 例而已， 并不用于限制本发明， 凡在本发明的精神和原则之内， 所做的 任何修改、 等同替换、 改进等， 均应包含在本发明的保护范围之内。

Claims

权利要求
1、 一种阻变随机存储单元， 其特征在于， 该存储单元包括： 相 互串联的阻变存储器和双态电阻器；
所述双态电阻器自下至上包括： 下导电电极、双态电阻功能层和 中间导电电极；
所述双态电阻功能层为以下材料中的至少一种经过掺杂改性后 所形成的 n-p-n型结或 p-n-p型结： Si、 Ge、 GaAs, LnP或 SiGe。
2、 根据权利要求 1所述的阻变随机存储单元， 其特征在于： 所 述双态电阻功能层中， 所述 n-p-n 型结或 p-n-p 型结的惨杂浓度为 lxlO12 cm-2~lxl022 cm"2 0
3、 根据权利要求 2所述的阻变随机存储单元， 其特征在于： 所 述 n-p-n型结为 n-p-n型 Si纳米线。
4、 根据权利要求 1所述的阻变随机存储单元， 其特征在于， 所 述双态电阻功能层：
其厚度为 10 nm~500 nm;
其是采用热扩散或离子注入进行掺杂；
其是采用化学气相沉积、 原子层沉积或分子束外延方法进行沉 积。
5、 根据权利要求 1所述的阻变随机存储单元， 其特征在于， 所 述双态电阻器：
当正向扫描电压到达正向导通电压 V！时， 所述双态电阻器由高 阻态变到低阻态， 并正向保持该低阻态； 当扫描电压由 ！回扫时， 所述双态电阻器保持低阻状态， 当扫描电压小于 2时， 所述双态电 阻器由低阻态回到高阻态， 其中
当反向扫描电压到达负向导通电压 V3时， 所述双态电阻器由高 阻态变到低阻态， 并负向保持该低阻态； 当扫描电压由 V3回扫时， 所述双态电阻器保持低阻状态， 当扫描电压小于 4时， 所述双态电 阻器由低阻态回到高阻态， 其中 I v3 1 > I v4 1 。
6、 根据权利要求 5所述的阻变随机存储单元， 其特征在于， 当 所述阻变存储器为双极性阻变存储器时， 对于所述阻变随机存储单 元：
其编程电压 V编程满足： V S^Vse^Vj；
其擦除电压 V聽满足： I V擦除 I >v3;
其读电压 vread满足： ν^ν^ ν^和 I vread I < I v3 1 ； 其中， vset为所述双极性阻变存储器由高阻态转变到低阻态的阈 值电压。
7、 根据权利要求 5所述的阻变随机存储单元， 其特征在于， 当 所述阻变存储器为单极性阻变存储器时， 对于所述阻变随机存储单 元：
其编程电压 V编程满足： V S^Vse^Vj；
其擦除电压 V擦除满足： V^Vrese^V賺 <Vset;
其读电压 Vread满足： V^V^^V^t和 I Vread I < I V3 I； 其中， 所述 vset为单极性阻变存储器由高阻态转变到低阻态的阈 值电压； 所述 vreset为单极性阻变存储器的由低阻态转变到高阻态的 阈值电压。
8、 根据权利要求 1至 7中任一项所述的阻变随机存储单元， 其 特征在于，
所述阻变存储器自下至上包括： 所述中间导电电极、 阻变存储层 和上导电电极； 所述双态电阻器和阻变存储器共用所述中间导电电
9、 根据权利要求 8所述的阻变随机存储单元， 其特征在于： 所述阻变存储层的厚度为 5 rm！〜 500 nm;
所述阻变存储层采用以下方法中的一种沉积： 电子束蒸发、化学 气相沉积、 脉冲激光沉积、 原子层沉积、 旋涂或磁控溅射；
所述阻变存储层由以下材料中的至少一种或至少一种经掺杂改 性后所形成的材料组成： CuS; AgS; AgGeSe; CuIxS1-x,其中 0.1<χ<1 ; Zr02; Hf02; Ti02; Si02; WOx,其中 1<χ<3 ; NiO; CuOx，其中 0.5<χ<1 ; ZnO; TaOx， 其中 1<χ<2.5; CoO; Y203; Si; PrCaMnO; SrZr03; SrTi03; 铜的四氰基苯醌对二甲垸 Cu-TCNQ; 8-羟基喹啉铝入1(¾或 聚乙撑二氧噻吩 PEDOT。
10、 根据权利要求 8所述的阻变随机存储单元， 其特征在于， 导 电电极为所述上导电电极、 中间导电电极或下导电电极， 对于所述导 电电极：
其厚度为 l nm〜500 nm;
其釆用以下方法中的一种沉积： 电子束蒸发、 化学气相沉积、 脉 冲激光沉积、 原子层沉积或磁控溅射；
其由以下材料中的至少一种组成： W、 Al、 Cu、 Au、 Ag、 Pt、 Ru、 Ti、 Ta、 Pb、 Co、 Mo、 Ir、 M、 TiN、 TaN、 Ir02、 ITO或 IZO。
11、 一种阻变随机存储器， 其特征在于， 该存储器包括电阻读写 单元、 地址选择单元和若干个权利要求 1-10 中任一项所述的阻变随 机存储单元， 其中：
所述地址选择单元， 与所述若干阻变随机存储单元相连， 用于选 择进行操作的阻变随机存储单元，所述操作包括：置位、复位或编程; 所述电阻读写单元，与所述地址选择单元和所述若干阻变随机存 储单元相连， 用于对所选择的阻变随机存储单元进行所述操作。
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