WO2012075905A1 - Transistor bipolaire à porte isolée et son procédé de fabrication - Google Patents

Transistor bipolaire à porte isolée et son procédé de fabrication Download PDF

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Publication number
WO2012075905A1
WO2012075905A1 PCT/CN2011/083300 CN2011083300W WO2012075905A1 WO 2012075905 A1 WO2012075905 A1 WO 2012075905A1 CN 2011083300 W CN2011083300 W CN 2011083300W WO 2012075905 A1 WO2012075905 A1 WO 2012075905A1
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WO
WIPO (PCT)
Prior art keywords
gate
region
layer
emitter
drift region
Prior art date
Application number
PCT/CN2011/083300
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English (en)
Inventor
Le Wang
Original Assignee
Csmc Technologies Fab1 Co., Ltd.
Csmc Technologies Fab2 Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Csmc Technologies Fab1 Co., Ltd., Csmc Technologies Fab2 Co., Ltd. filed Critical Csmc Technologies Fab1 Co., Ltd.
Publication of WO2012075905A1 publication Critical patent/WO2012075905A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]

Definitions

  • the present invention generally relates to the field of semiconductor manufacturing and, more particularly, to Insulated Gate Bipolar Transistor (IGBT) technologies.
  • IGBT Insulated Gate Bipolar Transistor
  • An Insulated Gate Bipolar Transistor is a composite and fully-controllable voltage-driven power electronic device combining characteristics of the bipolar junction transistor (BGT) and the metal-oxide-semiconductor field-effect transistor (MOSFET).
  • the IGBT has both high input impedance of the MOSFET and the low conduction voltage drop of the power transistor, e.g., giant transistor (GTR).
  • GTR giant transistor
  • the GTR has a low saturation voltage drop and a high carrier density, but needs a relatively large driving current; while the MOSFET only needs small driving power and has a fast switching speed, but has a high conduction voltage drop and low carrier density.
  • the IGBT combines the advantages of these two devices and has a low saturation voltage drop and small driving power.
  • the IGBT is suitable for high direct-current (DC) voltage (e.g., 1500V) converter systems, such as AC motors, inverters, switching power supplies, lighting circuits, and traction drives, etc.
  • DC direct-current
  • FIG. 1 shows a conventional IGBT 100.
  • the IGBT 100 includes a substrate, an N-type epitaxial layer grown on the top side of the substrate, a P+ well region formed in the epitaxial layer, an N+ emitter drift region formed in the P+ well region.
  • the IGBT 100 also includes an emitter 101 formed on the P+ well region and the N+ emitter drift region, and a gate 102 connecting the P+ well region, the N+ emitter drift region, and the N-type epitaxial layer.
  • the IGBT 100 includes another epitaxial layer formed on the back side of the substrate, a P+ collector drift region formed in the another epitaxial layer, and a collector 103 formed on the P+ collector drift region.
  • the emitter and the gate are formed on the top or front side of the semiconductor wafer, while the collector is formed on the back side of the semiconductor wafer.
  • other semiconductor devices such as the MOS transistors widely used in very large scale integrated circuits (VLSI), often have the source, drain, and gate formed on the same side of the semiconductor chip. Thus, it may be difficult to integrate the IGBT devices with other semiconductor devices.
  • the IGBT includes a substrate containing a substrate layer and an epitaxial layer formed on one side of the substrate layer.
  • the IGBT also includes a well region formed in the epitaxial layer, and a gate region formed over a junction between the well region and the epitaxial layer.
  • the IGBT includes a collector drift region formed in the epitaxial layer, and an emitter drift region formed in the well region.
  • the IGBT also includes a collector formed on the collector drift region, an emitter formed on the emitter drift region, and a gate formed on the gate region. The collector, the emitter, and the gate are arranged at a same side of the substrate layer.
  • Another aspect of the present disclosure includes a method for manufacturing an insulated gate bipolar transistor (IGBT).
  • the method includes providing a substrate containing a substrate layer and an epitaxial layer formed on one side of the substrate layer.
  • the method also includes forming a well region in the epitaxial layer, and forming a gate region over a junction between the well region and the epitaxial layer.
  • the method includes forming a collector drift region in the epitaxial layer, and forming an emitter drift region in the well region.
  • the method also includes forming a collector on the collector drift region, forming an emitter on the emitter drift region, and forming a gate on the gate region.
  • the collector, the emitter, and the gate are formed at a same side of the substrate layer.
  • Figure 1 is a conventional IGBT
  • Figure 2 illustrates an exemplary IGBT consistent with the disclosed embodiments
  • Figure 3 illustrates another exemplary IGBT consistent with the disclosed embodiments
  • Figure 4 is a flow chart of a method for manufacturing an IGBT consistent with the disclosed embodiments.
  • Figures 5A-5E illustrate an exemplary IGBT during a manufacturing process consistent with the disclosed embodiments.
  • IGBT 200 includes a substrate 201.
  • the substrate 201 may include any appropriate material for making IGBT structures.
  • the substrate 201 may include a semiconductor structure, e.g., silicon, silicon germanium (SiGe) with a monocrystalline, polycrystalline, or amorphous structure.
  • the substrate 201 may also include a hybrid semiconductor structure, e.g., carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide, alloy semiconductor, or a combination thereof.
  • the substrate 201 may include a silicon-on-insulator (SOI) structure.
  • the substrate 201 may also include other materials, such as a multi-layered structure of epitaxial layer or buried layer.
  • Substrate 201 may include a substrate layer 201a and an epitaxial layer 201b.
  • Epitaxial layer 201b may be grown on the one side of the substrate layer 201a.
  • the epitaxial layer 201b may be a one-time growth N-type single epitaxial layer on the substrate layer 201a.
  • the thickness of the epitaxial layer 201b may be determined based on particular requirements of semiconductor devices containing the IGBT 200.
  • the epitaxial layer 201b may be formed on the top or front side of the substrate layer 201a or on the back side of the substrate layer 201a.
  • the substrate layer 201a may be a silicon substrate. Other methods and/or materials may also be used to form epitaxial layer 201b.
  • the IGBT 200 also includes a well region 202, a collector drift region 205, an emitter drift region 206, a collector 207, an emitter 208, and a gate 209.
  • the well region 202 may be formed in the epitaxial layer 201b.
  • the well region 202 may be a P-type doping region and may be formed by certain processes, such as first forming a photoresist pattern at the surface of the epitaxial layer 201b using photolithography, and forming the well region 202 by ion implantation using the photoresist pattern as a mask.
  • the ion implantation may use boron ion and/or other similar ions.
  • Gate 209 is formed on the epitaxial layer 201b through a gate oxide layer 203 and a polysilicon gate layer 204.
  • the gate oxide layer 203 and the polysilicon gate layer 204 may form a gate region for forming gate 209.
  • the gate region from the gate oxide layer 203 and the polysilicon gate layer 204 may cover the junction between the epitaxial layer 201b and the well region 202.
  • the gate oxide layer 203 and the polysilicon gate layer 204 may be formed by certain processes. For example, an oxide layer may be first formed on the surface of the epitaxial layer 201b using a thermal oxidation process, and a polysilicon layer may be deposited on the surface of the oxide layer.
  • a gate pattern is formed by a lithography process, and the oxide layer and the polysilicon layer outside the gate region in the gate pattern are removed by an etching process using the gate pattern as a mask.
  • the remaining oxide layer and polysilicon layer form the gate oxide layer 203 and the polysilicon gate layer 204, i.e., the gate region.
  • the oxide layer may be oxide silicon, and the polysilicon layer may include doped polysilicon, or a composite layer of polysilicon and metal silicide formed on the polysilicon.
  • the gate oxide layer 203 and the polysilicon gate layer 204 cover and connect the junction between the well region 202 and the epitaxial layer 201b. Other materials and configuration may also be used.
  • the collector drift region 205 and the emitter drift region 206 are formed in the epitaxial layer 201b. More particularly, respective patterns for the collector drift region 205 and the emitter drift region 206 can be formed by photolithography, and ion implantation processes are used to form the collector drift region 205 and the emitter drift region 206 using the respective patterns. For example, a P+ implantation in the pattern area of the collector drift region can form the collector drift region 205, and an N+ implantation in the pattern area of the emitter drift region can form the emitter drift region 206. Other ions and types may also be used.
  • the emitter drift region 206 in the well region 202 may overlap with the gate oxide layer 203, i.e., the gate oxide layer 203 may cover a junction between the emitter drift region 206 and the well region 202.
  • the collector 207 is formed on the collector drift region 205; the emitter 208 is formed on the emitter drift region 206; and the gate 209 is formed on the gate region (i.e., gate oxide layer 203 and polysilicon gate layer 204).
  • the emitter 208 can be configured to cover a junction between the emitter drift region 206 and the well region 202.
  • the gate oxide layer 203 may cover one side of the junction between the emitter drift region 206 and the well region 202, and the emitter 208 may cover the other side of the junction between the emitter drift region 206 and the well region 202.
  • Other configuration may also be used.
  • the collector 207 may be formed via certain processes. For example, an isolation layer (not shown) may be first deposited on the surface of the substrate 201, e.g., a dielectric layer. A photoresist pattern (not shown) may then be formed by a photolithography process on the dielectric layer. The photoresist pattern has a through-hole pattern corresponding to the collector 207. Further, an etching process is performed on the dielectric layer using the photoresist pattern as a mask to form a through-hole in the dielectric layer. Afterwards, metal is used to connect the collector drift region 205 via the through-hole to form the collector 207 (i.e., the collector electrode). The emitter 208 (the emitter electrode) and the gate 209 (the gate electrode) may be formed in similar ways, and the details of the processes are omitted.
  • Figure 2 shows that the collector drift region 205 and the emitter drift region 206 are formed on different sides of the gate oxide layer 203 and the polysilicon gate layer 204, other configurations may also be used.
  • the collector drift region 205 and the emitter drift region 206 may be formed on the same side of the gate oxide layer 203 and the polysilicon gate layer 204.
  • the collector drift region 205 and the emitter drift region 206 are formed on the same side of the substrate 201, e.g., the same epitaxial layer 201b.
  • the epitaxial layer 201b may have N-type doping
  • the substrate layer 201a may have P-type doping
  • the well region 202 may have P-type doping
  • the collector drift region 205 may have P-type doping
  • the emitter drift region 206 may have N-type doping.
  • Other doping types and configurations may also be used.
  • FIG. 3 illustrates another exemplary IGBT 300 consistent with the disclosed embodiments.
  • IGBT 300 may be a PT-type IGBT. As shown in Figure 3, IGBT 300 may be similar to IGBT 200 as shown in Figure 2. However, IGBT 300 also includes a buffer region 210 in the epitaxial layer 201b, and the collector drift region 205 is surrounded by the buffer region 210. Further, as previously explained, the collector drift region 205 may have P-type doping. Thus, the buffer region 210 may have N-type doping. Other configurations may also be used.
  • FIG 4 illustrates an exemplary process 400 for manufacturing an IGBT consistent with the disclosed embodiments.
  • IGBT 200 shown in Figure 2 is used as the corresponding device being manufactured by the process 400.
  • a substrate is provided (S401). More particularly, a substrate (e.g., a substrate layer) is provided and an epitaxial layer is grown on one side of the substrate such that the substrate contains a substrate layer and an epitaxial layer.
  • the epitaxial layer may also be doped, e.g., N-type doping.
  • Figure 5A shows a corresponding IGBT 200 after forming the epitaxial layer.
  • an epitaxial layer 201b is formed on a substrate layer 201a, and the substrate layer 201a and the epitaxial layer 201b form the substrate 201.
  • the epitaxial layer 201b may be a one-time growth N-type epitaxial layer on the substrate layer 201a.
  • the thickness of the epitaxial layer 201b may be determined based on particular predetermined requirements. Further, the epitaxial layer 201b may be formed on the top or front side of the substrate layer 201a or on the back side of the substrate layer 201a, which may be silicon.
  • a well region is formed in the epitaxial layer (S402).
  • Figure 5B shows a well region 202 formed in the substrate (i.e., epitaxial layer 201b) and the well region 202 may be a P-type doping region.
  • a photoresist pattern is first formed at the surface of the epitaxial layer 201b using photolithography, and the well region 202 is then formed by ion implantation using the photoresist pattern as a mask.
  • the ion implantation may use boron ion and/or other types of ions.
  • a gate oxide layer and a polysilicon gate layer are formed at a junction between the well region and the epitaxial layer (S403). That is, the gate oxide layer and the polysilicon gate layer may form a gate region for forming a gate.
  • Figure 5C shows gate oxide layer 203 and polysilicon gate layer 204 formed on the junction between the well region 202 and the epitaxial layer 201b. In other words, the gate oxide layer 203 and the polysilicon gate layer 204 cover and connect the junction between the well region 202 and the epitaxial layer 201b.
  • an oxide layer may be first formed on the surface of the epitaxial layer 201b using a thermal oxidation process, and a polysilicon layer may be deposited on the surface of the oxide layer.
  • the oxide layer includes at least oxide silicon.
  • a gate pattern is formed by a photolithography process, and the oxide layer and the polysilicon layer outside the gate region in the gate pattern are removed by an etching process using the gate pattern as a mask. The remaining oxide layer and polysilicon layer form the gate oxide layer 203 and the polysilicon gate layer 204, respectively.
  • Other materials may also be used.
  • the gate region may include doped polysilicon, or a composite layer of polysilicon and metal silicide formed on the polysilicon.
  • a collector drift region is formed in the epitaxial layer, and an emitter drift region is formed in the well region in the same epitaxial layer (S404).
  • Figure 5D shows a collector drift region 205 formed in the epitaxial layer 201b, and an emitter drift region 206 formed in the well region 202.
  • respective patterns for the collector drift region 205 and the emitter drift region 206 are formed by photolithography, and ion implantation processes are used to form the collector drift region 205 and the emitter drift region 206 using the respective patterns.
  • a P+ implantation in the pattern area of the collector drift region may be used to form the collector drift region 205
  • an N+ implantation in the pattern area of the emitter drift region may be used to form the emitter drift region 206.
  • Other ions and types may also be used. Because of the spreading drift, the emitter drift region 206 in the well region 202 may overlap with the gate oxide layer 203, i.e., the gate oxide layer 203 may cover a junction between the emitter drift region 206 and the well region 202.
  • collector drift region metal contacts are made on the collector drift region, the emitter drift region, and the polysilicon gate layer to form the collector electrode, emitter electrode, and gate electrode, respectively (S405).
  • Figure 5E shows the formation of the collector 207, emitter 208, and gate 209.
  • the emitter 208 may be arranged to cover one side of the junction between the emitter drift region 206 and the well region 202; while the gate oxide layer 203 may be arranged to cover the other side of the junction between the emitter drift region 206 and the well region 202.
  • Metal contact is made on the collector drift region 205 to form the collector electrode, metal contact is made on the emitter drift region 206 to form the emitter electrode, and metal contact is made on the polysilicon gate layer 204 to form the gate electrode.
  • an isolation layer may be first deposited on the surface of the substrate 201, e.g., a dielectric layer.
  • a photoresist pattern (not shown) may then be formed by a photolithography process on the dielectric layer.
  • the photoresist pattern has a through-hole pattern corresponding to the collector 207.
  • an etching process is performed on the dielectric layer using the photoresist pattern as a mask to form a through-hole in the dielectric layer.
  • metal is used to connect the collector drift region 205 via the through-hole to form the collector 207 (i.e., the collector electrode).
  • the emitter 208 (or the emitter electrode) and the gate 209 (the gate electrode) may be formed similarly.
  • a buffer region is formed in the epitaxial layer 201b.
  • a photoresist pattern of the buffer region is formed on the surface of the epitaxial layer 201b using photolithography. N+ ion may be implanted using the photoresist pattern as a mask to form the buffer region 210.
  • the collector drift region 205 may then be formed in the buffer region 210 and is surrounded by the buffer region 210.
  • Other configurations may also be used
  • the collector of the IGBT can be formed on the same side of the substrate as the emitter and the gate, which makes it more convenient to wire the IGBT with other semiconductor devices and to integrate the IGBT with other semiconductor devices. It is understood that the disclosed embodiments may be applied to any semiconductor devices. Various alternations, modifications, or equivalents to the technical solutions of the disclosed embodiments can be obvious to those skilled in the art.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thyristors (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

La présente invention concerne un transistor bipolaire à porte isolée. Le transistor bipolaire à porte isolée comprend un substrat contenant une couche de substrat et une couche épitaxiale formée sur un côté de la couche de substrat. Le transistor bipolaire à porte isolée comprend également une zone de puits formée dans la couche épitaxiale, et une zone de grille formée au-dessus d'une jonction entre la zone de puits et la couche épitaxiale. En outre, le transistor bipolaire à porte isolée comprend une zone de dérivation de collecteur formée dans la couche épitaxiale et une zone de dérivation d'émetteur formée dans la zone de puits. Le transistor bipolaire à porte isolée comprend également un collecteur formé sur la zone de dérivation de collecteur, un émetteur formé sur la zone de dérivation d'émetteur, et une grille formée sur la zone de grille. Le collecteur, l'émetteur et la grille sont disposés sur un même côté de la couche de substrat.
PCT/CN2011/083300 2010-12-06 2011-12-01 Transistor bipolaire à porte isolée et son procédé de fabrication WO2012075905A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN2010105744325A CN102487078A (zh) 2010-12-06 2010-12-06 绝缘栅双极型功率管及其制造方法
CN201010574432.5 2010-12-06

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CN103325821A (zh) * 2013-06-19 2013-09-25 南宁市柳川华邦电子有限公司 一种绝缘栅双极型双向可选功率管
CN104347397B (zh) 2013-07-23 2018-02-06 无锡华润上华科技有限公司 注入增强型绝缘栅双极型晶体管的制造方法
CN104576365B (zh) * 2013-10-25 2017-11-21 无锡华润上华科技有限公司 cluster‑IGBT的制备方法
CN109994470A (zh) * 2017-12-29 2019-07-09 苏州东微半导体有限公司 一种半导体功率器件
CN109994549B (zh) * 2017-12-29 2020-12-11 苏州东微半导体有限公司 半导体功率器件
CN109994538A (zh) * 2017-12-29 2019-07-09 苏州东微半导体有限公司 一种半导体超结功率器件
US11189698B2 (en) 2017-12-29 2021-11-30 Suzhou Oriental Semiconductor Co., Ltd Semiconductor power device
CN109994468B (zh) * 2017-12-29 2020-11-17 苏州东微半导体有限公司 半导体超结功率器件

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