WO2012073317A1 - Method of manufacturing recycled semiconductor wafer - Google Patents

Abstract

With respect to the manufacture of semiconductor integrated circuit devices, the percentage of the total loaded wafer as raw material thereof which is discharged from the line externally thereto from the loading of the wafer through the stages prior to the wafer chip making step, i.e., of used wafer, is very large, and hence, the recycling of the used wafer is considered to be crucial. The present invention provides a method of recycling used wafer, wherein: a structural layer on a substrate on a device face (obverse-side main face) is removed by wafer etching; thereafter, a comparatively rigid polishing pad and a slurry comprising free abrasive grains are used in executing a wet chemical mechanical polish, thus removing a pattern of unevenness on the face which is intended to serve as the device face; and thereafter, a comparatively flexible regular polishing pad and the slurry comprising free abrasive grains are used in removing particles on the same face.

Description

Manufacturing method of recycled semiconductor wafer

The present invention relates to a recycled semiconductor wafer suitable for manufacturing a semiconductor integrated circuit device or the like or testing in a manufacturing process from a used semiconductor wafer or the like on which a layer (functional layer) such as a circuit or a pattern including transistors and wirings is formed. It relates to a method of manufacturing.

Japanese Laid-Open Patent Publication No. 2001-358107 (Patent Document 1) or corresponding US Patent Publication No. 2001-0039101 (Patent Document 2) recycles a used semiconductor wafer into a semiconductor wafer suitable for manufacturing a semiconductor integrated circuit. As a method for this, a technique is disclosed in which isomeric substances on a semiconductor wafer are removed by wet etching, and then polishing is performed.

Japanese Patent Application Laid-Open No. 2004-260137 (Patent Document 3) or corresponding US Pat. No. 7,022,586 (Patent Document 4) also discloses a method for reclaiming a used semiconductor wafer into a semiconductor wafer suitable for manufacturing a semiconductor integrated circuit. A similar technique is disclosed.

Japanese Laid-Open Patent Publication No. 2002-057129 (Patent Document 5) or corresponding US Pat. No. 6,406,923 (Patent Document 6) discloses a method of reclaiming a used semiconductor wafer into a semiconductor wafer suitable for manufacturing a semiconductor integrated circuit. In order to reduce metal contamination instead of mechanical polishing, a technique using blasting or hard particle pressure welding is disclosed.

In Japanese Laid-Open Patent Publication No. 2007-243159 (Patent Document 7), a technique for reclaiming a semiconductor wafer on which a film such as a metal film is formed, a so-called dummy wafer, so that it can be used again by dry etching is disclosed. ing.

Japanese Unexamined Patent Application Publication No. 2004-356231 (Patent Document 8) or corresponding US Patent Publication No. 2007-0023395 (Patent Document 9) discloses that polishing using a slurry containing loose abrasive grains and a porous polyurethane polishing pad is used. A method of manufacturing a semiconductor wafer as a raw material is disclosed.

Japanese Laid-Open Patent Publication No. 2004-337992 (Patent Document 10) discloses a method of performing a CMP (Chemical Mechanical Polishing) process of a semiconductor manufacturing process using a fixed abrasive polishing pad.

Electronic Journal October 2007, page 47 (Non-Patent Document 1) describes a method for reclaiming a used semiconductor wafer into a semiconductor wafer suitable for manufacturing a semiconductor integrated circuit, without using polishing, wet etching and dry etching. A technique is disclosed in which the semiconductor wafer can be regenerated while the loss of the semiconductor wafer is suppressed to 9 micrometers by using together.

JP 2001-358107 A US Patent Publication 2001-0039101 JP 2004-260137 A US Pat. No. 7,022,586 JP 2002-057129 A US Pat. No. 6,406,923 JP 2007-243159 PR JP 2004-356231-A US Patent Publication No. 2007-0023395 Japanese Laid-Open Patent Publication No. 2004-337992

In the manufacture of a semiconductor device or a semiconductor integrated circuit device (wafer process), an element is formed mainly on the device surface of a single crystal silicon wafer, and a wiring layer is deposited on the device surface as necessary. A large number of unit chip areas are completed. Thereafter, the wafer is usually subjected to back surface grinding to a predetermined thickness, and then divided into unit chip regions (steps such as back surface grinding and division are collectively referred to as “wafer chip forming step”). However, since the ratio of the wafers that are discharged from the line to the outside, that is, the “halfway discharged wafers (used wafers)” in the stage before the wafer chip formation process from the wafer input as a raw material, is extremely high, The recycling of used wafers is regarded as important.

Generally, the thickness of a wafer is around 800 micrometers, and it is judged that a reduction in thickness of around 100 micrometers is acceptable in relation to a semiconductor manufacturing apparatus. However, since the main wafer recycling techniques so far use a lot of mechanical grinding, it has been unavoidable to reduce the thickness of several tens of micrometers by one recycling. In addition, a method using both wet etching and dry etching has been developed. However, it is still only possible to suppress the thickness reduction to about 9 micrometers. With such a wafer recycling technique that involves a large thickness reduction, it is not possible to ensure a sufficient number of times of recycling, and it is not possible to expand the reuse of wafers.

Hereinafter, the place where the inventors of the present application have examined the recycling of wafers will be described. Normally, when forming an integrated circuit on a semiconductor wafer, an oxide film layer for element isolation is formed by a shallow trench isolation (STI) method or the like. The depth is usually about 0.2 to 0.4 micrometers, but some devices may be 0.5 to 1.0 micrometers. Furthermore, it is necessary to form n-type and p-type deep well regions in order to create a CMOS (Complementary Metal Oxide Semiconductor) or CMIS (Complementary Metal Insulator Semiconductor) device using both n and p channels. . As a well structure, a double well in which two wells of p and n are formed in a low impurity concentration silicon wafer (mainly p-type, partly n-type), deep silicon substrate using high energy ion implantation, There is a triple well in which another well is formed. In the latter case, ions are implanted deeper, but the depth is known to be about 2 to 3 micrometers.

Therefore, when reproducing for the production of such a semiconductor integrated circuit, theoretically, the optimum loss amount is about 3 micrometers, and even if a large safety margin is taken, it is about 3 to 4 micrometers. When remanufacturing as a test wafer in process, a smaller amount of loss should be sufficient. However, a general wafer reclamation method far exceeds these theoretical values.

Therefore, a technique for recycling a used semiconductor wafer into a semiconductor integrated circuit device (or semiconductor device) manufacturing wafer or a test wafer used in the same process with a smaller amount of loss is expected.

The present invention has been made to solve these problems.

An object of the present invention is to provide a semiconductor wafer recycling technique suitable for a manufacturing process of a semiconductor device or a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

A typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, according to one aspect of the present invention, there is provided a polishing pad that does not have a relatively hard fixed abrasive grain after removing a structural layer on a substrate on a device surface (front side main surface) by wet etching in a method for reclaiming a used wafer. After removing the concavo-convex pattern on the surface to be the device surface by performing wet chemical mechanical polishing using a slurry having free abrasive grains, a polishing pad and free abrasive grains having relatively soft fixed abrasive grains are removed. Using this slurry, particles on the same surface are removed.

The following is a brief description of the effects obtained by the representative inventions disclosed in the present application.

That is, in the method for reclaiming used wafers, after removing the structural layer on the substrate on the device surface (front side main surface) by wet etching, the polishing pad does not contain slurry containing loose abrasive grains and relatively hard fixed abrasive grains After removing the uneven pattern on the surface to be the device surface by performing wet chemical mechanical polishing, using a slurry containing free abrasive grains and a polishing pad that does not have relatively soft fixed abrasive grains Since the particles on the same surface are removed, the amount of loss in wafer regeneration can be greatly reduced.

It is a main process block flowchart in the manufacturing method of the reproduction | regeneration semiconductor or board | substrate of one embodiment of this invention. It is sectional drawing of the used wafer which is the object of the manufacturing method of the reproduction | regeneration semiconductor or board | substrate of one Embodiment of this invention. FIG. 3 is an enlarged cross-sectional view of a wafer corresponding to a wafer partial enlarged portion G of FIG. FIG. 4 is an enlarged cross-sectional view of a wafer showing a typical cross-sectional structure after performing wet etching on the wafer of FIG. 3. It is the surface shape bird's-eye view which observed the typical surface shape after performing wet etching using the non-contact surface shape measuring device Zygo of Canon. FIG. 6 is a data plot diagram showing a profile in the X direction (lateral direction) of FIG. 5. 1 is a schematic cross-sectional view of a single-wafer CMP (Chemical Mechanical Polishing) apparatus used for polishing with a polishing pad that contains slurry containing loose abrasive grains and no fixed abrasive grains. It is a polishing pad periphery expanded cross-sectional schematic diagram for demonstrating the condition of grinding | polishing by the polishing pad which does not have the slurry and loose abrasive containing a free abrasive grain. FIG. 9 is a schematic enlarged cross-sectional view of a polishing pad corresponding to an enlarged portion H of the polishing pad in FIG. 8. It is a cross-sectional schematic diagram for demonstrating the mode of the wafer after completion | finish of main grinding | polishing. It is a cross-sectional schematic diagram of a batch type CMP apparatus used for main polishing, finish polishing, and final polishing. FIG. 2 is a process block flow diagram illustrating an example of detailed steps of the cleaning process of FIG. 1. It is explanatory drawing of the relationship between the uneven | corrugated pattern remainder after main polishing, and the final polishing characteristic. It is a columnar graph which shows the experimental data showing the presence or absence of the pattern loss | disappearance by finishing polishing in case there exists a pattern residue after main polishing. It is a columnar graph which shows the experimental data showing the main polishing time and finishing polishing time dependence of silicon loss (substrate loss amount). It is a columnar graph which shows the experimental data showing the finishing polishing time dependence of silicon loss (substrate loss amount). It is a columnar graph which shows the experimental data showing the main polishing time and finish polishing time dependence of TTV (Total Thickness Variation). It is a columnar graph which shows the experimental data showing the finish polishing time dependence of TTV. It is a columnar graph which shows the experimental data showing the finishing polishing time dependence of the number of residual particles. FIG. 6 is a plot of various polishing pad hardnesses that can be used for main polishing and finish polishing.

[Outline of Embodiment]
First, an outline of a typical embodiment of the invention disclosed in the present application will be described.

1. A method for producing a recycled semiconductor wafer including the following steps:
(A) A step of removing the structural layer on the substrate by performing wet etching on the first main surface of the used semiconductor wafer which is the device surface of the recycled semiconductor wafer ;
(B) After the step (a), wet chemistry using a polishing slurry containing a first polishing pad having a first hardness and free abrasive grains on the first main surface of the semiconductor wafer. Removing the concavo-convex pattern on the semiconductor surface on the first main surface side by executing a first polishing process by mechanical polishing;
(C) After the step (b), containing a second polishing pad and loose abrasive grains having a second hardness softer than the first hardness with respect to the first main surface of the semiconductor wafer Removing the particles on the semiconductor surface on the first main surface side by executing a second polishing process by wet chemical mechanical polishing using a polishing slurry.

2. In the method for manufacturing a recycled semiconductor wafer according to the first item, the first polishing process is performed in a state where a polishing head is on the upper side of the first polishing pad.

3. In the method for manufacturing a recycled semiconductor wafer according to the first or second aspect, there is no grinding step at least between the steps (a) and (b).

4. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 3, the polishing process of 2 is a state in which the polishing head is on the upper side of the second polishing pad, and an additional load is applied to the polishing head. It is executed in the added state.

5. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 4, there is no grinding step at least between the steps (a) and (c).

6). The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 5 further includes the following steps:
(D) After the step (c), wet chemical mechanical polishing using a third polishing pad having a third hardness lower than that of the first polishing pad and a polishing slurry containing loose abrasive grains The third polishing process is performed by the polishing load due to the weight of the polishing head without applying an additional load to the polishing head in a state where the polishing head is on the upper side of the third polishing pad.

7. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 6, the first polishing pad includes a polyurethane resin member as a main component.

8. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 7, the first hardness (durometer D) is 40 or more and 55 or less.

9. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 8, the second hardness (durometer D) is 15 or more and 35 or less.

10. 10. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 9, the polishing time for the first polishing process is about 2 minutes.

11. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 10, the polishing time for the second polishing treatment is about 1 minute.

12. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 10, the polishing time for the second polishing treatment is about 5 minutes.

13. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 12, the first polishing process is performed by wet chemical mechanical polishing using a polishing pad that does not contain fixed abrasive grains.

14. 14. In the method for manufacturing a recycled semiconductor wafer according to any one of Items 1 to 13, the second polishing process is performed by wet chemical mechanical polishing using a polishing pad that does not contain fixed abrasive grains.

15. 15. In the method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 14, there is no grinding step at least between the steps (a) and (d).

16. 16. The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 15, wherein the first polishing process is performed in a batch manner.

17. 17. The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 16, wherein the second polishing process is performed in a batch manner.

18. 18. In the method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 17, the third polishing process is performed in a batch manner.

19. 19. In the method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 18, the used semiconductor wafer is a single crystal silicon-based wafer.

20. 19. The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 18, wherein the recycled semiconductor wafer is a test wafer.

21. 19. The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 18, wherein the recycled semiconductor wafer is a product wafer.

22. 19. The method for manufacturing a recycled semiconductor wafer according to any one of items 1 to 18, wherein the recycled semiconductor wafer is a dummy wafer.

[Description format, basic terms, usage in this application]
1. In the present application, the description of the embodiment may be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Each part of a single example, one part is the other part of the details, or part or all of the modifications. Moreover, as a general rule, the same part is not repeated. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

2. Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It is not excluded that one of the main components. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but also includes SiGe alloys, other multi-component alloys containing silicon as a main component, and members containing other additives. Needless to say. Similarly, “silicon oxide film” is not only relatively pure undoped silicon oxide (Undoped ili Silicon dioxide Dioxide), but also FSG (Fluorosilicate Glass), TEOS-based silicon oxide (TEOS-based silicon oxide), SiOC ( Silicon Oxicarbide) or Carbon-doped Silicon Oxide (Carbon-doped Silicon Oxide) or OSG (Organosilicate Glass), PSG (Phosphorus Silicate Glass), BPSG (Borophosphosilicate Glass), etc. , Coated silicon oxide such as nano-clustering silica (NSC), silica-based low-k insulating film (porous insulating film) with pores in the same material, and the main components Needless to say, it includes a composite film with other silicon-based insulating films as elements.

3. Similarly, suitable examples of graphics, positions, attributes, and the like are given, but it is needless to say that the present invention is not strictly limited to those cases unless explicitly stated otherwise, and unless otherwise apparent from the context.

4. In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

5. “Wafer” usually refers to a single crystal silicon wafer (silicon-based) on which a semiconductor integrated circuit device (same as a semiconductor device or an electronic device) is formed, but an epitaxial wafer, an SOI substrate, an LCD glass substrate, etc. Needless to say, a composite wafer such as an insulating substrate and a semiconductor layer is also included. Needless to say, a non-silicon wafer such as GaAs may be used.

6. “Wafer” includes a product wafer or product wafer on which a product is formed, a test wafer such as a monitor wafer that is processed simultaneously with or before or after the product wafer for process monitoring or testing, and maintenance of the apparatus. And a dummy wafer used for a test run or the like. Test wafers and dummy wafers are collectively referred to as “non-product wafers”. What is to be reclaimed is a wafer that has not reached the final process of the wafer process (for example, before grinding), and is a so-called “used product wafer” (slipped wafer). The other target for regeneration is “used non-product wafer”. These are collectively referred to as “used wafers”.

Here, reclaiming a wafer mainly means that a used wafer can be reused as a non-product wafer. However, in some cases, a used product wafer (or a used non-product wafer) can be recycled as a product wafer.

7. In the present application, “CMP (Chemical Mechanical Polishing) or chemical mechanical polishing” includes not only those using free abrasive grains but also those using fixed abrasive grains, so-called dry polishing, etc., unless otherwise specified. .

Dry polishing was developed for the purpose of stress relief after back grinding (usually cutting using a wheel in which high-quality abrasive grains such as diamond abrasive grains are hardened with vitrified bonds). Thus, mirror polishing can be performed in a dry state without using a polishing liquid. Classifying, because a polishing wheel is used, it belongs to fixed abrasive polishing.

Also, “wet chemical mechanical polishing” refers to “chemical mechanical polishing” using a polishing liquid, unless otherwise specified. Wet chemical mechanical polishing includes chemical mechanical polishing with loose abrasive grains (chemical mechanical polishing in a narrow sense) and chemical mechanical polishing with loose abrasive grains. In the present application, wet chemical mechanical polishing mainly using loose abrasive grains will be described.

Also, the “polishing pad containing no fixed abrasive” refers to a polishing pad that is dispersed and held in the polishing pad or on the surface (or both). On the other hand, “a polishing pad that does not contain fixed abrasive grains” is, in principle, used for free abrasive chemical mechanical polishing that uses a slurry containing abrasive grains as a polishing liquid. Abrasive grains are not dispersed and held on the surface and inside. However, free abrasive grains may adhere to the surface and the vicinity thereof by performing polishing.

In this application, the term “slurry” refers to a polishing liquid that substantially contains abrasive grains before being supplied onto the polishing pad.

8. “Substrate loss” (silicon loss) is the thickness (cutting amount or polishing amount) from the upper end surface of the semiconductor substrate region 1s (FIGS. 3 and 4) of the wafer to the device surface 1a of the wafer after polishing or the like. Indicates.

“Additional load (polishing pressure)” refers to a mechanical load applied in addition to the weight of the polishing head (load due to its own weight). On the other hand, the “abrasive load” is the sum of an additional load and a load due to its own weight.

[Details of the embodiment]
The embodiment will be further described in detail. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments for carrying out the invention, and the repetitive description thereof will be omitted.

Regarding the recycling method of used semiconductor wafers, there are the following prior applications by the present inventors. Specifically, Japanese Patent Application No. 2007-322809 (filing date: November 26, 2007), Japanese Patent Application No. 2008-218723 (filing date: July 17, 2008), and international application PCT, which is a subsequent application of these, / JP2009 / 001081 (International filing date March 11, 2009).

1. Description from reception of used wafer to wet etching in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention (mainly FIG. 1 and FIGS. 2 to 6)
FIG. 1 is a main process block flow diagram in a method for manufacturing a recycled semiconductor or substrate according to an embodiment of the present invention. FIG. 2 is a cross-sectional view of a used wafer which is an object of a method for manufacturing a recycled semiconductor or substrate according to an embodiment of the present invention. FIG. 3 is an enlarged cross-sectional view of the wafer corresponding to the wafer partial enlarged portion G of FIG. FIG. 4 is an enlarged cross-sectional view of the wafer showing a typical cross-sectional structure after wet etching is performed on the wafer of FIG. FIG. 5 is a bird's eye view of a surface shape observed by using a non-contact surface shape measuring instrument Zygo manufactured by Canon Inc. after performing a wet etching. FIG. 6 is a data plot diagram showing a profile in the X direction (lateral direction) of FIG. Based on these, the process from receiving a used wafer to wet etching in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention will be described.

First, as shown in FIG. 1, when a used wafer is received 101, it is desirable to perform a simple inspection to determine whether or not it can be regenerated (but not essential). This is because a used wafer having scratches or chips is not only wasteful of the recycling process itself but also becomes a source of contamination and dust. In addition, it is desirable (but not essential) to perform the same or simpler cleaning process as in section 3 before the following process. These are called “reproduction preparation processing”.

As shown in FIGS. 2 and 3, on the front surface 1a (device surface or first main surface, that is, the surface opposite to the back surface 1b) of the wafer 1 at the time of reception, the semiconductor substrate internal structural layer 2 (main surface) is provided. And a structural layer 3 on the semiconductor substrate (mainly a product wafer, a test wafer, and a dummy wafer). Examples of the structure layer 2 in the semiconductor substrate are a well region 1w of the wafer, an STI insulating film (element isolation region) 4, and other impurity doped regions. That is, it is a portion other than the non-processed region 1n in the semiconductor substrate region 1s of the wafer 1.

On the other hand, examples of the structural layer 3 on the semiconductor substrate include a gate structure 5 such as a gate insulating film, a gate electrode, and a sidewall, a metal wiring 7 constituting a multilayer wiring layer, an interlayer insulating film 6, a bonding pad 8, and a final passivation film. 9 mag.

As shown in FIG. 1, a wet etching process 102 is performed on the used wafer 1 for which the regeneration preparation process has been completed. The wet etching process 102 is usually performed by a batch process. For example, about 25 wafers (here, a silicon single crystal 300φ wafer will be described as an example, but 200φ or 450φ may be used) are accommodated in a cleaning jig made of Teflon (registered trademark, the same applies hereinafter), and an etching solution Immerse in (chemical). As an etching solution, for example, about 0.3% by weight (the preferred concentration range is about 0.2 to 0.5% by weight, and other concentration ranges are not excluded. Appropriate additives For example, hydrofluoric acid (HF). The temperature of the chemical solution is normal temperature, that is, about 25 degrees Celsius (15 to 30 degrees Celsius can be exemplified as a suitable range in mass production). The etching time (processing time) is, for example, about 15 minutes. One minute to 30 minutes can be exemplified as a suitable range. The required etching time is calculated by dividing the maximum thickness of the structure layer 3 on the semiconductor substrate in the wafer to be processed by the etching rate of the silicon oxide film (about 0.6 μm / min). Then, an over-etching time (for example, about 20% of the required etching time) may be added thereto.

Normally, even if there is a film that is hardly soluble in a silicon oxide etching solution such as a silicon nitride film, it is removed by the isotropic property of wet etching. However, if it is difficult, hot phosphoric acid treatment (in the case of a silicon nitride film) or the like may be inserted along the way. When the poorly soluble film is an organic substance, a treatment with an organic solvent may be inserted, and when the hardly soluble film is a metal film, a treatment with an acid or the like that dissolves the film may be inserted. As described above, when two or more chemical liquid treatments are performed, it is desirable to introduce a pure water rinsing treatment in the same manner as in the section 3 (not essential).

FIG. 4 shows a cross section of the wafer 1 after the wet etching process 102 is completed. Of the structural layer 3 on the semiconductor substrate, almost all but the gate structure 5 is removed. The gate structure 5 may be removed (usually, it can be removed if immersed for a long time). In addition, the field insulating film such as the STI insulating film 4 and the LOCOS insulating film is the semiconductor substrate internal structural layer 2, but is removed together under normal conditions, and the element isolation trench 4t is exposed. There is also a choice not to remove the field insulating film (for example, to shorten the overetch time).

FIG. 5 shows a three-dimensional image obtained by the non-contact surface measuring device on the front side surface 1a of the wafer in the state of FIG. Further, the surface profiles in the X (lateral) direction are shown in FIG. From these, it can be seen that in this example, there is a step of about 298 nm (generally about 0.2 to 1 micrometer).

Next, the process proceeds to the polishing step 103 with loose abrasive grains in FIG. 1 (section 2).

2. Description from used wafer final polishing to final polishing and final polishing in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention (mainly FIG. 1, FIG. 4 and FIG. 7 to FIG. 10)
FIG. 7 is a schematic cross-sectional view of a single-wafer CMP (Chemical Mechanical Polishing) apparatus used for polishing with a slurry containing loose abrasive grains and a polishing pad having no fixed abrasive grains. FIG. 8 is an enlarged schematic cross-sectional view of the periphery of the polishing pad for explaining the state of polishing with a slurry containing loose abrasive grains and a polishing pad having no fixed abrasive grains. FIG. 9 is a schematic enlarged sectional view of the polishing pad corresponding to the enlarged portion H of the fixed abrasive polishing pad in FIG. FIG. 10 is a schematic cross-sectional view for explaining the state of the wafer after the main polishing is completed. A process from main polishing to final polishing of a used wafer in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention will be described with reference to FIGS. 1, 4, and 7 to 11.

As shown in FIG. 1, the first chemical etching by wet chemical mechanical polishing using a polishing pad containing no fixed abrasive is performed on the device surface 1 a (surface to be the device surface) of the wafer 1 on which the wet etching process 102 has been completed. The polishing process is executed. In this polishing, as shown in FIG. 4, the first polishing region (main polishing region) 11 is removed by polishing. The lower end 12 is slightly lower than the lower end of the well region 1w of the wafer in the case of a product wafer or the like. It goes to a deep position. In the case of a test wafer, a dummy wafer or the like without the impurity doped region or the element isolation region 4, the lower end 12 may be slightly below the upper end of the semiconductor substrate region 1s of the wafer.

Next, the free abrasive CMP apparatus 60a (wet chemical mechanical polishing apparatus using free abrasive grains) used in the polishing step 103 with free abrasive grains shown in FIG. 1 will be described with reference to FIG. As shown in FIG. 7, a polishing platen rotation drive unit 52 is provided on a polishing apparatus base unit 51, and a polishing platen 53 is provided on the polishing platen rotation drive unit 52 so as to rotate. A polishing pad 54 that does not contain fixed abrasive grains is affixed to the upper surface of the polishing platen 53. A polishing liquid nozzle 55 is provided on the polishing pad 54, and a polishing liquid (ie, slurry) 66 containing abrasive grains is supplied onto the polishing pad 54. Above the polishing pad 54, there is a polishing head holding portion 58, thereby holding the polishing head rotation driving portion 59. The wafer 1 to be processed is held on the lower surface of the polishing head 57 at the lower end of the polishing head rotation drive unit 59 with the device surface 1a facing downward and rotates.

The CMP apparatus applied to this step (the same applies to final polishing and final polishing) can be any apparatus ("CMP apparatus for integrated circuit planarization" used for planarization during the manufacturing process of a semiconductor integrated circuit device. ”). In particular, a strict accuracy is not required as in the case of a CMP device for planarizing an integrated circuit, so that even a relatively simple device can be applied. For example, SPM-19, SPM-33, MCP-302 manufactured by Fujikoshi Machinery Co., Ltd., FAM59 SPAW, FAM50 SPAW manufactured by SPEED FAM, and the like can be exemplified. Needless to say, Reflexion LK CMP manufactured by Applied Materials, which is commonly used as a CMP apparatus for planarizing integrated circuits, may be used.

FIG. 8 is an enlarged view of the cross section of FIG. As shown in FIG. 8, the polishing pad 54 that does not contain fixed abrasive grains includes a polishing pad base 54b having a thickness of about 0.5 to 2 millimeters, and a polishing pad main part 54a that does not contain fixed abrasive grains (for example, polyurethane-based). Non-woven polishing cloth). Non-diamond abrasive grains 67 (for example, silica abrasive grains, alumina abrasive grains, etc.) are dispersed and fixed in the main portion 54a of the polishing pad. As the hardness of the polishing pad (first polishing pad), for example, a hardness by durometer D (that is, Shore D) is about 50 (preferable range is, for example, about 40 or more and about 55 or less). . As a polishing pad suitable for use here, for example, a polishing pad IC1000 manufactured by Nitta Haas Co., Ltd. can be exemplified.

FIG. 9 shows an enlarged cross section corresponding to the enlarged portion H around the polishing pad not containing the fixed abrasive grains in FIG. As shown in FIG. 9, the abrasive grains are not dispersed in the main polishing pad 54a, and a large number of non-diamond abrasive grains 67 (for example, silica abrasive grains) float on the slurry 66 on the surface. ing.

An example of polishing conditions is as follows. The polishing load is, for example, about 30 kPa (in this case, if the load due to the weight of the polishing head is, for example, about 30 kPa, the additional load is 0 or relatively small), and the rotational speed of the polishing head 57 is, for example, 40 rpm. Degree. On the other hand, the rotation direction of the polishing platen 53 is the same as that of the polishing head 57, and the rotation speed is, for example, about 40 rpm. Further, it is desirable to use an alkaline polishing liquid 56 that does not substantially contain abrasive grains. As the alkaline polishing liquid 56, for example, an aqueous solution having a pH of about 11.5 (preferably about 10 to 12) including KOH or the like as one of main additives can be exemplified. . The supply rate of the alkaline polishing liquid 56 is, for example, about 200 ml / min. The polishing temperature is, for example, about 36 degrees Celsius, and the polishing time depends on the polishing amount, but if the polishing amount is about 1.5 micrometers, it is about 2 minutes.

Since the total polishing amount of final polishing and final polishing is at most about 1 micrometer, the substrate loss amount is about 2 to 2.5 micrometers.

1 is completed, the wafer 1 is in a state as shown in FIG. That is, the uneven pattern on the surface to be the device surface 1a of the wafer 1 has substantially disappeared. However, in this state, only the macro pattern disappears, and a large number of micro irregularities and particles adhering therebetween remain. Therefore, it is necessary to perform the following finishing polishing (second polishing process).

Hereinafter, the finish polishing 104 will be described. First, a CMP apparatus 60 (wet chemical mechanical polishing apparatus using a polishing pad that does not contain fixed abrasive grains) used for finish polishing 104 will be described. The structure is the same as that described in FIGS. Therefore, only different parts will be described. As described with reference to FIG. 7, a polishing pad 54 that does not contain fixed abrasive grains (a commercially available pad applicable to this, such as SUBA400 manufactured by Nita Haas Co., Ltd.) is attached to the upper surface of the polishing platen 53. ing. A polishing liquid nozzle 55 is provided on the polishing pad 54, and a polishing liquid 66 (slurry) containing abrasive grains (for example, non-diamond-based abrasive grains such as silica-based and alumina-based) is supplied onto the polishing pad 54. Has been. Above the polishing pad 54, there is a polishing head holding portion 58, thereby holding the polishing head rotation driving portion 59. The wafer 1 to be processed is held on the lower surface of the polishing head 57 at the lower end of the polishing head rotation drive unit 59 with the device surface 1a facing downward and rotates. An example of polishing conditions is as follows. The polishing load is, for example, about 230 kPa (in this case, if the load due to the weight of the polishing head is about 30 kPa, for example, the additional load is about 200 kPa), and the rotational speed of the polishing head 57 is, for example, about 45 rpm. On the other hand, the rotation direction of the polishing platen 53 is the same as that of the polishing head 57, and the rotation speed is, for example, about 45 rpm. The polishing liquid is preferably an alkaline polishing liquid 66 (slurry) containing loose abrasive grains. As the alkaline polishing liquid 66, for example, a polishing slurry having a pH of about 11.5 (preferably about 10 to 12 as a preferable range) containing KOH or the like as one of main additives can be exemplified. it can. The supply rate of the alkaline polishing liquid 66 is, for example, about 200 ml / min. The polishing temperature is, for example, about 35 degrees Celsius, and the polishing time is about 1 minute. As the hardness of the polishing pad (second polishing pad), for example, a hardness by durometer D (that is, Shore D) is about 22 (preferable range is, for example, about 15 or more and about 35 or less). . An example of the polishing slurry containing loose abrasive grains that can be used for this final polishing (second polishing process) is GLANZOX 1304 of Fujimi Corporation.

When the finish polishing 104 (second polishing process) in FIG. 1 is executed, the unevenness of the wafer surface is usually about 0.1 to several nm. The polishing amount at this time is about 100 nm. A preferable polishing amount range in the second polishing process is about 10 nm to 1 micrometer.

Thereafter, a relatively low load is applied by a polishing apparatus similar to that shown in FIG. 7 (for example, polishing may be performed only by the weight of the polishing head as in “water polishing” usually performed at the final stage of polishing). The final polishing is effective in removing haze and the like on the surface. Of course, it may be omitted if not necessary. As an example of this final polishing condition, the following can be exemplified, that is, the rotational speed of the polishing head 57 is, for example, about 25 rpm. On the other hand, the rotation direction of the polishing platen 53 is the same as that of the polishing head 57, and the rotation speed is, for example, about 25 rpm. Further, it is desirable to use an alkaline polishing liquid 56 containing free abrasive grains as the polishing liquid. As the alkaline polishing liquid 56, for example, an aqueous solution having a pH of about 11.5 (preferably about 10 to 12) including KOH or the like as one of main additives can be exemplified. . The supply rate of the alkaline polishing liquid 56 is, for example, about 200 ml / min. The polishing temperature is, for example, about 35 degrees Celsius, and the polishing time is about 5 minutes (the polishing amount is about several nm). A final polishing pad (third polishing pad) that does not contain fixed abrasive grains and that has a hardness (third hardness) in a range substantially similar to that of the finishing polishing pad is suitable (commercially applicable to this). (For example, Fujimi Corporation's SURFIN). An example of the polishing slurry containing loose abrasive grains that can be used for this final polishing (third polishing treatment) is Fujimi Corporation's GLANZOX 3900.

1 is transferred to the cleaning step 105 in FIG. 1 after finishing polishing 104 or final polishing 106 in FIG.

3. Description of the used wafer cleaning process in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention (mainly FIGS. 1 and 12)
FIG. 12 is a process block flow diagram showing an example of detailed steps of the cleaning process of FIG. Based on FIG. 1 and FIG. 12, a used wafer cleaning process in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention will be described.

1 The cleaning process 105 in FIG. 1 is performed on the wafer 1 on which the finish polishing 104 in FIG. 1 has been completed. This cleaning is technically not essential in consideration of the cleaning on the receiving side, but if performed, it has the effect of preventing the diffusion of defects or contamination (especially contamination due to slurry or the like) during shipment or transportation. Also, usually, the current CMP apparatus is often of a dry-in / dry-out type. Therefore, when the wafer double-side cleaning for removing the slurry component is performed in the post-CMP cleaning unit of the CMP apparatus, the following cleaning can be replaced by the post-CMP cleaning.

Usually, the following cleaning steps up to drying 115 are performed by batch processing. For example, about 25 wafers are accommodated in a Teflon cleaning jig and immersed in a cleaning solution (chemical solution). First, as shown in FIG. 12, the first chemical cleaning 111 for removing particles and organic substances is performed. As a chemical | medical solution, SC1 (Standard Clean 1) etc. can be illustrated, for example. That is, ammonia: hydrogen peroxide: water is about 1: 1: 5 by volume ratio (the concentration of the stock solution is 29% ammonia and 30% hydrogen peroxide). The liquid temperature is about 70 to 80 degrees Celsius, and the processing time is about 10 minutes, for example.

Next, as shown in FIG. 12, the first pure water rinse 112 is executed. The water temperature is room temperature, that is, about 25 degrees Celsius. An example of a suitable range for mass production is about 15 to 30 degrees Celsius. For example, the time is about 10 minutes (same as the first chemical cleaning 111) in order to adjust the timing.

Next, the second chemical cleaning 113 for removing metal contamination is executed. As a chemical | medical solution, SC2 (Standard Clean 2) etc. can be illustrated, for example. That is, the volume ratio of hydrochloric acid: hydrogen peroxide: water is about 1: 1: 5 (the concentration of the stock solution is 36% hydrochloric acid and 30% hydrogen peroxide). The liquid temperature is about 70 to 80 degrees Celsius, and the processing time is, for example, about 10 minutes (same as the first chemical cleaning 111).

Next, as shown in FIG. 12, the second pure water rinse 114 is executed. The water temperature is room temperature, that is, about 25 degrees Celsius. An example of a suitable range for mass production is about 15 to 30 degrees Celsius. For example, the time is about 10 minutes (same as the first chemical cleaning 111) in order to adjust the timing.

Next, as shown in FIG. 12, the wafer 1 drying process 115 is executed.

4). Consideration about main polishing process of used wafer in manufacturing method of reclaimed semiconductor wafer according to embodiment of present invention As described in section 2, the main polishing process of used wafer is relatively hard and does not include fixed abrasive grains. The reason why wet polishing using a polishing liquid (polishing slurry) containing a polishing pad and abrasive grains is effective is as follows.

(1) Since the polishing pad has a high hardness, flattening is fast. That is, the substrate loss amount is small.
(2) Since no grinding wheel is used (from the wet etching step 102 to the final polishing 106 in FIG. 1), no damage layer is generated. Therefore, the substrate loss amount can be greatly reduced.
Further, since no diamond abrasive grains are used, grinding marks and the like cannot be made.
(3) Since it is not necessary to use a polishing pad (fixed abrasive polishing pad) containing abrasive grains that is relatively difficult to produce a large size, it is easy to apply batch processing (finish polishing) And the same for the final polishing).

That is, as is generally done, when mechanical cutting or grinding such as grinding is used as the initial polishing, although a certain level of flattening is performed, a considerably thick altered layer or damaged layer remains. Then, in order to remove the deteriorated layer, secondary polishing is required, and as a result, the polishing amount, that is, the substrate loss amount is greatly increased. Therefore, in order to reduce the amount of substrate loss, mechanical cutting or grinding such as grinding is not used at all, or even if it is used, as in the present embodiment, it is minimized (that is, the grinding is substantially reduced. It is important not to generate a deteriorated layer or the like by using a mechanical cutting or grinding process such as a padding) or to make the thickness very thin. That is, basically, it is desirable not to apply mechanical processing with an altered layer having a considerable thickness, such as a grinding process, at least between the wet etching and the first polishing process. It is more preferable not to apply mechanical processing with an altered layer having a considerable thickness, such as a grinding process, throughout the entire recycle wafer manufacturing process.

5. Explanation of batch processing as a modified example of main polishing processing of used wafers in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention (mainly FIG. 11)
FIG. 11 is a schematic cross-sectional view of a batch type CMP apparatus used for main polishing, finish polishing, and final polishing.

As described in the previous section, it is also possible to use a batch-type CMP apparatus as illustrated in FIG. 11 for main polishing, finish polishing, and final polishing. Since this type of batch type CMP apparatus has a plurality of polishing heads 57 (about 2 to 10), the efficiency of the process can be dramatically increased. In this case, a polishing pad having a relatively large area is required, but it is easy to prepare a relatively large polishing pad as long as the polishing pad does not contain abrasive grains. Examples of apparatuses that can be used here include SPM-19 and SPM-33 manufactured by Fujikoshi Machine Industry Co., Ltd., FAM59 SPAW and FAM50 SPAW manufactured by SPEEDFAM, and the like.

6). Supplementary explanation for the whole process in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention (mainly FIGS. 13 to 20)
FIG. 13 is an explanatory diagram of the relationship between the uneven pattern remaining after the main polishing and the final polishing characteristics. FIG. 14 is a columnar graph showing experimental data indicating the possibility of pattern disappearance due to finish polishing when there is a pattern remaining after main polishing. FIG. 15 is a columnar graph showing experimental data representing the main polishing time and finish polishing time dependence of silicon loss (substrate loss amount). FIG. 16 is a columnar graph showing experimental data representing the dependency of silicon loss (substrate loss amount) on the polishing time. FIG. 17 is a columnar graph showing experimental data indicating the dependency of the main polishing time and the final polishing time of TTV (Total Thickness Variation). FIG. 18 is a columnar graph showing experimental data representing the finish polishing time dependence of TTV. FIG. 19 is a columnar graph showing experimental data indicating the dependency of the number of residual particles on the finishing polishing time. FIG. 20 is a plot of various polishing pad hardnesses that can be used for main polishing and finish polishing. Based on these, a supplementary explanation will be given for the overall process in the method for manufacturing a recycled semiconductor wafer according to the embodiment of the present invention.

First, the relationship between the main polishing and the final uneven pattern residue will be explained. As shown in the upper part of FIG. 13, when there is a concavo-convex pattern remaining after main polishing, it is difficult to eliminate the concavo-convex pattern even if the subsequent finishing polishing time is extended in a normal range. This is because the polishing pad (second polishing pad) is softer than the polishing pad (first polishing pad) used in the final polishing (second polishing process) in the main polishing (first polishing process). This is considered to be because the pad sufficiently follows the remaining unevenness.

This is shown in FIG. That is, it is examined whether or not the remaining uneven pattern can be removed by the final polishing by setting the polishing time longer than usual for the wafer in which the uneven pattern remains by the main polishing. As shown in FIG. 14, even if the polishing amount is larger than the normal polishing amount, it seems difficult to remove the remaining uneven pattern by extending the finishing polishing.

Next, FIG. 15 shows changes in silicon loss (amount of substrate loss) by changing the main polishing time and the final polishing time under various conditions under which the residual unevenness pattern disappears due to the main polishing. As shown in FIG. 15, even if the main polishing time is increased to 2 minutes or more, the silicon loss simply increases monotonously. Similarly, increasing the finishing polishing time to 1 minute or more simply increases the silicon loss monotonically. This already indicates that polishing after flattening (after the concavo-convex pattern disappears) macroscopically (with respect to the size of the concavo-convex pattern) only reduces the overall thickness macroscopically. It is considered a thing.

Next, FIG. 16 shows the finish polishing time dependence of silicon loss (amount of substrate loss) when the main polishing time is fixed at 4 minutes under the condition that the residual unevenness pattern disappears by main polishing. As shown in FIG. 16, it can be seen that when the finishing polishing time is increased, the silicon loss is proportionally increased. This is considered to indicate that the finishing polishing does not contribute to the macro flatness as in the previous case.

Next, the dependency of wafer flatness (TTV) on the main polishing time and the finishing polishing time is shown in FIG. As shown in FIG. 17, the main polishing time is best about 2 minutes, and even if it is further increased, the flatness only decreases. In addition, it can be seen that the finishing polishing time is more advantageous in terms of wafer flatness than the relatively long time of about 1 minute in about 1 minute. This shows that the global flatness is determined by main polishing of about 2 minutes, and further main polishing is counterproductive. Further, finishing polishing for a long time exceeding about 2 minutes similarly has an adverse effect on global flatness.

Next, FIG. 18 shows the dependency of the flatness (TTV) of the wafer on the final polishing time under the condition that the residual unevenness pattern disappears by the main polishing. Again, with regard to global flatness, it is not an appropriate condition without finishing polishing, and finishing polishing over a period of more than about 2 minutes is likewise counterproductive with respect to global flatness. It is the result to confirm.

Next, the number of particles at the time of completion of cleaning after finishing polishing when the final polishing time is variously changed under the condition that the residual unevenness pattern disappears by main polishing (main polishing time is fixed at 4 minutes). FIG. 19 shows a configuration of 0.16 micrometer or more, less than 0.2 micrometer, and 0.2 micrometer or more. As shown in FIG. 19, regarding the number of particles, it can be said that the number of particles decreases as the finishing polishing time becomes longer. However, it can be seen that the reduction in the number of particles is almost completed in a polishing time of about 1 minute (finish polishing time). These results show that the particles captured by the surface micro structure are polished and removed by the polishing pad with a relatively hard pad so that the particles captured in the surface micro structure can be wiped off by the finished polishing pad with the characteristics of following the surface. It is thought to be for this purpose.

FIG. 20 plots the hardness (durometer D, that is, Shore D) of the main polishing pad and the finishing polishing pad that can be used in the above-described embodiment to obtain substantially the same results. Accordingly, the hardness of the main polishing pad is preferably about 50 (the range is about 40 to 65, more preferably about 40 to 55), and the hardness of the finishing polishing pad is about 22 (as the range). Is about 15 to 35). In addition, since the role of the main polishing pad is to remove the remaining uneven pattern in the surface region, use a pad with higher hardness (durometer D, that is, Shore D hardness of about 70) than those individually exemplified. Is also possible.

7. Summary The invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited thereto, and it goes without saying that various changes can be made without departing from the scope of the invention.

For example, in the embodiment of the present invention, a semiconductor device having a silicon-based CMOSFET (Complementary Metal Oxide Semiconductor Field Effect Transistor) or CMISFET (Complementary Metal Insulator Semiconductor Semiconductor Field Effect Transistor) has been described as an example. Needless to say, the present invention can be applied to the manufacture of other semiconductor integrated circuit devices or single devices, the manufacture of reclaimed wafers used therefor, and the like.

1 Wafer 1a Wafer front side (device side or first main side)
DESCRIPTION OF SYMBOLS 1b Back surface of a wafer 1n Non-working area | region of a wafer 1s Semiconductor substrate area | region of a wafer 1w Well area | region of a wafer 2 Structure layer in a semiconductor substrate 3 Structure layer on a semiconductor substrate 4 STI insulating film (element isolation region)
4t element isolation trench 5 gate structure 6 interlayer insulating film 7 metal wiring 8 bonding pad 9 final passivation film 11 first polishing region (main polishing region)
12 Polishing device base part 52 Polishing platen rotation drive part 53 Polishing platen 54 Polishing pad not containing fixed abrasive grains 54a Polishing pad main part not containing fixed abrasive grains 54b Polishing not containing fixed abrasive grains Pad base part 55 Slurry supply nozzle or polishing liquid nozzle 57 Polishing head 58 Polishing head holding part 59 Polishing head rotation drive part 60a Single wafer wet chemical mechanical polishing apparatus 60b using a polishing pad not containing fixed abrasive grains Fixed abrasive grains Batch type wet chemical mechanical polishing equipment using a polishing pad that does not contain 66 Slurry 67 Free abrasive grains 101 Semiconductor wafer preparation 102 Wet etching 103 Polishing with free abrasive grains (first polishing process)
104 Final polishing (second polishing process)
105 Cleaning process 106 Final polishing (third polishing process)
111 First chemical cleaning 112 First pure water rinse 113 Second chemical cleaning 114 Second pure water rinse 115 Drying G Wafer partial enlarged portion H Fixed abrasive polishing pad enlarged portion

Claims (19)

1. A method for producing a recycled semiconductor wafer including the following steps:
   (A) A step of removing the structural layer on the substrate by performing wet etching on the first main surface of the used semiconductor wafer which is the device surface of the recycled semiconductor wafer ;
   (B) After the step (a), wet chemistry using a polishing slurry containing a first polishing pad having a first hardness and free abrasive grains on the first main surface of the semiconductor wafer. Removing the concavo-convex pattern on the semiconductor surface on the first main surface side by executing a first polishing process by mechanical polishing;
   (C) After the step (b), containing a second polishing pad and loose abrasive grains having a second hardness softer than the first hardness with respect to the first main surface of the semiconductor wafer Removing the particles on the semiconductor surface on the first main surface side by executing a second polishing process by wet chemical mechanical polishing using a polishing slurry.
2. In the method for manufacturing a recycled semiconductor wafer according to item 1, the first polishing process is performed in a state where a polishing head is on the upper side of the first polishing pad.
3. In the method for producing a recycled semiconductor wafer according to the second item, there is no grinding step at least between the steps (a) and (b).
4. In the method for manufacturing a recycled semiconductor wafer according to item 3, the polishing process of 2 is performed in a state where the polishing head is above the second polishing pad and an additional load is applied to the polishing head. The
5. In the method for manufacturing a recycled semiconductor wafer according to the fourth item, there is no grinding step at least between the steps (a) and (c).
6. The method for manufacturing a recycled semiconductor wafer according to the fifth aspect further includes the following steps:
   (D) After the step (c), wet chemical mechanical polishing using a third polishing pad having a third hardness lower than that of the first polishing pad and a polishing slurry containing loose abrasive grains The third polishing process is performed by the polishing load due to the weight of the polishing head without applying an additional load to the polishing head in a state where the polishing head is on the upper side of the third polishing pad.
7. In the method for manufacturing a recycled semiconductor wafer according to item 6, the first polishing pad is mainly composed of a polyurethane resin member.
8. In the method for manufacturing a recycled semiconductor wafer according to item 7, the first hardness (durometer D) is 40 or more and 55 or less.
9. In the method for producing a recycled semiconductor wafer according to item 8, the second hardness (durometer D) is 15 or more and 35 or less.
10. In the method for producing a recycled semiconductor wafer according to item 9, the polishing time for the first polishing process is about 2 minutes.
11. In the method for producing a recycled semiconductor wafer according to item 10, the polishing time for the second polishing treatment is about 1 minute.
12. In the method for manufacturing a recycled semiconductor wafer according to item 10, the polishing time for the second polishing treatment is about 5 minutes.
13. In the method for manufacturing a recycled semiconductor wafer according to item 9, the first polishing process is performed by wet chemical mechanical polishing using a polishing pad that does not contain fixed abrasive grains.
14. In the method for manufacturing a recycled semiconductor wafer according to item 13, the second polishing process is performed by wet chemical mechanical polishing using a polishing pad that does not contain fixed abrasive grains.
15. In the method for manufacturing a recycled semiconductor wafer according to item 14, there is no grinding step at least between the steps (a) and (d).
16. In the method for manufacturing a recycled semiconductor wafer according to the item 15, the used semiconductor wafer is a single crystal silicon wafer.
17. In the method for manufacturing a recycled semiconductor wafer according to item 16, the first polishing process is performed in a batch manner.
18. In the method for manufacturing a recycled semiconductor wafer according to Item 17, the second polishing process is performed in a batch manner.
19. In the method for manufacturing a recycled semiconductor wafer according to Item 18, the third polishing process is performed in a batch manner.

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