WO2012056995A1 - Module de circuit, carte de circuit, dispositif à circuit et procédé de fabrication d'un module de circuit - Google Patents

Module de circuit, carte de circuit, dispositif à circuit et procédé de fabrication d'un module de circuit Download PDF

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Publication number
WO2012056995A1
WO2012056995A1 PCT/JP2011/074198 JP2011074198W WO2012056995A1 WO 2012056995 A1 WO2012056995 A1 WO 2012056995A1 JP 2011074198 W JP2011074198 W JP 2011074198W WO 2012056995 A1 WO2012056995 A1 WO 2012056995A1
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circuit
spacer
circuit board
circuit device
circuit module
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PCT/JP2011/074198
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English (en)
Japanese (ja)
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誠 玉木
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シャープ株式会社
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly

Definitions

  • the present invention relates to connection between a circuit board and a circuit device using an anisotropic conductive layer.
  • an anisotropic conductive layer 60 (including conductive particles 53) that connects circuit boards (20, 30) is made of polyimide or polyamic acid, and is larger than the conductive particles.
  • the structure which suppresses peeling (interface peeling) from the circuit board (20 * 30) of the anisotropic conductive layer 60 by adding the insulating particle 51 is disclosed.
  • JP 2008-150573 release date: July 3, 2008
  • the number of conductive particles and insulating particles sandwiched between the two terminals (22, 32) that are paired varies, so that the load on each conductive particle becomes non-uniform, and the load
  • the load on each conductive particle becomes non-uniform, and the load
  • poor connection due to insufficient deformation of the conductive particles due to an excessive amount and poor connection due to peeling of the conductive particles due to excessive load are likely to occur.
  • the conductive particles sandwiched between the latter terminals Is less than the load on the conductive particles sandwiched between the former terminals. That is, the deformation amount of the conductive particles sandwiched between the latter terminals is smaller than the deformation amount of the conductive particles sandwiched between the former terminals.
  • An object of the present invention is to increase the reliability of connection between a circuit board and a circuit device.
  • This circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to or integrated with one of the circuit board and the circuit device.
  • a spacer for defining a distance between the substrate and the circuit device is provided.
  • the distance between the circuit board and the circuit device is defined by the spacer, variation in the deformation amount of each conductive particle that conducts between the circuit board and the circuit device can be suppressed. Thereby, the reliability of connection of a circuit board and a circuit device can be improved.
  • the reliability of connection between the circuit board and the circuit device can be improved.
  • FIG. It is a schematic diagram which shows the structure of this display module. It is sectional drawing of the IC mounting part in FIG. It is another sectional drawing of the IC mounting part in FIG. It is sectional drawing which shows the terminal structure of the pixel substrate before IC mounting. It is sectional drawing which shows the sticking process of the sheet-like spacer in one example of formation of the IC mounting part shown in FIG. It is sectional drawing which shows the sticking process of the anisotropic conductive film in one example of formation of the IC mounting part shown in FIG. It is a top view which shows the sticking position of a sheet-like spacer and an anisotropic conductive film. It is sectional drawing which shows the position alignment process of IC in one example of formation of the IC mounting part shown in FIG.
  • FIG. 18 is a cross-sectional view of the active matrix substrate of FIG. 17. It is sectional drawing which shows the modification of FIG. It is sectional drawing which shows the position alignment process of IC in another example of formation of the IC mounting part shown in FIG. It is sectional drawing which shows the crimping
  • the display module includes a liquid crystal panel LCP, a driver IC chip DT, and an FPC (Flexible Printed Circuit), and the liquid crystal panel LCP is an active matrix substrate AM (hereinafter referred to as a substrate). And a counter substrate (not shown) on which a common electrode is formed and a liquid crystal layer (not shown).
  • the substrate AM has a display area DAR and a non-display area located around the display area DAR, and an IC chip DT is mounted on a part of the non-display area by COG (Chip on Glass).
  • COG Chip on Glass
  • One is a flexible printed circuit (Flexible-Printed-Circuit) FPC.
  • FIGS. 2 and 3 are examples of XX ′, YY ′, and ZZ ′ cross sections in the IC mounting portion of FIG.
  • two opposing edges are bump regions, and a plurality of bumps VP (connection protrusions) are formed in a row in each bump region.
  • terminal areas are formed on the substrate AM corresponding to the bump areas on the IC chip DT side, and a plurality of terminals TM (connection protrusions) are formed in a row in each terminal area.
  • a portion sandwiched between terminals on the active matrix substrate and bumps VP on the IC chip DT side (a pair of bumps VP and terminals TM) facing each other is referred to as a conductive portion.
  • the gap between the substrate AM and the IC chip DT is filled with an anisotropic conductive layer ACL containing conductive particles CP, and the conductive particles CP trapped in each conductive portion are bumps VP and terminals.
  • the active matrix substrate and the IC chip DT are electrically connected by being pressed from the TM and deformed.
  • a sheet-like spacer SS (insulator) that defines the gap between the bumps and the terminals is provided. It is provided so as not to overlap the area. Therefore, the height of the conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform, and even if there is a variation in the number and arrangement of the conductive particles CP trapped in each conductive portion, the conductive portion is trapped in the conductive portion. The amount of compressive deformation of each conductive particle CP is unlikely to vary.
  • the sheet-like spacer SS is insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the sheet-like spacer SS is provided so as not to overlap the bump region and the terminal region, it is also suitable when the pitch of the bump VP and the terminal TM is narrowed (fine pitch). Further, by increasing the area of the sheet-like spacer SS or making the elastic modulus (Young's modulus) of the sheet-like spacer SS larger than the elastic modulus (Young's modulus) of the conductive particles CP, the IC chip DT and the substrate The interval with the AM can be defined more reliably.
  • the surface of the conductive particles CP (diameter of about 3.0 [ ⁇ m]) is made of nickel Ni (Young's modulus 200 [GPa]) or gold Au (Young's modulus 78 [GPa]).
  • the sheet-like spacer SS (thickness of about 2.8 [ ⁇ m]) includes, for example, alumina Al 2 O 3 (Young's modulus 280 to 340 [GPa]), aluminum nitride AlN (Young's modulus 320 [GPa]), or mullite 3Al. 2 O 3 2SiO 2 (Young's modulus 210 [GPa]) is used.
  • the gate insulating film GI is formed on the glass substrate GS, the wiring W (for example, wiring connected to the data signal line) is formed on the gate insulating film GI, and the passivation is formed on the wiring W.
  • a film PA is formed, a terminal TM is formed on the passivation film PA, and the terminal TM and the wiring W are connected by a contact hole provided in the passivation film PA.
  • FIGS. 1 and 3 The formation process of the IC mounting part in FIGS. 2 and 3 is shown in FIGS.
  • a sheet-like spacer SS is attached to a portion sandwiched between two terminal regions (regions in which terminals are arranged in a row) of the substrate AM shown in FIG. 4 (see FIG. 5).
  • the separator support film, not shown
  • ACF anisotropic conductive film
  • the anisotropic conductive material ACM is exposed (see FIG. 7).
  • FIG. 8 the IC chip DT is aligned above the anisotropic conductive material ACM (the bump area of the IC chip DT and the terminal area of the substrate AM are matched in plan view).
  • the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion are substantially equal, but the IC chip
  • the DT and the substrate AM are not in contact with the sheet-like spacer SS (because the thickness of the sheet-like spacer SS is smaller than the diameter of the conductive particles CP).
  • the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 11, the IC chip DT and the substrate AM are sufficiently in contact with the sheet-like spacer SS and trapped in the conductive portion.
  • the electrical connection between the conductive particles CP and the bumps VP is caused by the balance between the condensing force FC of the anisotropic conductive layer ACL and the restoring force FR of the deformed conductive particles CP.
  • the connection and the electrical connection between the conductive particles CP and the terminals TM are maintained.
  • the shape of the sheet-like spacer SS is such that the deformation amount of the conductive particles CP is about 10 percent (the smaller particle size after deformation is about 90 percent of the particle size before deformation). It is desirable to set dimensions and characteristics (materials).
  • the interval between the IC chip DT and the substrate AM is defined by the sheet-like spacer SS, and the height of each conductive portion (the interval between the bump VP and the terminal TM) is fixed. Even if there is a variation in the number and arrangement of the conductive particles CP trapped in the conducting portion, the deformation amount of the trapped conductive particles CP is difficult to vary.
  • the sheet-like spacer SS separate from the IC chip DT and the substrate AM is used, but the present invention is not limited to this.
  • a rib-shaped rib-shaped spacer RS having an insulating property (height of about 2.8 [ ⁇ m], alumina Al 2 O as shown in FIG. 15). 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed.
  • one or more pillar-shaped rib-like spacers RS ′ having an insulating property may be previously integrally formed.
  • a bowl-shaped rib-like spacer rs (height of about 2.8 [ ⁇ m] having an insulating property as shown in FIG. 18, alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed.
  • alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be previously integrally formed.
  • one or a plurality of insulating columnar rib spacers rs ′ may be previously integrally formed.
  • rib-like spacers rs and rs ′ are formed by locally changing the film thickness of the passivation film (channel protective film) in the substrate AM forming process (that is, rib-like spacers rs). (It is also possible to form rs ′ with the same material as the channel protective film).
  • each conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacers (RS, RS ′, rs, rs ′) having insulating properties, Even if the number and arrangement of the conductive particles CP trapped in each conducting portion vary, the amount of compression deformation of each conductive particle CP trapped in the conducting portion is difficult to vary. Since the rib-like spacers (RS / RS ′ / rs / rs ′) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the pitch of the bumps VP and the terminals TM is reduced (the pitch is made finer). ) Is also suitable.
  • the area of the rib-shaped spacer (RS / RS ′ / rs / rs ′) is increased, or the elastic modulus (Young's modulus) of the rib-shaped spacer (RS / RS ′ / rs / rs ′)
  • the elastic modulus Young's modulus
  • Example 3 In the configuration shown in FIGS. 14 to 16, rib-shaped spacers are formed on the IC chip DT so as not to overlap the bump regions (regions where the bumps are arranged in a line), but the present invention is not limited to this.
  • a plurality of rib-shaped spacers Rs (height 2.8 [ ⁇ m] in the gap between two adjacent bumps VP. ]
  • C., alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be left to integrally form.
  • the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started.
  • the anisotropic conductive layer ACL is formed (see FIG. 21).
  • the interval between the IC chip DT and the substrate AM is narrowed.
  • the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion are substantially equal.
  • the DT and the substrate AM are not in contact with the rib-like spacer Rs. From the state of FIG.
  • the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 22, the IC chip DT and the substrate AM are sufficiently in contact with the rib-shaped spacer Rs, and the conductivity trapped in the conductive portion.
  • the particles CP are deformed, the mounting of the IC chip is completed.
  • rib-like spacers are formed on the substrate AM so as not to overlap with the terminal regions (regions where the terminals are arranged in a row), but the present invention is not limited to this.
  • a plurality of insulating rib-shaped spacers rS (height of about 2.8 [ ⁇ m]) are provided in the gap between two adjacent terminals TM in the terminal region of the surface (mounting surface) of the substrate AM.
  • alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be left to integrally form.
  • the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started.
  • the anisotropic conductive layer ACL is formed (see FIG. 24).
  • the interval between the IC chip DT and the substrate AM is narrowed.
  • the particle size of the conductive particles CP trapped in each conduction part and the height of each conduction part are substantially equal, but the IC chip The DT and the substrate AM are not in contact with the rib-like spacer rS.
  • the distance between the IC chip DT and the substrate AM is further reduced.
  • the IC chip DT and the substrate AM are sufficiently in contact with the rib-like spacer rS, and the conductivity trapped in the conductive portion.
  • the mounting of the IC chip is completed.
  • the rib-shaped spacer rS is formed by locally changing the thickness of the passivation film (channel protective film) in the substrate AM forming step (that is, the rib-shaped spacer rS is formed as the channel protective film). And the same material).
  • each conductive portion (the distance between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacer (Rs ⁇ rS) having an insulating property, and is trapped by each conductive portion. Even if there are variations in the number and arrangement of the conductive particles CP, the amount of compression deformation of each of the conductive particles CP trapped in the conductive portion is difficult to vary. Since the rib-like spacers (Rs ⁇ rS) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the area of the rib-like spacer (Rs ⁇ rS) is increased, or the elastic modulus (Young's modulus) of the rib-like spacer (Rs ⁇ rS) is made larger than the elastic modulus (Young's modulus) of the conductive particles CP.
  • the interval between the IC chip DT and the substrate AM can be defined more reliably.
  • Example 4 The above embodiment is a case where the IC chip DT is mounted on the substrate AM, but the circuit device to be mounted is not limited to the IC chip DT.
  • FIG. 26 and FIG. 27 which is a cross-sectional view of PP ′ / QQ ′, circuit devices CD (COF (Chip on Film), TCP (Tape Carrier Package), FPC (Flexible Printed Circuit)
  • the sheet-shaped spacer SS and the rib-shaped spacer RS ⁇ rs can be provided on the mounting portion of any one of the substrates AM.
  • a rib-like spacer RS ′ as shown in FIG. 16
  • a rib-like spacer rs ′ as shown in FIG. 19
  • a rib-like spacer Rs as shown in FIG. 20
  • a rib-like spacer rS as shown in FIG.
  • the connection portion between the substrate AM and the FPC in FIG. 1 is preferably configured as shown in FIGS.
  • the mounting board is not limited to the active matrix substrate AM.
  • a circuit device CD IC (Integrated Circuit) chip, COF (Chip on Film), TCP (Tape Carrier Package),
  • a sheet-like spacer SS and a rib-like spacer RS ⁇ rs may be provided on a mounting portion of an FPC (Flexible Printed Circuit)) on a PWB (Printed Wiring Board).
  • FPC Flexible Printed Circuit
  • PWB Print Wiring Board
  • the anisotropic conductive layer ACL may include the conductive particles CP and the insulating particles IP.
  • the particle size of the insulating particles IP is smaller than the particle size of the conductive particles CP (for example, the particle size of the insulating particles IP is about 90% of the particle size of the conductive particles CP).
  • the elastic modulus Youngng's modulus
  • the diameter of the conductive particles CP is about 3.0 [ ⁇ m]
  • the diameter of the insulating particles IP is about 2.8 [ ⁇ m]
  • the material of the insulating particles IP is alumina Al 2 O 3 (Young's modulus 280). ⁇ 340 [GPa]).
  • this circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to one of the circuit board and the circuit device.
  • a spacer is provided which is integrated and defines a distance between the circuit board and the circuit device.
  • the spacer may have an insulating property.
  • one of the plurality of connection protrusions included in the circuit board and one of the plurality of connection protrusions included in the circuit device may be connected by the conductive particles.
  • the spacer may be arranged in the anisotropic conductive layer.
  • the elastic modulus of the spacer may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
  • the plurality of connection protrusions are arranged in a row in the connection area, and the spacer is arranged so as not to overlap the connection area of the circuit board and the circuit device in plan view. It can also be set as the structure.
  • connection regions of the circuit board and the circuit device each have a strip shape, and the spacer may have a sheet shape along each connection region.
  • the spacer may be formed in a rib shape integrally formed on the circuit board or the circuit device.
  • one portion is provided on the circuit board and the other is provided on the circuit device, and a portion sandwiched between two opposing connection protrusions is defined as a conductive portion, and the spacer is disposed in a gap between two adjacent conductive portions. It can also be set as the structure.
  • the anisotropic conductive layer may include insulating particles.
  • the particle size of the insulating particles may be smaller than the particle size of the conductive particles.
  • the elastic modulus of the insulating particles may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
  • the circuit board may be an active matrix substrate or a PWB (Printed Wiring Board).
  • PWB Print Wiring Board
  • the circuit device may be any one of an IC (Integrated Circuit) chip, a COF (Chip On Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed Circuit).
  • IC Integrated Circuit
  • COF Chip On Film
  • TCP Transmission Carrier Package
  • FPC Flexible Printed Circuit
  • This circuit device is a circuit device connected to a circuit board via an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit board.
  • the spacer may have an insulating property.
  • the circuit device may be configured to function as any one of an IC (Integrated Circuit) chip, a COF (Chip on Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed circuit).
  • IC Integrated Circuit
  • COF Chip on Film
  • TCP Transmission Carrier Package
  • FPC Flexible Printed circuit
  • the circuit board is a circuit board connected to a circuit device through an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit device.
  • the spacer may have an insulating property.
  • the circuit board may be configured to function as an active matrix substrate or a PWB (Printed Wiring Board).
  • PWB Print Wiring Board
  • the present circuit board functions as an active matrix substrate, and the spacer may be formed using an insulating film that protects the channel of the transistor.
  • the method for manufacturing a circuit module is a method for manufacturing a circuit module, in which a circuit board and a circuit device each having a plurality of connection protrusions are connected to form a circuit module.
  • the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
  • the present invention is suitable when, for example, an IC chip, a COF (Chip on Film), or an FPC (Flexible Printed Circuit) is mounted on various substrates.
  • IC chip a COF (Chip on Film), or an FPC (Flexible Printed Circuit) is mounted on various substrates.
  • COF Chip on Film
  • FPC Flexible Printed Circuit
  • LCP liquid crystal panel AM active matrix substrate (circuit board) DT IC chip (circuit device) ACL Anisotropic Conductive Layer CP Conductive Particle SS Sheet Spacer RS rs Rs rS Rib Spacer RS 'rs' Rib Spacer VP Bump (Connection Protrusion) TM terminal (connection protrusion) W wiring (metal wiring) GS glass substrate GI gate insulating film PA passivation film IP insulating particles

Abstract

L'invention concerne un module d'affichage dans lequel un substrat de matrice active (AM) et une puce de circuit intégré (DT) destinés à un circuit d'attaque sont connectés l'un à l'autre par l'intermédiaire d'une couche conductrice anisotrope (ACL, Anisotropic Conductive Layer) contenant des particules conductrices (CP). Le module d'affichage est muni d'un élément intercalaire du type feuille (SS) lié au substrat de matrice active (AM) et définit la distance entre le substrat de matrice active (AM) et la puce de circuit intégré (DT). Du fait de la configuration décrite ci-dessus, la fiabilité du montage de la puce de circuit intégré sur le substrat peut être améliorée.
PCT/JP2011/074198 2010-10-27 2011-10-20 Module de circuit, carte de circuit, dispositif à circuit et procédé de fabrication d'un module de circuit WO2012056995A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010240841 2010-10-27
JP2010-240841 2010-10-27

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Publication Number Publication Date
WO2012056995A1 true WO2012056995A1 (fr) 2012-05-03

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317426A (ja) * 1998-05-06 1999-11-16 Matsushita Electric Ind Co Ltd 実装ユニット
JP2000236153A (ja) * 1999-02-16 2000-08-29 Nec Corp プリント配線基板構造
JP2004095879A (ja) * 2002-08-30 2004-03-25 Optrex Corp 半導体チップの実装構造
JP2006012992A (ja) * 2004-06-23 2006-01-12 Sharp Corp 回路基板の電極接続構造
JP2007250825A (ja) * 2006-03-16 2007-09-27 Epson Imaging Devices Corp 基板の接続構造及びその製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317426A (ja) * 1998-05-06 1999-11-16 Matsushita Electric Ind Co Ltd 実装ユニット
JP2000236153A (ja) * 1999-02-16 2000-08-29 Nec Corp プリント配線基板構造
JP2004095879A (ja) * 2002-08-30 2004-03-25 Optrex Corp 半導体チップの実装構造
JP2006012992A (ja) * 2004-06-23 2006-01-12 Sharp Corp 回路基板の電極接続構造
JP2007250825A (ja) * 2006-03-16 2007-09-27 Epson Imaging Devices Corp 基板の接続構造及びその製造方法

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