WO2012056995A1 - Circuit module, circuit board, circuit device and method for manufacturing circuit module - Google Patents

Circuit module, circuit board, circuit device and method for manufacturing circuit module Download PDF

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Publication number
WO2012056995A1
WO2012056995A1 PCT/JP2011/074198 JP2011074198W WO2012056995A1 WO 2012056995 A1 WO2012056995 A1 WO 2012056995A1 JP 2011074198 W JP2011074198 W JP 2011074198W WO 2012056995 A1 WO2012056995 A1 WO 2012056995A1
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Prior art keywords
circuit
spacer
circuit board
circuit device
circuit module
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PCT/JP2011/074198
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French (fr)
Japanese (ja)
Inventor
誠 玉木
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シャープ株式会社
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Publication of WO2012056995A1 publication Critical patent/WO2012056995A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/819—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector with the bump connector not providing any mechanical bonding
    • H01L2224/81901—Pressing the bump connector against the bonding areas by means of another connector
    • H01L2224/81903—Pressing the bump connector against the bonding areas by means of another connector by means of a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/83138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8314—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9211—Parallel connecting processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly

Definitions

  • the present invention relates to connection between a circuit board and a circuit device using an anisotropic conductive layer.
  • an anisotropic conductive layer 60 (including conductive particles 53) that connects circuit boards (20, 30) is made of polyimide or polyamic acid, and is larger than the conductive particles.
  • the structure which suppresses peeling (interface peeling) from the circuit board (20 * 30) of the anisotropic conductive layer 60 by adding the insulating particle 51 is disclosed.
  • JP 2008-150573 release date: July 3, 2008
  • the number of conductive particles and insulating particles sandwiched between the two terminals (22, 32) that are paired varies, so that the load on each conductive particle becomes non-uniform, and the load
  • the load on each conductive particle becomes non-uniform, and the load
  • poor connection due to insufficient deformation of the conductive particles due to an excessive amount and poor connection due to peeling of the conductive particles due to excessive load are likely to occur.
  • the conductive particles sandwiched between the latter terminals Is less than the load on the conductive particles sandwiched between the former terminals. That is, the deformation amount of the conductive particles sandwiched between the latter terminals is smaller than the deformation amount of the conductive particles sandwiched between the former terminals.
  • An object of the present invention is to increase the reliability of connection between a circuit board and a circuit device.
  • This circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to or integrated with one of the circuit board and the circuit device.
  • a spacer for defining a distance between the substrate and the circuit device is provided.
  • the distance between the circuit board and the circuit device is defined by the spacer, variation in the deformation amount of each conductive particle that conducts between the circuit board and the circuit device can be suppressed. Thereby, the reliability of connection of a circuit board and a circuit device can be improved.
  • the reliability of connection between the circuit board and the circuit device can be improved.
  • FIG. It is a schematic diagram which shows the structure of this display module. It is sectional drawing of the IC mounting part in FIG. It is another sectional drawing of the IC mounting part in FIG. It is sectional drawing which shows the terminal structure of the pixel substrate before IC mounting. It is sectional drawing which shows the sticking process of the sheet-like spacer in one example of formation of the IC mounting part shown in FIG. It is sectional drawing which shows the sticking process of the anisotropic conductive film in one example of formation of the IC mounting part shown in FIG. It is a top view which shows the sticking position of a sheet-like spacer and an anisotropic conductive film. It is sectional drawing which shows the position alignment process of IC in one example of formation of the IC mounting part shown in FIG.
  • FIG. 18 is a cross-sectional view of the active matrix substrate of FIG. 17. It is sectional drawing which shows the modification of FIG. It is sectional drawing which shows the position alignment process of IC in another example of formation of the IC mounting part shown in FIG. It is sectional drawing which shows the crimping
  • the display module includes a liquid crystal panel LCP, a driver IC chip DT, and an FPC (Flexible Printed Circuit), and the liquid crystal panel LCP is an active matrix substrate AM (hereinafter referred to as a substrate). And a counter substrate (not shown) on which a common electrode is formed and a liquid crystal layer (not shown).
  • the substrate AM has a display area DAR and a non-display area located around the display area DAR, and an IC chip DT is mounted on a part of the non-display area by COG (Chip on Glass).
  • COG Chip on Glass
  • One is a flexible printed circuit (Flexible-Printed-Circuit) FPC.
  • FIGS. 2 and 3 are examples of XX ′, YY ′, and ZZ ′ cross sections in the IC mounting portion of FIG.
  • two opposing edges are bump regions, and a plurality of bumps VP (connection protrusions) are formed in a row in each bump region.
  • terminal areas are formed on the substrate AM corresponding to the bump areas on the IC chip DT side, and a plurality of terminals TM (connection protrusions) are formed in a row in each terminal area.
  • a portion sandwiched between terminals on the active matrix substrate and bumps VP on the IC chip DT side (a pair of bumps VP and terminals TM) facing each other is referred to as a conductive portion.
  • the gap between the substrate AM and the IC chip DT is filled with an anisotropic conductive layer ACL containing conductive particles CP, and the conductive particles CP trapped in each conductive portion are bumps VP and terminals.
  • the active matrix substrate and the IC chip DT are electrically connected by being pressed from the TM and deformed.
  • a sheet-like spacer SS (insulator) that defines the gap between the bumps and the terminals is provided. It is provided so as not to overlap the area. Therefore, the height of the conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform, and even if there is a variation in the number and arrangement of the conductive particles CP trapped in each conductive portion, the conductive portion is trapped in the conductive portion. The amount of compressive deformation of each conductive particle CP is unlikely to vary.
  • the sheet-like spacer SS is insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the sheet-like spacer SS is provided so as not to overlap the bump region and the terminal region, it is also suitable when the pitch of the bump VP and the terminal TM is narrowed (fine pitch). Further, by increasing the area of the sheet-like spacer SS or making the elastic modulus (Young's modulus) of the sheet-like spacer SS larger than the elastic modulus (Young's modulus) of the conductive particles CP, the IC chip DT and the substrate The interval with the AM can be defined more reliably.
  • the surface of the conductive particles CP (diameter of about 3.0 [ ⁇ m]) is made of nickel Ni (Young's modulus 200 [GPa]) or gold Au (Young's modulus 78 [GPa]).
  • the sheet-like spacer SS (thickness of about 2.8 [ ⁇ m]) includes, for example, alumina Al 2 O 3 (Young's modulus 280 to 340 [GPa]), aluminum nitride AlN (Young's modulus 320 [GPa]), or mullite 3Al. 2 O 3 2SiO 2 (Young's modulus 210 [GPa]) is used.
  • the gate insulating film GI is formed on the glass substrate GS, the wiring W (for example, wiring connected to the data signal line) is formed on the gate insulating film GI, and the passivation is formed on the wiring W.
  • a film PA is formed, a terminal TM is formed on the passivation film PA, and the terminal TM and the wiring W are connected by a contact hole provided in the passivation film PA.
  • FIGS. 1 and 3 The formation process of the IC mounting part in FIGS. 2 and 3 is shown in FIGS.
  • a sheet-like spacer SS is attached to a portion sandwiched between two terminal regions (regions in which terminals are arranged in a row) of the substrate AM shown in FIG. 4 (see FIG. 5).
  • the separator support film, not shown
  • ACF anisotropic conductive film
  • the anisotropic conductive material ACM is exposed (see FIG. 7).
  • FIG. 8 the IC chip DT is aligned above the anisotropic conductive material ACM (the bump area of the IC chip DT and the terminal area of the substrate AM are matched in plan view).
  • the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion are substantially equal, but the IC chip
  • the DT and the substrate AM are not in contact with the sheet-like spacer SS (because the thickness of the sheet-like spacer SS is smaller than the diameter of the conductive particles CP).
  • the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 11, the IC chip DT and the substrate AM are sufficiently in contact with the sheet-like spacer SS and trapped in the conductive portion.
  • the electrical connection between the conductive particles CP and the bumps VP is caused by the balance between the condensing force FC of the anisotropic conductive layer ACL and the restoring force FR of the deformed conductive particles CP.
  • the connection and the electrical connection between the conductive particles CP and the terminals TM are maintained.
  • the shape of the sheet-like spacer SS is such that the deformation amount of the conductive particles CP is about 10 percent (the smaller particle size after deformation is about 90 percent of the particle size before deformation). It is desirable to set dimensions and characteristics (materials).
  • the interval between the IC chip DT and the substrate AM is defined by the sheet-like spacer SS, and the height of each conductive portion (the interval between the bump VP and the terminal TM) is fixed. Even if there is a variation in the number and arrangement of the conductive particles CP trapped in the conducting portion, the deformation amount of the trapped conductive particles CP is difficult to vary.
  • the sheet-like spacer SS separate from the IC chip DT and the substrate AM is used, but the present invention is not limited to this.
  • a rib-shaped rib-shaped spacer RS having an insulating property (height of about 2.8 [ ⁇ m], alumina Al 2 O as shown in FIG. 15). 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed.
  • one or more pillar-shaped rib-like spacers RS ′ having an insulating property may be previously integrally formed.
  • a bowl-shaped rib-like spacer rs (height of about 2.8 [ ⁇ m] having an insulating property as shown in FIG. 18, alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed.
  • alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be previously integrally formed.
  • one or a plurality of insulating columnar rib spacers rs ′ may be previously integrally formed.
  • rib-like spacers rs and rs ′ are formed by locally changing the film thickness of the passivation film (channel protective film) in the substrate AM forming process (that is, rib-like spacers rs). (It is also possible to form rs ′ with the same material as the channel protective film).
  • each conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacers (RS, RS ′, rs, rs ′) having insulating properties, Even if the number and arrangement of the conductive particles CP trapped in each conducting portion vary, the amount of compression deformation of each conductive particle CP trapped in the conducting portion is difficult to vary. Since the rib-like spacers (RS / RS ′ / rs / rs ′) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the pitch of the bumps VP and the terminals TM is reduced (the pitch is made finer). ) Is also suitable.
  • the area of the rib-shaped spacer (RS / RS ′ / rs / rs ′) is increased, or the elastic modulus (Young's modulus) of the rib-shaped spacer (RS / RS ′ / rs / rs ′)
  • the elastic modulus Young's modulus
  • Example 3 In the configuration shown in FIGS. 14 to 16, rib-shaped spacers are formed on the IC chip DT so as not to overlap the bump regions (regions where the bumps are arranged in a line), but the present invention is not limited to this.
  • a plurality of rib-shaped spacers Rs (height 2.8 [ ⁇ m] in the gap between two adjacent bumps VP. ]
  • C., alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be left to integrally form.
  • the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started.
  • the anisotropic conductive layer ACL is formed (see FIG. 21).
  • the interval between the IC chip DT and the substrate AM is narrowed.
  • the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion are substantially equal.
  • the DT and the substrate AM are not in contact with the rib-like spacer Rs. From the state of FIG.
  • the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 22, the IC chip DT and the substrate AM are sufficiently in contact with the rib-shaped spacer Rs, and the conductivity trapped in the conductive portion.
  • the particles CP are deformed, the mounting of the IC chip is completed.
  • rib-like spacers are formed on the substrate AM so as not to overlap with the terminal regions (regions where the terminals are arranged in a row), but the present invention is not limited to this.
  • a plurality of insulating rib-shaped spacers rS (height of about 2.8 [ ⁇ m]) are provided in the gap between two adjacent terminals TM in the terminal region of the surface (mounting surface) of the substrate AM.
  • alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2 may be left to integrally form.
  • the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started.
  • the anisotropic conductive layer ACL is formed (see FIG. 24).
  • the interval between the IC chip DT and the substrate AM is narrowed.
  • the particle size of the conductive particles CP trapped in each conduction part and the height of each conduction part are substantially equal, but the IC chip The DT and the substrate AM are not in contact with the rib-like spacer rS.
  • the distance between the IC chip DT and the substrate AM is further reduced.
  • the IC chip DT and the substrate AM are sufficiently in contact with the rib-like spacer rS, and the conductivity trapped in the conductive portion.
  • the mounting of the IC chip is completed.
  • the rib-shaped spacer rS is formed by locally changing the thickness of the passivation film (channel protective film) in the substrate AM forming step (that is, the rib-shaped spacer rS is formed as the channel protective film). And the same material).
  • each conductive portion (the distance between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacer (Rs ⁇ rS) having an insulating property, and is trapped by each conductive portion. Even if there are variations in the number and arrangement of the conductive particles CP, the amount of compression deformation of each of the conductive particles CP trapped in the conductive portion is difficult to vary. Since the rib-like spacers (Rs ⁇ rS) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved.
  • the area of the rib-like spacer (Rs ⁇ rS) is increased, or the elastic modulus (Young's modulus) of the rib-like spacer (Rs ⁇ rS) is made larger than the elastic modulus (Young's modulus) of the conductive particles CP.
  • the interval between the IC chip DT and the substrate AM can be defined more reliably.
  • Example 4 The above embodiment is a case where the IC chip DT is mounted on the substrate AM, but the circuit device to be mounted is not limited to the IC chip DT.
  • FIG. 26 and FIG. 27 which is a cross-sectional view of PP ′ / QQ ′, circuit devices CD (COF (Chip on Film), TCP (Tape Carrier Package), FPC (Flexible Printed Circuit)
  • the sheet-shaped spacer SS and the rib-shaped spacer RS ⁇ rs can be provided on the mounting portion of any one of the substrates AM.
  • a rib-like spacer RS ′ as shown in FIG. 16
  • a rib-like spacer rs ′ as shown in FIG. 19
  • a rib-like spacer Rs as shown in FIG. 20
  • a rib-like spacer rS as shown in FIG.
  • the connection portion between the substrate AM and the FPC in FIG. 1 is preferably configured as shown in FIGS.
  • the mounting board is not limited to the active matrix substrate AM.
  • a circuit device CD IC (Integrated Circuit) chip, COF (Chip on Film), TCP (Tape Carrier Package),
  • a sheet-like spacer SS and a rib-like spacer RS ⁇ rs may be provided on a mounting portion of an FPC (Flexible Printed Circuit)) on a PWB (Printed Wiring Board).
  • FPC Flexible Printed Circuit
  • PWB Print Wiring Board
  • the anisotropic conductive layer ACL may include the conductive particles CP and the insulating particles IP.
  • the particle size of the insulating particles IP is smaller than the particle size of the conductive particles CP (for example, the particle size of the insulating particles IP is about 90% of the particle size of the conductive particles CP).
  • the elastic modulus Youngng's modulus
  • the diameter of the conductive particles CP is about 3.0 [ ⁇ m]
  • the diameter of the insulating particles IP is about 2.8 [ ⁇ m]
  • the material of the insulating particles IP is alumina Al 2 O 3 (Young's modulus 280). ⁇ 340 [GPa]).
  • this circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to one of the circuit board and the circuit device.
  • a spacer is provided which is integrated and defines a distance between the circuit board and the circuit device.
  • the spacer may have an insulating property.
  • one of the plurality of connection protrusions included in the circuit board and one of the plurality of connection protrusions included in the circuit device may be connected by the conductive particles.
  • the spacer may be arranged in the anisotropic conductive layer.
  • the elastic modulus of the spacer may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
  • the plurality of connection protrusions are arranged in a row in the connection area, and the spacer is arranged so as not to overlap the connection area of the circuit board and the circuit device in plan view. It can also be set as the structure.
  • connection regions of the circuit board and the circuit device each have a strip shape, and the spacer may have a sheet shape along each connection region.
  • the spacer may be formed in a rib shape integrally formed on the circuit board or the circuit device.
  • one portion is provided on the circuit board and the other is provided on the circuit device, and a portion sandwiched between two opposing connection protrusions is defined as a conductive portion, and the spacer is disposed in a gap between two adjacent conductive portions. It can also be set as the structure.
  • the anisotropic conductive layer may include insulating particles.
  • the particle size of the insulating particles may be smaller than the particle size of the conductive particles.
  • the elastic modulus of the insulating particles may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
  • the circuit board may be an active matrix substrate or a PWB (Printed Wiring Board).
  • PWB Print Wiring Board
  • the circuit device may be any one of an IC (Integrated Circuit) chip, a COF (Chip On Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed Circuit).
  • IC Integrated Circuit
  • COF Chip On Film
  • TCP Transmission Carrier Package
  • FPC Flexible Printed Circuit
  • This circuit device is a circuit device connected to a circuit board via an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit board.
  • the spacer may have an insulating property.
  • the circuit device may be configured to function as any one of an IC (Integrated Circuit) chip, a COF (Chip on Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed circuit).
  • IC Integrated Circuit
  • COF Chip on Film
  • TCP Transmission Carrier Package
  • FPC Flexible Printed circuit
  • the circuit board is a circuit board connected to a circuit device through an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit device.
  • the spacer may have an insulating property.
  • the circuit board may be configured to function as an active matrix substrate or a PWB (Printed Wiring Board).
  • PWB Print Wiring Board
  • the present circuit board functions as an active matrix substrate, and the spacer may be formed using an insulating film that protects the channel of the transistor.
  • the method for manufacturing a circuit module is a method for manufacturing a circuit module, in which a circuit board and a circuit device each having a plurality of connection protrusions are connected to form a circuit module.
  • the present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
  • the present invention is suitable when, for example, an IC chip, a COF (Chip on Film), or an FPC (Flexible Printed Circuit) is mounted on various substrates.
  • IC chip a COF (Chip on Film), or an FPC (Flexible Printed Circuit) is mounted on various substrates.
  • COF Chip on Film
  • FPC Flexible Printed Circuit
  • LCP liquid crystal panel AM active matrix substrate (circuit board) DT IC chip (circuit device) ACL Anisotropic Conductive Layer CP Conductive Particle SS Sheet Spacer RS rs Rs rS Rib Spacer RS 'rs' Rib Spacer VP Bump (Connection Protrusion) TM terminal (connection protrusion) W wiring (metal wiring) GS glass substrate GI gate insulating film PA passivation film IP insulating particles

Abstract

A display module of the present invention is a display module wherein an active matrix substrate (AM) and an IC chip (DT) for a driver are connected with each other via an anisotropic conductive layer (ACL) that contains conductive particles (CP). The display module is provided with a sheet-like spacer (SS) that is bonded to the active matrix substrate (AM) and defines the distance between the active matrix substrate (AM) and the IC chip (DT). Due to the above-described configuration, reliability of mounting of the IC chip on the substrate can be increased.

Description

回路モジュール、回路基板、回路デバイス、回路モジュールの製造方法Circuit module, circuit board, circuit device, and circuit module manufacturing method
　本発明は、異方性導電層による回路基板と回路デバイスとの接続に関する。 The present invention relates to connection between a circuit board and a circuit device using an anisotropic conductive layer.
　特許文献１（図３１参照）には、回路基板同士（２０・３０）を接続する異方性導電層６０（導電性粒子５３含む）に、ポリイミドやポリアミック酸からなり、導電性粒子よりも大きい絶縁性粒子５１を添加することで、異方性導電層６０の回路基板（２０・３０）からの剥離（界面剥離）を抑制する構成が開示されている。 In Patent Document 1 (see FIG. 31), an anisotropic conductive layer 60 (including conductive particles 53) that connects circuit boards (20, 30) is made of polyimide or polyamic acid, and is larger than the conductive particles. The structure which suppresses peeling (interface peeling) from the circuit board (20 * 30) of the anisotropic conductive layer 60 by adding the insulating particle 51 is disclosed.
日本国公開特許公報「特開２００８－１５０５７３（公開日：２００８年７月３日）」Japanese Patent Publication “JP 2008-150573 (release date: July 3, 2008)”
　しかしながら、図３１の構成では、対となる２つの端子（２２・３２）間に挟まれる導電性粒子および絶縁性粒子の個数がばらつくことで、各導電性粒子への荷重が不均一となり、荷重過少による導電性粒子の変形不足に起因する接続不良や、荷重過多による導電性粒子の皮膜剥離に起因する接続不良が起こり易いという問題がある。例えば、ある端子間に導電性粒子１個のみが挟まれ、別の端子間に導電性粒子１個と絶縁性粒子１個とが挟まれた場合、後者の端子間に挟まれた導電性粒子への加重は、前者の端子間に挟まれた導電性粒子への荷重よりも小さくなる。すなわち、後者の端子間に挟まれた導電性粒子の変形量は、前者の端子間に挟まれた導電性粒子の変形量よりも小さくなる。 However, in the configuration of FIG. 31, the number of conductive particles and insulating particles sandwiched between the two terminals (22, 32) that are paired varies, so that the load on each conductive particle becomes non-uniform, and the load There is a problem that poor connection due to insufficient deformation of the conductive particles due to an excessive amount and poor connection due to peeling of the conductive particles due to excessive load are likely to occur. For example, when only one conductive particle is sandwiched between certain terminals and one conductive particle and one insulating particle are sandwiched between other terminals, the conductive particles sandwiched between the latter terminals Is less than the load on the conductive particles sandwiched between the former terminals. That is, the deformation amount of the conductive particles sandwiched between the latter terminals is smaller than the deformation amount of the conductive particles sandwiched between the former terminals.
　本発明の目的は、回路基板および回路デバイスの接続の信頼性を高めることにある。 An object of the present invention is to increase the reliability of connection between a circuit board and a circuit device.
　本回路モジュールは、回路基板と回路デバイスとが導電性粒子を含む異方性導電層を介して接続された回路モジュールであって、上記回路基板および回路デバイスの一方に貼付あるいは一体化され、回路基板と回路デバイスとの距離を規定するスペーサを備えることを特徴とする。 This circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to or integrated with one of the circuit board and the circuit device. A spacer for defining a distance between the substrate and the circuit device is provided.
　上記構成によれば、回路基板および回路デバイスの間隔がスペーサによって規定されるため、回路基板および回路デバイス間を導通させる各導電性粒子の変形量のばらつきが抑えられる。これにより、回路基板および回路デバイスの接続の信頼性を高めることができる。 According to the above configuration, since the distance between the circuit board and the circuit device is defined by the spacer, variation in the deformation amount of each conductive particle that conducts between the circuit board and the circuit device can be suppressed. Thereby, the reliability of connection of a circuit board and a circuit device can be improved.
　本発明によれば、回路基板および回路デバイスの接続の信頼性を高めることができる。 According to the present invention, the reliability of connection between the circuit board and the circuit device can be improved.
本表示モジュールの構成を示す模式図である。It is a schematic diagram which shows the structure of this display module. 図１におけるＩＣ実装部の断面図である。It is sectional drawing of the IC mounting part in FIG. 図１におけるＩＣ実装部の別の断面図である。It is another sectional drawing of the IC mounting part in FIG. ＩＣ実装する前の画素基板の端子構造を示す断面図である。It is sectional drawing which shows the terminal structure of the pixel substrate before IC mounting. 図１に示すＩＣ実装部の一形成例におけるシート状スペーサの貼り付け工程を示す断面図である。It is sectional drawing which shows the sticking process of the sheet-like spacer in one example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の一形成例における異方性導電性フィルムの貼り付け工程を示す断面図である。It is sectional drawing which shows the sticking process of the anisotropic conductive film in one example of formation of the IC mounting part shown in FIG. シート状スペーサおよび異方性導電性フィルムの貼り付け位置を示す平面図である。It is a top view which shows the sticking position of a sheet-like spacer and an anisotropic conductive film. 図１に示すＩＣ実装部の一形成例におけるＩＣの位置合わせ工程を示す断面図である。It is sectional drawing which shows the position alignment process of IC in one example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の一形成例における圧着工程（初期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (initial stage) in one example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の一形成例における圧着工程（中期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (mid term) in one formation example of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の一形成例における圧着工程（終期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (final stage) in one example of formation of the IC mounting part shown in FIG. 導電性粒子と端子およびバンプとの接続について説明する模式図である。It is a schematic diagram explaining the connection of electroconductive particle, a terminal, and a bump. 本発明の効果を説明するための圧着工程（終期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (final stage) for demonstrating the effect of this invention. ＩＣチップの別構成を示す平面図である。It is a top view which shows another structure of an IC chip. 図１４のＩＣの断面図である。It is sectional drawing of IC of FIG. 図１５の変形例を示す断面図である。It is sectional drawing which shows the modification of FIG. アクティブマトリクス基板の別構成を示す平面図である。It is a top view which shows another structure of an active matrix substrate. 図１７のアクティブマトリクス基板の断面図である。FIG. 18 is a cross-sectional view of the active matrix substrate of FIG. 17. 図１８の変形例を示す断面図である。It is sectional drawing which shows the modification of FIG. 図１に示すＩＣ実装部の別形成例におけるＩＣの位置合わせ工程を示す断面図である。It is sectional drawing which shows the position alignment process of IC in another example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の別形成例における圧着工程（中期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (mid term) in another example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部の別形成例における圧着工程（終期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (final stage) in another example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部のさらなる別形成例におけるＩＣの位置合わせ工程を示す断面図である。It is sectional drawing which shows the position alignment process of IC in the further another example of formation of the IC mounting part shown in FIG. 図１に示すＩＣ実装部のさらなる別形成例における圧着工程（中期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (mid term) in the further another formation example of the IC mounting part shown in FIG. 図１に示すＩＣ実装部のさらなる別形成例における圧着工程（終期）を示す断面図である。It is sectional drawing which shows the crimping | compression-bonding process (final stage) in the further another example of formation of the IC mounting part shown in FIG. 本発明の別形態（アクティブマトリクス基板とＣＯＦ等との接続）を示す平面図である。It is a top view which shows another form (connection of an active matrix substrate, COF, etc.) of this invention. 図２６の断面図である。It is sectional drawing of FIG. 本発明のさらなる別形態（ＰＷＢとＣＯＦ等との接続）を示す平面図である。It is a top view which shows the further another form (connection of PWB, COF, etc.) of this invention. 図２８の断面図である。It is sectional drawing of FIG. 別構成の異方性導電性フィルムを用いたときの効果を示す断面図（圧着工程中期→圧着工程終期）である。It is sectional drawing (the crimping | compression-bonding process middle stage-> crimping | compression-bonding end stage) which shows an effect when the anisotropic conductive film of another structure is used. 回路基板同士の従来の接続構造を示す断面図である。It is sectional drawing which shows the conventional connection structure of circuit boards.
　本発明の実施の形態を、図１～３０を用いて説明すれば、以下のとおりである。図１に示すように、本表示モジュール（回路モジュール）は、液晶パネルＬＣＰ、ドライバ用のＩＣチップＤＴ、およびＦＰＣ（Flexible Printed Circuit）を備え、液晶パネルＬＣＰは、アクティブマトリクス基板ＡＭ（以下、基板ＡＭと略記）と共通電極が形成された対向基板（図示せず）と液晶層（図示せず）とを含む。基板ＡＭは、表示領域ＤＡＲとその周囲に位置する非表示領域とを有しており、この非表示領域の一部にＩＣチップＤＴがＣＯＧ（Chip on Glass）実装され、非表示領域のエッジの１つにフレキシブルプリント回路（Flexible Printed Circuit）ＦＰＣが接続されている。 Embodiments of the present invention will be described with reference to FIGS. 1 to 30 as follows. As shown in FIG. 1, the display module (circuit module) includes a liquid crystal panel LCP, a driver IC chip DT, and an FPC (Flexible Printed Circuit), and the liquid crystal panel LCP is an active matrix substrate AM (hereinafter referred to as a substrate). And a counter substrate (not shown) on which a common electrode is formed and a liquid crystal layer (not shown). The substrate AM has a display area DAR and a non-display area located around the display area DAR, and an IC chip DT is mounted on a part of the non-display area by COG (Chip on Glass). One is a flexible printed circuit (Flexible-Printed-Circuit) FPC.
　〔実施例１〕
　図２・３は、図１のＩＣ実装部におけるＸ－Ｘ’・Ｙ－Ｙ’・Ｚ－Ｚ’断面の一例である。図２・３に示されるように、ＩＣチップＤＴでは、向かい合う２つのエッジそれぞれがバンプ領域となっており、各バンプ領域には複数のバンプＶＰ（接続突起）が列状に形成されている。また、基板ＡＭには、ＩＣチップＤＴ側のバンプ領域に対応して端子領域が形成され、各端子領域には複数の端子ＴＭ（接続突起）が列状に形成されている。以下、互いに対向する、アクティブマトリクス基板側の端子およびＩＣチップＤＴ側のバンプＶＰ（対となるバンプＶＰおよび端子ＴＭ）で挟まれた部分を導通部と称する。基板ＡＭとＩＣチップＤＴとの間隙は、導電性粒子ＣＰを含む異方性導電層（Anisotropic Conductive Layer）ＡＣＬで満たされており、各導通部にトラップされた導電性粒子ＣＰがバンプＶＰおよび端子ＴＭから圧迫され、変形することで、アクティブマトリクス基板とＩＣチップＤＴとが電気的に接続される。 [Example 1]
FIGS. 2 and 3 are examples of XX ′, YY ′, and ZZ ′ cross sections in the IC mounting portion of FIG. As shown in FIGS. 2 and 3, in the IC chip DT, two opposing edges are bump regions, and a plurality of bumps VP (connection protrusions) are formed in a row in each bump region. Further, terminal areas are formed on the substrate AM corresponding to the bump areas on the IC chip DT side, and a plurality of terminals TM (connection protrusions) are formed in a row in each terminal area. Hereinafter, a portion sandwiched between terminals on the active matrix substrate and bumps VP on the IC chip DT side (a pair of bumps VP and terminals TM) facing each other is referred to as a conductive portion. The gap between the substrate AM and the IC chip DT is filled with an anisotropic conductive layer ACL containing conductive particles CP, and the conductive particles CP trapped in each conductive portion are bumps VP and terminals. The active matrix substrate and the IC chip DT are electrically connected by being pressed from the TM and deformed.
　そして、本表示モジュールでは、ＩＣチップＤＴとアクティブマトリクス基板との間隙（すなわち、異方性導電層ＡＣＬ内）に、両者の間隔を規定するシート状スペーサＳＳ（絶縁体）が、バンプ領域および端子領域に重ならないように設けられている。したがって、導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）がほぼ均一化され、各導通部にトラップされる導電性粒子ＣＰの個数や配置にばらつきがあっても、導通部にトラップされる導電性粒子ＣＰそれぞれの圧迫変形量はばらつき難くなる。なお、シート状スペーサＳＳは絶縁性であるため、バンプＶＰ－端子ＴＭ間等の短絡が生じるおそれはない。これにより、基板ＡＭとＩＣチップＤＴとの接続の信頼性を高めることができる。なお、シート状スペーサＳＳが、バンプ領域および端子領域に重ならないように設けられているため、バンプＶＰや端子ＴＭのピッチが狭くなった（ファインピッチ化した）場合にも好適である。また、シート状スペーサＳＳの面積を広くしたり、シート状スペーサＳＳの弾性率（ヤング率）を導電性粒子ＣＰの弾性率（ヤング率）よりも大きくしたりすることで、ＩＣチップＤＴと基板ＡＭとの間隔をより確実に規定することができる。 In this display module, in the gap between the IC chip DT and the active matrix substrate (that is, in the anisotropic conductive layer ACL), a sheet-like spacer SS (insulator) that defines the gap between the bumps and the terminals is provided. It is provided so as not to overlap the area. Therefore, the height of the conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform, and even if there is a variation in the number and arrangement of the conductive particles CP trapped in each conductive portion, the conductive portion is trapped in the conductive portion. The amount of compressive deformation of each conductive particle CP is unlikely to vary. Since the sheet-like spacer SS is insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved. In addition, since the sheet-like spacer SS is provided so as not to overlap the bump region and the terminal region, it is also suitable when the pitch of the bump VP and the terminal TM is narrowed (fine pitch). Further, by increasing the area of the sheet-like spacer SS or making the elastic modulus (Young's modulus) of the sheet-like spacer SS larger than the elastic modulus (Young's modulus) of the conductive particles CP, the IC chip DT and the substrate The interval with the AM can be defined more reliably.
　ここで、導電性粒子ＣＰ（直径３．０〔μｍ〕程度）の表面は、ニッケルＮｉ（ヤング率２００〔ＧＰａ〕）や金Ａｕ（ヤング率７８〔ＧＰａ〕）で構成される。また、シート状スペーサＳＳ（厚み２．８〔μｍ〕程度）には、例えばアルミナＡｌ２Ｏ３（ヤング率２８０～３４０〔ＧＰａ〕）や窒化アルミＡｌＮ（ヤング率３２０〔ＧＰａ〕）あるいはムライト３Ａｌ２Ｏ３２ＳｉＯ２（ヤング率２１０〔ＧＰａ〕）が用いられる。 Here, the surface of the conductive particles CP (diameter of about 3.0 [μm]) is made of nickel Ni (Young's modulus 200 [GPa]) or gold Au (Young's modulus 78 [GPa]). The sheet-like spacer SS (thickness of about 2.8 [μm]) includes, for example, alumina Al 2 O 3 (Young's modulus 280 to 340 [GPa]), aluminum nitride AlN (Young's modulus 320 [GPa]), or mullite 3Al. 2 O 3 2SiO 2 (Young's modulus 210 [GPa]) is used.
　なお、基板ＡＭの端子領域では、ガラス基板ＧＳ上にゲート絶縁膜ＧＩが形成され、ゲート絶縁膜ＧＩ上に配線Ｗ（例えば、データ信号線に接続する配線）が形成され、配線Ｗ上にパッシベーション膜ＰＡが形成され、パッシベーション膜ＰＡ上に端子ＴＭが形成され、パッシベーション膜ＰＡに設けられたコンタクトホールによって端子ＴＭと配線Ｗとが接続されている。 In the terminal region of the substrate AM, the gate insulating film GI is formed on the glass substrate GS, the wiring W (for example, wiring connected to the data signal line) is formed on the gate insulating film GI, and the passivation is formed on the wiring W. A film PA is formed, a terminal TM is formed on the passivation film PA, and the terminal TM and the wiring W are connected by a contact hole provided in the passivation film PA.
　図２・３のＩＣ実装部の形成工程を、図４～１１に示す。まず、図４に示す基板ＡＭの２つの端子領域（端子が列状に並ぶ領域）で挟まれた部分に、シート状スペーサＳＳを貼り付ける（図５参照）。ついで、図６に示すように、上記２つの端子領域ＴＡ１・ＴＡ２およびシート状スペーサＳＳを覆うように異方性導電フィルム（ＡＣＦ）を貼り付けた後にセパレータ（支持フィルム、図示せず）を除去し、異方性導電材ＡＣＭを露出させる（図７参照）。ついで、図８に示すように、異方性導電材ＡＣＭの上方にＩＣチップＤＴを位置合わせする（平面視で、ＩＣチップＤＴのバンプ領域と基板ＡＭの端子領域とを一致させる）。 The formation process of the IC mounting part in FIGS. 2 and 3 is shown in FIGS. First, a sheet-like spacer SS is attached to a portion sandwiched between two terminal regions (regions in which terminals are arranged in a row) of the substrate AM shown in FIG. 4 (see FIG. 5). Next, as shown in FIG. 6, the separator (support film, not shown) is removed after the anisotropic conductive film (ACF) is pasted so as to cover the two terminal areas TA1 and TA2 and the sheet-like spacer SS. Then, the anisotropic conductive material ACM is exposed (see FIG. 7). Next, as shown in FIG. 8, the IC chip DT is aligned above the anisotropic conductive material ACM (the bump area of the IC chip DT and the terminal area of the substrate AM are matched in plan view).
　ここで、圧着ヘッド（図示せず）によってＩＣチップＤＴに圧力（例えば、９０〔ＭＰａ〕）と熱（例えば、１８０〔℃〕）を与える（図９）。これにより、異方性導電材ＡＣＭが濡れ広がりながらＩＣチップＤＴおよび基板ＡＭ間に充填されるとともに熱硬化を始め、異方性導電層ＡＣＬとなる（図１０参照）。これにより、ＩＣチップＤＴおよび基板ＡＭの間隔は狭まる。なお、図１０の状態では、各導通部にトラップされた導電性粒子ＣＰの粒径と、各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）とがほぼ等しくなっているが、ＩＣチップＤＴおよび基板ＡＭはシート状スペーサＳＳに接触していない（導電性粒子ＣＰの直径よりもシート状スペーサＳＳの厚みが小さいため）。図１０の状態から、ＩＣチップＤＴおよび基板ＡＭの間隔がさらに縮まり、図１１に示すように、ＩＣチップＤＴおよび基板ＡＭそれぞれがシート状スペーサＳＳに十分接触し、導通部にトラップされた導電性粒子ＣＰが変形した段階（図９の状態から１０秒程度）でＩＣチップの実装が完了する。 Here, pressure (for example, 90 [MPa]) and heat (for example, 180 [° C.]) are applied to the IC chip DT by a crimping head (not shown) (FIG. 9). As a result, the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while wetting and spreading, and thermosetting is started to become the anisotropic conductive layer ACL (see FIG. 10). Thereby, the interval between the IC chip DT and the substrate AM is narrowed. In the state of FIG. 10, the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion (the distance between the bump VP and the terminal TM) are substantially equal, but the IC chip The DT and the substrate AM are not in contact with the sheet-like spacer SS (because the thickness of the sheet-like spacer SS is smaller than the diameter of the conductive particles CP). From the state of FIG. 10, the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 11, the IC chip DT and the substrate AM are sufficiently in contact with the sheet-like spacer SS and trapped in the conductive portion. When the particles CP are deformed (about 10 seconds from the state shown in FIG. 9), the mounting of the IC chip is completed.
　図１１の状態では、図１２に示すように、異方性導電層ＡＣＬの凝縮力ＦＣと変形した導電性粒子ＣＰの復元力ＦＲとの釣り合いによって、導電性粒子ＣＰとバンプＶＰとの電気的接続、および導電性粒子ＣＰと端子ＴＭとの電気的接続が維持される。この釣り合いを考慮して、導電性粒子ＣＰの変形量が１０パーセント程度となる（変形後の小さい方の粒径が変形前の粒経の９０パーセント程度となる）ようにシート状スペーサＳＳの形状寸法や特性（材料）を設定することが望ましい。 In the state of FIG. 11, as shown in FIG. 12, the electrical connection between the conductive particles CP and the bumps VP is caused by the balance between the condensing force FC of the anisotropic conductive layer ACL and the restoring force FR of the deformed conductive particles CP. The connection and the electrical connection between the conductive particles CP and the terminals TM are maintained. In consideration of this balance, the shape of the sheet-like spacer SS is such that the deformation amount of the conductive particles CP is about 10 percent (the smaller particle size after deformation is about 90 percent of the particle size before deformation). It is desirable to set dimensions and characteristics (materials).
　以上のように、ＩＣチップＤＴおよび基板ＡＭの間隔をシート状スペーサＳＳで規定し、各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）を固定することで、仮に図１３のように各導通部にトラップされる導電性粒子ＣＰの個数や配置にばらつきがあっても、これらトラップされた導電性粒子ＣＰの変形量はばらつき難くなる。 As described above, the interval between the IC chip DT and the substrate AM is defined by the sheet-like spacer SS, and the height of each conductive portion (the interval between the bump VP and the terminal TM) is fixed. Even if there is a variation in the number and arrangement of the conductive particles CP trapped in the conducting portion, the deformation amount of the trapped conductive particles CP is difficult to vary.
　〔実施例２〕
　上記の実施の形態では、図２や図５に示すように、ＩＣチップＤＴおよび基板ＡＭとは別体のシート状スペーサＳＳを用いているがこれに限定されない。図１４に示すＩＣチップＤＴの裏面（実装面）中央部に、図１５に示すような、絶縁性を有する畝型のリブ状スペーサＲＳ（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を予め一体形成しておくこともできる。また、図１５のような畝型ではなく、図１６のように、１または複数個の絶縁性を有する柱型のリブ状スペーサＲＳ’（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を予め一体形成しておくこともできる。 [Example 2]
In the above embodiment, as shown in FIG. 2 and FIG. 5, the sheet-like spacer SS separate from the IC chip DT and the substrate AM is used, but the present invention is not limited to this. In the central portion of the back surface (mounting surface) of the IC chip DT shown in FIG. 14, a rib-shaped rib-shaped spacer RS having an insulating property (height of about 2.8 [μm], alumina Al 2 O as shown in FIG. 15). 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed. Further, instead of the saddle type as shown in FIG. 15, as shown in FIG. 16, one or more pillar-shaped rib-like spacers RS ′ having an insulating property (height of about 2.8 [μm], alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed.
　また、図１７のような基板ＡＭの表面（実装面）中央部に、図１８に示すような絶縁性を有する畝型のリブ状スペーサｒｓ（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を予め一体形成しておくこともできる。また、図１８のような畝型ではなく、図１９のように、１または複数個の絶縁性を有する柱型のリブ状スペーサｒｓ’（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を予め一体形成しておくこともできる。図１８・１９の場合には、基板ＡＭ形成工程で、パッシベーション膜（チャネル保護膜）の膜厚を局所的に変えることで、リブ状スペーサｒｓ・ｒｓ’を形成する（すなわち、リブ状スペーサｒｓ・ｒｓ’をチャネル保護膜と同材料で形成する）こともできる。 In addition, in the center portion of the surface (mounting surface) of the substrate AM as shown in FIG. 17, a bowl-shaped rib-like spacer rs (height of about 2.8 [μm] having an insulating property as shown in FIG. 18, alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed. Further, instead of the saddle type as shown in FIG. 18, as shown in FIG. 19, one or a plurality of insulating columnar rib spacers rs ′ (height of about 2.8 [μm], alumina Al 2 O 3 or manufactured by aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be previously integrally formed. In the case of FIGS. 18 and 19, rib-like spacers rs and rs ′ are formed by locally changing the film thickness of the passivation film (channel protective film) in the substrate AM forming process (that is, rib-like spacers rs). (It is also possible to form rs ′ with the same material as the channel protective film).
　図１４～図１９の場合においても、絶縁性を有するリブ状スペーサ（ＲＳ・ＲＳ’・ｒｓ・ｒｓ’）によって各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）がほぼ均一化され、各導通部にトラップされる導電性粒子ＣＰの個数や配置にばらつきがあっても、導通部にトラップされる導電性粒子ＣＰそれぞれの圧迫変形量はばらつき難くなる。なお、リブ状スペーサ（ＲＳ・ＲＳ’・ｒｓ・ｒｓ’）は絶縁性であるため、バンプＶＰ－端子ＴＭ間等の短絡が生じるおそれはない。これにより、基板ＡＭとＩＣチップＤＴとの接続の信頼性を高めることができる。なお、リブ状スペーサ（ＲＳ・ＲＳ’・ｒｓ・ｒｓ’）が、バンプ領域および端子領域に重ならないように設けられているため、バンプＶＰや端子ＴＭのピッチが狭くなった（ファインピッチ化した）場合にも好適である。また、リブ状スペーサ（ＲＳ・ＲＳ’・ｒｓ・ｒｓ’）の面積を広くしたり、リブ状スペーサ（ＲＳ・ＲＳ’・ｒｓ・ｒｓ’）の弾性率（ヤング率）を導電性粒子ＣＰの弾性率（ヤング率）よりも大きくしたりすることで、ＩＣチップＤＴと基板ＡＭとの間隔をより確実に規定することができる。 Also in the case of FIGS. 14 to 19, the height of each conductive portion (the interval between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacers (RS, RS ′, rs, rs ′) having insulating properties, Even if the number and arrangement of the conductive particles CP trapped in each conducting portion vary, the amount of compression deformation of each conductive particle CP trapped in the conducting portion is difficult to vary. Since the rib-like spacers (RS / RS ′ / rs / rs ′) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved. In addition, since the rib-like spacers (RS / RS ′ / rs / rs ′) are provided so as not to overlap the bump region and the terminal region, the pitch of the bumps VP and the terminals TM is reduced (the pitch is made finer). ) Is also suitable. Further, the area of the rib-shaped spacer (RS / RS ′ / rs / rs ′) is increased, or the elastic modulus (Young's modulus) of the rib-shaped spacer (RS / RS ′ / rs / rs ′) By making it larger than the elastic modulus (Young's modulus), the interval between the IC chip DT and the substrate AM can be more reliably defined.
　〔実施例３〕
　図１４～図１６に示す構成では、ＩＣチップＤＴに、バンプ領域（バンプが列状に並ぶ領域）と重ならないようにリブ状スペーサが形成されているがこれに限定されない。図２０に示すように、ＩＣチップＤＴの裏面（実装面）のバンプ領域において、隣り合う２つのバンプＶＰの間隙に、複数個の絶縁性を有するリブ状スペーサＲｓ（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を一体形成しておくこともできる。この場合は、圧着ヘッド（図示せず）によってＩＣチップＤＴに圧力と熱を与えることで、異方性導電材ＡＣＭが濡れ広がりながらＩＣチップＤＴおよび基板ＡＭ間に充填されるとともに熱硬化を始め、異方性導電層ＡＣＬとなる（図２１参照）。これにより、ＩＣチップＤＴおよび基板ＡＭの間隔は狭まる。なお、図２１の状態では、各導通部にトラップされた導電性粒子ＣＰの粒径と、各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）とがほぼ等しくなっているが、ＩＣチップＤＴおよび基板ＡＭはリブ状スペーサＲｓに接触していない。図２１の状態から、ＩＣチップＤＴおよび基板ＡＭの間隔がさらに縮まり、図２２に示すように、ＩＣチップＤＴおよび基板ＡＭそれぞれがリブ状スペーサＲｓに十分接触し、導通部にトラップされた導電性粒子ＣＰが変形した段階でＩＣチップの実装が完了する。 Example 3
In the configuration shown in FIGS. 14 to 16, rib-shaped spacers are formed on the IC chip DT so as not to overlap the bump regions (regions where the bumps are arranged in a line), but the present invention is not limited to this. As shown in FIG. 20, in the bump region on the back surface (mounting surface) of the IC chip DT, a plurality of rib-shaped spacers Rs (height 2.8 [μm] in the gap between two adjacent bumps VP. ] C., alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be left to integrally form. In this case, by applying pressure and heat to the IC chip DT with a crimping head (not shown), the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started. Thus, the anisotropic conductive layer ACL is formed (see FIG. 21). Thereby, the interval between the IC chip DT and the substrate AM is narrowed. In the state shown in FIG. 21, the particle size of the conductive particles CP trapped in each conductive portion and the height of each conductive portion (the interval between the bump VP and the terminal TM) are substantially equal. The DT and the substrate AM are not in contact with the rib-like spacer Rs. From the state of FIG. 21, the distance between the IC chip DT and the substrate AM is further reduced, and as shown in FIG. 22, the IC chip DT and the substrate AM are sufficiently in contact with the rib-shaped spacer Rs, and the conductivity trapped in the conductive portion. When the particles CP are deformed, the mounting of the IC chip is completed.
　図１７～図１９に示す構成では、基板ＡＭに、端子領域（端子が列状に並ぶ領域）と重ならないようにリブ状スペーサが形成されているがこれに限定されない。図２３に示すように、基板ＡＭの表面（実装面）の端子領域における隣り合う２つの端子ＴＭの間隙に、複数個の絶縁性を有するリブ状スペーサｒＳ（高さ２．８〔μｍ〕程度、アルミナＡｌ２Ｏ３あるいは窒化アルミＡｌＮまたはムライト３Ａｌ２Ｏ３２ＳｉＯ２製）を一体形成しておくこともできる。この場合は、圧着ヘッド（図示せず）によってＩＣチップＤＴに圧力と熱を与えることで、異方性導電材ＡＣＭが濡れ広がりながらＩＣチップＤＴおよび基板ＡＭ間に充填されるとともに熱硬化を始め、異方性導電層ＡＣＬとなる（図２４参照）。これにより、ＩＣチップＤＴおよび基板ＡＭの間隔は狭まる。なお、図２４の状態では、各導通部にトラップされた導電性粒子ＣＰの粒径と、各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）とがほぼ等しくなっているが、ＩＣチップＤＴおよび基板ＡＭはリブ状スペーサｒＳに接触していない。図２４の状態から、ＩＣチップＤＴおよび基板ＡＭの間隔がさらに縮まり、図２５に示すように、ＩＣチップＤＴおよび基板ＡＭそれぞれがリブ状スペーサｒＳに十分接触し、導通部にトラップされた導電性粒子ＣＰが変形した段階でＩＣチップの実装が完了する。なお、図２３の構成では、基板ＡＭ形成工程で、パッシベーション膜（チャネル保護膜）の膜厚を局所的に変えることで、リブ状スペーサｒＳを形成する（すなわち、リブ状スペーサｒＳをチャネル保護膜と同材料で形成する）こともできる。 In the configurations shown in FIGS. 17 to 19, rib-like spacers are formed on the substrate AM so as not to overlap with the terminal regions (regions where the terminals are arranged in a row), but the present invention is not limited to this. As shown in FIG. 23, a plurality of insulating rib-shaped spacers rS (height of about 2.8 [μm]) are provided in the gap between two adjacent terminals TM in the terminal region of the surface (mounting surface) of the substrate AM. , alumina Al 2 O 3 or aluminum nitride AlN or mullite 3Al 2 O 3 2SiO 2) may be left to integrally form. In this case, by applying pressure and heat to the IC chip DT with a crimping head (not shown), the anisotropic conductive material ACM is filled between the IC chip DT and the substrate AM while spreading, and thermosetting is started. Thus, the anisotropic conductive layer ACL is formed (see FIG. 24). Thereby, the interval between the IC chip DT and the substrate AM is narrowed. In the state of FIG. 24, the particle size of the conductive particles CP trapped in each conduction part and the height of each conduction part (the interval between the bump VP and the terminal TM) are substantially equal, but the IC chip The DT and the substrate AM are not in contact with the rib-like spacer rS. 24, the distance between the IC chip DT and the substrate AM is further reduced. As shown in FIG. 25, the IC chip DT and the substrate AM are sufficiently in contact with the rib-like spacer rS, and the conductivity trapped in the conductive portion. When the particles CP are deformed, the mounting of the IC chip is completed. In the configuration of FIG. 23, the rib-shaped spacer rS is formed by locally changing the thickness of the passivation film (channel protective film) in the substrate AM forming step (that is, the rib-shaped spacer rS is formed as the channel protective film). And the same material).
　図２０～図２５の場合においても、絶縁性を有するリブ状スペーサ（Ｒｓ・ｒＳ）によって各導通部の高さ（バンプＶＰおよび端子ＴＭの間隔）がほぼ均一化され、各導通部にトラップされる導電性粒子ＣＰの個数や配置にばらつきがあっても、導通部にトラップされる導電性粒子ＣＰそれぞれの圧迫変形量はばらつき難くなる。なお、リブ状スペーサ（Ｒｓ・ｒＳ）は絶縁性であるため、バンプＶＰ－端子ＴＭ間等の短絡が生じるおそれはない。これにより、基板ＡＭとＩＣチップＤＴとの接続の信頼性を高めることができる。また、リブ状スペーサ（Ｒｓ・ｒＳ）の面積を広くしたり、リブ状スペーサ（Ｒｓ・ｒＳ）の弾性率（ヤング率）を導電性粒子ＣＰの弾性率（ヤング率）よりも大きくしたりすることで、ＩＣチップＤＴと基板ＡＭとの間隔をより確実に規定することができる。 Also in the case of FIGS. 20 to 25, the height of each conductive portion (the distance between the bump VP and the terminal TM) is made substantially uniform by the rib-shaped spacer (Rs · rS) having an insulating property, and is trapped by each conductive portion. Even if there are variations in the number and arrangement of the conductive particles CP, the amount of compression deformation of each of the conductive particles CP trapped in the conductive portion is difficult to vary. Since the rib-like spacers (Rs · rS) are insulative, there is no possibility of short circuit between the bump VP and the terminal TM. Thereby, the reliability of the connection between the substrate AM and the IC chip DT can be improved. Further, the area of the rib-like spacer (Rs · rS) is increased, or the elastic modulus (Young's modulus) of the rib-like spacer (Rs · rS) is made larger than the elastic modulus (Young's modulus) of the conductive particles CP. As a result, the interval between the IC chip DT and the substrate AM can be defined more reliably.
　〔実施例４〕
　上記実施の形態は、基板ＡＭ上にＩＣチップＤＴを実装する場合であるが、実装する回路デバイスは、ＩＣチップＤＴに限定されない。例えば図２６とそのＰ－Ｐ’・Ｑ－Ｑ’断面図である図２７に示すように、回路デバイスＣＤ（ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）、ＦＰＣ（Flexible Printed Circuit）のいずれか）の基板ＡＭへの実装部に、シート状スペーサＳＳやリブ状スペーサＲＳ・ｒｓを設けることもできる。もちろん、図１６のようなリブ状スペーサＲＳ’、図１９のようなリブ状スペーサｒｓ’、図２０のようなリブ状スペーサＲｓ、図２３のようなリブ状スペーサｒＳを設けることもできる。なお、図１の基板ＡＭとＦＰＣとの接続部分は、図２６－２７のように構成することが望ましい。 Example 4
The above embodiment is a case where the IC chip DT is mounted on the substrate AM, but the circuit device to be mounted is not limited to the IC chip DT. For example, as shown in FIG. 26 and FIG. 27 which is a cross-sectional view of PP ′ / QQ ′, circuit devices CD (COF (Chip on Film), TCP (Tape Carrier Package), FPC (Flexible Printed Circuit) The sheet-shaped spacer SS and the rib-shaped spacer RS · rs can be provided on the mounting portion of any one of the substrates AM. Of course, a rib-like spacer RS ′ as shown in FIG. 16, a rib-like spacer rs ′ as shown in FIG. 19, a rib-like spacer Rs as shown in FIG. 20, and a rib-like spacer rS as shown in FIG. Note that the connection portion between the substrate AM and the FPC in FIG. 1 is preferably configured as shown in FIGS.
　また、実装先の基板もアクティブマトリクス基板ＡＭに限られない。例えば図２８とそのｐ－ｐ’・ｑ－ｑ’断面図である図２９に示すように、回路デバイスＣＤ（ＩＣ（Integrated Circuit）チップ、ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）、ＦＰＣ（Flexible Printed Circuit））のＰＷＢ（Printed Wiring Board）への実装部に、シート状スペーサＳＳやリブ状スペーサＲＳ・ｒｓを設けることもできる。もちろん、図１６のようなリブ状スペーサＲＳ’、図１９のようなリブ状スペーサｒｓ’、図２０のようなリブ状スペーサＲｓ、図２３のようなリブ状スペーサｒＳを設けることもできる。 Also, the mounting board is not limited to the active matrix substrate AM. For example, as shown in FIG. 28 and FIG. 29 which is a pp ′ / qq ′ cross-sectional view thereof, a circuit device CD (IC (Integrated Circuit) chip, COF (Chip on Film), TCP (Tape Carrier Package), A sheet-like spacer SS and a rib-like spacer RS · rs may be provided on a mounting portion of an FPC (Flexible Printed Circuit)) on a PWB (Printed Wiring Board). Of course, rib-like spacers RS 'as shown in FIG. 16, rib-like spacers rs' as shown in FIG. 19, rib-like spacers Rs as shown in FIG. 20, and rib-like spacers rS as shown in FIG.
　〔実施例５〕
　なお、本実施の形態では、図３０に示すように、異方性導電層ＡＣＬに、導電性粒子ＣＰおよび絶縁性粒子ＩＰが含まれる構成でも構わない。この場合、絶縁性粒子ＩＰの粒経を導電性粒子ＣＰ粒経よりも小さくする（例えば、絶縁性粒子ＩＰの粒経を導電性粒子ＣＰ粒経の９０パーセント程度とする）ことが望ましい。こうすれば、図３０に示すように、導通部にトラップされる導電性粒子ＣＰの変形量のばらつきを一層抑制することができる。この観点から、絶縁性粒子ＩＰの弾性率（ヤング率）を導電性粒子ＣＰの弾性率よりも大きくすることがなお望ましい。ここでは、導電性粒子ＣＰの直径を３．０〔μｍ〕程度、絶縁性粒子ＩＰの直径を２．８〔μｍ〕程度とし、絶縁性粒子ＩＰの材質をアルミナＡｌ２Ｏ３（ヤング率２８０～３４０〔ＧＰａ〕）としている。 Example 5
In the present embodiment, as shown in FIG. 30, the anisotropic conductive layer ACL may include the conductive particles CP and the insulating particles IP. In this case, it is desirable that the particle size of the insulating particles IP is smaller than the particle size of the conductive particles CP (for example, the particle size of the insulating particles IP is about 90% of the particle size of the conductive particles CP). By so doing, as shown in FIG. 30, it is possible to further suppress variation in the deformation amount of the conductive particles CP trapped in the conduction part. From this viewpoint, it is still desirable to make the elastic modulus (Young's modulus) of the insulating particles IP larger than the elastic modulus of the conductive particles CP. Here, the diameter of the conductive particles CP is about 3.0 [μm], the diameter of the insulating particles IP is about 2.8 [μm], and the material of the insulating particles IP is alumina Al 2 O 3 (Young's modulus 280). ~ 340 [GPa]).
　以上のように、本回路モジュールは、回路基板と回路デバイスとが導電性粒子を含む異方性導電層を介して接続された回路モジュールであって、上記回路基板および回路デバイスの一方に貼付あるいは一体化され、回路基板と回路デバイスとの距離を規定するスペーサを備えることを特徴とする。 As described above, this circuit module is a circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles, and is attached to one of the circuit board and the circuit device. A spacer is provided which is integrated and defines a distance between the circuit board and the circuit device.
　本回路モジュールでは、上記スペーサは絶縁性を有する構成とすることもできる。 In this circuit module, the spacer may have an insulating property.
　本回路モジュールでは、回路基板が有する複数の接続突起の１つと、回路デバイスが有する複数の接続突起部の１つとが、上記導電性粒子によって接続されている構成とすることもできる。 In this circuit module, one of the plurality of connection protrusions included in the circuit board and one of the plurality of connection protrusions included in the circuit device may be connected by the conductive particles.
　本回路モジュールでは、上記スペーサは、異方性導電層内に配されている構成とすることもできる。 In this circuit module, the spacer may be arranged in the anisotropic conductive layer.
　本回路モジュールでは、上記スペーサの弾性率は導電性粒子の弾性率（例えば、ヤング率）よりも大きい構成とすることもできる。 In the present circuit module, the elastic modulus of the spacer may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
　本回路モジュールでは、回路基板および回路デバイスそれぞれにおいて、上記複数の接続突起が接続領域に列状に並び、上記スペーサは、平面視において回路基板および回路デバイスそれぞれの接続領域と重ならないように配されている構成とすることもできる。 In the circuit module, in each of the circuit board and the circuit device, the plurality of connection protrusions are arranged in a row in the connection area, and the spacer is arranged so as not to overlap the connection area of the circuit board and the circuit device in plan view. It can also be set as the structure.
　本回路モジュールでは、回路基板および回路デバイスそれぞれの接続領域は帯状であり、上記スペーサは、各接続領域に沿ったシート状である構成とすることもできる。 In this circuit module, the connection regions of the circuit board and the circuit device each have a strip shape, and the spacer may have a sheet shape along each connection region.
　本回路モジュールでは、上記スペーサは、回路基板または回路デバイスに一体形成されたリブ状である構成とすることもできる。 In the circuit module, the spacer may be formed in a rib shape integrally formed on the circuit board or the circuit device.
　本回路モジュールでは、一方が回路基板で他方が回路デバイスに設けられ、かつ対向する２つの接続突起によって挟まれた部分を導通部とし、上記スペーサが、隣り合う２つの導通部の間隙に配されている構成とすることもできる。 In this circuit module, one portion is provided on the circuit board and the other is provided on the circuit device, and a portion sandwiched between two opposing connection protrusions is defined as a conductive portion, and the spacer is disposed in a gap between two adjacent conductive portions. It can also be set as the structure.
　本回路モジュールでは、上記異方性導電層に絶縁性粒子を含む構成とすることもできる。 In this circuit module, the anisotropic conductive layer may include insulating particles.
　本回路モジュールでは、上記絶縁性粒子の粒経は導電性粒子の粒経よりも小さい構成とすることもできる。 In this circuit module, the particle size of the insulating particles may be smaller than the particle size of the conductive particles.
　本回路モジュールでは、上記絶縁性粒子の弾性率は導電性粒子の弾性率（例えば、ヤング率）よりも大きい構成とすることもできる。 In the present circuit module, the elastic modulus of the insulating particles may be larger than the elastic modulus (for example, Young's modulus) of the conductive particles.
　本回路モジュールでは、上記回路基板が、アクティブマトリクス基板またはＰＷＢ（Printed Wiring Board）である構成とすることもできる。 In the present circuit module, the circuit board may be an active matrix substrate or a PWB (Printed Wiring Board).
　本回路モジュールでは、上記回路デバイスが、ＩＣ（Integrated Circuit）チップ、ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）およびＦＰＣ（Flexible Printed Circuit）のいずれかである構成とすることもできる。 In the circuit module, the circuit device may be any one of an IC (Integrated Circuit) chip, a COF (Chip On Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed Circuit).
　本回路デバイスは、導電性粒子を含む異方性導電層を介して回路基板に接続される回路デバイスであって、上記回路基板との間隔を規定するためのスペーサを備えることを特徴とする。 This circuit device is a circuit device connected to a circuit board via an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit board.
　本回路デバイスでは、上記スペーサは絶縁性を有する構成とすることもできる。 In this circuit device, the spacer may have an insulating property.
　本回路デバイスは、ＩＣ（Integrated Circuit）チップ、ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）およびＦＰＣ（Flexible Printed circuit）のいずれかとして機能する構成とすることもできる。 The circuit device may be configured to function as any one of an IC (Integrated Circuit) chip, a COF (Chip on Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed circuit).
　本回路基板は、導電性粒子を含む異方性導電層を介して回路デバイスに接続される回路基板であって、上記回路デバイスとの間隔を規定するためのスペーサを備えることを特徴とする。 The circuit board is a circuit board connected to a circuit device through an anisotropic conductive layer containing conductive particles, and is characterized by including a spacer for defining a distance from the circuit device.
　本回路基板では、上記スペーサは絶縁性を有する構成とすることもできる。 In the circuit board, the spacer may have an insulating property.
　本回路基板は、アクティブマトリクス基板またはＰＷＢ（Printed Wiring Board）として機能する構成とすることもできる。 The circuit board may be configured to function as an active matrix substrate or a PWB (Printed Wiring Board).
　本回路基板は、アクティブマトリクス基板として機能し、上記スペーサはトランジスタのチャネルを保護する絶縁膜を用いて形成されている構成とすることもできる。 The present circuit board functions as an active matrix substrate, and the spacer may be formed using an insulating film that protects the channel of the transistor.
　本回路モジュールの製造方法は、それぞれが複数の接続突起を有する回路基板および回路デバイスを接続して回路モジュールとする、回路モジュールの製造方法であって、回路基板上に、上記複数の接続突起と重ならないようにシート状スペーサを貼り付ける工程と、上記複数の接続突起およびシート状スペーサを覆うように異方性導電フィルムを貼り付けて異方性導電層を形成する工程と、異方性導電層上に回路デバイスを位置合わせし、回路デバイスおよび回路基板を圧着させる工程とを含むことを特徴とする。 The method for manufacturing a circuit module is a method for manufacturing a circuit module, in which a circuit board and a circuit device each having a plurality of connection protrusions are connected to form a circuit module. A step of attaching a sheet-like spacer so as not to overlap, a step of attaching an anisotropic conductive film so as to cover the plurality of connection protrusions and the sheet-like spacer, and forming an anisotropic conductive layer; Aligning the circuit device on the layer and crimping the circuit device and the circuit board.
　本発明は上記の実施の形態に限定されるものではなく、上記実施の形態を技術常識に基づいて適宜変更したものやそれらを組み合わせて得られるものも本発明の実施の形態に含まれる。 The present invention is not limited to the above-described embodiments, and those obtained by appropriately modifying the above-described embodiments based on common general technical knowledge and those obtained by combining them are also included in the embodiments of the present invention.
　本発明は、例えば各種基板にＩＣチップやＣＯＦ（Chip on Film）あるいはＦＰＣ（Flexible Printed Circuit）を実装する場合に好適である。 The present invention is suitable when, for example, an IC chip, a COF (Chip on Film), or an FPC (Flexible Printed Circuit) is mounted on various substrates.
　ＬＣＰ　液晶パネル
　ＡＭ　アクティブマトリクス基板（回路基板）
　ＤＴ　ＩＣチップ（回路デバイス）
　ＡＣＬ　異方性導電層
　ＣＰ　導電性粒子
　ＳＳ　シート状スペーサ
　ＲＳ　ｒｓ　Ｒｓ　ｒＳ　リブ状スペーサ
　ＲＳ’　ｒｓ’　リブ状スペーサ
　ＶＰ　バンプ（接続突起）
　ＴＭ　端子（接続突起）
　Ｗ　配線（メタル配線）
　ＧＳ　ガラス基板
　ＧＩ　ゲート絶縁膜
　ＰＡ　パッシベーション膜
　ＩＰ　絶縁性粒子 LCP liquid crystal panel AM active matrix substrate (circuit board)
DT IC chip (circuit device)
ACL Anisotropic Conductive Layer CP Conductive Particle SS Sheet Spacer RS rs Rs rS Rib Spacer RS 'rs' Rib Spacer VP Bump (Connection Protrusion)
TM terminal (connection protrusion)
W wiring (metal wiring)
GS glass substrate GI gate insulating film PA passivation film IP insulating particles

Claims (22)

  1. 　回路基板と回路デバイスとが導電性粒子を含む異方性導電層を介して接続された回路モジュールであって、
    　上記回路基板および回路デバイスの一方に貼付あるいは一体化され、回路基板と回路デバイスとの距離を規定するスペーサを備える回路モジュール。     A circuit module in which a circuit board and a circuit device are connected via an anisotropic conductive layer containing conductive particles,
    A circuit module comprising a spacer attached to or integrated with one of the circuit board and the circuit device and defining a distance between the circuit board and the circuit device.
  2. 　上記スペーサは絶縁性を有する請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the spacer has an insulating property.
  3. 　回路基板が有する複数の接続突起の１つと、回路デバイスが有する複数の接続突起部の１つとが、上記導電性粒子によって接続されている請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein one of the plurality of connection protrusions included in the circuit board and one of the plurality of connection protrusions included in the circuit device are connected by the conductive particles.
  4. 　上記スペーサは、異方性導電層内に配されている請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the spacer is disposed in the anisotropic conductive layer.
  5. 　上記スペーサの弾性率は導電性粒子の弾性率よりも大きい請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the elastic modulus of the spacer is larger than the elastic modulus of the conductive particles.
  6. 　回路基板および回路デバイスそれぞれにおいて、上記複数の接続突起が接続領域に列状に並び、上記スペーサは、平面視において回路基板および回路デバイスそれぞれの接続領域と重ならないように配されている請求項３記載の回路モジュール。 4. The circuit board and the circuit device, respectively, wherein the plurality of connection protrusions are arranged in a row in the connection region, and the spacer is arranged so as not to overlap the connection region of the circuit board and the circuit device in plan view. The circuit module as described.
  7. 　回路基板および回路デバイスそれぞれの接続領域は帯状であり、上記スペーサは、各接続領域に沿ったシート状である請求項６記載の回路モジュール。 The circuit module according to claim 6, wherein each connection region of the circuit board and the circuit device has a strip shape, and the spacer has a sheet shape along each connection region.
  8. 　上記スペーサは、回路基板または回路デバイスに一体形成されたリブ状である請求項３記載の回路モジュール。 4. The circuit module according to claim 3, wherein the spacer has a rib shape formed integrally with a circuit board or a circuit device.
  9. 　一方が回路基板で他方が回路デバイスに設けられ、かつ対向する２つの接続突起によって挟まれた部分を導通部とし、上記スペーサが、隣り合う２つの導通部の間隙に配されている請求項８記載の回路モジュール。 9. A portion where one is a circuit board and the other is provided in a circuit device and is sandwiched between two opposing connection protrusions is a conducting portion, and the spacer is disposed in a gap between two adjacent conducting portions. The circuit module as described.
  10. 　上記異方性導電層に絶縁性粒子を含む請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the anisotropic conductive layer contains insulating particles.
  11. 　上記絶縁性粒子の粒経は導電性粒子の粒経よりも小さい請求項１０記載の回路モジュール。 The circuit module according to claim 10, wherein the particle size of the insulating particles is smaller than the particle size of the conductive particles.
  12. 　上記絶縁性粒子の弾性率は導電性粒子の弾性率よりも大きい請求項１１記載の回路モジュール。 The circuit module according to claim 11, wherein the elastic modulus of the insulating particles is larger than the elastic modulus of the conductive particles.
  13. 　上記回路基板が、アクティブマトリクス基板またはＰＷＢ（Printed Wiring Board）である請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the circuit board is an active matrix substrate or a PWB (Printed Wiring Board).
  14. 　上記回路デバイスが、ＩＣ（Integrated Circuit）チップ、ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）およびＦＰＣ（Flexible Printed Circuit）のいずれかである請求項１記載の回路モジュール。 The circuit module according to claim 1, wherein the circuit device is any one of an IC (Integrated Circuit) chip, a COF (Chip on Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed Circuit).
  15. 　導電性粒子を含む異方性導電層を介して回路基板に接続される回路デバイスであって、
    　上記回路基板との間隔を規定するためのスペーサを備える回路デバイス。     A circuit device connected to a circuit board via an anisotropic conductive layer containing conductive particles,
    A circuit device comprising a spacer for defining a distance from the circuit board.
  16. 　上記スペーサは絶縁性を有する請求項１５記載の回路デバイス。 The circuit device according to claim 15, wherein the spacer has an insulating property.
  17. 　ＩＣ（Integrated Circuit）チップ、ＣＯＦ（Chip on Film）、ＴＣＰ（Tape Carrier Package）およびＦＰＣ（Flexible Printed circuit）のいずれかとして機能する請求項１６記載の回路デバイス。 17. The circuit device according to claim 16, which functions as one of an IC (Integrated Circuit) chip, a COF (Chip on Film), a TCP (Tape Carrier Package), and an FPC (Flexible Printed circuit).
  18. 　導電性粒子を含む異方性導電層を介して回路デバイスに接続される回路基板であって、
    　上記回路デバイスとの間隔を規定するためのスペーサを備える回路基板。     A circuit board connected to a circuit device through an anisotropic conductive layer containing conductive particles,
    A circuit board comprising a spacer for defining a distance from the circuit device.
  19. 　上記スペーサは絶縁性を有する請求項１８記載の回路基板。 19. The circuit board according to claim 18, wherein the spacer has an insulating property.
  20. 　アクティブマトリクス基板またはＰＷＢ（Printed Wiring Board）として機能する請求項１８記載の回路基板。 19. The circuit board according to claim 18, which functions as an active matrix substrate or a PWB (Printed Wiring Board).
  21. 　アクティブマトリクス基板として機能し、上記スペーサはトランジスタのチャネルを保護する絶縁膜を用いて形成されている請求項１８記載の回路基板。 19. The circuit board according to claim 18, wherein the circuit board functions as an active matrix substrate, and the spacer is formed using an insulating film that protects a channel of the transistor.
  22. 　それぞれが複数の接続突起を有する回路基板および回路デバイスを接続して回路モジュールとする、回路モジュールの製造方法であって、
    　回路基板上に、上記複数の接続突起と重ならないようにシート状スペーサを貼り付ける工程と、
    　上記複数の接続突起およびシート状スペーサを覆うように異方性導電フィルムを貼り付けて異方性導電層を形成する工程と、
    　異方性導電層上に回路デバイスを位置合わせし、回路デバイスおよび回路基板を圧着させる工程とを含む回路モジュールの製造方法。     A circuit module manufacturing method, in which a circuit board and a circuit device each having a plurality of connection protrusions are connected to form a circuit module,
    A step of attaching a sheet-like spacer on the circuit board so as not to overlap the plurality of connection protrusions;
    A step of forming an anisotropic conductive layer by attaching an anisotropic conductive film so as to cover the plurality of connection protrusions and the sheet-like spacer;
    A circuit module manufacturing method comprising: aligning a circuit device on an anisotropic conductive layer and crimping the circuit device and the circuit board.
PCT/JP2011/074198 2010-10-27 2011-10-20 Circuit module, circuit board, circuit device and method for manufacturing circuit module WO2012056995A1 (en)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317426A (en) * 1998-05-06 1999-11-16 Matsushita Electric Ind Co Ltd Mounting unit
JP2000236153A (en) * 1999-02-16 2000-08-29 Nec Corp Printed wiring board structure
JP2004095879A (en) * 2002-08-30 2004-03-25 Optrex Corp Mounting structure of semiconductor chip
JP2006012992A (en) * 2004-06-23 2006-01-12 Sharp Corp Electrode connection structure of circuit board
JP2007250825A (en) * 2006-03-16 2007-09-27 Epson Imaging Devices Corp Connection structure of substrate and its manufacturing method

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317426A (en) * 1998-05-06 1999-11-16 Matsushita Electric Ind Co Ltd Mounting unit
JP2000236153A (en) * 1999-02-16 2000-08-29 Nec Corp Printed wiring board structure
JP2004095879A (en) * 2002-08-30 2004-03-25 Optrex Corp Mounting structure of semiconductor chip
JP2006012992A (en) * 2004-06-23 2006-01-12 Sharp Corp Electrode connection structure of circuit board
JP2007250825A (en) * 2006-03-16 2007-09-27 Epson Imaging Devices Corp Connection structure of substrate and its manufacturing method

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