WO2012005185A1 - 発光ダイオードの製造方法、切断方法及び発光ダイオード - Google Patents

発光ダイオードの製造方法、切断方法及び発光ダイオード Download PDF

Info

Publication number
WO2012005185A1
WO2012005185A1 PCT/JP2011/065176 JP2011065176W WO2012005185A1 WO 2012005185 A1 WO2012005185 A1 WO 2012005185A1 JP 2011065176 W JP2011065176 W JP 2011065176W WO 2012005185 A1 WO2012005185 A1 WO 2012005185A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
layer
emitting diode
light emitting
compound semiconductor
Prior art date
Application number
PCT/JP2011/065176
Other languages
English (en)
French (fr)
Japanese (ja)
Inventor
篤 松村
Original Assignee
昭和電工株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 昭和電工株式会社 filed Critical 昭和電工株式会社
Publication of WO2012005185A1 publication Critical patent/WO2012005185A1/ja

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0093Wafer bonding; Removal of the growth substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/405Reflective materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/64Heat extraction or cooling elements
    • H01L33/641Heat extraction or cooling elements characterized by the materials

Definitions

  • the present invention relates to a light emitting diode manufacturing method, a cutting method, and a light emitting diode, and more particularly to a light emitting diode manufacturing method, a cutting method, and a light emitting diode using a metal substrate as a substrate.
  • a high-power light-emitting diode an abbreviation: LED
  • a light - emitting layer made of aluminum gallium arsenide compositional formula Al X Ga 1-X As; 0 ⁇ X ⁇ 1
  • Compound semiconductor LEDs are known.
  • a high-intensity light-emitting diode (English abbreviation: LED) that emits red, orange, yellow, or yellow-green visible light
  • aluminum phosphide gallium, indium (composition formula (Al X Ga 1-X ) Y In 1-Y
  • LED high-intensity light-emitting diode
  • a compound semiconductor LED having a light emitting layer composed of P; 0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1) is known.
  • a substrate material such as gallium arsenide (GaAs) that is optically opaque to light emitted from the light emitting layer and that is not mechanically strong has been used as a substrate for these LEDs.
  • GaAs gallium arsenide
  • the degree of freedom of a substrate that can be applied as a support layer has increased, and the application of a metal substrate having great advantages such as cost, mechanical strength, and heat dissipation has been proposed.
  • a high-power light-emitting diode that needs to emit light at a high current has a larger amount of heat generation than a conventional one, and ensuring heat dissipation is a problem. Since the metal substrate can efficiently release the heat generated from the light emitting part (compound semiconductor layer) to the outside of the light emitting diode, bonding the metal substrate to the compound semiconductor layer increases the output of the light emitting diode and increases the lifetime. It is useful for conversion.
  • a light emitting diode using a metal substrate is disclosed in, for example, Patent Document 8 and Patent Document 9.
  • a wafer obtained by bonding a metal substrate to a compound semiconductor layer having a light emitting layer is formed into a chip by blade dicing, laser dicing, or the like.
  • blade dicing is performed by pressing a disk-shaped cutting blade rotating at high speed on a substrate.
  • Laser dicing is performed by irradiating a substrate with a laser, absorbing the laser energy, and melting and evaporating (ablating) the cut portion with heat energy generated.
  • a metal substrate in which dissimilar metals for example, Mo and Cu
  • they are bonded in a state having different extension widths corresponding to the thermal expansion coefficient of each metal at the time of bonding.
  • the metal substrate is composed of three metal layers of the first to third metal layers
  • the first metal layer is cut in the second metal layer when the first metal layer is cut by laser dicing (laser cutting).
  • laser dicing laser cutting
  • the interfacial stress is released on the surface on the metal layer side
  • the interfacial stress remains on the surface on the third metal layer side, so that the balance of stress is lost during cutting, and the metal substrate is distorted.
  • the dicing line is shifted from the intended position, the chip division property is deteriorated, and the light emitting diode chip becomes an abnormal shape.
  • debris generated at the time of cutting becomes a problem.
  • debris is a by-product generated by irradiation with a laser beam, and is obtained by adhering a melted material or scattered material of an irradiated material around the cut portion (material surface or cut surface). .
  • the reliability of the light emitting diode may be lowered, for example, a short circuit occurs due to contact with the side surface of the compound semiconductor layer constituting the light emitting part.
  • An object of the present invention is to provide a method for manufacturing a light emitting diode, a cutting method, and a light emitting diode.
  • the present invention provides the following means in order to solve the above problems.
  • (1) In a method for manufacturing a chip-shaped light emitting diode by irradiating a laser on a wafer, Etching a portion of a compound semiconductor layer on a planned cutting line of a wafer comprising a metal substrate composed of a plurality of metal layers and a compound semiconductor layer including a light emitting layer formed on the metal substrate; Removing the portion of the plurality of metal layers on the line to be cut of at least one layer opposite to the laser irradiation surface by etching, and removing the metal layer in plan view. And a step of cutting the metal substrate by irradiating a laser along the formed portion.
  • the “scheduled cutting line” indicates a position to be cut on the wafer, and a line formed by actually performing some processing on the substrate or the like is also subjected to actual processing. Virtual lines that are not included are also included.
  • the “part on the planned cutting line” means a part including the “scheduled cutting line” in plan view.
  • a plurality of metal layers are, for example, two adjacent metal layers formed in two stages, and those made of the same metal material are a single metal layer and a single metal layer. In this case, at least the adjacent metal layers are made of different kinds of metal materials.
  • a method for producing a light-emitting diode according to item (1) which is characterized in that (3)
  • the plurality of metal layers include a material having a thermal expansion coefficient larger than that of the compound semiconductor layer and a material having a thermal expansion coefficient smaller than that of the compound semiconductor layer.
  • the material having a thermal expansion coefficient larger than that of the compound semiconductor layer is any one of aluminum, copper, silver, gold, nickel, titanium, or an alloy thereof.
  • any one of (1) to (4) above wherein the material having a thermal expansion coefficient smaller than that of the compound semiconductor layer is any one of molybdenum, tungsten, chromium, or an alloy thereof.
  • a method for producing a light-emitting diode according to claim 1. (6) The method for manufacturing a light-emitting diode according to any one of (1) to (5), wherein the plurality of metal layers are three metal layers. (7) The method for manufacturing a light-emitting diode according to (6) above, wherein, of the three metal layers, two metal layers sandwiching one metal layer are made of the same metal material.
  • the metal substrate including a plurality of metal layers, a light emitting diode that includes a compound semiconductor layer including a light emitting layer formed on the metal substrate, the side surface of the metal substrate, the thickness of the metal substrate
  • the wet etching surface and the laser cutting surface arranged side by side in the vertical direction, and among the plurality of metal layers, at least one side surface of at least one metal layer on the compound semiconductor layer side and at least one layer on the opposite side of the compound semiconductor layer
  • the plurality of metal layers are three metal layers, the side surfaces of the two metal layers sandwiching one metal layer are formed by a wet etching surface, and the side surfaces of the one metal layer are formed by a laser cut surface.
  • the step of removing at least one portion of the plurality of metal layers on the cutting line on the opposite side of the laser irradiation surface by etching, and the metal in plan view And a step of cutting the metal substrate by irradiating a laser along the removed portion of the layer, so that the portion on the cutting line of the metal layer on the side opposite to the side irradiated with the laser by etching is previously
  • the degree to which the balance of stress is lost during laser cutting can be further reduced.
  • the degree of stress balance in the metal substrate during laser cutting is reduced.
  • the degree to which the metal substrate is distorted can be reduced, the degree to which the dicing line is displaced from the intended position can be reduced, and the chip can be divided. It can be maintained well, and the light emitting diode chip can be prevented from becoming an abnormal shape.
  • the degree to which the dicing line deviates from the intended position can be reduced.
  • the thickness of the metal substrate to be laser cut is reduced by removing the portion of the metal layer on the planned cutting line by etching, so that the amount of heat generated during laser cutting is reduced, and the metal substrate due to heat generation is reduced. Expansion can be suppressed, and as a result, fluctuations in the pitch width of dicing can be reduced, and it is possible to prevent the shape of the back surface side of the light-emitting diode chip from changing due to heat.
  • the metal substrate is composed of a plurality of metal layers, etching can be performed for each metal layer using the etching selectivity, and the etching depth of the metal substrate can be easily controlled. Furthermore, instead of laser cutting the entire metal layer, the amount of metal to be laser cut is reduced by removing a part by etching, so the amount of debris generated during laser cutting is reduced and the light emitting layer is reduced. It is possible to prevent a short circuit due to contact with the side surface of the compound semiconductor layer. Further, debris can be prevented from adhering to the front surface and the back surface of the metal substrate, or the amount of adhesion can be reduced, so that appearance defects can be reduced, and wire bonding defects and die bonding defects can be reduced.
  • the step of removing before the step of cutting the metal substrate, at least one layer of the laser irradiation surface side of the plurality of metal layers, a portion of the cutting line by etching Since the portion on the planned cutting line of the metal layer on the laser irradiation side is previously removed by etching, the amount of the metal substrate to be laser cut is reduced, and the amount of debris generated is reduced. be able to. Further, by this arrangement, when the laser irradiation surface is a compound semiconductor layer side containing the light-emitting layer, the metal layer of the surface side is etched, the position of the metal substrate laser cutting is started becomes far from the compound semiconductor layer. As a result, the debris does not reach the compound semiconductor layer and can be prevented from being short-circuited, and the yield can be improved.
  • the plurality of metal layers are made of a material having a thermal expansion coefficient larger than that of the compound semiconductor layer and a material having a thermal expansion coefficient smaller than that of the compound semiconductor layer.
  • the interface generated between the compound semiconductor layer and the metal substrate As a result, one of the interfacial stresses existing on the compound semiconductor layer side and the opposite side of the compound semiconductor layer of the metal substrate is first released during laser cutting. Distortion of the metal substrate can be reduced by as.
  • a configuration in which a plurality of metal layers are formed as a three-layer metal layer, so that the metal layer on the side opposite to the laser-irradiated surface is removed by etching and the dicing line shift or The fluctuation of the dicing pitch width can be reduced.
  • the amount of generated debris can be reduced only by etching and removing the metal layer on the laser irradiation surface side, and the debris can be prevented from adhering to the compound semiconductor layer and short-circuiting, thereby improving the yield. .
  • a plurality of metal layers are made into three metal layers, and two metal layers sandwiching one metal layer among the three metal layers are made of the same metal material.
  • two metal layers sandwiching one metal layer can be etched using the same etchant, which is economical and simple, and the two metal layers are simultaneously removed by etching. Can also reduce the process time.
  • the plurality of metal layers is a three-layer metal layer, and among the three metal layers, the two metal layers sandwiching one metal layer are made of copper, Since the metal layer of one layer is made of molybdenum, the mechanical strength of molybdenum is strong. Therefore, even if the metal layer made of copper is etched deeply, the stability of the metal substrate can be maintained.
  • the opposite side of the at least one layer of the laser irradiation surface of the plurality of metal layers, a portion on the line to cut, removing by etching is the removal of the metal layer
  • cutting the metal substrate by irradiating a laser along the portion, so that the portion on the cutting line of the metal layer on the side opposite to the laser irradiation side by etching is removed in advance to remove the metal layer.
  • the interfacial stress between the metal layer and the adjacent metal layer is released in advance to reduce the degree of stress balance in the metal substrate during laser cutting, and as a result, the degree to which the metal substrate is distorted can be reduced, resulting in the expected dicing line.
  • the degree of deviation from the position can be reduced, the splitting property of the chip can be maintained well, and the light emitting diode chip can be prevented from having an abnormal shape.
  • laser cutting is performed by aligning several interfacial stresses among the multiple interfacial stresses, the degree to which the dicing line deviates from the intended position is reduced. can do.
  • the thickness of the metal substrate to be laser cut is reduced by removing the portion of the metal layer on the planned cutting line by etching, so that the amount of heat generated during laser cutting is reduced, and the metal substrate due to heat generation is reduced. Expansion can be suppressed.
  • the metal substrate is composed of a plurality of metal layers, etching can be performed for each metal layer using the etching selectivity, and the etching depth of the metal substrate can be easily controlled.
  • a portion of the cutting line further comprising the step of removing by etching as configuration, since the previously removed cut portion on the line side of the metal layer to laser radiation by etching, can be the amount of the metal substrate to be laser cutting is reduced, to reduce the debris amount produced.
  • the metal layer on the surface side is etched, so the position of the metal substrate where laser cutting is started Becomes far from the compound semiconductor layer. As a result, the debris does not reach the compound semiconductor layer and can be prevented from being short-circuited, and the yield can be improved.
  • the light emitting diode according to the present invention is a light emitting diode comprising a metal substrate composed of a plurality of metal layers and a compound semiconductor layer including a light emitting layer formed on the metal substrate, wherein the side surface of the metal substrate is A wet etching surface and a laser cutting surface arranged side by side in the thickness direction of the metal substrate, and of the plurality of metal layers, the side surface of at least one metal layer on the compound semiconductor layer side and the opposite side of the compound semiconductor layer
  • the side surface of at least one of the metal layers consists of a wet-etched surface, and by-products generated by laser irradiation are deposited only on the side surfaces of the metal substrate, so that debris adheres to the front and back surfaces of the metal substrate. The appearance is improved compared to conventional light emitting diodes.
  • FIG. 1 is a diagram illustrating an example of a light emitting diode according to an embodiment of the present invention.
  • a light emitting diode (LED) 1 according to an embodiment of the present invention includes a metal substrate 5 composed of a plurality of metal layers 21A, 22 and 21B, and a light emitting layer 2 formed on the metal substrate 5.
  • a light-emitting diode 1 having a compound semiconductor layer 3 including a side surface 5aa of a metal substrate 5 includes a wet etching surface and a laser cutting surface arranged side by side in the thickness direction of the metal substrate 5, and a plurality of metals Among the layers, the side surface 21Ba of at least one metal layer from the side far from the compound semiconductor layer is a wet etching surface, and the side surface 22a of the metal layer and the side surface 21Aa of the metal layer near the compound semiconductor layer are laser cutting surfaces. The by-products generated by laser irradiation are attached only to the side surface 5aa of the metal substrate 5.
  • the side surface 21Aa of the metal layer far from the compound semiconductor layer may be a wet etching surface.
  • the compound semiconductor layer 3 is a stacked structure of compound semiconductors including the light emitting layer 2 and is an epitaxial stacked structure formed by stacking a plurality of epitaxially grown layers.
  • the AlGaInP layer is a layer made of a material represented by the general formula (Al X Ga 1-X ) Y In 1-YP (0 ⁇ X ⁇ 1, 0 ⁇ Y ⁇ 1). This composition is determined according to the emission wavelength of the light emitting diode.
  • the composition of the constituent material is determined in accordance with the emission wavelength of the light emitting diode.
  • the compound semiconductor layer 3 is a compound semiconductor of either n-type or p-type conductivity, and a pn junction is formed inside.
  • the polarity of the surface of the compound semiconductor layer 3 may be either p-type or n-type.
  • the compound semiconductor layer 3 includes, for example, a contact layer 12c, a cladding layer 10a, a light emitting layer 2, a cladding layer 10b, and a GaP layer 13.
  • the contact layer 12c is a layer for reducing the contact resistance of the ohmic electrode, and is made of, for example, Si-doped n-type GaAs, having a carrier concentration of 1 ⁇ 10 18 cm ⁇ 3 and a layer thickness of 0.1. 05 ⁇ m.
  • the clad layer 10a is made of, for example, n-type Al 0.5 In 0.5 P doped with Si, has a carrier concentration of 3 ⁇ 10 18 cm ⁇ 3 , and a layer thickness of 0.5 ⁇ m.
  • the light emitting layer 2 includes, for example, 10 pairs of undoped (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P / (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P. It consists of a laminated structure and the layer thickness is 0.2 ⁇ m.
  • the light emitting layer 2 has a structure such as a double hetero structure (Double Hetero: DH), a single quantum well structure (Single Quantum Well: SQW), or a multiple quantum well structure (Multi Quantum Well: MQW).
  • the double heterostructure is a structure in which carriers responsible for radiative recombination can be confined.
  • the quantum well structure has a well layer and two barrier layers sandwiching the well layer.
  • the SQW has one well layer and the MQW has two or more well layers.
  • a method for forming the compound semiconductor layer 3 an MOCVD method or the like can be used.
  • an MQW structure As the light emitting layer 2, it is preferable to use an MQW structure as the light emitting layer 2.
  • the clad layer 10b is made of, for example, p-type Al 0.5 In 0.5 P doped with Mg, has a carrier concentration of 8 ⁇ 10 17 cm ⁇ 3 , and a layer thickness of 0.5 ⁇ m.
  • the GaP layer 13 is, for example, a p-type GaP layer doped with Mg, and has a carrier concentration of 5 ⁇ 10 18 cm ⁇ 3 and a layer thickness of 2 ⁇ m.
  • the configuration of the compound semiconductor layer 3 is not limited to the structure described above.
  • a current diffusion layer for planarly diffusing the element driving current in the entire compound semiconductor layer 3 or the element driving current flowing therethrough.
  • a current blocking layer or a current confinement layer for limiting the region may be provided.
  • the first electrode 6 and the second electrode 8 are each ohmic electrode, their shape and arrangement, as long as it can uniformly diffuse current to the compound semiconductor layer 3 is not particularly limited.
  • a circular or rectangular electrode can be used when viewed from above, and the electrodes can be arranged as a single electrode or a plurality of electrodes can be arranged in a grid.
  • the material of the first electrode 6 when an n-type compound semiconductor is used as the contact layer 12c, for example, AuGe, AuGeNi, AuSi or the like can be used, and a p-type compound semiconductor is used as the contact layer 12c.
  • AuBe, AuZn, or the like when used, for example, AuBe, AuZn, or the like can be used. Further, Au or the like can be further laminated thereon to prevent oxidation and improve wire bonding.
  • the material of the second electrode 8 when an n-type compound semiconductor is used as the GaP layer 13, for example, AuGe, AuGeNi, AuSi or the like can be used, and a p-type compound semiconductor is used as the GaP layer 13.
  • AuBe, AuZn, or the like when used, for example, AuBe, AuZn, or the like can be used.
  • the reflective structure 4 is formed on the surface 3 b of the compound semiconductor layer 3 on the reflective structure 4 side so as to cover the second electrode 8.
  • the reflective structure 4 is formed by laminating a metal film 15 and a transparent conductive film 14.
  • the metal film 15 is made of a metal such as copper, silver, gold, or aluminum, or an alloy thereof. These materials have high light reflectivity, and the light reflectivity from the reflective structure 4 can be 90% or more.
  • the metal film 15 the light from the light emitting layer 2 is reflected by the metal film 15 in the front direction f, and the light extraction efficiency in the front direction f can be improved. Thereby, the brightness of the light emitting diode can be further increased.
  • the metal film 15 preferably has a laminated structure made of Ag, a Ni / Ti barrier layer, and an Au-based eutectic metal (connecting metal) from the transparent conductive film 14 side.
  • the connecting metal formed on the surface 15b of the metal film 15 opposite to the compound semiconductor layer 3 is a metal having a low electrical resistance and melting at a low temperature.
  • the metal substrate can be connected without applying thermal stress to the compound semiconductor layer 3.
  • an Au-based eutectic metal that is chemically stable and has a low melting point is used.
  • the Au-based eutectic metal include a eutectic composition (Au-based eutectic metal) of an alloy such as AuSn, AuGe, and AuSi.
  • connection metal a metal such as titanium, chromium, or tungsten to the connection metal.
  • metals such as titanium, chromium, and tungsten can function as barrier metals, and impurities contained in the metal substrate can be prevented from diffusing to the metal film 15 side and reacting.
  • the transparent conductive film 14 is composed of an ITO film, an IZO film, or the like.
  • the reflective structure 4 may be composed of only the metal film 15.
  • a so-called cold mirror using a difference in refractive index of a transparent material for example, a multilayer film of titanium oxide film, silicon oxide film, white alumina, AlN May be combined with the metal film 15.
  • the metal substrate 5 is composed of a plurality of metal layers. A bonding surface 5a of the metal substrate 5 is bonded to a surface 15b on the opposite side of the compound semiconductor layer 3 of the metal film 15 constituting the reflective structure 4.
  • the thickness of the metal substrate 5 is preferably 50 ⁇ m or more and 150 ⁇ m or less. When the thickness of the metal substrate 5 is thicker than 150 ⁇ m, the manufacturing cost of the light emitting diode increases, which is not preferable. In addition, when the thickness of the metal substrate 5 is less than 50 ⁇ m, cracking, hooking, warping, etc. easily occur during handling, which may reduce the manufacturing yield.
  • first metal layer 21 and the second metal layer 22 are alternately laminated.
  • the total number of first metal layers 21 and second metal layers 22 per metal substrate is preferably 3 to 9 layers, more preferably 3 to 5 layers.
  • the thermal expansion in the thickness direction becomes unbalanced, warpage of the metal substrate 5 is generated.
  • the layer thickness of the second metal layer 22 Each needs to be thin.
  • the number of first metal layers 21 and second metal layers 22 is an odd number in total.
  • the two metal layers sandwiching one metal layer are preferably made of the same metal material.
  • the portion corresponding to the line to be cut can be removed by wet etching using the same etchant between the two metal layers sandwiched.
  • the first metal layer 21 (21A, 21B) is made of a material having a coefficient of thermal expansion larger than that of the compound semiconductor layer 3 at least when a material having a smaller coefficient of thermal expansion than that of the compound semiconductor layer 3 is used as the second metal layer. It is preferable.
  • the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, thus suppressing warpage and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate. This is because the manufacturing yield of light emitting diodes can be improved.
  • the first metal layer 21 (21A, 21B) is made of at least a material having a smaller thermal expansion coefficient than the compound semiconductor layer 3. It is preferable to become.
  • the thickness of the first metal layer 21 is preferably 5 ⁇ m or more and 50 ⁇ m or less, and more preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the thickness of the first metal layer 21 and the thickness of the second metal layer 21 may be different.
  • the thicknesses of the respective layers may be different from each other.
  • the bonding surface 5a of the metal substrate 5 is preferably formed of Ni / Au film from the metal substrate 5 side.
  • the Ni film and Au film can be formed by plating. Thereby, a joining process can be performed simply.
  • As the auxiliary bonding film Au, AuSn, or the like can be used.
  • the method of bonding the metal substrate 5 to the compound semiconductor layer 3 is not limited to the method described above, and known techniques such as diffusion bonding, an adhesive, and a room temperature bonding method can also be applied.
  • the total thickness of the first metal layer 21 is preferably 5% to 50%, more preferably 10% to 30%, and more preferably 15% to 25% of the thickness of the metal substrate 5. More preferably, it is as follows. If the total thickness of the first metal layer 21 is less than 5% of the thickness of the metal substrate 5, the effect of the thermal expansion coefficient is higher the first metal layer 21 is reduced, the heat sink function is lowered. Conversely, when the thickness of the first metal layer 21 exceeds 50% of the thickness of the metal substrate 5, cracking of the metal substrate 5 due to heat when the metal substrate 5 is connected to the compound semiconductor layer 3 is suppressed. Can not.
  • the total thickness of copper is preferably 5% to 40% of the thickness of the metal substrate 5, and is preferably 10% to 30%. It is more preferable that it is 15% or more and 25% or less.
  • the thickness of the first metal layer 21 is preferably 5 ⁇ m or more and 30 ⁇ m or less, and more preferably 5 ⁇ m or more and 20 ⁇ m or less.
  • the second metal layer 22 is made of a material whose thermal expansion coefficient is smaller than that of the compound semiconductor layer 3 when a material having a larger thermal expansion coefficient than that of the compound semiconductor layer 3 is used as the first metal layer. Is preferred.
  • the thermal expansion coefficient of the entire metal substrate is close to the thermal expansion coefficient of the compound semiconductor layer, thus suppressing warpage and cracking of the metal substrate when joining the compound semiconductor layer and the metal substrate. This is because the manufacturing yield of light emitting diodes can be improved. Therefore, when a material having a smaller thermal expansion coefficient than that of the compound semiconductor layer 3 is used as the first metal layer, the second metal layer 22 is made of a material whose thermal expansion coefficient is larger than that of the compound semiconductor layer 3. It is preferable.
  • thermo expansion coefficient about 5.3 ppm / K
  • tungsten as the second metal layer 22
  • Thermal expansion coefficient 4.3 ppm / K
  • alloys thereof are preferably used.
  • the light emitting diode 1 is a light emitting diode 1 in which a metal substrate 5 is bonded to a compound semiconductor layer 3 including a light emitting layer 2, and the metal substrate 5 includes a first metal layer 21 and a second metal layer 5.
  • the first metal layer 21 has a larger coefficient of thermal expansion than the material of the compound semiconductor layer 3, and the second metal layer 22 has a coefficient of thermal expansion of the compound semiconductor layer 3. If a structure made of a material smaller than the above material is employed, heat dissipation is excellent, cracking of the substrate during bonding can be suppressed, and high voltage can be applied to emit light with high luminance.
  • the material of the second metal layer 22 is a material having a thermal expansion coefficient that is within ⁇ 1.5 ppm / K of the thermal expansion coefficient of the compound semiconductor layer 3.
  • it is excellent in heat dissipation, can suppress cracking of the substrates during bonding, and can emit light with high brightness by applying a high voltage.
  • the substrate when the first metal layer 21 adopts a configuration made of aluminum, copper, silver, gold, nickel, or an alloy thereof, the substrate is excellent in heat dissipation and bonded. Can be suppressed, and high voltage can be applied to emit light with high brightness.
  • the second metal layer 22 is made of molybdenum, tungsten, chromium, or an alloy thereof as the light-emitting diode 1 according to an embodiment of the present invention, the heat dissipation is excellent, and cracking of the substrate during bonding is suppressed. It is possible to emit light with high luminance by applying a high voltage.
  • the first metal layer 21 is made of copper
  • the second metal layer 22 is made of molybdenum
  • the first metal layer 21 and the second metal layer 22 are layers. Adopting a configuration in which the number of layers is 3 or more and 9 or less, it is excellent in heat dissipation, can suppress the cracking of the substrate during bonding, and can emit light with high luminance by applying a high voltage it can.
  • a method of manufacturing a light emitting diode includes a step of manufacturing a wafer including a metal substrate including a plurality of metal layers and a compound semiconductor layer including a light emitting layer formed on the metal substrate; the cut portion on the line of said compound semiconductor layer, and removing by etching at least one layer of the opposite side of the laser irradiation surface of the plurality of metal layers, a portion on the line to cut, etched away And a step of irradiating a laser along the removed portion of the metal layer in plan view to cut the metal substrate.
  • the manufacturing process of a metal substrate is demonstrated.
  • a first metal layer having a thermal expansion coefficient larger than the material of the compound semiconductor layer 3 and a second metal layer having a thermal expansion coefficient smaller than the material of the compound semiconductor layer 3 are adopted and hot pressed. Form.
  • first metal plates 21 and one substantially flat plate-like second metal plate 22 are prepared.
  • 10 ⁇ m thick Cu is used as the first metal plate 21, and 75 ⁇ m thick Mo is used as the second metal plate 22.
  • the second metal plate 22 is inserted between the two first metal plates 21, and these are stacked.
  • substrate is arrange
  • the first metal layer 21 is Cu
  • the second metal layer 22 is Mo
  • the three layers of Cu (10 ⁇ m) / Mo (75 ⁇ m) / Cu (10 ⁇ m) are used.
  • a metal substrate 5 is formed.
  • the metal substrate 5 has a thermal expansion coefficient of 5.7 ppm / K and a thermal conductivity of 220 W / m ⁇ K.
  • the surface after cutting according to the size of the bonding surface of the compound semiconductor layer 3, the surface may be mirror-finished. Further, a bonding auxiliary film may be formed on the bonding surface 5a of the metal substrate 5 in order to stabilize electrical contact.
  • the bonding auxiliary film gold, platinum, nickel, or the like can be used. For example, after depositing 2 ⁇ m of nickel on the bonding surface 5a of the metal substrate 5 by plating, 1 ⁇ m of gold is deposited on the nickel. Furthermore, a eutectic metal such as die bonding AuSn may be formed instead of the auxiliary bonding film. Thereby, a joining process can be simplified.
  • a plurality of epitaxial layers are grown on the one surface 11 a of the semiconductor substrate 11 to form an epitaxial multilayer 17.
  • the semiconductor substrate 11 is a substrate for forming an epitaxial layered body 17 and is, for example, a Si-doped n-type GaAs single crystal substrate in which one surface 11a is inclined by 15 ° from the (100) plane.
  • a gallium arsenide (GaAs) single crystal substrate can be used as the substrate on which the epitaxial multilayer 17 is formed.
  • a metal organic chemical vapor deposition (MOCVD) method As a method for forming the compound semiconductor layer 3, a metal organic chemical vapor deposition (MOCVD) method, a molecular beam epitaxy (MBE) method, or a liquid phase epitaxy (Liquid Phase EpiLex) method is used. Etc. can be used.
  • MOCVD metal organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • Liquid Phase EpiLex Liquid Phase EpiLex
  • Each layer is epitaxially grown using Note that biscyclopentadiethynylmagnesium ((C 5 H 5 ) 2 Mg) is used as a Mg doping material. Further, disilane (Si 2 H 6 ) is used as a Si doping raw material. Further, phosphine (PH 3 ) or arsine (AsH 3 ) is used as a raw material for the group V constituent element.
  • the p-type GaP layer 13 is grown at 750 ° C., for example, and the other epitaxial growth layers are grown at 730 ° C., for example.
  • a buffer layer 12 a made of n-type GaAs doped with Si is formed on one surface 11 a of the semiconductor substrate 11.
  • the buffer layer 12a for example, n-type GaAs doped with Si is used, the carrier concentration is 2 ⁇ 10 18 cm ⁇ 3 , and the layer thickness is 0.2 ⁇ m.
  • an etching stop layer 12b made of Si-doped n-type (Al 0.5 Ga 0.5 ) 0.5 In 0.5 P is formed on the buffer layer 12a.
  • Etch stop layer 12b at the time of the semiconductor substrate etched away until the cladding layer and the luminescent layer is a layer for preventing are etched, for example, the Si-doped (Al 0.5 Ga 0.5) 0 It consists .5 In 0.5 P, the thickness and 0.5 [mu] m.
  • a contact layer 12c made of Si-doped n-type GaAs is formed on the etching stop layer 12b.
  • a cladding layer 10a made of n-type Al 0.5 In 0.5 P doped with Si is formed on the contact layer 12c.
  • undoped (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P / (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P 10 is formed on the cladding layer 10a.
  • a light emitting layer 2 having a pair of laminated structures is formed.
  • a clad layer 10b made of p-type Al 0.5 In 0.5 P doped with Mg is formed on the light emitting layer 2.
  • a Mg-doped p-type GaP layer 13 is formed on the cladding layer 10b.
  • the surface 13a opposite to the semiconductor substrate 11 of the p-type GaP layer 13 is mirror-polished to a depth of 1 ⁇ m from the surface to make the surface roughness within 0.18 nm, for example.
  • a second electrode (ohmic electrode) 8 is formed on the surface 13 a opposite to the semiconductor substrate 11 of the p-type GaP layer 13.
  • the second electrode 8 is formed by laminating Au having a thickness of 0.2 ⁇ m on AuBe having a thickness of 0.4 ⁇ m.
  • the second electrode 8 has a circular shape of 20 ⁇ m ⁇ when viewed in plan, and is formed at intervals of 60 ⁇ m.
  • a transparent conductive film 14 made of an ITO film is formed so as to cover the surface 13 a opposite to the semiconductor substrate 11 of the p-type GaP layer 13 and the second electrode 8.
  • a heat treatment at 450 ° C. is performed to form an ohmic contact between the second electrode 8 and the transparent conductive film 14.
  • a metal film 15 was formed by forming a film made of nickel (Ni) / titanium (Ti) to a thickness of 0.5 ⁇ m and a film made of gold (Au) to a thickness of 1 ⁇ m. Thereby, the reflective structure 4 including the metal film 15 and the transparent conductive film 14 is formed.
  • etching stop layer 12b is selectively removed with a hydrochloric acid-based etchant. Thereby, the compound semiconductor layer 3 having the light emitting layer 2 is formed.
  • a conductive film for an electrode is formed on the surface 3a of the compound semiconductor layer 3 opposite to the reflective structure 4 by using a vacuum deposition method.
  • a metal layer structure made of AuGe / Ni / Au can be used as the electrode conductive film.
  • AuGe Ga mass ratio 12%) is formed to a thickness of 0.15 ⁇ m
  • Ni is then formed to a thickness of 0.05 ⁇ m
  • Au is further formed to a thickness of 1 ⁇ m.
  • the electrode conductive film is patterned into a circular shape in plan view, for example, and a light emitting diode wafer is produced as an n-type ohmic electrode (first electrode) 6. To do.
  • a mixed solution of ammonia water (NH 4 OH) / hydrogen peroxide (H 2 O 2 ) / pure water (H 2 0) in the contact layer 12c for example, a mixed solution of ammonia water (NH 4 OH) / hydrogen peroxide (H 2 O 2 ) / pure water (H 2 0) in the contact layer 12c.
  • NH 4 OH ammonia water
  • H 2 O 2 hydrogen peroxide
  • pure water H 2 0
  • each metal of the n-type ohmic electrode (first electrode) 6 is alloyed by performing a heat treatment at 420 ° C. for 3 minutes, for example. Thereby, the resistance of the n-type ohmic electrode (first electrode) 6 can be reduced.
  • a resist is applied on the compound semiconductor layer 3 of the wafer of light emitting diodes, and a resist pattern 31 including a line pattern to be cut having a width of about 60 ⁇ m is formed by photolithography, for example.
  • the removal width of the compound semiconductor layer determines the removal width of the subsequent metal layer. Accordingly, the removal width of the compound semiconductor layer is preferably wider than the cutting width by the laser in order to reduce the amount of debris generated during the subsequent laser cutting. For example, when laser cutting is performed by laser irradiation from the front surface, the width is preferably about 40 ⁇ m wider than the laser cutting width. Further, when laser cutting is performed by laser irradiation from the back surface, the cutting width by the laser is preferably about 20 ⁇ m wide.
  • the wafer is immersed in a hydrofluoric acid-based liquid, for example, a solution obtained by adding water to hydrogen difluoride 2-3%, ammonium fluoride 0.05-0.1%, A portion of the Ti layer 34 located below the removed portion is removed by etching (see reference numeral 34A).
  • a hydrofluoric acid-based liquid for example, a solution obtained by adding water to hydrogen difluoride 2-3%, ammonium fluoride 0.05-0.1%
  • a portion of the Ti layer 34 located below the removed portion is removed by etching (see reference numeral 34A).
  • an Au-based etching solution for example, a cyan-based etching solution, and portions of the Au layers 35 and 36 located below the removed portion are etched and removed (see reference numerals 35A and 36A).
  • the wafer is immersed in a ferric chloride solution whose etching rate for Ni and Cu is higher than that for Mo and Ni and Cu can be selectively etched, and the removed portions of the Ni layer 37 and the Cu layer 21A are removed.
  • the portion located below is removed by etching until the Mo layer 22 is exposed (see reference numerals 37A and 21AA).
  • a resist is applied on the Au / Ni layer formed on the metal substrate 5 on the back surface of the light emitting diode wafer, and includes a line pattern to be cut having a width of about 40 ⁇ m, for example, by photolithography.
  • a resist pattern 41 is formed.
  • the wafer is immersed in an Au-based etching solution, for example, a cyan-based etching solution, and the portion of the Au layer 42 located below the removed portion is etched and removed ( Part indicated by reference numeral 42A).
  • an Au-based etching solution for example, a cyan-based etching solution
  • the wafer is immersed in a ferric chloride solution in which the etching rate for Ni and Cu is higher than the etching rate for Mo and Ni and Cu can be selectively etched.
  • a portion of 21B located below the removed portion is removed by etching until the Mo layer is exposed (portions indicated by reference numerals 43A and 21BB).
  • the back surface Cu layer on the cutting scheduled line is removed by the above procedure.
  • the compound semiconductor layer removal step, the front surface Cu layer removal step, and the back surface Cu layer removal step are all preferably performed.
  • the compound semiconductor layer removal step and the back surface Cu layer removal step are performed. Even if it only performs, the bad influence of the heat generated at the time of laser cutting can be reduced.
  • laser irradiation is performed from the back surface, even if only the compound semiconductor layer removal step and the front Cu layer removal step are performed, the adverse effect of heat generated during laser cutting can be reduced.
  • the compound semiconductor layer removal step, the front surface metal layer removal step, and the back surface metal layer removal step may be performed in this order, or the compound after the back surface metal layer removal step is performed first.
  • You may perform a semiconductor layer removal process and a front surface metal layer removal process in order.
  • it can also carry out in order of a compound semiconductor layer removal process, a back surface metal layer removal process, and a front surface metal layer removal process.
  • the back surface metal layer removing step and the front surface metal layer removing step can be performed simultaneously.
  • laser irradiation is performed from the front surface, it is convenient and preferable to perform the back surface metal layer removing step, the compound semiconductor layer removing step, and the front surface metal layer removing step in this order.
  • the laser irradiation is performed from the back surface, it is convenient and preferable to perform the compound semiconductor layer removal step, the front surface metal layer removal step, and the back surface metal layer removal step in this order.
  • the metal layer is cut by irradiating a laser along the portion where the metal layer on the line to be cut on the back surface is removed to cut the metal substrate.
  • the laser cutting conditions may be those used in the LED element manufacturing process.
  • the metal substrate can be cut under conditions where the laser wavelength is 355 nm and the feed rate is 20 mm / sec.
  • Laser scanning of laser dicing may be performed in multiple times. At that time, dicing may be performed by changing the thickness of the laser beam.
  • the laser cut surface of the metal substrate is then preferably Au plated.
  • FIG. 11 is a schematic cross-sectional view showing an example of a light-emitting diode lamp according to an embodiment of the present invention.
  • a light emitting diode lamp 50 according to an embodiment of the present invention is mounted on a package substrate 55, two electrode terminals 53, 54 formed on the package substrate 55, and the electrode terminal 54.
  • the light-emitting diode 1 includes a transparent resin (sealing resin) 51 made of silicon or the like formed so as to cover the light-emitting diode 1.
  • the light-emitting diode 1 includes the compound semiconductor layer 3, the reflective structure 4, the metal substrate 5, the first electrode 6, and the second electrode 8, and is arranged so that the metal substrate 5 is connected to the electrode terminal 53. Has been.
  • the first electrode 6 and the electrode terminal 54 are wire bonded.
  • the voltage applied to the electrode terminals 53 and 54 is applied to the compound semiconductor layer 3 through the first electrode 6 and the second electrode 8, and the light emitting layer included in the compound semiconductor layer 3 emits light. The emitted light is extracted in the front direction f.
  • the package substrate 55 has a thermal resistance of 10 ° C./W or less. Thereby, even when 1 W or more of electric power is applied to the light emitting layer 2 to emit light, the light emitting layer 2 can function as a heat sink, and the heat dissipation of the light emitting diode 1 can be further enhanced.
  • the shape of the package substrate is not limited to this, and a package substrate having another shape may be used. Also in LED lamp products using package substrates of other shapes, sufficient heat dissipation can be ensured, so that a light-emitting diode lamp with high output and high brightness can be obtained.
  • the light emitting layer has a laminated structure of 10 pairs of (Al 0.2 Ga 0.8 ) 0.5 In 0.5 P / (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P. 3 ⁇ m thick, GaP layer 2 ⁇ m, reflective structure Ag layer 0.7 ⁇ m, Ni / Ti barrier layer 0.5 ⁇ m, Au layer 1 ⁇ m, metal substrate Cu layer 10 ⁇ m / Mo layer 75 ⁇ m / Cu layer 10 ⁇ m A wafer having a Ni layer of 2 ⁇ m and an Au layer of 1 ⁇ m formed in order on both sides of the layer structure was produced.
  • the Cu layer on the front surface side of the metal substrate was removed by etching to form a groove having a width of 60 ⁇ m.
  • the Cu layer on the back surface side of the metal substrate was removed by etching to form a groove having a width of 40 ⁇ m.
  • the Mo layer of the metal substrate was laser-cut from the front surface of the wafer under the conditions of a laser wavelength of 355 nm and a feed rate of 20 mm / sec.
  • the chip-shaped light emitting diode thus fabricated was observed with a laser microscope.
  • the debris was attached to the side surface of the Cu layer on the front surface side and the side surface of the Cu layer on the back surface side of the metal substrate, but the Cu layer on the front surface side and the Cu layer on the back surface side were exposed. No debris adhering to the surface was observed.
  • the present invention is particularly applicable to a manufacturing method, a cutting method, and an industry using a light emitting diode using a metal substrate as a substrate.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)
  • Dicing (AREA)
PCT/JP2011/065176 2010-07-09 2011-07-01 発光ダイオードの製造方法、切断方法及び発光ダイオード WO2012005185A1 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2010156722A JP5605033B2 (ja) 2010-07-09 2010-07-09 発光ダイオードの製造方法、切断方法及び発光ダイオード
JP2010-156722 2010-07-09

Publications (1)

Publication Number Publication Date
WO2012005185A1 true WO2012005185A1 (ja) 2012-01-12

Family

ID=45441164

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2011/065176 WO2012005185A1 (ja) 2010-07-09 2011-07-01 発光ダイオードの製造方法、切断方法及び発光ダイオード

Country Status (3)

Country Link
JP (1) JP5605033B2 (zh)
TW (1) TWI489651B (zh)
WO (1) WO2012005185A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5792694B2 (ja) 2012-08-14 2015-10-14 株式会社東芝 半導体発光素子
KR101999315B1 (ko) * 2012-08-27 2019-07-11 엘지디스플레이 주식회사 유기발광표시장치 제조 방법 및 장치
JP6824581B2 (ja) * 2017-04-04 2021-02-03 株式会社ディスコ 加工方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207508A (ja) * 2002-12-25 2004-07-22 Shin Etsu Handotai Co Ltd 発光素子及びその製造方法
JP2007081010A (ja) * 2005-09-13 2007-03-29 Matsushita Electric Ind Co Ltd 発光素子
WO2007046164A1 (ja) * 2005-10-18 2007-04-26 Eiki Tsushima クラッド材およびその製造方法、クラッド材の成型方法、クラッド材を用いた放熱基板
WO2008013279A1 (fr) * 2006-07-28 2008-01-31 Kyocera Corporation Boîtier de stockage de composant électronique et dispositif électronique
JP2009004766A (ja) * 2007-05-24 2009-01-08 Hitachi Cable Ltd 化合物半導体ウェハ、発光ダイオード及びその製造方法
WO2011043240A1 (ja) * 2009-10-07 2011-04-14 昭和電工株式会社 発光ダイオード用金属基板、発光ダイオード及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004207508A (ja) * 2002-12-25 2004-07-22 Shin Etsu Handotai Co Ltd 発光素子及びその製造方法
JP2007081010A (ja) * 2005-09-13 2007-03-29 Matsushita Electric Ind Co Ltd 発光素子
WO2007046164A1 (ja) * 2005-10-18 2007-04-26 Eiki Tsushima クラッド材およびその製造方法、クラッド材の成型方法、クラッド材を用いた放熱基板
WO2008013279A1 (fr) * 2006-07-28 2008-01-31 Kyocera Corporation Boîtier de stockage de composant électronique et dispositif électronique
JP2009004766A (ja) * 2007-05-24 2009-01-08 Hitachi Cable Ltd 化合物半導体ウェハ、発光ダイオード及びその製造方法
WO2011043240A1 (ja) * 2009-10-07 2011-04-14 昭和電工株式会社 発光ダイオード用金属基板、発光ダイオード及びその製造方法

Also Published As

Publication number Publication date
TW201210060A (en) 2012-03-01
JP5605033B2 (ja) 2014-10-15
TWI489651B (zh) 2015-06-21
JP2012019137A (ja) 2012-01-26

Similar Documents

Publication Publication Date Title
JP5865695B2 (ja) 発光ダイオード及びその製造方法
JP5913955B2 (ja) 発光ダイオード及びその製造方法
WO2010095361A1 (ja) 発光ダイオード、発光ダイオードランプ及び発光ダイオードの製造方法
JP6077201B2 (ja) 発光ダイオードおよびその製造方法
WO2013061735A1 (ja) 発光ダイオード、発光ダイオードの製造方法、発光ダイオードランプ及び照明装置
JP5245970B2 (ja) 発光ダイオード及びその製造方法、並びにランプ
JP5961358B2 (ja) 発光ダイオード及びその製造方法
WO2012073993A1 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
WO2010095353A1 (ja) 発光ダイオード及びその製造方法、並びに発光ダイオードランプ
JP5557649B2 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP5586372B2 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP5586371B2 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP5605033B2 (ja) 発光ダイオードの製造方法、切断方法及び発光ダイオード
JP6101303B2 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP5605032B2 (ja) 発光ダイオードの製造方法、切断方法及び発光ダイオード
WO2011090016A1 (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP2012222033A (ja) 発光ダイオードの製造方法、切断方法及び発光ダイオード
JP2012129249A (ja) 発光ダイオード、発光ダイオードランプ及び発光ダイオードの製造方法
JP2014168101A (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP2014158057A (ja) 発光ダイオード、発光ダイオードランプ及び照明装置
JP2011086917A (ja) 発光ダイオード、発光ダイオードランプ及び照明装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 11803519

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 11803519

Country of ref document: EP

Kind code of ref document: A1