WO2011148551A1 - 不揮発スイッチング装置を駆動する方法 - Google Patents
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- 238000000034 method Methods 0.000 title claims abstract description 27
- 239000004065 semiconductor Substances 0.000 claims description 38
- 230000010287 polarization Effects 0.000 description 19
- 239000000758 substrate Substances 0.000 description 8
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910004121 SrRuO Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
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- G—PHYSICS
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- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
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- G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
Definitions
- the present invention relates to a method for driving a nonvolatile switching device including a laminated film formed of a ferroelectric film and a semiconductor film.
- Patent Document 1 discloses a nonvolatile switching device.
- FIG. 8 shows a conventional nonvolatile switching device disclosed in FIG.
- the nonvolatile switching device includes a substrate 11, a control electrode 12, a ferroelectric layer 13, a semiconductor layer 14, and first to third electrodes 15a to 15c.
- the control electrode 12, the ferroelectric layer 13, and the semiconductor layer 14 are laminated on the substrate 11 in this order.
- the first to third electrodes 15 a to 15 c are provided on the semiconductor layer 14.
- a voltage is applied between the control electrode 12 and the first to third electrodes 15a to 15c to change the polarization direction of the ferroelectric layer 13.
- the part of the semiconductor layer 14 laminated on the part has a low resistance. This corresponds to the on state.
- FIG. 8A only a part of the ferroelectric layer 13 located under the third electrode 15c has a downward polarization direction. Therefore, as shown in FIG. 8B, a current selectively flows from the first electrode 15a to the second electrode 15b.
- FIG. 9A shows a modification of the nonvolatile switching device shown in FIG.
- an X direction, a Y direction, and a Z direction are a longitudinal direction of the ferroelectric layer 13, a direction orthogonal to the longitudinal direction, and a stacking direction, respectively.
- the nonvolatile switching device shown in FIG. 9A is the same as the nonvolatile switching device shown in FIG. 8 except that it includes a first electrode 15, a second electrode 16, a third electrode 17, and a fourth electrode 18. Are the same. These four electrodes 15 to 18 are arranged at four positions corresponding to the apexes of the square.
- the first electrode 15 and the third electrode 17 are provided along the X direction.
- the second electrode 16 and the fourth electrode 18 are provided along the X direction.
- the first electrode 15 and the second electrode 16 are provided along the Y direction.
- the third electrode 17 and the fourth electrode 18 are provided along the Y direction.
- a method of selectively flowing a current between two electrodes using the nonvolatile switching device will be described below.
- a current is selectively passed between the first electrode 15 and the third electrode 17.
- a ferroelectric is applied between the control electrode 12 and the first electrode 15 and between the control electrode 12 and the third electrode 17 and is located below the first electrode 15 and the third electrode 17.
- Each part of the body layer 13 has an upward polarization direction. In this way, each portion has a low resistance, that is, an on state.
- a voltage is applied between the control electrode 12 and the second electrode 16, and between the control electrode 12 and the fourth electrode 18, and is positioned below the second electrode 16 and the fourth electrode 18.
- Each part of the ferroelectric layer 13 has a downward polarization direction. In this way, each portion has a high resistance, that is, an off state.
- a current can selectively flow from the first electrode 15 to the third electrode 17. In other words, no current flows through the second electrode 16 or the fourth electrode 18.
- a current is selectively passed between the first electrode 15 and the fourth electrode 18.
- each part of the ferroelectric layer 13 located under the first electrode 15 and the fourth electrode 18 has an upward polarization direction.
- a part of the ferroelectric layer 13 located below the third electrode 17 and the second electrode 16 has a downward polarization direction.
- the first electrode 15 and the fourth electrode 18 have an on state
- the third electrode 17 and the second electrode 16 have an off state. Therefore, theoretically, a current can selectively flow between the first electrode 15 and the fourth electrode 18.
- FIG. 10 is a plan view of the first to fourth electrodes 15 to 18.
- the distance L1 between the first electrode 15 and the second electrode 16 is shorter than the distance L2 between the first electrode 15 and the fourth electrode 18. Therefore, the resistance R1 between the first electrode 15 and the second electrode 16 is smaller than the resistance R2 between the first electrode 15 and the fourth electrode 18.
- first electrode 15 and the second electrode 16 There are three electrical resistances between the first electrode 15 and the second electrode 16. That is, they have a low resistance RL 15 and a resistance R 1 included in a portion of the semiconductor layer 14 located under the first electrode 15, and a high resistance included in the portion of the semiconductor layer 14 located under the second electrode 16. RH 16 .
- first electrode 15 and the fourth electrode 18 there are three electrical resistances between the first electrode 15 and the fourth electrode 18. That is, they have a low resistance RL 15 , a resistance R 2, and a low resistance of a portion of the semiconductor layer 14 located under the fourth electrode 18. RL 18 is present electrically.
- An object of the present invention is to provide a method of selectively flowing a current using a nonvolatile switching device that operates accurately.
- a method of selectively flowing a current using a nonvolatile switching device includes the following steps: Preparing the nonvolatile switching device (a), wherein the nonvolatile switching device comprises a control electrode, a ferroelectric film, a semiconductor film, and an electrode group; The control electrode, the ferroelectric film, the semiconductor film, and the electrode group are laminated in this order,
- the electrode group includes a first electrode, a second electrode, and a third electrode,
- the first electrode includes a side L2 having a length of LL and a side L3 having a length of LS.
- the second electrode comprises a side L4 having a length of LS and a length L6 having a length of LS;
- the third electrode includes a side L7 having a length of LS and a side L8 having a length of LL.
- the side L2, the side L3, and the side L6 are parallel to the side L8, the side L4, and the side L7, respectively.
- IL / LL IS / LS (A)
- IL is an interval between the side L2 and the side L8
- IS is an interval between the side L3 and the side L4
- the distance between the side L6 and the side L7 is equal to the IS
- in the first state no current flows between the electrode groups
- In the second state a current selectively flows between the first electrode and the second electrode
- a current selectively flows between the first electrode and the third electrode
- Voltages V1, Va, Vb, and Vc are applied to the control electrode, the first electrode, the second electrode, and the third electrode, respectively
- a voltage that satisfies any of the following inequalities (a) to (d) is applied: V1> Va, V1 ⁇ Vb, and V1 ⁇ Vc (a) V1
- the first electrode, the second electrode, and the third electrode may be congruent.
- step (c) may further be provided: Applying a voltage Vin to the first electrode, the second electrode, and the third electrode, and simultaneously applying a voltage Vreset to the control electrode (c)
- Vin ⁇ Vreset.
- any one of the first state, the second state, the third state, and the fourth state may be set:
- a current flows between the first electrode, the second electrode, and the third electrode,
- a voltage that satisfies the following inequality is applied: V1> Va, V1> Vb, V1> Vc.
- the nonvolatile switching device may further include a fourth electrode, wherein the fourth electrode includes a side L10 having a length of LS, a side L11 having a length of LL, and the LS.
- Side L12 having a length of The first electrode further includes a side L1 having a length of the LS, The second electrode further includes a side L5 having a length of the LL, The third electrode further includes a side L9 having the length of the LS, The side L1, the side L5, and the side L9 are parallel to the side L12, the side L11, and the side L10, respectively.
- the distance between the side L5 and the side L11 is equal to the IL
- the distance between the side L1 and the side L12 and the distance between the side L9 and the side L10 are all equal to the IS.
- the first electrode, the second electrode, the third electrode, and the fourth electrode may be congruent.
- any one of the first state, the second state, the third state, and the fourth state to the twelfth state may be set.
- the voltage Vd is Applied to the fourth electrode;
- a current flows between the first electrode, the second electrode, and the third electrode,
- a voltage Vd is applied to the fourth electrode.
- a voltage that satisfies the following inequality is applied: V1> Va, V1> Vb, V1> Vc, and V1 ⁇ Vd
- a current selectively flows between the second electrode and the third electrode
- a voltage that satisfies the following inequality is applied: V1 ⁇ Va, V1> Vb, V1> Vc, and V1 ⁇ Vd
- a current selectively flows between the first electrode and the fourth electrode,
- a voltage that satisfies the following inequality is applied: V1> Va, V1 ⁇ Vb
- the present invention provides a method of selectively flowing current using a nonvolatile switching device that operates accurately.
- FIG. 6 is a diagram for explaining a method of driving the nonvolatile switching device according to the first embodiment.
- FIG. 6 is a diagram for explaining a method of driving the nonvolatile switching device according to the first embodiment.
- FIG. 6 is a diagram for explaining a method of driving the nonvolatile switching device according to the first embodiment.
- Cross-sectional view showing low and high resistance states Plan view of nonvolatile switching device according to embodiment 2
- Electrical circuit diagram of nonvolatile switching device according to embodiment 2 The figure which shows the result of Example 1
- FIG. 1 is a plan view of the nonvolatile switching device 20 according to the first embodiment.
- FIG. 2 is a cross-sectional view taken along line AA ′ in FIG.
- a control electrode 12, a ferroelectric film 13, and a semiconductor film 14 are laminated on the substrate 11 in this order.
- an electrode group is formed on the semiconductor film 14.
- the electrode group includes a first electrode 15, a second electrode 16, and a third electrode 17. These electrodes 15 to 17 are arranged rotationally symmetrical. The electrodes 15 to 17 are congruent in plan view.
- the X direction, the Y direction, and the Z direction are the longitudinal direction of the ferroelectric film 13, the direction orthogonal to the longitudinal direction, and the stacking direction, respectively. Is defined.
- the term “plan view” means viewing from the Z direction.
- the second electrode 16 is adjacent to the third electrode 17 along the X direction.
- the first electrode 15 is adjacent to the second electrode 16 along the Y direction.
- the first electrode 15 includes a side L1, a side L2, and a side L3.
- the second electrode 16 includes a side L4, a side L5, and a side L6.
- the third electrode 17 includes a side L7, a side L8, and a side L9.
- the side L1, the side L3, the side L4, the side L6, the side L7, and the side L9 all have a length of LS.
- the term “short sides” as used herein means those sides having a length LS.
- Side L2, side L5, and side L8 have a length of LL.
- the term “long sides” as used herein means those sides having a length LL.
- the side L2 is parallel to the side L8.
- the interval between the side L2 and the side L8 is IL.
- the side L3 is parallel to the side L4.
- the interval between the side L3 and the side L4 is IS.
- the side L6 is parallel to the side L7.
- the interval between the side L6 and the side L7 is also IS.
- the current flowing through the semiconductor film 14 is controlled according to the direction of polarization in the ferroelectric film 13. That is, when the polarization direction of the ferroelectric film 13 matches the + Z direction, the electrons induced in the semiconductor film 14 make the semiconductor film 14 have a low resistance. When the polarization direction matches the ⁇ Z direction, the discharge of electrons from the semiconductor film 14 makes the semiconductor film 14 highly resistive.
- a voltage is applied between each of the electrodes 15 to 17 and the control electrode 12, and the resistance value of the semiconductor film 14 is controlled. As a result, the resistance value between the electrodes 15 to 17 is controlled.
- the three electrodes 15-17 can be electrically connected or disconnected independently.
- Table 1 below shows the conduction state between the first electrode 15 and the other electrodes 16 to 17 and the potentials of the electrodes 15 to 17.
- the voltage applied to the control electrode 12 is always constant.
- the constant voltage is 0V.
- 3A to 3C show the potentials of the electrodes 15 to 17 in the top view.
- 3A, 3B, and 3C show the first state, the second state, and the third state, respectively.
- FIG. 4 shows the polarization state of the ferroelectric film 13 and the state of the semiconductor film 14 when a voltage of ⁇ 10 V and a voltage of 10 V are applied to the second electrode 16 and the third electrode 17.
- the semiconductor 31 located under the electrode 16 to which ⁇ 10 V is applied has a low resistance due to the accumulation of electrons caused by the ferroelectric polarization 30a.
- the semiconductor 32 positioned under the electrode 34 to which 10 V is applied has a high resistance due to retreat of electrons generated by the ferroelectric polarization 30b.
- a reset operation is performed before setting.
- the voltage Vin is applied to the electrodes 15 to 17 and the voltage Vreset that satisfies the relationship Vin ⁇ Vreset is applied to the control electrode 12. More specifically, it is preferable that 10 V is applied to the control electrode 12 while 0 V is applied to the electrodes 15 to 17. Thereby, all the polarizations of the ferroelectric film 13 are set upward.
- V1 is applied to the control electrode 12
- Va is applied to the first electrode
- Vb is applied to the second electrode 16
- Vc is applied to the third electrode 17, respectively.
- the ferroelectric film 13 located under 17 is polarized. This polarization causes each portion of the semiconductor film 14 located under these electrodes 15 to 17 to have a high resistance state or a low resistance state.
- Any one of the first state, the second state, and the third state is set in the nonvolatile switching device 20.
- V1> Va, V1 ⁇ Vb, and V1 ⁇ Vc (specifically, ⁇ 10V Va, + 10V Vb, and + 10V Vc are applied while V1 is held at 0V)
- V1 ⁇ Va, V1> Vb, and V1 ⁇ Vc (specifically, + 10V Va, ⁇ 10V Vb, and + 10V Vc are applied while V1 is held at 0V)
- V1 ⁇ Va, V1 ⁇ Vb, and V1> Vc specifically, + 10V Va, + 10V Vb, and ⁇ 10V Vc are applied while V1 is held at 0V)
- V1 ⁇ Va, V1 ⁇ Vb, and V1 ⁇ Vc (specifically, + 10V Va, + 10V Vb, and + 10V Vc are applied while V1 is held at 0V)
- d In the second state, a current selectively flows between the first electrode 15 and the second electrode 16.
- a current flows selectively between electrode A and electrode B means that a current flows only between electrode A and electrode B, and a current flows between the other electrodes. Means no.
- selective as used herein is interpreted as described above.
- a current selectively flows between the first electrode 15 and the third electrode 17. No current flows between the second electrode 16 and the first electrode 15. No current flows between the second electrode 16 and the third electrode 17. That is, in the third state, the resistance value between the first electrode 15 and the third electrode 17 is low. The resistance value between the second electrode 16 and the other electrodes 15 and 17 is high.
- R 1 Resistance between the first electrode 15 and the second electrode 16
- RH 16 Below the second electrode 16
- R2 resistance between the first electrode 15 and the third electrode 17
- RL 17 part of the semiconductor layer 14 located below the third electrode 17 Low resistance (see FIG. 10).
- inequality (II) is further transformed into the following inequality (III): RH 16 >> RL 17 (III) Since inequality (III) is always satisfied, inequality (I) is always satisfied. In this way, a current selectively flows between the first electrode 15 and the third electrode 17.
- FIG. 5 is a plan view of the nonvolatile switching device 20 according to the second embodiment.
- a fourth electrode 18 is formed on the semiconductor film 14.
- the electrodes 15 to 18 are arranged rotationally symmetrical.
- the electrodes 15 to 18 are congruent in plan view.
- the fourth electrode 18 includes a side L10 having a length of LS, a side L11 having a length of LL, and a side L12 having a length of LS.
- the side L11 is parallel to the side L5.
- the distance between the side L11 and the side L5 is equal to IL.
- the side L10 and the side L12 are parallel to the side L9 and the side L1, respectively.
- the distance between these sides is equal to IS.
- the four electrodes 15-18 can be electrically connected or disconnected independently.
- Table 3 below shows the potentials of the electrodes 15 to 18 when the conduction state between the electrodes 15 to 18 is changed.
- the voltage applied to the control electrode 12 is always constant.
- the constant voltage is 0V.
- the reset operation is preferable.
- V1 is applied to the control electrode 12
- Va is applied to the first electrode
- Vb is applied to the second electrode
- Vc is applied to the third electrode 17
- Vd is applied to the fourth electrode 18.
- Va is applied to polarize each portion of the ferroelectric film 13 located under the electrodes 15-18. This polarization causes the semiconductor film 14 located under these electrodes 15 to 18 to have a high resistance state or a low resistance state.
- Any one of the first to twelfth states is set in the nonvolatile switching device 20.
- the first to fourth states in the second embodiment are the same as those in the first embodiment.
- a current selectively flows between the second electrode 16 and the third electrode 17.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- a current selectively flows between the first electrode 15 and the fourth electrode 18.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- a current selectively flows between the second electrode 16 and the fourth electrode 18.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- a current selectively flows between the first electrode 15, the second electrode 16, and the fourth electrode 18.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- a current selectively flows between the first electrode 15, the third electrode 17, and the fourth electrode 18.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- a current selectively flows between the second electrode 16, the third electrode 17, and the fourth electrode 18.
- voltages V1, Va, Vb, Vc, and Vd that satisfy the following inequality are applied.
- the control electrode 12 was formed on the silicon substrate 11 having a surface covered with a silicon oxide film according to the following procedure.
- a Ti film having a thickness of 5 nm and a Pt film having a thickness of 30 nm were formed in this order on the substrate 11 by electron gun evaporation.
- an SrRuO 3 (hereinafter, SRO) film having a thickness of 10 nm was formed by a pulse laser deposition method.
- the substrate was heated to 700 ° C., and a ferroelectric film 13 made of Pb (Zr, Ti) O 3 having a thickness of 450 nm was formed by a pulse laser deposition method.
- the substrate temperature was set to 400 ° C., and the semiconductor film 14 made of ZnO having a thickness of 30 nm was formed.
- a resist pattern was formed on the semiconductor film 14 by photolithography. Thereafter, the portion of the semiconductor film 14 not covered with the resist pattern was removed by etching using nitric acid.
- a resist was patterned on the semiconductor film 14 by photolithography.
- a Ti film having a thickness of 5 nm and a Pt film having a thickness of 30 nm were formed thereon by an electron gun evaporation method.
- the resist was removed to form electrodes 15 to 18 shown in FIG.
- LS, IS, LL, and IL were 10 ⁇ m, 8 ⁇ m, 63 ⁇ m, and 51 ⁇ m, respectively.
- the first, second, third, and sixth states were set for the obtained nonvolatile switching device based on Table 3.
- FIG. 7 shows the resistance values calculated in the first, second, third, and sixth states. As understood from FIG. 7, in the first state, the resistance value between all the electrodes is high. In the second state, the resistance value between the first electrode 15 and the second electrode 16 is low. In the third state, the resistance value between the first electrode 15 and the third electrode 17 is low. In the sixth state, the resistance value between the first electrode 15 and the fourth electrode 18 is low.
- control electrode 12 made of a laminated film of SRO / Pt / Ti and the electrodes 15 to 18 made of a laminated film of Pt / Ti were used.
- Conductive films made of other materials can also be used.
- ferroelectric film 13 As Sr (Bi, Ta) material of the ferroelectric film 13 other ferroelectric materials such as O x or BiTiO x may be used. Other semiconductor materials such as GaN or InGaZnO x can be used as the material of the semiconductor film 14.
- the present invention provides a method of selectively flowing current using a nonvolatile switching device that operates accurately.
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Abstract
Description
ここで、記号「>>」は、左側の値が右側の値よりも十分に大きいという意味である。すなわち、「値A>>値B」は、値Aが値Bよりも十分に大きいという意味である。
前記不揮発スイッチング装置を準備する工程(a)、および
ここで、前記不揮発スイッチング装置は、制御電極、強誘電体膜、半導体膜、および電極群を備え、
前記制御電極、前記強誘電体膜、前記半導体膜、および前記電極群がこの順に積層されており、
前記電極群は、第1の電極、第2の電極、および第3の電極を具備しており、
前記第1の電極は、LLの長さを有する辺L2およびLSの長さを有する辺L3を具備しており、
前記第2の電極は、LSの長さを有する辺L4およびLSの長さを有するL6を具備しており、
前記第3の電極は、LSの長さを有する辺L7およびLLの長さを有する辺L8を具備しており、
前記辺L2、前記辺L3、および前記辺L6は、それぞれ、前記辺L8、前記辺L4、および前記辺L7に平行であり、
以下の等式(A)が充足され、
IL/LL=IS/LS ・・・ (A)
ここで、ILは、前記辺L2と前記辺L8との間の間隔であり、
ISは前記辺L3と前記辺L4との間の間隔であり、
前記辺L6および前記辺L7との間の間隔は前記ISに等しく、
前記不揮発スイッチング装置に第1の状態、第2の状態、および第3の状態のいずれかを設定する工程(b)、
ここで、前記第1の状態では、前記電極群の間で電流が流れず、
前記第2の状態では、前記第1の電極と前記第2の電極との間に選択的に電流が流れ、
前記第3の状態では、前記第1の電極と前記第3の電極との間に選択的に電流が流れ、
前記制御電極、前記第1の電極、前記第2の電極、および前記第3の電極には、それぞれ、電圧V1、Va、Vb、およびVcが印加され、
前記第1の状態が設定される場合には、以下の不等式(a)~(d)のいずれかを充足する電圧が印加され、
V1>Va、V1<Vb、かつV1<Vc・・・(a)
V1<Va、V1>Vb、かつV1<Vc・・・(b)
V1<Va、V1<Vb、かつV1>Vc・・・(c)、または
V1<Va、V1<Vb、かつV1<Vc・・・(d)
前記第2の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1>Vb、かつV1<Vc
前記第3の状態が設定される場合には、以下の不等式を充足する電圧が印加される
V1>Va、V1<Vb、かつV1>Vc。
前記第1の電極、前記第2の電極、および前記第3の電極に電圧Vinを印加し、同時に前記制御電極に電圧Vresetを印加する工程(c)
ここで、Vin<Vresetである。
前記第4の状態では、前記第1の電極、前記第2の電極、および前記第3の電極の間で電流が流れ、
前記第4の状態が設定される場合には、以下の不等式を充足する電圧が印加される:
V1>Va、V1>Vb、V1>Vc。
前記第4の電極は、前記LSの長さを有する辺L10、前記LLの長さを有する辺L11、および前記LSの長さを有する辺L12を具備しており、
前記第1の電極は、前記LSの長さを有する辺L1をさらに具備しており、
前記第2の電極は、前記LLの長さを有する辺L5をさらに具備しており、
前記第3の電極は、前記LSの長さを有する辺L9をさらに具備しており、
前記辺L1、前記辺L5、および前記辺L9は、それぞれ、前記辺L12、前記辺L11、および前記辺L10に平行であり、
前記辺L5と前記辺L11との間の間隔は前記ILに等しく、
前記辺L1と前記辺L12との間の間隔および前記辺L9および前記辺L10との間の間隔はいずれも前記ISに等しい。
電圧Vdが前記第4の電極に印加され、
前記第4の状態では、前記第1の電極、前記第2の電極、および前記第3の電極の間で電流が流れ、
ここで、前記第4の電極には、電圧Vdが印加され、
前記第4の状態が設定される場合には、以下の不等式を充足する電圧が印加される:
V1>Va、V1>Vb、V1>Vc、およびV1<Vd
前記第5の状態では、前記第2の電極と前記第3の電極との間に選択的に電流が流れ、
前記第5の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1>Vc、およびV1<Vd
前記第6の状態では、前記第1の電極と前記第4の電極との間に選択的に電流が流れ、
前記第6の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1<Vb、V1<Vc、およびV1>Vd
前記第7の状態では、前記第2の電極と前記第4の電極との間に選択的に電流が流れ、
前記第7の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1<Vc、およびV1>Vd
前記第8の状態では、前記第3の電極と第4の電極との間に選択的に電流が流れ、
前記第8の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1<Vb、V1>Vc、およびV1>Vd
前記第9の状態では、前記第1の電極、前記第2の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第9の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1>Vb、V1<Vc、およびV1>Vd
前記第10の状態では、前記第1の電極、前記第3の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第10の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1<Vb、V1>Vc、およびV1>Vd
前記第11の状態では、前記第2の電極、前記第3の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第11の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1>Vc、およびV1>Vd
前記第12の状態では、前記第1の電極、前記第2の電極、前記第3の電極、および前記第4の電極の間に電流が流れ、
前記第12の状態が設定される場合には、以下の不等式を充足する電圧が印加される
V1>Va、V1>Vb、V1>Vc、およびV1>Vd。
図1は、実施の形態1による不揮発スイッチング装置20の平面図を示す。図2は図1におけるA-A’線断面図を示す。
IL/LL=IS/LS ・・・ (A)
当該等式(A)が充足されるので、実施の形態1に係る不揮発スイッチング装置は、正確に動作する。この理由は、後に詳細に説明される。
次に、図3、図4、および図5を参照しながら、不揮発スイッチング装置20における導通区間の設定手順が説明される。
V1<Va、V1>Vb、およびV1<Vc(具体的には、V1が0Vに保持されながら、+10VのVa、-10VのVb、そして+10VのVcが印加される)・・・(b)
V1<Va、V1<Vb、およびV1>Vc(具体的には、V1が0Vに保持されながら、+10VのVa、+10VのVb、そして-10VのVcが印加される)・・・(c)、または
V1<Va、V1<Vb、およびV1<Vc(具体的には、V1が0Vに保持されながら、+10VのVa、+10VのVb、そして+10VのVcが印加される)・・・(d)
第2の状態では、第1の電極15と第2の電極16との間に選択的に電流が流れる。第3の電極17と第1の電極15との間には電流が流れない。第3の電極17と第2の電極16との間にも電流が流れない。すなわち、第2の状態では、第1の電極15と第2の電極16との間の抵抗値が低い。第3の電極17と他の電極15、16との間の抵抗値は高い。
具体的には、V1が0Vに保持されながら、-10VのVa、-10VのVb、そして+10VのVcが印加される。
具体的には、V1が0Vに保持されながら、-10VのVa、+10VのVb、そして-10VのVcが印加される。
ここで、
RL15:第1の電極15の下に位置する部分の半導体層14が有する低い抵抗
R1:第1の電極15と第2の電極16との間の抵抗
RH16:第2の電極16の下に位置する部分の半導体層14が有する高い抵抗
R2:第1の電極15と第3の電極17との間の抵抗
RL17:第3の電極17の下に位置する部分の半導体層14が有する低い抵抗
(図10を参照)。
R1+RH16>>R2+RL17 ・・・ (II)
本実施の形態では、等式(A) IL/LL=IS/LSが充足される。抵抗は、長さ(ILおよびIS)に比例し、断面積(LLおよびLS)に反比例するので、R2はR1に等しい。
RH16>>RL17・・・(III)
不等式(III)は常に充足されるので、不等式(I)も常に充足される。このようにして、第1の電極15と第3の電極17との間に選択的に電流が流れる。
具体的には、V1が0Vに保持されながら、-10VのVa、-10VのVb、そして-10VのVcが印加される。
図5は、実施の形態2による不揮発スイッチング装置20の平面図を示す。
IL/LL=IS/LS ・・・ (A)
そのため、実施の形態1において説明した理由と同様に、図6に示されるように、電極15~18の間に選択的に電流が流れ得る。
次に、実施の形態2による不揮発スイッチング装置20における導通区間の設定手順が説明される。
具体的には、V1が0Vに保持されながら、+10VのVa、-10VのVb、-10VのVc、そして+10VのVdが印加される。
具体的には、V1が0Vに保持されながら、-10VのVa、+10VのVb、+10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、+10VのVa、-10VのVb、+10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、+10VのVa、+10VのVb、-10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、-10VのVa、-10VのVb、+10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、-10VのVa、+10VのVb、-10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、+10VのVa、-10VのVb、-10VのVc、そして-10VのVdが印加される。
具体的には、V1が0Vに保持されながら、-10VのVa、-10VのVb、-10VのVc、そして-10VのVdが印加される。
以下、実施例を参照しながら本発明をより詳細に説明する。
12 制御電極
13 強誘電体膜
14 半導体膜
15 第1の電極
16 第2の電極
17 第3の電極
18 第4の電極
20 不揮発スイッチング装置
30a 強誘電体の上向き分極
30b 強誘電体の下向き分極
31 半導体膜のうち低抵抗部分
32 半導体膜のうち高抵抗部分
Claims (7)
- 不揮発スイッチング装置を用いて、選択的に電流を流す方法であって、以下の工程を具備する:
前記不揮発スイッチング装置を準備する工程(a)、および
ここで、前記不揮発スイッチング装置は、制御電極、強誘電体膜、半導体膜、および電極群を備え、
前記制御電極、前記強誘電体膜、前記半導体膜、および前記電極群がこの順に積層されており、
前記電極群は、第1の電極、第2の電極、および第3の電極を具備しており、
前記第1の電極は、LLの長さを有する辺L2およびLSの長さを有する辺L3を具備しており、
前記第2の電極は、LSの長さを有する辺L4およびLSの長さを有するL6を具備しており、
前記第3の電極は、LSの長さを有する辺L7およびLLの長さを有する辺L8を具備しており、
前記辺L2、前記辺L3、および前記辺L6は、それぞれ、前記辺L8、前記辺L4、および前記辺L7に平行であり、
以下の等式(A)が充足され、
IL/LL=IS/LS ・・・ (A)
ここで、ILは、前記辺L2と前記辺L8との間の間隔であり、
ISは前記辺L3と前記辺L4との間の間隔であり、
前記辺L6および前記辺L7との間の間隔は前記ISに等しく、
前記不揮発スイッチング装置に第1の状態、第2の状態、および第3の状態のいずれかを設定する工程(b)、
ここで、前記第1の状態では、前記電極群の間で電流が流れず、
前記第2の状態では、前記第1の電極と前記第2の電極との間に選択的に電流が流れ、
前記第3の状態では、前記第1の電極と前記第3の電極との間に選択的に電流が流れ、
前記制御電極、前記第1の電極、前記第2の電極、および前記第3の電極には、それぞれ、電圧V1、Va、Vb、およびVcが印加され、
前記第1の状態が設定される場合には、以下の不等式(a)~(d)のいずれかを充足する電圧が印加され、
V1>Va、V1<Vb、かつV1<Vc・・・(a)
V1<Va、V1>Vb、かつV1<Vc・・・(b)
V1<Va、V1<Vb、かつV1>Vc・・・(c)、または
V1<Va、V1<Vb、かつV1<Vc・・・(d)
前記第2の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1>Vb、かつV1<Vc
前記第3の状態が設定される場合には、以下の不等式を充足する電圧が印加される
V1>Va、V1<Vb、かつV1>Vc。 - 請求項1に記載の方法であって、
平面視において、前記第1の電極、前記第2の電極、および前記第3の電極は合同である。 - 請求項1に記載の方法であって、
前記工程(a)と前記工程(b)との間に、以下の工程(c)をさらに具備する:
前記第1の電極、前記第2の電極、および前記第3の電極に電圧Vinを印加し、同時に前記制御電極に電圧Vresetを印加する工程(c)
ここで、Vin<Vresetである。 - 請求項1に記載の方法であって、
工程(b)においては、前記第1の状態、前記第2の状態、前記第3の状態、および第4の状態のいずれかが設定される:
前記第4の状態では、前記第1の電極、前記第2の電極、および前記第3の電極の間で電流が流れ、
前記第4の状態が設定される場合には、以下の不等式を充足する電圧が印加される:
V1>Va、V1>Vb、V1>Vc。 - 請求項3に記載の方法であって、
前記不揮発スイッチング装置が、さらに第4の電極を具備し、ここで
前記第4の電極は、前記LSの長さを有する辺L10、前記LLの長さを有する辺L11、および前記LSの長さを有する辺L12を具備しており、
前記第1の電極は、前記LSの長さを有する辺L1をさらに具備しており、
前記第2の電極は、前記LLの長さを有する辺L5をさらに具備しており、
前記第3の電極は、前記LSの長さを有する辺L9をさらに具備しており、
前記辺L1、前記辺L5、および前記辺L9は、それぞれ、前記辺L12、前記辺L11、および前記辺L10に平行であり、
前記辺L5と前記辺L11との間の間隔は前記ILに等しく、
前記辺L1と前記辺L12との間の間隔および前記辺L9および前記辺L10との間の間隔はいずれも前記ISに等しい。 - 平面視において、前記第1の電極、前記第2の電極、前記第3の電極、および前記第4の電極は合同である、請求項5に記載の方法。
- 請求項5に記載の方法であって、
工程(b)においては、前記第1の状態、前記第2の状態、前記第3の状態、第4の状態~第12の状態のいずれかが設定され、ここで
電圧Vdが前記第4の電極に印加され、
前記第4の状態では、前記第1の電極、前記第2の電極、および前記第3の電極の間で電流が流れ、
ここで、前記第4の電極には、電圧Vdが印加され、
前記第4の状態が設定される場合には、以下の不等式を充足する電圧が印加される:
V1>Va、V1>Vb、V1>Vc、およびV1<Vd
前記第5の状態では、前記第2の電極と前記第3の電極との間に選択的に電流が流れ、
前記第5の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1>Vc、およびV1<Vd
前記第6の状態では、前記第1の電極と前記第4の電極との間に選択的に電流が流れ、
前記第6の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1<Vb、V1<Vc、およびV1>Vd
前記第7の状態では、前記第2の電極と前記第4の電極との間に選択的に電流が流れ、
前記第7の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1<Vc、およびV1>Vd
前記第8の状態では、前記第3の電極と第4の電極との間に選択的に電流が流れ、
前記第8の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1<Vb、V1>Vc、およびV1>Vd
前記第9の状態では、前記第1の電極、前記第2の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第9の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1>Vb、V1<Vc、およびV1>Vd
前記第10の状態では、前記第1の電極、前記第3の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第10の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1>Va、V1<Vb、V1>Vc、およびV1>Vd
前記第11の状態では、前記第2の電極、前記第3の電極、および前記第4の電極の間に選択的に電流が流れ、
前記第11の状態が設定される場合には、以下の不等式を充足する電圧が印加され、
V1<Va、V1>Vb、V1>Vc、およびV1>Vd
前記第12の状態では、前記第1の電極、前記第2の電極、前記第3の電極、および前記第4の電極の間に電流が流れ、
前記第12の状態が設定される場合には、以下の不等式を充足する電圧が印加される
V1>Va、V1>Vb、V1>Vc、およびV1>Vd。
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WO2013111200A1 (ja) * | 2012-01-23 | 2013-08-01 | パナソニック株式会社 | ニューラルネットワーク回路の学習方法 |
JP5659361B1 (ja) | 2013-07-04 | 2015-01-28 | パナソニックIpマネジメント株式会社 | ニューラルネットワーク回路、およびその学習方法 |
JP6087030B2 (ja) * | 2015-01-22 | 2017-03-01 | オリンパス株式会社 | 内視鏡システム |
TWI620920B (zh) * | 2015-09-23 | 2018-04-11 | 中原大學 | 多軸向壓電應力感測元件、多軸向壓電應力感測元件極化之方法及其壓電感應偵測系統 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009099606A (ja) * | 2007-10-12 | 2009-05-07 | Panasonic Corp | 半導体記憶装置及びその製造方法並びに半導体スイッチング装置 |
Family Cites Families (4)
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DE102005017533A1 (de) * | 2004-12-29 | 2006-07-13 | Hynix Semiconductor Inc., Ichon | Nichtflüchtige ferroelektrische Speichervorrichtung |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
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WO2013118449A1 (ja) * | 2012-02-07 | 2013-08-15 | パナソニック株式会社 | 不揮発性半導体装置を駆動する方法 |
CN103460375A (zh) * | 2012-02-07 | 2013-12-18 | 松下电器产业株式会社 | 驱动非易失性半导体装置的方法 |
JP5406415B1 (ja) * | 2012-02-07 | 2014-02-05 | パナソニック株式会社 | 不揮発性半導体装置を駆動する方法 |
US8830723B2 (en) | 2012-02-07 | 2014-09-09 | Panasonic Corporation | Method of driving nonvolatile semiconductor device |
CN103460375B (zh) * | 2012-02-07 | 2016-11-02 | 松下知识产权经营株式会社 | 驱动非易失性半导体装置的方法 |
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CN102742161A (zh) | 2012-10-17 |
JP4852670B1 (ja) | 2012-01-11 |
CN102742161B (zh) | 2015-05-20 |
US20120008365A1 (en) | 2012-01-12 |
US8565001B2 (en) | 2013-10-22 |
JPWO2011148551A1 (ja) | 2013-07-25 |
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