WO2011146453A3 - Circuits de liaison de support physique hétérogène destiné à des dispositifs à circuits intégrés - Google Patents

Circuits de liaison de support physique hétérogène destiné à des dispositifs à circuits intégrés Download PDF

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Publication number
WO2011146453A3
WO2011146453A3 PCT/US2011/036773 US2011036773W WO2011146453A3 WO 2011146453 A3 WO2011146453 A3 WO 2011146453A3 US 2011036773 W US2011036773 W US 2011036773W WO 2011146453 A3 WO2011146453 A3 WO 2011146453A3
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WO
WIPO (PCT)
Prior art keywords
speed
circuitry
integrated circuit
physical media
low
Prior art date
Application number
PCT/US2011/036773
Other languages
English (en)
Other versions
WO2011146453A2 (fr
Inventor
Sergey Shumarayev
Edwin Yew Fatt Kok
Lip Kai Soh
Chee Hong Aw
Tee Wee Tan
Original Assignee
Altera Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Altera Corporation filed Critical Altera Corporation
Priority to JP2013511282A priority Critical patent/JP5779241B2/ja
Priority to EP11784073.6A priority patent/EP2572453B1/fr
Priority to CN201180025141.3A priority patent/CN103039004B/zh
Publication of WO2011146453A2 publication Critical patent/WO2011146453A2/fr
Publication of WO2011146453A3 publication Critical patent/WO2011146453A3/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/1774—Structural details of routing resources for global signals, e.g. clock, reset
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources
    • H03K19/17744—Structural details of routing resources for input/output signals
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

Un circuit intégré comprend des circuits de liaison de support physique (« PMA ») qui comprennent deux types différents de canaux émetteurs/récepteurs pour signaux de données série. Un type de canal émetteur/récepteur est adapté pour émettre/recevoir des signaux de données série à vitesse relativement faible. L'autre type de canal émetteur/récepteur est adapté pour émettre/recevoir des signaux de données série à vitesse relativement élevée. Un canal à grande vitesse peut en variante être utilisé comme circuit à boucle en verrouillage de phase (« PLL ») afin de fournir un signal d'horloge destiné à être utilisé par d'autres canaux à vitesse élevée et/ou faible. Un canal à faible vitesse peut en variante obtenir un signal d'horloge de la part de circuits PLL à faible vitesse distincts.
PCT/US2011/036773 2010-05-21 2011-05-17 Circuits de liaison de support physique hétérogène destiné à des dispositifs à circuits intégrés WO2011146453A2 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013511282A JP5779241B2 (ja) 2010-05-21 2011-05-17 集積回路デバイスのための異種物理媒体アタッチメント回路
EP11784073.6A EP2572453B1 (fr) 2010-05-21 2011-05-17 Circuit intégré ayant un circuit de liaison de support physique hétérogène
CN201180025141.3A CN103039004B (zh) 2010-05-21 2011-05-17 用于集成电路设备的异构物理介质附件电路系统

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US12/785,047 US8397096B2 (en) 2010-05-21 2010-05-21 Heterogeneous physical media attachment circuitry for integrated circuit devices
US12/785,047 2010-05-21

Publications (2)

Publication Number Publication Date
WO2011146453A2 WO2011146453A2 (fr) 2011-11-24
WO2011146453A3 true WO2011146453A3 (fr) 2012-01-12

Family

ID=44972003

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US2011/036773 WO2011146453A2 (fr) 2010-05-21 2011-05-17 Circuits de liaison de support physique hétérogène destiné à des dispositifs à circuits intégrés

Country Status (5)

Country Link
US (1) US8397096B2 (fr)
EP (1) EP2572453B1 (fr)
JP (1) JP5779241B2 (fr)
CN (1) CN103039004B (fr)
WO (1) WO2011146453A2 (fr)

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KR20110134197A (ko) * 2010-06-08 2011-12-14 삼성전자주식회사 전압제어지연라인, 상기 전압제어지연라인을 구비하는 지연고정루프회로 및 다중위상클럭생성기
KR101727719B1 (ko) * 2010-10-11 2017-04-18 삼성전자주식회사 위상 보간기 및 그를 포함하는 반도체 장치 및 위상 보간 방법
US8464088B1 (en) * 2010-10-29 2013-06-11 Altera Corporation Multiple channel bonding in a high speed clock network
US8700825B1 (en) * 2012-11-16 2014-04-15 Altera Corporation Heterogeneous high-speed serial interface system with phase-locked loop architecture and clock distribution system
US8958513B1 (en) * 2013-03-15 2015-02-17 Xilinx, Inc. Clock and data recovery with infinite pull-in range
US9148192B1 (en) * 2013-08-08 2015-09-29 Xilinx, Inc. Transceiver for providing a clock signal
US10298348B2 (en) * 2016-04-01 2019-05-21 Ipg Photonics Corporation Transparent clocking in a cross connect system
CN114629493A (zh) * 2017-07-19 2022-06-14 円星科技股份有限公司 用于多线接口的实体层电路
CN112311458B (zh) * 2019-08-02 2022-03-08 杭州海康威视数字技术股份有限公司 信号的传输方法、装置、设备以及系统
CN114362770B (zh) * 2022-01-10 2023-07-11 中国船舶集团有限公司第七一一研究所 数据发送器件、数据接收器件、电子装置以及方法

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US20050286669A1 (en) * 2004-06-28 2005-12-29 Broadcom Corporation Phase interpolator based transmission clock control
US7158587B2 (en) * 2001-09-18 2007-01-02 Agere Systems Inc. Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
US7493095B2 (en) * 2003-09-11 2009-02-17 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
US20090052600A1 (en) * 2007-08-20 2009-02-26 Trendchip Technologies Corp. Clock and data recovery circuits
US20090146852A1 (en) * 2007-12-05 2009-06-11 Broadcom Corporation Multi-speed burst mode serializer/de-serializer

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US7227918B2 (en) * 2000-03-14 2007-06-05 Altera Corporation Clock data recovery circuitry associated with programmable logic device circuitry
US7315596B2 (en) * 2004-02-17 2008-01-01 Texas Instruments Incorporated Interpolator based clock and data recovery (CDR) circuit with digitally programmable BW and tracking capability
US7254797B2 (en) * 2004-09-30 2007-08-07 Rambus Inc. Input/output cells with localized clock routing
US7698482B2 (en) * 2005-07-08 2010-04-13 Altera Corporation Multiple data rates in integrated circuit device serial interface
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Publication number Priority date Publication date Assignee Title
US7158587B2 (en) * 2001-09-18 2007-01-02 Agere Systems Inc. Multi-channel serdes receiver for chip-to-chip and backplane interconnects and method of operation thereof
US7493095B2 (en) * 2003-09-11 2009-02-17 Xilinx, Inc. PMA RX in coarse loop for high speed sampling
US20050286669A1 (en) * 2004-06-28 2005-12-29 Broadcom Corporation Phase interpolator based transmission clock control
US20090052600A1 (en) * 2007-08-20 2009-02-26 Trendchip Technologies Corp. Clock and data recovery circuits
US20090146852A1 (en) * 2007-12-05 2009-06-11 Broadcom Corporation Multi-speed burst mode serializer/de-serializer

Also Published As

Publication number Publication date
WO2011146453A2 (fr) 2011-11-24
EP2572453B1 (fr) 2018-08-15
CN103039004B (zh) 2016-12-21
US8397096B2 (en) 2013-03-12
US20110285434A1 (en) 2011-11-24
JP2013531418A (ja) 2013-08-01
JP5779241B2 (ja) 2015-09-16
EP2572453A2 (fr) 2013-03-27
EP2572453A4 (fr) 2016-03-02
CN103039004A (zh) 2013-04-10

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