WO2011144459A1 - Capteur d'image matriciel a transfert de charges a grille dissymetrique - Google Patents
Capteur d'image matriciel a transfert de charges a grille dissymetrique Download PDFInfo
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- WO2011144459A1 WO2011144459A1 PCT/EP2011/057243 EP2011057243W WO2011144459A1 WO 2011144459 A1 WO2011144459 A1 WO 2011144459A1 EP 2011057243 W EP2011057243 W EP 2011057243W WO 2011144459 A1 WO2011144459 A1 WO 2011144459A1
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- fingers
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- photodiode
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- 239000011159 matrix material Substances 0.000 title description 15
- 238000003860 storage Methods 0.000 claims abstract description 32
- 230000010354 integration Effects 0.000 claims abstract description 26
- 238000011144 upstream manufacturing Methods 0.000 claims abstract description 25
- 238000002955 isolation Methods 0.000 claims abstract description 13
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- 238000005286 illumination Methods 0.000 claims description 5
- 230000002596 correlated effect Effects 0.000 claims description 2
- 230000009977 dual effect Effects 0.000 claims description 2
- 238000005070 sampling Methods 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 description 14
- 238000005036 potential barrier Methods 0.000 description 12
- 239000000758 substrate Substances 0.000 description 10
- 230000004888 barrier function Effects 0.000 description 4
- 230000000875 corresponding effect Effects 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 230000035945 sensitivity Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 210000004457 myocytus nodalis Anatomy 0.000 description 2
- 238000012935 Averaging Methods 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000009607 mammography Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14806—Structural or functional details thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/148—Charge coupled imagers
- H01L27/14831—Area CCD imagers
- H01L27/14856—Time-delay and integration
Definitions
- the invention relates to image sensors, in particular but not exclusively to signal-scrolling and integration sensors (or TDI sensors, in English: “Time Delay Integration” Linear Sensors "), in which an image of a line of points of an observed scene is reconstructed by adding successive images taken by several photosensitive lines successively observing the same line of the scene as the scene passes in front of the sensor perpendicular to the lines.
- signal-scrolling and integration sensors or TDI sensors, in English: “Time Delay Integration” Linear Sensors "
- These sensors are used, for example, in satellite earth observation systems. They include several parallel lines of photosensitive pixels; the sequencing of the control circuits of the different lines (control of exposure time and then reading of the photogenerated charges) is synchronized with respect to the relative scrolling of the scene and the sensor, so that all the lines of the sensor see a single line of the observed scene. The generated signals are then added point by point for each point of the observed line.
- the theoretical signal-to-noise ratio is improved in the ratio of the square root of the number N of lines of the sensor. This number can range from a few lines to a hundred depending on the applications (industrial control, earth observation, panoramic dental X-ray or mammography).
- the non-uniformities of sensitivity of the pixels of the same strip, and the non-uniformities of the darkness current of the pixels, are decreased as a result of the averaging which results from the addition of the signals of the different lines.
- CCD sensors charge-coupled image sensors
- the addition of the point-by-point signals was natural and without reading noise by emptying in a row of pixels the charges generated and accumulated in the previous pixel line, in synchronism with the relative displacement of the scene and the sensor.
- the last line of pixels, having accumulated N times the charges generated by the observed image line, can be read.
- the usual CCD image sensor technology uses high supply voltages and consumes a lot of energy; this technology is based on the use of adjacent polycrystalline silicon grids and in mutual recovery.
- CMOS sensors active pixel sensors with transistors
- CMOS complementary-metal-oxide-semiconductor
- active pixels with transistors which collect photogenerated electric charges and convert them directly into a voltage or a current.
- the different lines of the sensor therefore successively supply voltages or currents representing the illumination received by the line.
- These structures do not allow noise-free summation of these currents or voltages; it is therefore difficult to produce a sensor with scrolling and load integration.
- the manufacturing technology is however simple, it consumes little, and it operates under low voltage.
- the aim of the invention is to propose a simple solution for producing sensors operating according to the principle of charge transfer structures, using only two control phases, and using a technology compatible with CMOS technology circuits, in particular a technology that using only one level of polycrystalline silicon grid for storage or charge transfer grids and not a double level of overlapping grids as is the case in conventional CCD technologies.
- a charge transfer image sensor comprising N adjacent lines of P pixels, the adjacent pixels of the same rank belonging to two consecutive lines each comprising an alternation of at least one photodiode and a storage grid adjacent to the photodiode, the grids covering a region of active layer of a first conductivity type (in practice p) and the photodiodes being formed in the active layer by an individual region of a second conductivity type (n) itself covered by an individual surface region of the first type ( p) connected to a reference potential of the active layer, characterized in that the grids comprise a main body and, on the upstream side in the direction of charge transfer but not on the downstream side, a series of narrow fingers (20) starting the main body extending to the upstream side, the ends of the fingers of the upstream side being adjacent to a photodiode located upstream of the gate, the narrow fingers being separated from each other by doped isolation regions of the first conductivity type , more doped (and preferably deeper) than the superficial
- the fingers are sufficiently narrow that the potential of the active layer under these fingers is influenced by the presence of the insulating regions doped on either side of the fingers, so that the potential under the fingers is locally lower than under the main body of the grid despite the fact that the fingers are brought to the same potential as the main body of the grid.
- lower potential By lower potential is meant that a potential barrier is created in the active layer under the fingers relative to the potential under the main body.
- This notion of potential barrier created by a lower potential refers to the fact that the stored charges are electrons.
- the active layer is of type p, that the photogenerated and stored charges under the gate are electrons and not holes, and therefore that a lower potential is a potential barrier for electrons compared to a higher potential.
- the senor is made with a p-type active layer, that the photodiodes store electrons in n-type individual regions, and that the regions superficial and the doped regions separating the narrow fingers are of type p.
- the charges stored under the grid of a pixel can not flow to the photodiode upstream, or between the fingers of this grid because of the presence of isolation regions, neither under these fingers because of the potential induced under the fingers by these regions; they can only flow to a photodiode downstream of the storage grid, by the side of the grid which has no fingers; on this side, the gate is directly adjacent to the surface region p of the downstream photodiode. Conversely, the gate can receive charges from the photodiode immediately upstream, through the fingers whose ends are directly adjacent to the photodiode (provided that the potential barrier indicated above is not excessively high).
- the fingers are completely separated from each other from the main body of the grid.
- the ends of the fingers of the upstream side are connected to each other by sections of a narrow band of grid serving as an alignment mask for the implantation of the doped regions which constitute the photodiodes (and regions d insulation that separate the fingers).
- a narrow band of grid serving as an alignment mask for the implantation of the doped regions which constitute the photodiodes (and regions d insulation that separate the fingers).
- the isolation regions are preferably regions implanted at the same time as the source and drain regions of the transistors that can be formed on the same integrated circuit as the pixel matrix itself; they therefore have the same concentration of impurities and the same depth of implantation as these source and drain regions. The manufacturing process is simplified.
- the image sensor is preferably a multi-linear scroll sensor and load integration but it can also be a matrix sensor providing an image of NxP points. In the latter case, the charges of the NxP pixels must be extracted rapidly after each integration period and preferably the illumination of the sensor during this transfer is interrupted.
- FIG. 1 represents the general structure of a charge transfer matrix image sensor
- FIG. 2 represents a structure of adjacent pixels in columns formed by an alternation of storage gates and photodiodes
- FIG. 3 represents a view from above of a pixel according to the invention
- FIG. 6 represents a diagram of the potentials in the epitaxial layer of the substrate below a pixel according to the invention.
- FIG. 7 represents a view from above of an alternative embodiment of the grids of the pixel
- FIG. 8 shows a particular configuration of the fingers.
- the sensor comprises a matrix MT of N lines of P pixels sensitive to light.
- the charges resulting from the illumination of a pixel Pjj of rank i in line and in column are integrated in the pixel during an integration period T; then they are transferred in the pixel of the next line of rank i + 1 in line and of same rank j in column; the adjacent pixels in the direction of the columns (vertical direction in the figure) are arranged in a vertical shift register with charge transfer.
- the sensor may be a matrix sensor providing successive images of NxP image points or a multilinear sensor providing linear images of P points viewed and accumulated by the N rows of pixels.
- each pixel behave like vertical shift registers, but it is only in the second case that each pixel accumulates on the one hand from a previous pixel and secondly the photogenerated charges during a T integration period.
- the senor is a matrix sensor intended to provide images of NxP pixels generated during an integration T
- the charges of the NxP pixels are transferred after the duration T; the transfer is from pixel to pixel in N steps to a horizontal read register RL or to a temporary storage array not shown, or to charge / voltage conversion circuits each assigned to a column of pixels; the read register RL may be a P-cell horizontal load transfer register. For each new line, the read register RL directs the charges of P cells to a read circuit CL which converts them into voltage.
- the charges contained in the NxP pixels are not read after each integration period T, but the charges read by the N pixels of a column are accumulated during N durations. successive integration, in synchronism with the scrolling of the image in front of the sensor.
- Each of the N rows of pixels successively sees the same image line during the scrolling of the image relative to the sensor; the charges integrated in a line of rank i, which correspond to an observed image line, are added in the pixels of this line to the charges previously read by the i-1 preceding lines which have seen the same image line during the previous integration times.
- the last row of pixels contains the sum of the charges collected by all lines that have seen the same image line. This line is read at the end of each duration T by the register RL and the read circuit CL.
- FIG. 2 represents a general structure of the pixels of the same column of the matrix in a configuration in which the pixels consist of simple alternations of grids and photodiodes. This structure is a structure of principle from which the invention will then be more fully explained.
- the pixels are formed in a semiconductor substrate 10 whose upper part is a low doped epitaxial semiconductor active layer 12.
- the substrate is p ++ strongly doped, and the epitaxial active layer is p-type. If the epitaxial layer was of type n, it would be necessary to invert all types of conductivity, as well as the signs of potentials applied to photodiodes and grids.
- the substrate is in principle of the same type of conductivity as the epitaxial layer, but it could also be of the opposite type.
- the columns comprise a regular alternation of photodiodes and charge storage grids. It can be conventionally considered that a group of a photodiode and an adjacent storage grid constitute either a half-pixel or an entire pixel.
- a pixel comprises two photodiodes and two storage grids and all the pixels of the matrix are controlled with identical phases from one pixel to another; in the second convention, a pixel comprises a single photodiode and a single storage grid, but two adjacent pixels of the same column are systematically controlled in phase opposition.
- a photodiode and an adjacent grid constitute a half-pixel, all the pixels of the sensor receiving the same control signals. Two adjacent pixels Py and P i + j are represented.
- Each pixel therefore comprises two photodiodes PH1, PH2 and two charge storage gates G1, G2 alternated with the photodiodes.
- the photodiodes and grids are assigned indices i and i + 1 in FIG. 2 for the pixels P i; j and P i + 1 j, respectively.
- the grids are polycrystalline silicon grids, isolated from the epitaxial layer 12 by a thin insulating layer 13 (oxide or silicon nitride).
- the photodiodes are made by a stack comprising: the p-type epitaxial layer 12 (common active layer for all the photodiodes of all the pixels), an n-type individual region 14 diffused in the epitaxial layer between two transfer gates, and a p-type individual surface region 16, more doped than the epitaxial layer, covering the individual region 14.
- the electrons generated by the illumination may accumulate in potential wells formed at the junction between the n region and the epitaxial layer. .
- the second photodiode PH2j j of the pixel P jj is immediately followed (in the direction of charge transfer from the left to the right) of the first storage gate G1 i + -ij of the following pixel P i + ij, as is the first gate transfer G1, pixel Py is immediately preceded by the second photodiode of the previous pixel PM.
- the invention proposes that the pixels have a particular configuration which ensures a directivity of the transfer without having to act on the potential of the p-type surface regions 16 during the transfer, and without providing additional electrodes and additional control phases in the pixels.
- FIG. 3 top view of a pixel Py
- FIG. 4 sectional view along line IV-IV of FIG. 3
- FIG. 5 sectional view along line VV of FIG. Figure 3
- the pixel further comprises an alternation of storage gates and photodiodes under the same conditions as those of FIG. 2.
- the grids of the pixels according to the invention are asymmetrical; their side facing downstream in the direction of charge transfer is different from the upstream side.
- the upstream is located on the left, the downstream on the right in Figure 3.
- each grid G1, G2 has a series of narrow fingers extending upstream from a rectangular main surface or main body of the grid.
- the grids do not have narrow fingers.
- the photodiodes are defined by the N-type doped region 14 covered by a p-type surface area 16 brought to the potential of the active layer 12 (and the substrate 10); they are adjacent to the gate located downstream of the photodiode at the end of the fingers 20 of this gate; but they are not adjacent to the main surface of the grid; apart from the end of the narrow fingers, the photodiodes are not adjacent to the gate and they are separated by p + doped insulating regions 18, more doped than the surface regions 16 which cover the photodiodes. If the surface regions 16 are very shallow as desired to improve sensitivity in the blue, then the regions 18 are preferably deeper than the regions 16.
- the photodiodes are adjacent to the main surface of the gate.
- This arrangement of a grid with respect to a photodiode applies for an adjacent grid and photodiode belonging to the same pixel as well as for an adjacent grid and photodiode belonging to two neighboring pixels.
- the doped isolation regions 18 come in close proximity to the fingers on either side of them. They are brought to the reference potential in depth of the active layer 12, that is to say (if the substrate is of the same type as the active layer) to the potential of the substrate 10 which is a reference potential for the whole of the pixel matrix. This connection of the regions 18 to the potential of the substrate occurs here naturally since the regions 18 are p + regions diffused in an active layer p itself in contact with the substrate p +. In practice, if the sensor comprises PMOS transistor circuits outside the pixel array, the p + isolation regions 18 may be made at the same time as the p + source and drain regions of these transistors. They therefore have the same depth and the same concentration (both higher than those of the superficial region).
- regions 18 may also be made at the same time as other p + regions, in particular those used to isolate laterally from each other the pixels belonging to different columns, as has been shown in FIG.
- the width of the narrow fingers 20 in the direction perpendicular to the charge transfer from a photodiode to a storage gate is sufficiently small and the doping of the regions 18 is sufficiently strong for the potential of the upper part of the epitaxial active layer 12 to be reduced.
- the fingers 20 is influenced by the presence of the regions 18 on either side of the finger.
- the potential in the active layer is of course influenced by the electric potential applied to the grid, but under the fingers it is different because of the presence of the regions 18 located on both sides of the finger and because of the narrowness of the fingers, although the fingers are worn at the same potential as the main body of the grid.
- Figure 6 shows a potential diagram within the active layer, at a depth where storage and charge transfer is located, i.e. slightly below the upper surface of the active layer. .
- This figure is drawn in the same sectional plane as in Figure 5, that is to say where there are fingers. The charge transfer takes place only under the fingers because the 18 p + regions brought to the reference potential of the substrate create potential barriers. high levels preventing charge transfer from a photodiode to a grid or vice versa.
- the sensor works with only two phases. All the gates G1 are connected at the same time and alternately receive a low potential which is in principle the reference potential 0, and a high potential which is in principle the supply potential Vdd of the pixel matrix. Vdd can be 5 volts. All the gates G2 are connected together to alternately receive this low potential and this high potential, but in phase opposition with the G1 gates.
- Two potential plots are shown in Figure 6; one corresponds to the first phase (grids G1 at low potential, grids G2 at high potential); the other corresponds to the second phase (G1 at high potential, G2 at low potential).
- the duration of each of the two phases is half of the integration period T corresponding to the observation of an image line by a line of pixels.
- the increasing potentials are directed downwards to show wells of potential and potential barriers for electrons.
- the induced potential under gates G2 to Vdd is higher than that of adjacent photodiodes and higher than that induced under gates G1; the charges which were stored under the storage gate G1 at the end of the previous integration period are discharged, at the beginning of the new integration period, under the storage gate G2, through the photodiode PH1 ,, in because of the passage of the gate G1, to Ov, and through the fingers of the gate G2,; the charges do not pass through the insulating regions 18.
- the gates G1 which pass to Vdd before the gates G2 pass to 0.
- the induced potential under the gates G1 becomes lower than that of the photodiodes and that which is induced under the gates G2; the charges which were under the storage gate G2, at the end of the first phase are discharged, at the beginning of the new integration period, under the storage gate G1 i + i of the following pixel, passing through the photodiode ⁇ 2 , which is at an intermediate potential, and through the fingers of this grid G1 i + i.
- the height of the potential barrier is BP1 BP2, varies with the width of narrow fingers 20; typically it can vary from 0.5 volts to 2.5 volts for finger widths ranging from 0.7 micrometer to 0.3 micrometers, widths that are easily achievable; these values are indicative because they depend on the engraving technology and the implantation levels used.
- the height of the potential barrier must not, however, be too high not to prevent the discharge of charges from the photodiode to the gate located downstream during the integration period; indeed the barrier formed between the region below the main body of the grid and the region under the fingers also exists when the gates are at potential Vdd and it is not necessary that this barrier exceeds the reference potential level of the photodiodes.
- a finger width less than or equal to 0.4 micrometer is well suited.
- the ends of the fingers on the upstream side of the gate are connected to each other by sections 22 of a narrow band of polycrystalline silicon gate 22 serving as a mask for alignment for the implantation of the doped regions of the photodiodes and isolation regions 18.
- the regions 18 are then delimited by the two fingers, by a main body portion of the gate, and by a portion of the narrow gate strip. .
- the surface of the photodiodes is then better controlled, which is important for a better uniformity of response of the pixels of the matrix.
- the width of the sections 22 narrow band preferably less than the width of the fingers so that the influence of the regions 18 on the potential in the active layer is also exerted in this band.
- the shape of the end of the finger may include a recess where the narrow band meets the finger, as shown in Figure 8, to avoid the risk of creating undesirable pockets of potential under the fingers, pockets in which charges could remain trapped during transfers.
- the length of the fingers in the direction of the transfer may be substantially equal to their width.
- the constitution of the pixels with a photodiode between two storage grids makes it possible to have a good response in the blue wavelengths, the photodiode not being masked by a grid that absorbs blue.
- the sensor may be a thinned sensor illuminated by the rear face, and it is then possible to increase the implantation depth of the surface regions of the photodiodes without reducing the sensitivity in the blue.
- the depth of implantation of the insulating regions 18 is not necessarily greater than the depth of the surface regions 16.
- the surface regions 16 are as deep as the insulating regions 18 because their depth then has little consequences on the sensitivity of the sensor ..
- the conversion circuit includes a plurality of transistors, analogous to transistors of a CMOS sensor active pixel, including a follower transistor and a reset transistor.
- the conversion circuit is then preferably associated with a correlated dual sampling circuit that first samples a reset potential level at the time of resetting the charge storage node potential, and then a useful signal level after spilling of loads of the last row of the matrix in the load storage nodes. The difference of the two samples is converted by an analog-to-digital converter.
- An elementary converter may be provided for each column of pixels or a global converter sequentially performs the conversion for each of the columns.
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Abstract
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Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201180024387.9A CN102971852B (zh) | 2010-05-18 | 2011-05-05 | 具有非对称栅极的矩阵电荷转移图像传感器 |
EP11717657.8A EP2572382B1 (fr) | 2010-05-18 | 2011-05-05 | Capteur d'image matriciel a transfert de charges a grille dissymetrique |
JP2013510553A JP6044044B2 (ja) | 2010-05-18 | 2011-05-05 | 非対称ゲート式マトリクス電荷転送イメージ・センサ |
KR1020127030172A KR20130079405A (ko) | 2010-05-18 | 2011-05-05 | 비대칭 게이트를 갖는 매트릭스 전하 전송 이미지 센서 |
US13/698,318 US8816406B2 (en) | 2010-05-18 | 2011-05-05 | Matrix charge-transfer image sensor with asymmetric gate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR1002086 | 2010-05-18 | ||
FR1002086A FR2960341B1 (fr) | 2010-05-18 | 2010-05-18 | Capteur d'image matriciel a transfert de charges a grille dissymetrique. |
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WO2011144459A1 true WO2011144459A1 (fr) | 2011-11-24 |
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Application Number | Title | Priority Date | Filing Date |
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PCT/EP2011/057243 WO2011144459A1 (fr) | 2010-05-18 | 2011-05-05 | Capteur d'image matriciel a transfert de charges a grille dissymetrique |
Country Status (7)
Country | Link |
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US (1) | US8816406B2 (fr) |
EP (1) | EP2572382B1 (fr) |
JP (1) | JP6044044B2 (fr) |
KR (1) | KR20130079405A (fr) |
CN (1) | CN102971852B (fr) |
FR (1) | FR2960341B1 (fr) |
WO (1) | WO2011144459A1 (fr) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2013164169A1 (fr) * | 2012-05-03 | 2013-11-07 | E2V Semiconductors | Capteur d'image matriciel a transfert de charges bidirectionnel a grilles dissymetriques |
US8736924B2 (en) | 2011-09-28 | 2014-05-27 | Truesense Imaging, Inc. | Time-delay-and-integrate image sensors having variable integration times |
WO2016188778A1 (fr) * | 2015-05-28 | 2016-12-01 | E2V Semiconductors | Capteur d'image a transfert de charges a double implantation de grille |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
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FR2953642B1 (fr) * | 2009-12-09 | 2012-07-13 | E2V Semiconductors | Capteur d'image multilineaire a integration de charges. |
CN103402061B (zh) * | 2013-08-12 | 2016-05-18 | 长春长光辰芯光电技术有限公司 | Cmos tdi图像传感器及其电荷转移控制方法 |
CN104934450B (zh) * | 2014-03-18 | 2018-09-18 | 中芯国际集成电路制造(上海)有限公司 | 图像传感器及其制作方法 |
FR3047112B1 (fr) * | 2016-01-22 | 2018-01-19 | Teledyne E2V Semiconductors Sas | Capteur d'image multilineaire a transfert de charges a reglage de temps d'integration |
JP2020009883A (ja) * | 2018-07-06 | 2020-01-16 | ソニーセミコンダクタソリューションズ株式会社 | 受光素子、測距モジュール、および、電子機器 |
CN111447386A (zh) * | 2020-04-01 | 2020-07-24 | 上海奕瑞光电子科技股份有限公司 | 基于cmos ic的探测器阵列和tdi-cmos线阵探测器的叠层结构 |
US20240022835A1 (en) * | 2020-09-10 | 2024-01-18 | Teledyne Digital Imaging, Inc. | A method and apparatus for high-speed charge-coupled cmos tdi imaging |
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- 2011-05-05 WO PCT/EP2011/057243 patent/WO2011144459A1/fr active Application Filing
- 2011-05-05 KR KR1020127030172A patent/KR20130079405A/ko not_active Application Discontinuation
- 2011-05-05 EP EP11717657.8A patent/EP2572382B1/fr not_active Not-in-force
- 2011-05-05 CN CN201180024387.9A patent/CN102971852B/zh not_active Expired - Fee Related
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Cited By (13)
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US8964088B2 (en) | 2011-09-28 | 2015-02-24 | Semiconductor Components Industries, Llc | Time-delay-and-integrate image sensors having variable intergration times |
US9503606B2 (en) | 2011-09-28 | 2016-11-22 | Semiconductor Components Industries, Llc | Time-delay-and-integrate image sensors having variable integration times |
US8736924B2 (en) | 2011-09-28 | 2014-05-27 | Truesense Imaging, Inc. | Time-delay-and-integrate image sensors having variable integration times |
US9049353B2 (en) | 2011-09-28 | 2015-06-02 | Semiconductor Components Industries, Llc | Time-delay-and-integrate image sensors having variable integration times |
US9093353B2 (en) | 2012-05-03 | 2015-07-28 | E2V Semiconductors | Matrix image sensor providing bidirectional charge transfer with asymmetric gates |
KR20150017698A (ko) * | 2012-05-03 | 2015-02-17 | 이2브이 세미콘덕터스 | 비대칭 게이트들을 이용하여 양방향 전하 전송을 제공하는 매트릭스 이미지 센서 |
WO2013164169A1 (fr) * | 2012-05-03 | 2013-11-07 | E2V Semiconductors | Capteur d'image matriciel a transfert de charges bidirectionnel a grilles dissymetriques |
JP2015524159A (ja) * | 2012-05-03 | 2015-08-20 | イー・2・ブイ・セミコンダクターズ | 非対称ゲートを備えた双方向電荷転送を実現するマトリクス画像センサ |
FR2990299A1 (fr) * | 2012-05-03 | 2013-11-08 | E2V Semiconductors | Capteur d'image matriciel a transfert de charges bidirectionnel a grilles dissymetriques |
KR102105730B1 (ko) * | 2012-05-03 | 2020-04-28 | 텔레다인 이2브이 세미컨덕터스 에스에이에스 | 비대칭 게이트들을 이용하여 양방향 전하 전송을 제공하는 매트릭스 이미지 센서 |
WO2016188778A1 (fr) * | 2015-05-28 | 2016-12-01 | E2V Semiconductors | Capteur d'image a transfert de charges a double implantation de grille |
FR3036848A1 (fr) * | 2015-05-28 | 2016-12-02 | E2V Semiconductors | Capteur d'image a transfert de charges a double implantation de grille |
TWI711167B (zh) * | 2015-05-28 | 2020-11-21 | 法商泰勒岱e2v半導體公司 | 具有雙閘極植入之電荷轉移影像感測器 |
Also Published As
Publication number | Publication date |
---|---|
KR20130079405A (ko) | 2013-07-10 |
JP6044044B2 (ja) | 2016-12-14 |
FR2960341B1 (fr) | 2012-05-11 |
US20130140609A1 (en) | 2013-06-06 |
US8816406B2 (en) | 2014-08-26 |
CN102971852B (zh) | 2015-11-25 |
FR2960341A1 (fr) | 2011-11-25 |
EP2572382A1 (fr) | 2013-03-27 |
EP2572382B1 (fr) | 2015-03-25 |
JP2013531879A (ja) | 2013-08-08 |
CN102971852A (zh) | 2013-03-13 |
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