WO2011142288A9 - 半導体装置、貼り合せ基板およびそれらの製造方法 - Google Patents
半導体装置、貼り合せ基板およびそれらの製造方法 Download PDFInfo
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- WO2011142288A9 WO2011142288A9 PCT/JP2011/060507 JP2011060507W WO2011142288A9 WO 2011142288 A9 WO2011142288 A9 WO 2011142288A9 JP 2011060507 W JP2011060507 W JP 2011060507W WO 2011142288 A9 WO2011142288 A9 WO 2011142288A9
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- 239000000758 substrate Substances 0.000 title claims abstract description 430
- 239000004065 semiconductor Substances 0.000 title claims abstract description 426
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 123
- 239000013078 crystal Substances 0.000 claims abstract description 466
- 239000000463 material Substances 0.000 claims abstract description 185
- 238000000034 method Methods 0.000 claims abstract description 88
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 52
- 229910052799 carbon Inorganic materials 0.000 claims abstract description 52
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 288
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 280
- 230000008569 process Effects 0.000 claims description 29
- 230000001681 protective effect Effects 0.000 claims description 29
- 230000001590 oxidative effect Effects 0.000 claims description 19
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 150000004767 nitrides Chemical class 0.000 claims description 12
- 229920002120 photoresistant polymer Polymers 0.000 claims description 12
- 229910052594 sapphire Inorganic materials 0.000 claims description 11
- 239000010980 sapphire Substances 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 239000004020 conductor Substances 0.000 claims description 8
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 238000007761 roller coating Methods 0.000 claims description 3
- 238000005507 spraying Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 abstract description 14
- 238000007254 oxidation reaction Methods 0.000 abstract description 14
- 239000010410 layer Substances 0.000 description 311
- 238000010438 heat treatment Methods 0.000 description 42
- 238000010586 diagram Methods 0.000 description 27
- 239000012298 atmosphere Substances 0.000 description 26
- 230000015556 catabolic process Effects 0.000 description 17
- 239000012535 impurity Substances 0.000 description 15
- 238000000137 annealing Methods 0.000 description 14
- 238000005498 polishing Methods 0.000 description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 12
- 230000004913 activation Effects 0.000 description 11
- 239000007789 gas Substances 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 10
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 9
- 239000001301 oxygen Substances 0.000 description 9
- 229910052760 oxygen Inorganic materials 0.000 description 9
- 230000002093 peripheral effect Effects 0.000 description 9
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 8
- 150000002500 ions Chemical class 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 230000004048 modification Effects 0.000 description 7
- 238000012986 modification Methods 0.000 description 7
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 description 6
- 229910052786 argon Inorganic materials 0.000 description 6
- 238000000206 photolithography Methods 0.000 description 6
- 238000000926 separation method Methods 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- 239000007787 solid Substances 0.000 description 5
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000002344 surface layer Substances 0.000 description 4
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000011261 inert gas Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 238000005092 sublimation method Methods 0.000 description 3
- 229910002601 GaN Inorganic materials 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010000 carbonizing Methods 0.000 description 2
- 239000008119 colloidal silica Substances 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000011344 liquid material Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000011343 solid material Substances 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- WQZGKKKJIJFFOK-GASJEMHNSA-N Glucose Natural products OC[C@H]1OC(O)[C@H](O)[C@@H](O)[C@@H]1O WQZGKKKJIJFFOK-GASJEMHNSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- 239000008103 glucose Substances 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 239000012299 nitrogen atmosphere Substances 0.000 description 1
- 125000004433 nitrogen atom Chemical group N* 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
Images
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
- H01L21/048—Making electrodes
- H01L21/0495—Schottky electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1066—Gate region of field-effect devices with PN junction gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/47—Schottky barrier electrodes
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/6606—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/80—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier
- H01L29/808—Field effect transistors with field effect produced by a PN or other rectifying junction gate, i.e. potential-jump barrier with a PN junction gate, e.g. PN homojunction gate
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
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- H—ELECTRICITY
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
- H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
- H01L29/0873—Drain regions
- H01L29/0878—Impurity concentration or distribution
Definitions
- the present invention relates to a semiconductor device, a bonded substrate, and a method for manufacturing the same, and more specifically, a bonded substrate configured by bonding a single crystal semiconductor member to a supporting base material and the bonded substrate.
- the present invention relates to a semiconductor device and a manufacturing method thereof.
- Patent Document 1 Japanese Patent Application Laid-Open No. 2007-158133 (hereinafter referred to as Patent Document 1))
- Patent Document 2 Japanese Patent Laid-Open No. 2006-173582
- Patent Document 1 a nitride semiconductor layer constituting a light-emitting element structure is formed on a sapphire substrate, and a silicon substrate as another supporting base is joined to the nitride semiconductor layer by soldering, and then the sapphire substrate is removed. This improves the light extraction efficiency.
- Patent Document 2 a lateral device GaN-HEMT is formed on a sapphire substrate via a buffer layer, a support substrate is bonded to the GaN-HEMT side, and then the sapphire substrate is peeled off and the buffer layer is removed. Thus, the back surface of the carrier running layer of the GaN-HEMT is exposed, and a hole discharge electrode is formed on the back surface, thereby improving the breakdown voltage of the device.
- Patent Documents 1 and 2 described above As a semiconductor device using the nitride semiconductor disclosed in Patent Documents 1 and 2 described above, a vertical power device is also conceivable. However, such a vertical power device is required to reduce on-resistance. ing. However, Patent Documents 1 and 2 described above do not particularly mention reduction of the on-resistance. The present inventor also considered reducing the thickness of the substrate on which the element structure is formed after forming the device (for example, shaving the substrate from the back side) with respect to reducing the on-resistance in the vertical power device. There has been a problem that the element structure may be damaged during processing.
- the compound semiconductors such as the nitride semiconductors described above have a limited number of devices that can be manufactured at a time because the size of a substrate that can be obtained as a high-quality single crystal substrate is smaller than that of a silicon substrate. For this reason, there was a problem that it was difficult to reduce the manufacturing cost as a result.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a low-cost, high-quality semiconductor device, a bonded substrate used for manufacturing the semiconductor device, and these It is to provide a manufacturing method.
- a method of manufacturing a semiconductor device includes a step of preparing a single crystal semiconductor member, a step of preparing a support base, and a support base and the single crystal semiconductor member via a bonding layer containing carbon. After the step of bonding, the step of forming an epitaxial layer on the surface of the single crystal semiconductor member, the step of forming a semiconductor element using the epitaxial layer, and the step of forming the semiconductor element, oxidizing the bonding layer Disassembling and separating the single crystal semiconductor member from the support substrate; and dividing the single crystal semiconductor member separated from the support substrate.
- the handling property of the single crystal semiconductor member in the step can be improved.
- the treatment since the treatment is performed with the single crystal semiconductor member connected to the support base material, it is not always necessary to secure a self-supporting thickness as the thickness of the single crystal semiconductor member. It can be determined in consideration of the characteristics of the semiconductor element (for example, on-resistance). Therefore, for example, in order to reduce the on-resistance, it is possible to set the thickness of the single crystal semiconductor member to a thickness that is lower than the lower limit of the thickness that can be self-supported. As a result, a semiconductor device having excellent characteristics (for example, sufficiently low on-resistance) can be realized.
- the bonding layer for bonding the single crystal semiconductor member to the supporting base material contains carbon, it can be easily decomposed by oxidizing the bonding layer. For this reason, after forming a semiconductor element on a single crystal semiconductor member, the single crystal semiconductor member can be easily separated from the support base material.
- the bonding layer containing carbon is preferably a bonding layer containing carbon as a main component.
- a layer obtained by heat-treating (carbonizing) a photoresist, a resin, or the like to be solidified and using substantially solid carbon can be used as the bonding layer.
- Such a bonding layer containing carbon as a main component is sufficiently formed from a single crystal semiconductor member if the bonding layer is not exposed to an oxidizing atmosphere even at a heat treatment temperature (for example, about 1000 ° C.) in the process of forming a semiconductor element.
- the connection state with the support base material can be maintained.
- a method for manufacturing a bonded substrate according to the present invention includes a step of preparing a single crystal semiconductor member, a step of preparing a support base, and a support base and a single crystal semiconductor member via a bonding layer containing carbon. And joining.
- the handling property as a bonded substrate can be kept good even if the thickness of the single crystal semiconductor member is reduced.
- the process is performed in a state where the single crystal semiconductor member is connected to the supporting base material, so that the thickness of the single crystal semiconductor member can be self-supporting.
- the thickness is not necessarily ensured, and can be determined in consideration of the final characteristics of the semiconductor element (for example, on-resistance). Therefore, for example, in order to reduce the on-resistance, the thickness of the single crystal semiconductor member can be set so as to be less than the lower limit of the thickness that can be self-supported.
- a bonded substrate capable of manufacturing a semiconductor device having excellent characteristics for example, sufficiently low on-resistance
- the bonding layer for bonding the single crystal semiconductor member to the supporting base material contains carbon, it can be easily decomposed by oxidizing the bonding layer. For this reason, the single crystal semiconductor member can be easily separated from the support base material.
- the semiconductor device includes a support base, a single crystal semiconductor layer, and an electrode.
- the single crystal semiconductor layer is bonded to the surface of the support base via a bonding layer containing carbon.
- the electrode is formed over the single crystal semiconductor layer.
- the single crystal semiconductor layer may include, for example, a single crystal semiconductor member bonded to the surface of the support base via the bonding layer, and an epitaxial layer formed on the surface of the single crystal semiconductor member. .
- the bonded substrate according to the present invention includes a supporting base material and a single crystal semiconductor member.
- the single crystal semiconductor member is bonded to the surface of the support base material via a bonding layer containing carbon.
- the handling property as a bonded substrate can be kept good even if the thickness of the single crystal semiconductor member is reduced.
- the process is performed in a state where the single crystal semiconductor member is connected to the supporting base material, so that the thickness of the single crystal semiconductor member can be self-supporting.
- the thickness is not necessarily ensured, and can be determined in consideration of the final characteristics of the semiconductor element (for example, on-resistance). Therefore, for example, in order to reduce the on-resistance, the thickness of the single crystal semiconductor member can be set so as to be less than the lower limit of the thickness that can be self-supported.
- the bonding layer for bonding the single crystal semiconductor member to the supporting base material contains carbon, it can be easily decomposed by oxidizing the bonding layer. For this reason, the single crystal semiconductor member can be easily separated from the support base material.
- a low-cost and high-quality semiconductor device and a bonded substrate suitable for manufacturing the semiconductor device can be obtained.
- FIG. 5 is a flowchart for explaining the first embodiment of the method for producing a semiconductor device according to the present invention. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG. It is a schematic diagram for demonstrating the manufacturing method of the semiconductor device shown in FIG.
- FIG. 10 is a schematic diagram for illustrating a first modification of the method for manufacturing the semiconductor device illustrated in FIG. 1.
- FIG. 10 is a schematic diagram for illustrating a second modification of the method for manufacturing the semiconductor device illustrated in FIG. 1. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention. It is a schematic diagram which shows Embodiment 2 of the manufacturing method of the semiconductor device by this invention.
- FIG. 28 is a schematic view for illustrating the method for manufacturing the semiconductor device shown in FIG. 27.
- FIG. 28 is a schematic view for illustrating the method for manufacturing the semiconductor device shown in FIG. 27.
- FIG. 28 is a schematic view for illustrating the method for manufacturing the semiconductor device shown in FIG. 27. It is a cross-sectional schematic diagram which shows the semiconductor device obtained by Embodiment 5 of the manufacturing method of the semiconductor device by this invention. It is a flowchart for demonstrating Embodiment 5 of the manufacturing method of the semiconductor device by this invention. It is a cross-sectional schematic diagram which shows the semiconductor device obtained by the manufacturing method of the semiconductor device by this invention.
- a step (S10) of preparing a single crystal semiconductor member is performed.
- a silicon carbide (SiC) single crystal substrate 1 which is an example of a single crystal semiconductor member is prepared.
- the SiC single crystal substrate 1 shown in FIG. 2 has a circular planar shape, but the planar shape can be any shape.
- a gallium nitride (GaN) single crystal substrate can be used as the single crystal semiconductor member.
- a step of preparing a support base material is performed.
- a support base material 20 is prepared. 3 is the same as the planar shape of SiC single crystal substrate 1 shown in FIG. 2, and is, for example, a circular shape.
- the size of the upper surface of support base 20 may be the same as the size of the bottom surface of SiC single crystal substrate 1 shown in FIG. 2, but is preferably larger than the size of the bottom surface of SiC single crystal substrate 1. It is good. Any material can be used as the material of the support base material 20 as long as it can withstand the process temperature in the process performed on the SiC single crystal substrate 1. For example, SiC is used. be able to.
- a step (S30) of joining the supporting base material and the single crystal semiconductor member is performed.
- the upper surface of support base material 20 and the back surface of SiC single crystal substrate 1 are bonded together by bonding layer 22.
- the bonding layer 22 is an adhesive layer containing carbon.
- a material containing carbon for example, a resin material such as a resist
- SiC single crystal substrate 1 is mounted on the surface on which the carbon-containing material is arranged. By performing heat treatment in this state, the material containing carbon is solidified so as to become a solid containing carbon as a main component.
- the heat treatment when a resist is used as the material, the following treatment can be applied.
- the resist is solidified at a predetermined temperature (for example, 100 ° C.).
- a high temperature heat treatment for example, heat treatment at a temperature of about 800 ° C.
- a vacuum furnace with a predetermined pressure and a load applied in the vertical direction, so that a solid bonding layer mainly composed of carbon from the resist is obtained. 22 can be formed.
- a bonded substrate 21 as shown in FIG. 4 is obtained.
- an epitaxial layer forming step (S40) is performed. Specifically, an epitaxial layer is formed on the surface of SiC single crystal substrate 1 of bonded substrate 21 shown in FIG. 4 using an epitaxial growth method.
- a step of forming a semiconductor element is performed. Specifically, a semiconductor element having a predetermined structure is formed on the surface of SiC single crystal substrate 1 using the above-described epitaxial layer. As a result, element 30 is formed on the surface of SiC single crystal substrate 1 as shown in FIG. A plurality of the elements 30 are preferably formed.
- a step (S60) of separating the single crystal semiconductor member from the support base material is performed.
- second support base material 25 is bonded onto the surface of SiC single crystal substrate 1 on which element 30 is formed.
- the second support base material 25 can be joined to the SiC single crystal substrate 1 using, for example, a heat-resistant tape.
- a process capable of selectively removing the bonding layer 22 is performed.
- the bonding layer 22 containing carbon is decomposed and removed by disposing the bonded substrate 21 to which the second support base material 25 is bonded in oxygen plasma, for example.
- SiC single crystal substrate 1 can be separated from support base material 20.
- a step (S70) of forming an electrode on the back surface of the single crystal semiconductor member is performed.
- back electrode 26 is formed on the back side of SiC single crystal substrate 1.
- any method can be used as a method for forming the back electrode 26, for example, a sputtering method or the like can be used.
- any material can be used as the material of the back electrode 26, but for example, a conductor such as metal can be used.
- a step of injecting conductive impurities into the back surface of SiC single crystal substrate 1 or an activation heat treatment step may be performed in advance.
- a step (S80) of dividing the single crystal semiconductor member is performed. Specifically, in order to separate each of elements 30 formed on the surface of SiC single crystal substrate 1, SiC single crystal substrate 1 is divided into a predetermined size using, for example, a dicing apparatus. As a result, the individual elements 30 can be separated. Thus, the semiconductor device according to the present invention can be obtained.
- a material to be the bonding layer 22 containing carbon so as to cover the upper surface of the support base material 20 is used.
- the arrangement of the material may take other forms. That is, as long as SiC single crystal substrate 1 and supporting base material 20 can be connected and fixed, bonding layer 22 may be disposed only at a part of the bonding interface between supporting base material 20 and SiC single crystal substrate 1. For example, as shown in FIG. 8, bonding layer 22 may be arranged only on the outer periphery of SiC single crystal substrate 1.
- FIG. 8 is a schematic plan view showing another example of the arrangement of the bonding layers in the step (S30) of bonding the supporting base material and the single crystal semiconductor member.
- FIG. 8 is a schematic plan view showing another example of the arrangement of the bonding layers in the step (S30) of bonding the supporting base material and the single crystal semiconductor member, and shows another example of the bonded substrate 21 shown in FIG. It is the plane perspective view which looked at the example from the upper part.
- bonding layer 22 is disposed only on the outer peripheral portion of bonded substrate 21 (the outer peripheral portion of the bonding interface between support base material 20 and SiC single crystal substrate 1).
- the plasma atmosphere used for removing the bonding layer 22 such as oxygen plasma or other reactive atmosphere is the bonding layer 22. Therefore, the SiC single crystal substrate 1 can be separated earlier from the support base material 20 in the step (S60).
- an arrow 27 indicates the back side of SiC single crystal substrate 1 (the side bonded to support base material 20).
- ion implantation may be performed.
- the back electrode 26 formed in the step of forming the back electrode of the single crystal semiconductor member (S70) and the back surface of the SiC single crystal substrate 1 can be more reliably ohmic-connected.
- activation heat treatment for activating the implanted ions is preferably performed.
- the process after the process (S30) shown in FIG. 1 is implemented.
- the second embodiment of the semiconductor device manufacturing method according to the present invention shown in FIGS. 10 to 15 is basically the same as the first embodiment of the semiconductor device manufacturing method according to the present invention shown in FIGS.
- the shapes of the SiC single crystal substrate 1 and the support base 20 and the shape of the bonded substrate 21 obtained by combining these are different.
- a single crystal semiconductor member (S10) see FIG. 1
- a plurality of SiC single crystal substrates 1 having a square planar shape are prepared as shown in FIG.
- four SiC single crystal substrates 1 are prepared.
- the planar shape is a square shape, and a plurality of the SiC single crystal substrates 1 can be mounted relatively.
- a support base material 20 having a plane size larger than the plane size of SiC single crystal substrate 1 is prepared.
- the same material as the support base material 20 shown in FIG. 3 can be used.
- a step (S30) of joining the supporting base material and the single crystal semiconductor member is performed. Specifically, as shown in FIG. 12, a layer to be the bonding layer 22 containing carbon is formed on the upper surface of the support base 20. Then, a plurality of SiC single crystal substrates 1 are mounted on the layer, and a predetermined heat treatment is performed to form bonding layer 22 from the layer. As a result, a bonded substrate composed of the supporting base material 20 in which a plurality of SiC single crystal substrates 1 are bonded by the bonding layer 22 is obtained. At this time, as shown in FIG.
- the SiC single crystal substrates 1 arranged side by side on the upper surface of the support base material 20 may be arranged at intervals from each other, but in a state where the end surfaces are in contact with each other. It may be arranged. If SiC single crystal substrates 1 are arranged in a state of being separated from each other as shown in FIG. 12, each SiC single crystal substrate 1 is separated in a step (S60) of separating a single crystal semiconductor member from a supporting base material to be described later. A reaction atmosphere such as oxygen plasma can easily reach the bonding layer 22 located at the bonding interface between the substrate 20 and the support substrate 20. For this reason, the SiC single crystal substrate 1 can be easily peeled off from the support base material 20.
- epitaxial layer 23 is also formed on bonding layer 22 on the upper surface of the SiC single crystal substrate and on the upper surface of support base material 20. As a result, the surface of the bonding layer 22 located at the connection portion between the SiC single crystal substrate 1 and the support base 20 is covered with the epitaxial layer 23.
- step (S50) of forming a semiconductor element is performed.
- this step (S50) the same processing conditions as in step (S50) in the first embodiment described above can be used.
- separates a single crystal semiconductor member from the support base material shown in FIG. 1 is implemented.
- the second support base material 25 is bonded onto the upper surface of the SiC single crystal substrate 1 by an arbitrary method such as heat-resistant tape, as in the case of the first embodiment described above. To do.
- the bonded substrate 21 is placed in an atmosphere such as oxygen plasma, so that the bonding layer 22 located between the SiC single crystal substrate 1 and the support base 20 is decomposed and removed.
- the epitaxial layer 23 (see FIG. 12) covering the bonding layer 22 is formed as described above, before the second support base material 25 is bonded onto the upper surface of the SiC single crystal substrate 1, the SiC layer is previously formed.
- a step of removing the epitaxial layer 23 from the vicinity of the junction between the single crystal substrate 1 and the support base 20 is performed.
- the epitaxial layer 23 is removed using an arbitrary method such as reactive ion etching (RIE). To do.
- RIE reactive ion etching
- step (S70) of forming an electrode on the back surface of the single crystal semiconductor member shown in FIG. 1 is performed.
- This step (S70) is basically the same as the step (S70) in the first embodiment described above.
- back electrode 26 can be formed on the back side of SiC single crystal substrate 1.
- the semiconductor device according to the present invention can be obtained by performing the step (S80) of dividing the single crystal semiconductor member.
- FIG. 16 corresponds to FIG.
- the bonding layer 22 is formed only at the outer peripheral portion of the bonding interface between the SiC single crystal substrate 1 and the supporting base material 20. May be. In this case, the same effect as that obtained when the arrangement of the bonding layer 22 shown in FIG. 8 is adopted can be obtained.
- FIG. 17 corresponds to FIG.
- ion implantation may be performed in advance on the back surface of the SiC single crystal substrate 1 as shown by an arrow 27 as shown in FIG.
- activation annealing treatment is preferably performed. Even if it does in this way, the effect similar to the case where the process demonstrated in FIG. 9 is implemented can be acquired.
- the manufacturing method of the semiconductor device shown in FIGS. 18 to 26 basically includes the same steps as those of the first embodiment of the semiconductor device according to the present invention shown in FIGS.
- the shape of (refer FIG. 18) and the shape of the support base material 20 differ.
- the shape of the bonded substrate 21 is also different. This will be specifically described below.
- the step (S10) of preparing the single crystal semiconductor member shown in FIG. 1 is performed.
- the specific processing content is the same as the process described in FIG. 2, the size and shape of the SiC single crystal substrate 1 to be prepared are different from those in the method for manufacturing the semiconductor device shown in FIG. That is, as shown in FIG. 18, a plate-shaped SiC single crystal substrate 1 having a square planar shape is prepared as a single crystal semiconductor member.
- a step (S20) of preparing a support base material is performed. Specifically, a support base 20 having a circular planar shape as shown in FIG. 19 and having an opening 41 formed therein is prepared.
- the planar shape of opening 41 formed in support base material 20 is similar to the planar shape of SiC single crystal substrate 1 shown in FIG. Further, a stepped portion 42 having a width relatively wider than the opening 41 is formed above the opening 41.
- the size of the step portion 42 is set to a size that allows the SiC single crystal substrate 1 to be disposed therein. That is, the dimension of the planar shape of the step portion 42 is a dimension obtained by adding the thickness of the bonding layer 22 (see FIG. 22) to the planar dimension of the SiC single crystal substrate 1.
- the opening 41 is formed so as to penetrate the support base 20 as shown in FIGS.
- the planar shape of the opening 41 can be, for example, a square shape.
- a stepped portion 42 that forms a wider opening is formed at the upper end of the opening 41.
- the planar shape of the stepped portion 42 is a square shape, which is the same as the planar shape of the SiC single crystal substrate 1 shown in FIG.
- a plurality of such openings 41 are formed in the support base 20.
- the four said opening parts 41 are formed.
- a step (S30) of joining the supporting base material and the single crystal semiconductor member is performed. Specifically, as shown in FIGS. 22 and 23, SiC single crystal substrate 1 is fitted into stepped portion 42 formed above opening 41 of support base 20 described above. At this time, as shown in FIG. 22, a layer (for example, a resist) to be the bonding layer 22 containing carbon is disposed in advance on the inner peripheral side of the stepped portion 42, and then the SiC single crystal substrate 1 is fitted into the stepped portion 42. Include. As the layer to be the bonding layer 22, for example, a liquid material can be used. Then, by performing a predetermined heat treatment, the layer to be the bonding layer 22 is a bonding layer 22 containing carbon, which is a solid layer.
- the SiC single crystal substrate 1 is similarly installed about all the opening parts of the support base material 20 shown in FIG. Note that the depth of the stepped portion 42 is smaller than the thickness of the SiC single crystal substrate 1.
- FIG. 23 are schematic sectional views taken along line XX-XX in FIG.
- the step of forming an epitaxial layer (S40) and the step of forming a semiconductor element (S50) shown in FIG. 1 are performed.
- a plurality of elements 30 using the above-described epitaxial layer are formed on the surface of SiC single crystal substrate 1.
- a step (S60) of separating the single crystal semiconductor member from the support base shown in FIG. 1 is performed.
- the bonding layer 22 containing carbon is decomposed by bonding the second support base material 25 to the upper surface of the SiC single crystal substrate 1 on which the plurality of elements 30 are formed, and then performing oxygen plasma treatment or the like. Remove.
- the second support base material 25 and the SiC single crystal substrate 1 can be separated from the support base material 20.
- the step of forming the back electrode of the single crystal semiconductor member (S70) and the step of dividing the single crystal semiconductor member (S80) shown in FIG. 1 are performed, whereby the semiconductor device according to the present invention can be obtained. .
- the SiC single crystal substrate 1 shown in FIG. 18 may be previously subjected to an ion implantation step on the back surface side as shown in FIG. At this time, an activation annealing treatment may be subsequently performed.
- the step (S10) of preparing the single crystal semiconductor member shown in FIG. 27 is basically the same as the step (S10) in the second embodiment of the semiconductor device manufacturing method according to the present invention.
- ion implantation and activation annealing are performed on the back side of SiC single crystal substrate 1 which is a single crystal semiconductor member.
- the process (S70) of forming the back surface electrode of a single crystal semiconductor member is implemented.
- back electrode 26 is formed on the back side of SiC single crystal substrate 1.
- the planar size of back electrode 26 is smaller than the planar size of the back surface of SiC single crystal substrate 1.
- Such a back electrode 26 can be formed by the following processes, for example.
- a resist mask in which a region where the back electrode 26 is to be formed on the back surface of the SiC single crystal substrate 1 is formed is formed.
- a conductor film (for example, a metal film) to be the back electrode is formed on the back surface by using a sputtering method or the like.
- a part of the conductor film formed on the resist mask together with the resist mask is removed (lift-off). In this way, the back electrode 26 can be formed. As a result, a structure as shown in FIG. 28 is obtained.
- a step of preparing a support base material (S20) is performed. This step is basically the same as the step (S20) in the second embodiment of the present invention.
- a step (S30) of bonding the supporting base material and the single crystal semiconductor member is performed. Specifically, a film to be the bonding layer 22 containing carbon is formed on the outer peripheral portion where the back electrode 26 is not formed on the back surface side of the SiC single crystal substrate 1, and the surface of the supporting base material is formed by the film. The SiC single crystal substrate 1 is bonded. Thereafter, the bonding layer 22 containing carbon is formed from the film by performing a predetermined heat treatment. As a result, a bonded substrate in which the SiC single crystal substrate 1 is bonded onto the surface of the support base 20 as shown in FIG. 29 can be obtained. At this time, as shown in FIG.
- the back electrode 26 is exposed to a film forming atmosphere, an etching atmosphere, or the like in the subsequent process. There is no. Further, the bonding layer 22 may be disposed in a region between the back electrode 26 and the support base material 20 as long as the back electrode 26 is embedded inside.
- This is carried out in the same manner as in the semiconductor device manufacturing method according to the second embodiment of the present invention. Even in this case, the semiconductor device according to the present invention can be obtained.
- FIG. 31 is a flowchart for explaining a method of manufacturing the semiconductor device shown in FIG.
- the semiconductor device according to the present invention is a lateral JFET and is formed using the bonded substrate according to the present invention.
- a bonded substrate composed of the support base 20, the bonding layer 22, and the SiC single crystal substrate 1 is used as the semiconductor substrate.
- the conductivity type of SiC single crystal substrate 1 does not matter.
- p ⁇ type epitaxial layer 2 having a thickness h is provided as a first semiconductor layer containing a first conductivity type impurity.
- an n-type epitaxial layer 3 having a thickness d2 is provided as a second semiconductor layer containing a second conductivity type impurity having a higher impurity concentration than the p ⁇ -type epitaxial layer 2. It has been.
- a p-type epitaxial layer 6 as a third semiconductor layer is provided on the n-type epitaxial layer 3.
- the p-type epitaxial layer 6 includes a second conductivity type impurity having a concentration higher than the impurity concentration of the n-type epitaxial layer 3 at a predetermined interval, and an n + -type source region layer having a thickness d1. 5 and an n + -type drain region layer 9 are provided.
- the first conductivity type having a concentration higher than the impurity concentration of the n-type epitaxial layer 3 so that the lower surface extends into the n-type epitaxial layer 3 between the source region layer 5 and the drain region layer 9.
- p + -type gate region layer 7 containing an impurity is provided in the.
- a source electrode 10, a gate electrode 11, and a drain electrode 12 are provided on the surfaces of the n + -type source region layer 5, the n + -type drain region layer 9, and the p + -type gate region layer 7, respectively. Incidentally, the side of the source region layer 5, p - -type epitaxial layer 2 p + -type semiconductor layer 4 to reach is formed.
- a step of preparing a single crystal semiconductor member (S10), a step of preparing a support substrate (S20), a step of bonding the support substrate and the single crystal semiconductor member (S30), and an epitaxial layer A forming step (S40) and a semiconductor element forming step (S50) are respectively performed.
- These steps (S10) to (S50) are basically performed in the same manner as the corresponding steps in the method of manufacturing a semiconductor device in the first or second embodiment of the present invention.
- the step (S80) of dividing the single crystal semiconductor member is performed without separating the SiC single crystal substrate 1 from the support base material 20.
- bonding layer 22 and support base material 20 are also divided together with SiC single crystal substrate 1.
- a semiconductor device as shown in FIG. 30 can be obtained.
- the SiC single crystal substrate 1 is used as an example of the single crystal semiconductor member.
- a nitride semiconductor substrate for example, a gallium nitride (GaN) substrate
- GaN gallium nitride
- Other compound semiconductor substrates such as may be used.
- Example 1 a method for manufacturing a semiconductor device as an example corresponding to the above-described first embodiment will be described.
- a 2-inch silicon carbide single crystal ingot grown by a sublimation method is sliced at a thickness of 100 ⁇ m to cut out a substrate to be the SiC single crystal substrate 1.
- One main surface (one side) of the substrate is mirror-finished by mechanical polishing, and then a TiAlSi film is formed on the mirror-finished surface by a sputtering method.
- the silicon carbide polycrystalline substrate is finished by grinding to a thickness of about 400 ⁇ m.
- one surface of the substrate is mirror-finished by mechanical polishing to prepare a first support base material.
- a resist is applied to the mirror finished surface of the first support substrate, and the surface of the SiC single crystal substrate on which the TiAlSi film is formed is attached to the surface of the first support substrate to which the resist is applied.
- the resist is hardened by heat treatment at a heating temperature of 100 ° C.
- a heat treatment is performed at a heating temperature of 800 ° C. by applying a load of 500 g so as to press the first support base and the SiC single crystal substrate against each other at a pressure of 10 ⁇ 3 Torr or less in a vacuum furnace.
- the bonding layer 22 containing carbon as a main component is formed from the resist.
- the SiC single crystal substrate and the support base material are bonded by the bonding layer 22.
- an epitaxial layer having a thickness of 10 ⁇ m and a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 was formed on the surface of the bonded substrate on the SiC single crystal substrate side using a CVD apparatus.
- the substrate temperature 1550 °C, 150SLM hydrogen flow rate for the gas used 50 sccm flow rate of SiH 4, 50 sccm flow rate of C 2 H 6, the flow rate of 2ppm nitrogen 6 sccm, and the growth time was 90 minutes.
- Al ions were implanted into the epitaxial layer by ion implantation, and a guard ring was formed by activation annealing.
- titanium (Ti) is vacuum-deposited on the entire surface of the epitaxial layer, and then a mask pattern is formed by photolithography, followed by etching to form a 2.4 mm square Schottky electrode. After the Schottky annealing at 500 ° C., a SiO 2 passivation film is formed. Then, an opening is formed in the region of the passivation film on the Schottky electrode. Then, an electrode pad made of Al / Si that contacts the Schottky electrode and extends on the passivation film is formed inside the opening.
- the surface on which the electrode pad is formed is fixed to the second support base with heat-resistant tape.
- the bonding substrate is disposed in oxygen plasma by disposing the bonded substrate to which the second supporting substrate is fixed, so that the first supporting substrate is peeled from the SiC single crystal substrate.
- the surface of the TiAlSi film from which the bonding layer has been removed is sputtered with argon plasma to clean the surface.
- the second support base material is removed from the SiC single crystal substrate.
- the SiC single crystal substrate on which the Schottky barrier diode (SBD) is formed as described above is diced, and the SDB is chipped.
- an SBD can be obtained as a semiconductor device according to the present invention.
- the first support base material can be reused by being connected and fixed to another SiC single crystal substrate again.
- Example 2 A method for manufacturing a semiconductor device as an example corresponding to the above-described second embodiment will be described below.
- a silicon carbide single crystal ingot grown by a sublimation method is shaped, and an SiC single crystal substrate which is a rectangular single crystal material having a length of 20 mm, a width of 40 mm, and a thickness of 100 ⁇ m is cut out.
- One side of the SiC single crystal substrate is mirror-finished by mechanical polishing.
- a TiAlSi film is formed on the mirror-finished surface (back surface) by sputtering.
- a rectangular silicon carbide polycrystalline plate having a length and width of 150 mm is separately prepared as a first support base.
- One main surface of the first support substrate is mirror-finished by mechanical polishing.
- a resist is applied to the mirror-finished surface of the first support substrate, and the polishing surface (surface on which the TAlSi film is formed) of the SiC single crystal substrate is attached to the first support substrate, and the heating temperature is 100 ° C.
- the resist is hardened by heat treatment.
- a bonded substrate according to the present invention as shown in FIG. 12 is obtained.
- a plurality of SiC single crystal substrates were arranged in a matrix of 3 rows ⁇ 7 columns on the surface of the support base material.
- an epitaxial layer having a thickness of 10 ⁇ m and a carrier concentration of 1 ⁇ 10 16 cm ⁇ 3 was formed on the surface of the bonded substrate on the SiC single crystal substrate side using a CVD apparatus.
- the substrate temperature was 1550 ° C.
- the hydrogen flow rate was 150 SLM
- the SiH 4 flow rate was 50 sccm
- the C 2 H 6 flow rate was 50 sccm
- the 2 ppm nitrogen flow rate was 6 sccm
- the growth time was 90 minutes.
- the epitaxial layer (SiC) is coated on the bonding boundary between the SiC single crystal substrate and the first support base (that is, on the surface of the bonding layer).
- phosphorus (P) ions are implanted into the epitaxial layer using the SiO 2 layer having the opening pattern as a mask to form a source portion of the n + -type transistor.
- Al ions are implanted by self-alignment using the W layer formed on the epitaxial layer as a mask to form a p-type body part.
- the p + region of the source portion and the guard ring are formed by Al ion implantation. Thereafter, activation annealing of the implanted ions is performed.
- a gate oxide film is formed by thermal oxidation.
- a gate electrode made of polysilicon is formed on the gate oxide film.
- a source electrode made of TiAlSi an SiO 2 interlayer insulating film having a barrier layer made of SiN is formed.
- an upper layer wiring of a laminated structure of Al / Si is formed on the interlayer insulating film.
- a protective film is formed so as to cover the upper layer wiring.
- the silicon carbide portion (epitaxial layer) covering the end portion of the bonding interface between the supporting base material and the SiC single crystal substrate (more specifically, the surface of the bonding layer located at the end portion) is removed by dry etching. . Thereafter, the surface on which the protective film is formed is fixed to the second support substrate with a heat-resistant tape. By disposing and removing the bonding layer from the portion exposed by the dry etching by disposing the bonded substrate to which the second supporting substrate is fixed in oxygen plasma, the first supporting substrate is made of the SiC single crystal substrate. Peel from.
- the surface of the TiAlSi film from which the bonding layer has been removed is sputtered with argon plasma to clean the surface.
- the second support base material is removed from the SiC single crystal substrate.
- the SiC single crystal substrate is diced into chips. The first support substrate can be reused.
- Example 3 a method for manufacturing a semiconductor device as an example corresponding to the above-described third embodiment will be described.
- a silicon carbide single crystal ingot grown by a sublimation method is shaped, and an SiC single crystal substrate which is a rectangular single crystal material having a length of 20 mm, a width of 40 mm, and a thickness of 100 ⁇ m is cut out.
- the cut surface is a ⁇ 03-38 ⁇ plane which is a plane inclined by 54.7 degrees from the (0001) plane.
- a sintered SiC substrate having a diameter of 6 inches and a thickness of 600 ⁇ m is separately prepared as a first support base.
- a number of holes are formed in the SiC substrate (that is, the SiC substrate here can be said to be a porous body).
- a step portion 42 (see FIG. 21) having a depth of 70 ⁇ m and an opening 41 are formed at a position where the SiC single crystal substrate is placed so that the SiC single crystal substrate can be fixed to the SiC substrate.
- a rectangular SiC single crystal substrate is fitted into the step portion 42.
- Nine steps 42 and openings 41 are formed in a matrix.
- the SiC single crystal substrate is bonded to the stepped portion 42 using a photoresist as shown in FIG. Thereafter, the photoresist is carbonized by performing a heat treatment at a heating temperature of 600 ° C. in a nitrogen atmosphere to form a bonding layer 22 (see FIG. 22) containing carbon (carbon as a main component).
- the bonding layer 22 fixes the SiC single crystal substrate to the support base material.
- an epitaxial layer having a thickness of 12 ⁇ m and a carrier concentration of 8 ⁇ 10 15 cm ⁇ 3 was formed on the surface of the bonded substrate on the SiC single crystal substrate side using a CVD apparatus.
- the substrate temperature was 1550 ° C.
- the hydrogen flow rate was 150 SLM
- the SiH 4 flow rate was 50 sccm
- the C 2 H 6 flow rate was 50 sccm
- the 2 ppm nitrogen flow rate was 5 sccm
- the growth time was 90 minutes.
- the epitaxial layer (SiC) is coated on the bonding boundary between the SiC single crystal substrate and the first support base (that is, on the surface of the bonding layer exposed at the outer peripheral portion of the stepped portion 42).
- phosphorus (P) ions are implanted into the epitaxial layer using the SiO 2 layer having the opening pattern as a mask to form a source portion having a transistor conductivity type of n + type.
- Al ions are implanted by self-alignment using the SiO 2 layer formed on the epitaxial layer as a mask to form a p-type body part.
- the p + region of the source portion and the guard ring are formed by Al ion implantation. Thereafter, activation annealing of the implanted ions is performed.
- a gate oxide film is formed by thermal oxidation.
- a gate electrode made of polysilicon is formed on the gate oxide film.
- a source electrode made of TiAlSi is formed.
- a drain electrode made of TiAlSi is also formed on the back surface side of the SiC single crystal substrate through the opening 41 of the support base material. Thereafter, alloy heat treatment is performed.
- a SiO 2 interlayer insulating film having a barrier layer made of SiN is formed on the interlayer insulating film.
- a protective film is formed so as to cover the upper layer wiring.
- the silicon carbide portion (epitaxial layer) covering the end portion of the bonding interface between the support base material and the SiC single crystal substrate (more specifically, the outer peripheral end portion of the stepped portion 42) is removed by dry etching. Thereafter, the surface on which the protective film is formed is fixed to the second support substrate with a heat-resistant tape.
- the sacrificial oxidation step described above also serves as a step of removing the resist-derived carbide that is the bonding layer (that is, the bonding layer is oxidized and removed from the opening 41 side in the sacrificial oxidation step). Therefore, the SiC single crystal substrate can be fixed to the second support base material, and the SiC single crystal substrate can be separated from the first support base material together with the second support base material. Finally, the SiC single crystal substrate is diced into chips. The first support substrate can be reused.
- the thickness of the first support base material is about 70 ⁇ m. Therefore, as described above, the first support base can be easily formed into chips (for example, with a laser) without removing the first support base from the SiC single crystal substrate.
- a vertical device as shown in FIG. 32 can be formed.
- a semiconductor device 101 according to the present invention is a vertical DiMOSFET (Double Implanted MOSFET), and includes a single crystal substrate 1, a buffer layer 121, a breakdown voltage holding layer 122, a p region 123, an n + region 124, p + region 125, oxide film 126, source electrode 111 and upper source electrode 127, gate electrode 110, and drain electrode 112 formed on the back side of single crystal substrate 1.
- a vertical DiMOSFET Double Implanted MOSFET
- buffer layer 121 made of silicon carbide is formed on the surface of single crystal substrate 1 made of silicon carbide of n-type conductivity.
- single crystal substrate 1 the silicon carbide substrate of the present invention including single crystal substrate 1 described in the first to fourth embodiments is employed.
- buffer layer 121 is formed on the main surface of single crystal substrate 1.
- Buffer layer 121 has n-type conductivity, and its thickness is, for example, 0.5 ⁇ m. Further, the concentration of the n-type conductive impurity in the buffer layer 121 can be set to 5 ⁇ 10 17 cm ⁇ 3 , for example.
- a breakdown voltage holding layer 122 is formed on the buffer layer 121.
- the breakdown voltage holding layer 122 is made of silicon carbide of n-type conductivity, and has a thickness of 10 ⁇ m, for example.
- concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 for example, a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
- p regions 123 having a p-type conductivity are formed at intervals. Inside the p region 123, an n + region 124 is formed in the surface layer of the p region 123. A p + region 125 is formed at a position adjacent to the n + region 124. From the n + region 124 in one p region 123 to the p region 123, the breakdown voltage holding layer 122 exposed between the two p regions 123, the other p region 123, and the n + region 124 in the other p region 123 An oxide film 126 is formed so as to extend to. A gate electrode 110 is formed on the oxide film 126.
- n + regions 124 and p + region 125 source electrode 111 is formed thereon.
- An upper source electrode 127 is formed on the source electrode 111.
- a drain electrode 112 is formed on the back surface of the substrate 102 which is the surface opposite to the surface on which the buffer layer 121 is formed.
- the silicon carbide substrate of the present invention such as the single crystal substrate 1 described in the first to fourth embodiments is employed as the single crystal substrate 1. That is, semiconductor device 101 is formed on single crystal substrate 1 as a silicon carbide substrate, buffer layer 121 and breakdown voltage holding layer 122 as epitaxial layers formed on single crystal substrate 1, and breakdown voltage holding layer 122. And a source electrode 111.
- the single crystal substrate 1 is the silicon carbide substrate of the present invention.
- the silicon carbide substrate of the present invention is joined to the support base material 20 (see, for example, FIG. 4 and FIG. 13) in the epitaxial layer forming step or the like, the thickness can be sufficiently reduced. . Therefore, the semiconductor device 101 is a semiconductor device with reduced on-resistance.
- a method for manufacturing the semiconductor device 101 shown in FIG. 32 will be briefly described.
- single crystal substrate 1 for example, see FIG. 2 made of silicon carbide having a (03-38) plane as a main surface is prepared.
- the silicon carbide substrate of the present invention including the single crystal substrate 1 described in the first to fourth embodiments is prepared.
- this single crystal substrate for example, a substrate having an n-type conductivity and a substrate resistance of 0.02 ⁇ cm may be used.
- buffer layer 121 is formed on the surface of single crystal substrate 1.
- Buffer layer 121 is formed on the main surface of single crystal substrate 1.
- Buffer layer 121 is formed of an n-type silicon carbide, and an epitaxial layer having a thickness of 0.5 ⁇ m, for example, is formed.
- concentration of the conductive impurity in the buffer layer 121 for example, a value of 5 ⁇ 10 17 cm ⁇ 3 can be used.
- the breakdown voltage holding layer 122 is formed on the buffer layer 121.
- breakdown voltage holding layer 122 a layer made of silicon carbide of n-type conductivity is formed by an epitaxial growth method.
- a thickness of the breakdown voltage holding layer 122 for example, a value of 10 ⁇ m can be used.
- concentration of the n-type conductive impurity in the breakdown voltage holding layer 122 for example, a value of 5 ⁇ 10 15 cm ⁇ 3 can be used.
- a step (S60) of forming the semiconductor element shown in FIG. an injection process is first performed. More specifically, the p region 123 is formed by injecting a p-type impurity into the breakdown voltage holding layer 122 using an oxide film formed by photolithography and etching as a mask. Further, after removing the used oxide film, an oxide film having a new pattern is formed again by photolithography and etching. Then, by using the oxide film as a mask, an n-type conductive impurity is implanted into a predetermined region, thereby forming an n + region 124. Further, the p + region 125 is formed by injecting a p-type conductive impurity in the same manner.
- activation annealing is performed.
- this activation annealing treatment for example, argon gas is used as an atmospheric gas, and conditions such as a heating temperature of 1700 ° C. and a heating time of 30 minutes can be used.
- a gate insulating film forming step is performed.
- the oxide film 126 is formed so as to cover the breakdown voltage holding layer 122, the p region 123, the n + region 124, and the p + region 125.
- a condition for forming this oxide film 126 for example, dry oxidation (thermal oxidation) may be performed.
- dry oxidation thermal oxidation
- conditions for this dry oxidation conditions such as a heating temperature of 1200 ° C. and a heating time of 30 minutes can be used.
- a nitrogen annealing step (S150) is performed. Specifically, the annealing process is performed using nitrogen monoxide (NO) as the atmosphere gas. As temperature conditions for the annealing treatment, for example, the heating temperature is 1100 ° C. and the heating time is 120 minutes. As a result, nitrogen atoms are introduced near the interface between the oxide film 126 and the underlying breakdown voltage holding layer 122, p region 123, n + region 124, and p + region 125. Further, after the annealing step using nitrogen monoxide as an atmospheric gas, annealing using argon (Ar) gas which is an inert gas may be performed. Specifically, argon gas may be used as the atmosphere gas, and the heating temperature may be 1100 ° C. and the heating time may be 60 minutes.
- an electrode forming step is performed. Specifically, a resist film having a pattern is formed on the oxide film 126 by using a photolithography method. Using the resist film as a mask, portions of the oxide film located on n + region 124 and p + region 125 are removed by etching. Thereafter, a conductor film such as a metal is formed so as to be in contact with n + region 124 and p + region 125 on the resist film and inside the opening formed in oxide film 126. Thereafter, the conductive film located on the resist film is removed (lifted off) by removing the resist film.
- nickel (Ni) can be used as the conductor. As a result, the source electrode 111 can be obtained.
- argon (Ar) gas which is an inert gas
- heat treatment is performed with a heating temperature of 950 ° C. and a heating time of 2 minutes.
- an upper source electrode 127 is formed on the source electrode 111.
- the gate electrode 110 is formed on the oxide film 126.
- a process (S70) is implemented. Specifically, the drain electrode 112 is formed on the back side of the single crystal substrate 1. In this way, the semiconductor device 101 shown in FIG. 32 can be obtained. That is, the semiconductor device 101 is manufactured by forming an epitaxial layer and an electrode on the main surface of the single crystal substrate 1.
- the semiconductor device is manufactured by forming the epitaxial layer functioning as the operation layer on the silicon carbide substrate having the (03-38) plane as the main surface.
- the crystal plane that can be used as a plane is not limited to this, and any crystal plane according to the application including the (0001) plane can be used as the main plane.
- the manufacturing method of semiconductor element 30 as a semiconductor device includes a step of preparing a single crystal semiconductor member (for example, SiC single crystal substrate 1) (S10), and a step of preparing support substrate 20 (S20).
- the bonding layer 22 is decomposed by being oxidized to form a supporting group.
- the SiC single crystal substrate in the step (S50) 1 can be improved. Further, in the step of forming the semiconductor element (S50), since the processing is performed with the SiC single crystal substrate 1 connected to the support base 20, it is necessary to ensure that the SiC single crystal substrate 1 has a thickness that can stand by itself. The thickness can be determined in consideration of the characteristics (for example, on-resistance) of the final semiconductor element (element 30).
- the thickness of SiC single crystal substrate 1 it is possible to set the thickness of SiC single crystal substrate 1 to a thickness that is lower than the lower limit of the thickness at which it can stand on its own. As a result, a semiconductor device having excellent characteristics (for example, sufficiently low on-resistance) can be realized.
- the bonding layer 22 for bonding the SiC single crystal substrate 1 to the support base 20 contains carbon, it can be easily decomposed by oxidizing the bonding layer 22. For this reason, after forming a semiconductor element (element 30) on SiC single crystal substrate 1, SiC single crystal substrate 1 can be easily separated from support base material 20.
- the carbon-containing bonding layer 22 is preferably a bonding layer containing carbon as a main component.
- a layer obtained by heat-treating (carbonizing) a photoresist, a resin, or the like to be solidified and using substantially solid carbon can be used as the bonding layer 22 .
- Such a bonding layer 22 containing carbon as a main component is sufficiently SiC single crystal substrate if it is not exposed to an oxidizing atmosphere even at a heat treatment temperature (for example, about 1000 ° C.) in the step of forming a semiconductor element (S50). 1 and the support substrate 20 can be kept connected.
- the bonding layer 22 As a material that becomes the bonding layer 22 by heat treatment, for example, phenol resin, glucose, or the like can be used in addition to the above-described photoresist.
- a liquid material such as the above-described photoresist may be used.
- a highly viscous gel material a solid material such as a tape or a film May be used. When such a solid material is used, the material preferably has adhesiveness.
- the heat treatment for forming the bonding layer 22 is preferably a heat treatment that carbonizes the layer to be the bonding layer 22 (for example, a layer containing carbon as a main component).
- conditions such as heat treatment in a vacuum or in an inert gas atmosphere at a heating temperature of 500 ° C. or higher, preferably 700 ° C. or higher for a predetermined time (for example, 30 minutes or more and 90 minutes or less) can be used.
- the protective film (exposing the bonding layer 22) is formed so as to cover the exposed surface of the bonding layer 22.
- a step (S40) of forming the epitaxial layer 23 formed so as to cover the surface may be provided (for example, a step of forming the epitaxial layer 23 described with reference to FIGS. 12 and 13).
- the method for manufacturing the semiconductor device includes a step of removing the protective film (for example, the SiC single layer previously described with reference to FIG. 14) after the step of forming the semiconductor element (S50) and before the step of separating (S60).
- the protective film is preferably made of a material having a higher resistance to the oxidizing atmosphere than the bonding layer 22, and is preferably made of, for example, an oxidation-resistant material.
- the SiC epitaxial film as described above can be used as the protective film, but silicon oxide (SiO 2 or the like), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ) or the like can be used as the other material. it can.
- the protective film may be formed at the same time as the formation of the epitaxial film formed on the SiC single crystal substrate 1 as described in the second embodiment, but an independent process for forming only the protective film. May be implemented. For example, a process of forming a mask layer having an opening pattern that exposes only the surface of the bonding layer 22 and forming a film serving as a protective film may be performed.
- the protective film exists, it is possible to prevent the processing atmosphere in the step of forming the semiconductor element (S50) from directly touching the bonding layer 22. Therefore, even if an atmosphere that decomposes the bonding layer 22 is used in the step of forming the semiconductor element (S50), the bonding layer 22 can be prevented from being damaged. Further, since the protective film is removed before the separation step, the bonding layer 22 can be reliably decomposed and removed in the separation step (S60).
- the step of forming a semiconductor element may include a step of applying a photoresist on the epitaxial layer 23.
- a photoresist on the epitaxial layer 23.
- either a roller coating method or a nozzle spray coating method may be used.
- the spin coating method can be used as long as it is a roller coating method or a nozzle spray coating method as described above. Rather than using it, the photoresist can be surely and uniformly arranged on the epitaxial layer formed on the upper surface (main surface) of SiC single crystal substrate 1.
- the support base material 20 from which the SiC single crystal substrate 1 has been separated in the separation step (S60) is reused as the support base material prepared in the step of preparing the support base material (S20). May be.
- the support base material 20 can be reused, the manufacturing cost of the semiconductor device can be reduced as compared with the case where the support base material 20 is made disposable.
- the method for manufacturing a bonded substrate according to the present invention includes a step of preparing a single crystal semiconductor member (SiC single crystal substrate 1) (S10), a step of preparing a support base 20 (S20), and a support base 20 And the SiC single crystal substrate 1 are bonded to each other via a bonding layer 22 containing carbon (S30).
- the handling property as the bonded substrate 21 is kept good even if the thickness of the SiC single crystal substrate 1 is reduced. Can do.
- the semiconductor element (element 30) is formed on the SiC single crystal substrate 1 of the bonded substrate 21, the processing is performed in a state where the SiC single crystal substrate 1 is connected to the support base 20, so that the SiC single crystal
- the thickness of substrate 1 does not necessarily have to be a self-supporting thickness, and the thickness of SiC single crystal substrate 1 can be determined in consideration of the final semiconductor element characteristics (for example, on-resistance).
- the thickness of SiC single crystal substrate 1 it is possible to set the thickness of SiC single crystal substrate 1 to a thickness that is lower than the lower limit of the thickness that can stand by itself.
- a bonded substrate 21 capable of manufacturing a semiconductor device having excellent characteristics (for example, sufficiently low on-resistance) can be obtained.
- the bonding layer 22 for bonding a single crystal semiconductor member such as the SiC single crystal substrate 1 to the support base 20 contains carbon, it can be easily decomposed by oxidizing the bonding layer 22. For this reason, the SiC single crystal substrate 1 and the like can be easily separated from the support base material 20.
- the thickness of the single crystal semiconductor member may be 100 ⁇ m or less, and the carrier concentration of the SiC single crystal substrate 1 is 1 ⁇ . It may be 10 18 cm ⁇ 3 or more.
- the thickness of the SiC single crystal substrate 1 is preferably 50 ⁇ m or less.
- the electrical resistance in the thickness direction of SiC single crystal substrate 1 can be kept sufficiently low (for example, 0.5 m ⁇ cm 2 or less). For this reason, the manufacturing method of the semiconductor device using the bonded substrate 21 can realize a semiconductor device in which the electrical resistance in the vertical direction can be sufficiently lowered and the loss can be sufficiently reduced as a result.
- the method for manufacturing the bonded substrate includes a protective film (on the boundary between the lower end surface of the SiC single crystal substrate 1 and the upper surface of the support base 20 so as to cover the exposed surface of the bonding layer 22).
- the method may further comprise a step of forming an epitaxial layer 23) formed in step (b).
- the protective film (SiC epitaxial layer 23) is preferably made of a material having a higher resistance to an oxidizing atmosphere than the bonding layer 22, and is preferably made of an oxidation-resistant material, for example.
- the protective film since the protective film is formed, it is possible to prevent the processing atmosphere from directly touching the bonding layer 22 when the semiconductor device is formed using the bonded substrate 21. Therefore, even if an atmosphere (for example, an oxidizing atmosphere) that decomposes the bonding layer 22 is used in the process of forming the semiconductor device, the bonding layer 22 can be prevented from being damaged.
- the material constituting the protective film is selected from the group consisting of silicon carbide (SiC), silicon oxide, silicon nitride, and aluminum oxide (Al 2 O 3 ). At least one of them may be included.
- SiC silicon carbide
- SiO silicon oxide
- silicon nitride silicon nitride
- Al 2 O 3 aluminum oxide
- all of the above-described materials are oxidation-resistant materials that can withstand relatively high temperatures (for example, about 1000 ° C.), and are sufficiently durable when a semiconductor device is formed using the bonded substrate 21. Showing gender. Therefore, the bonding layer 22 can be reliably protected.
- the protective film may be made of the same material (SiC) as the material constituting the single crystal semiconductor member (SiC single crystal substrate 1).
- silicon carbide SiC
- silicon carbide can also be used as the protective film.
- the protective film made of silicon carbide is simultaneously formed. Can be formed. Therefore, it is not necessary to carry out the step of forming only the protective film separately from the step of forming the epitaxial layer (S40). Therefore, when the semiconductor device is manufactured, an increase in the number of manufacturing steps can be suppressed.
- the step of preparing a single crystal semiconductor member (S10) includes the step of forming the support base material 20 and the bonding layer 22 in the single crystal semiconductor member (SiC single crystal substrate 1). There may be included a step of forming a metal layer (a conductor layer to be the back electrode 26) on the surface to be bonded through (step (S70) in FIG. 27).
- a metal layer (a metal layer to be the back electrode 26 shown in FIGS. 28 and 29) is formed in advance on the surface (back surface) to be bonded to the support base material 20 of the SiC single crystal substrate 1. Therefore, when the manufacturing method of the semiconductor device is performed using the bonded substrate 21, the ohmic junction is formed at the portion where the SiC single crystal substrate 1 and the metal layer are in contact with each other by the heat treatment in the manufacturing method. For this reason, in the semiconductor device formed using the bonded substrate 21, the metal layer can be used as the back electrode 26.
- a device structure is formed on the SiC single crystal substrate 1, and then the support base 20 is removed from the SiC single crystal substrate 1, and then an electrode is formed on the back surface.
- the (back electrode 26) it is not necessary to separately perform heat treatment for forming an ohmic junction after the metal layer to be the electrode is formed (or when heat treatment is separately required). However, the processing temperature of the heat treatment can be reduced).
- the single crystal semiconductor member (SiC single crystal substrate 1) is prepared.
- the bonding step (S30) a plurality of single crystal semiconductor members (SiC single crystal substrate 1) may be bonded to the support base 20 via the bonding layer 22.
- a plurality of single crystal semiconductor members (SiC single crystal substrates 1) may be arranged side by side on the surface of the support base 20. Further, it is preferable to form a gap between two adjacent single crystal semiconductor members (SiC single crystal substrate 1) as shown in FIG.
- the step (S60) of separating the single crystal semiconductor member in the method for manufacturing a semiconductor device an oxidizing atmosphere such as oxygen plasma can surely reach the bonding layer 22 through the gap. For this reason, the single crystal semiconductor member (SiC single crystal substrate 1) can be reliably separated from the support base material 20 in the separation step (S60).
- the planar shape of the support base material 20 may be a quadrangular shape as described in the second embodiment. Furthermore, the planar shape of the single crystal semiconductor member (SiC single crystal substrate 1) is also preferably a square shape.
- the planar shape of the support base 20 may be a polygonal shape such as a circular shape, a triangle other than a quadrangle, or a pentagon.
- it is preferable that a plurality of single crystal semiconductor members (SiC single crystal substrates 1) are bonded to the support base material 20 via the bonding layer 22, as described in the second and third embodiments.
- planar shape of support base 20 and the planar shape of single crystal semiconductor member (SiC single crystal substrate 1) may be similar, or may be polygons having the same number of angles.
- the single crystal semiconductor members (SiC single crystal substrate 1) are attached to the corners of the support base material 20. It becomes possible to join side by side. For this reason, since the number of SiC single crystal substrates 1 which can be processed at a time can be increased, a semiconductor device can be manufactured efficiently. (Alternatively, a bonded substrate 21 capable of efficiently manufacturing a semiconductor device can be obtained).
- planar shape of the support base 20 and the single crystal semiconductor member (SiC single crystal substrate 1) is a quadrangular shape as described above, the planar shape of the semiconductor device to be manufactured is often a quadrangular shape.
- the number of semiconductor devices obtained from one single crystal semiconductor member (SiC single crystal substrate 1) is increased as compared with the case where the planar shape of the single crystal semiconductor member (SiC single crystal substrate 1) is circular and the area is substantially the same. Can do.
- the material constituting the single crystal semiconductor member exemplified by the SiC single crystal substrate 1 includes either silicon carbide (SiC) or a nitride semiconductor. May be.
- the material constituting the support substrate 20 may include at least one selected from the group consisting of silicon carbide (SiC), alumina (Al 2 O 3 ), sapphire, silicon (Si), and silicon nitride. In the case of using such a material, it is possible to maintain a connection state with the bonding layer 22 containing carbon even in a relatively high temperature environment and to withstand a high temperature process.
- the support base 20 has a through hole (opening 41) in which a single crystal semiconductor member (SiC single crystal substrate 1) can be disposed. May be formed.
- the single crystal semiconductor member (SiC single crystal substrate 1) is disposed inside the opening 41 of the support base 20 (for example, the step portion 42 shown in FIGS. 22 and 23), the single crystal semiconductor member (SiC The bonding layer 22 is arranged on the outer periphery of the single crystal substrate 1) (the portion facing the inner wall of the stepped portion 42 of the opening 41).
- the separation step (S60) in the method for manufacturing a semiconductor device an oxidizing atmosphere can easily reach the bonding layer 22, so that the bonding layer 22 can be reliably decomposed. Therefore, the single crystal semiconductor member (SiC single crystal substrate 1) can be reliably separated from the support base 20 in the separation step (S60).
- the semiconductor device includes a supporting base 20 and a single crystal semiconductor layer (formed on the surfaces of the SiC single crystal substrate 1 and the SiC single crystal substrate 1, and the SiC single crystal substrate). 1 and an epitaxial layer positioned between the gate electrode 11 and an electrode (source electrode 10, gate electrode 11, drain electrode 12).
- the single crystal semiconductor layer (SiC single crystal substrate 1 and the epitaxial layer) is bonded onto the surface of support base 20 via bonding layer 22 containing carbon.
- the electrode is formed on the single crystal semiconductor layer (SiC single crystal substrate 1 and the epitaxial layer).
- the single crystal semiconductor layer includes a single crystal semiconductor member (SiC single crystal substrate 1) bonded to the surface of the support base 20 via the bonding layer 22 as described above, and the single crystal semiconductor member (SiC single member). Although it may include an epitaxial layer formed on the surface of the crystal substrate 1), it may be composed of only a single crystal semiconductor member (SiC single crystal substrate 1).
- the support base 20 may be made of a conductive material.
- the ground electrode of the semiconductor device can be formed on the back surface side of the single crystal semiconductor layer (the surface on the support substrate 20 side in the SiC single crystal substrate 1) (from the back surface side to the semiconductor).
- the equipment can be grounded).
- the bonding layer 22 containing carbon is preferably a bonding layer 22 containing carbon as a main component, and preferably has conductivity.
- the bonding layer 22 containing carbon as a main component means a bonding layer having a carbon content of 50% or more by volume%.
- the material constituting the single crystal semiconductor layer may contain either silicon carbide (SiC) or a nitride semiconductor (for example, GaN).
- the material constituting the support base 20 may include at least one selected from the group consisting of silicon carbide (SiC), alumina, sapphire, silicon, and silicon nitride. When such a material is used, it is possible to maintain a connection state with the bonding layer containing carbon even in a relatively high temperature environment and to withstand a high temperature process.
- the bonded substrate 21 includes a support base 20 and a single crystal semiconductor member (SiC single crystal substrate 1).
- the single crystal semiconductor member (SiC single crystal substrate 1) is bonded onto the surface of the support base 20 via a bonding layer 22 containing carbon.
- the supporting base material 20 is bonded to the single crystal semiconductor member (SiC single crystal substrate 1), it is attached even if the thickness of the single crystal semiconductor member (SiC single crystal substrate 1) is reduced.
- the handling property as the laminated substrate 21 can be kept good.
- the single crystal semiconductor member (SiC single crystal substrate 1) is connected to the support base 20. Since the processing is performed, it is not always necessary to secure a self-supporting thickness as the thickness of the single crystal semiconductor member (SiC single crystal substrate 1). It can be determined in consideration.
- the thickness of the single crystal semiconductor member (SiC single crystal substrate 1) can be set to a thickness that is lower than the lower limit of the thickness that can stand by itself.
- the bonded substrate 21 according to the present invention a semiconductor device having excellent characteristics (for example, sufficiently low on-resistance) can be realized.
- the bonding layer 22 for bonding the single crystal semiconductor member (SiC single crystal substrate 1) to the support base 20 contains carbon, the bonding layer 22 can be easily decomposed by oxidizing the bonding layer 22. . Therefore, the single crystal semiconductor member (SiC single crystal substrate 1) can be easily separated from the support base material 20.
- the bonded substrate 21 further includes an epitaxial layer (such as the epitaxial layer 23 in FIG. 13 or the p ⁇ -type epitaxial layer 2 in FIG. 30) formed on the surface of the single crystal semiconductor layer (SiC single crystal substrate 1). It may be.
- the bonded substrate 21 suitable for manufacturing the semiconductor device can be realized by forming the epitaxial layer so as to match the characteristics of the semiconductor device desired to be manufactured.
- the thickness of the single crystal semiconductor member (SiC single crystal substrate 1) may be 100 ⁇ m or less, and the carrier concentration of the single crystal semiconductor member (SiC single crystal substrate 1) is 1 ⁇ 10 18 cm. it may be 3 or more.
- the thickness of the single crystal semiconductor member (SiC single crystal substrate 1) is preferably 50 ⁇ m or less. In this case, when a semiconductor element is formed on the single crystal semiconductor member (SiC single crystal substrate 1), the mobility in the single crystal semiconductor member (SiC single crystal substrate 1) decreases due to the carrier concentration as described above (for example, 100 cmV / s).
- the electric resistance in the thickness direction of the single crystal semiconductor member (SiC single crystal substrate 1) is a sufficiently low value. (For example, 0.5 m ⁇ cm 2 or less). Therefore, by using the bonded substrate 21, the electrical resistance in the vertical direction can be sufficiently reduced in the semiconductor device, and as a result, the loss in the semiconductor device can be sufficiently reduced.
- the bonded substrate 21 is a protective film formed so as to cover the exposed surface of the bonding layer 22 (an epitaxial layer that covers the boundary between the end surface of the SiC single crystal substrate 1 and the surface of the support base 20 shown in FIG. 13). 23) may be provided.
- the protective film exists, it is possible to prevent the processing atmosphere from directly touching the bonding layer 22 when the semiconductor device is formed using the bonded substrate 21. Therefore, even if an atmosphere (for example, an oxidizing atmosphere) that decomposes the bonding layer 22 is used in the process of forming the semiconductor device, the bonding layer 22 can be prevented from being damaged.
- the material constituting the protective film may include at least one selected from the group consisting of silicon carbide (SiC), silicon oxide, silicon nitride, and aluminum oxide.
- SiC silicon carbide
- silicon oxide silicon oxide
- silicon nitride silicon oxide
- aluminum oxide aluminum oxide
- all of the above-described materials are oxidation-resistant materials that can withstand relatively high temperatures (for example, about 1000 ° C.), and are sufficiently durable when a semiconductor device is formed using the bonded substrate 21. Showing gender. Therefore, the bonding layer 22 can be reliably protected.
- the bonded substrate 21 is a metal formed on a surface (back surface) bonded to the support base material 20 via the bonding layer 22 in the single crystal semiconductor member (SiC single crystal substrate 1).
- a layer (back electrode 26) may be further provided.
- the metal layer (back electrode 26) is formed in advance on the surface (back surface) to be bonded to the support base material 20 of the single crystal semiconductor member (SiC single crystal substrate 1), the above bonding is performed.
- a semiconductor device is manufactured using the substrate 21, an ohmic junction is formed at a portion where the single crystal semiconductor member (SiC single crystal substrate 1) and the metal layer (back electrode 26) are in contact with each other by heat treatment in the manufacturing process of the semiconductor device. Is formed. For this reason, in the semiconductor device formed using the bonded substrate 21, the metal layer (back electrode 26) can be used as an electrode.
- a plurality of single crystal semiconductor members (SiC single crystal substrate 1) are bonded to the support base material 20 through the bonding layer 22.
- a plurality of single crystal semiconductor members (SiC single crystal substrate 1) may be arranged side by side on the surface of the support base 20.
- an oxidizing atmosphere such as oxygen plasma reliably reaches the bonding layer 22 through the gap. it can. For this reason, the single crystal semiconductor member (SiC single crystal substrate 1) can be reliably separated from the support base material 20.
- the planar shape of the support base material 20 may be a quadrangular shape as shown in FIGS.
- a plurality of single crystal semiconductor members (SiC single crystal substrates 1) are bonded to the support base material 20 via the bonding layer 22.
- the planar shape of the single crystal semiconductor member (SiC single crystal substrate 1) is also preferably a square shape.
- the single crystal semiconductor members (SiC single crystal substrate 1) are attached to the corners of the support base material 20. It becomes possible to join side by side. For this reason, since the number of the single crystal semiconductor members (SiC single crystal substrate 1) which can be processed at a time can be increased, the bonded substrate 21 which can manufacture a semiconductor device efficiently is realizable.
- the material constituting the single crystal semiconductor member may contain either silicon carbide or a nitride semiconductor.
- the material constituting the support substrate 20 may include at least one selected from the group consisting of silicon carbide, alumina, sapphire, silicon, and silicon nitride. When such a material is used, the connection state between the bonding layer 22 containing carbon, the single crystal semiconductor member (SiC single crystal substrate 1), and the support base material 20 can be maintained even in a relatively high temperature environment. A bonded substrate 21 capable of withstanding high temperature processes can be realized.
- a through hole (opening 41) may be formed in the support base 20 as shown in FIGS. 19 to 23.
- the single crystal semiconductor member (SiC single crystal substrate 1) may be disposed inside the through hole (inside the step portion 42 of the opening 41).
- the single crystal semiconductor member (SiC single crystal substrate 1) is disposed in the step portion 42 in the opening 41 of the support base material 20, the outer periphery of the single crystal semiconductor member (step portion in the SiC single crystal substrate 1).
- the bonding layer 22 is disposed on a portion facing the inner wall of 42. Therefore, when the single crystal semiconductor member (SiC single crystal substrate 1) and the support base material 20 are separated, an oxidizing atmosphere can easily reach the bonding layer 22, so that the bonding layer 22 is reliably decomposed. Can do.
- a countersink (recess) for facilitating positioning of SiC single crystal substrate 1 may be formed in advance on the surface of support base 20.
- the concave portion has a planar shape corresponding to the planar shape of SiC single crystal substrate 1 and has a size capable of disposing the back surface of SiC single crystal substrate 1 therein.
- bonding layer 22 disposed between SiC single crystal substrate 1 and support base material 20 is disposed on the entire surface (bonding interface) between SiC single crystal substrate 1 and support base material 20.
- bonding interface for example, as shown in FIGS. 8 and 16, only the outer peripheral part of the bonding interface, only a part of the outer peripheral part, only the central part of the bonding interface, or the bonding interface 1 or a plurality of any of them).
- the present invention is particularly advantageous for a bonded substrate configured by bonding a single crystal semiconductor member such as a SiC single crystal substrate or a GaN single crystal substrate to a supporting base material, and a semiconductor device manufactured using the bonded substrate. Applied.
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Abstract
Description
図1~図7を参照して、本発明による半導体装置の製造方法を説明する。
図10~図15を参照して、本発明による半導体装置の製造方法の実施の形態2を説明する。
図18~図26を参照して、本発明による半導体装置の製造方法の実施の形態3を説明する。
図27~図29を参照して、本発明による半導体装置の製造方法の実施の形態4を説明する。
図30および図31を参照して、本発明による半導体装置および半導体装置の製造方法の実施の形態5を説明する。なお、図31は、図30に示した半導体装置を製造する方法を説明するためのフローチャートである。
以下、上述した実施の形態1に対応する実施例としての半導体装置の製造方法について説明する。まず、昇華法により成長した2インチ炭化珪素単結晶インゴットを、厚さ100μmでスライスすることにより、SiC単結晶基板1となるべき基板を切り出す。当該基板の主表面の1つ(片面)を機械研磨により鏡面仕上げを行った後、当該鏡面仕上げ面上にTiAlSi膜をスパッタリング法により形成する。
以下、上述した実施の形態2に対応する実施例としての半導体装置の製造方法について説明する。まず、昇華法により成長した炭化珪素単結晶インゴットを整形して、縦20mm、横40mm、厚さ100μmの矩形単結晶材であるSiC単結晶基板を切り出す。当該SiC単結晶基板の片面を機械研磨により鏡面仕上げとする。その鏡面仕上げされた表面(裏面)に、TiAlSi膜をスパッタリングによる形成する。
以下、上述した実施の形態3に対応する実施例としての半導体装置の製造方法について説明する。まず、昇華法により成長した炭化珪素単結晶インゴットを整形して、縦20mm、横40mm、厚さ100μmの矩形単結晶材であるSiC単結晶基板を切り出す。切り出す面は(0001)面から54.7度傾けた面である{03-38}面である。
次に、SiC単結晶基板を支持基材に貼り合せた状態で、SiC単結晶基板の未研磨面を研削と機械研磨とにより、支持基材の表面と同じ高さになるまでラッピング、ポリッシングを行なう。そして、最後にコロイダルシリカを用いて化学的機械研磨(CMP)法により当該研磨面に対して仕上げ研磨を行う。この結果、図23に示すような構造を得る。
次に、図32に示した半導体装置101の製造方法を簡単に説明する。まず、図1などに示した単結晶半導体部材を準備する工程(S10)を実施する。ここでは、たとえば(03-38)面が主面となった炭化珪素からなる単結晶基板1(たとえば図2参照)を準備する。この単結晶基板1としては、上記実施の形態1~4において説明した単結晶基板1を含む上記本発明の炭化珪素基板が準備される。
次に、たとえば図1に示した工程(S20)および工程(S30)を実施した後、エピタキシャル層を形成する工程(S40)を実施する。具体的には、単結晶基板1の表面上にバッファ層121を形成する。このバッファ層121は、単結晶基板1の主表面上に形成される。バッファ層121としては、導電型がn型の炭化珪素からなり、たとえばその厚みが0.5μmのエピタキシャル層を形成する。バッファ層121における導電型不純物の濃度は、たとえば5×1017cm-3といった値を用いることができる。そして、このバッファ層121上に、耐圧保持層122を形成する。この耐圧保持層122としては、導電型がn型の炭化珪素からなる層をエピタキシャル成長法によって形成する。この耐圧保持層122の厚みとしては、たとえば10μmといった値を用いることができる。また、この耐圧保持層122におけるn型の導電性不純物の濃度としては、たとえば5×1015cm-3といった値を用いることができる。
Claims (27)
- 単結晶半導体部材(1)を準備する工程(S10)と、
支持基材(20)を準備する工程(S20)と、
前記支持基材(20)と前記単結晶半導体部材(1)とを、炭素を含む接合層(22)を介して接合する工程(S30)と、
前記単結晶半導体部材(1)の表面にエピタキシャル層(23)を形成する工程(S40)と、
前記エピタキシャル層(23)を利用して半導体素子を形成する工程(S50)と、
前記半導体素子を形成する工程(S50)の後、前記接合層(22)を酸化することにより分解して前記支持基材(20)から前記単結晶半導体部材(1)を分離する工程(S60)と、
前記支持基材(20)から分離された前記単結晶半導体部材(1)を分割する工程(S80)とを備える、半導体装置の製造方法。 - 前記単結晶半導体部材(1)の厚みが100μm以下であり、キャリア濃度が1×1018cm-3以上である、請求項1に記載の半導体装置の製造方法。
- 前記接合する工程(S30)の後であって前記半導体素子を形成する工程(S50)の前に、前記接合層(22)の露出面を覆うように保護膜(23)を形成する工程(S40)と、
前記半導体素子を形成する工程(S50)の後であって前記分離する工程(S60)の前に、前記保護膜(23)を除去する工程とを備える、請求項1に記載の半導体装置の製造方法。 - 前記保護膜(23)を構成する材料は、炭化珪素、酸化珪素、窒化珪素、酸化アルミニウムからなる群から選択される少なくとも1つを含む、請求項3に記載の半導体装置の製造方法。
- 前記単結晶半導体部材(1)を準備する工程(S10)では、前記単結晶半導体部材(1)において前記支持基材(20)と接合層(22)を介して接合される面上に金属層を形成する工程(S70)を含む、請求項1に記載の半導体装置の製造方法。
- 前記単結晶半導体部材(1)を準備する工程(S10)では、前記単結晶半導体部材(1)を複数準備し、
前記接合する工程(S30)では、複数の前記単結晶半導体部材(1)を前記支持基材(20)に前記接合層(22)を介して接合する、請求項1に記載の半導体装置の製造方法。 - 前記半導体素子を形成する工程(S50)は、前記エピタキシャル層(23)上にフォトレジストを塗布する工程を含み、
前記フォトレジストを塗布する工程では、ローラ塗布方法およびノズル噴射塗布方法のいずれかを用いる、請求項1に記載の半導体装置の製造方法。 - 前記支持基材(20)の平面形状が四角形状である、請求項1に記載の半導体装置の製造方法。
- 前記単結晶半導体部材(1)を構成する材料は、炭化珪素および窒化物半導体のいずれかを含み、
前記支持基材(20)を構成する材料は、炭化珪素、アルミナ、サファイア、珪素、窒化珪素からなる群から選択される少なくとも1つを含む、請求項1に記載の半導体装置の製造方法。 - 前記分離する工程(S60)において前記単結晶半導体部材(1)が分離された前記支持基材(20)は、前記支持基材(20)を準備する工程(S20)において準備される支持基材(20)として再利用される、請求項1に記載の半導体装置の製造方法。
- 前記支持基材(20)には、前記単結晶半導体部材(1)を内部に配置することが可能な貫通孔(41)が形成されている、請求項1に記載の半導体装置の製造方法。
- 単結晶半導体部材(1)を準備する工程(S10)と、
支持基材(20)を準備する工程(S20)と、
前記支持基材(20)と前記単結晶半導体部材(1)とを、炭素を含む接合層(22)を介して接合する工程(S30)とを備える、貼り合せ基板の製造方法。 - 前記単結晶半導体部材(1)の厚みが100μm以下であり、キャリア濃度が1×1018cm-3以上である、請求項12に記載の貼り合せ基板の製造方法。
- 前記接合層(22)の露出面を覆うように保護膜(23)を形成する工程をさらに備える、請求項12に記載の貼り合せ基板の製造方法。
- 前記単結晶半導体部材(1)を準備する工程(S10)では、前記単結晶半導体部材(1)において前記支持基材(20)と接合層(22)を介して接合される面上に金属層を形成する工程(S70)を含む、請求項12に記載の貼り合せ基板の製造方法。
- 前記単結晶半導体部材(1)を準備する工程(S10)では、前記単結晶半導体部材(1)を複数準備し、
前記接合する工程(S30)では、複数の前記単結晶半導体部材(1)を前記支持基材(20)に前記接合層(22)を介して接合する、請求項12に記載の貼り合せ基板の製造方法。 - 前記単結晶半導体部材(1)を構成する材料は、炭化珪素および窒化物半導体のいずれかを含み、
前記支持基材(20)を構成する材料は、炭化珪素、アルミナ、サファイア、珪素、窒化珪素からなる群から選択される少なくとも1つを含む、請求項12に記載の貼り合せ基板の製造方法。 - 支持基材(20)と、
前記支持基材(20)の表面上に、炭素を含む接合層(22)を介して接合された単結晶半導体層と、
前記単結晶半導体層上に形成された電極(10、11、12)とを備える、半導体装置。 - 前記支持基材(20)が導電性材料により構成されている、請求項18に記載の半導体装置。
- 前記単結晶半導体層を構成する材料は、炭化珪素および窒化物半導体のいずれかを含み、
前記支持基材(20)を構成する材料は、炭化珪素、アルミナ、サファイア、珪素、窒化珪素からなる群から選択される少なくとも1つを含む、請求項18に記載の半導体装置。 - 支持基材(20)と、
前記支持基材(20)の表面上に、炭素を含む接合層(22)を介して接合された単結晶半導体部材(1)とを備える、貼り合せ基板。 - 前記単結晶半導体部材(1)の表面上に形成されたエピタキシャル層(23)をさらに備える、請求項21に記載の貼り合せ基板。
- 前記単結晶半導体部材(1)の厚みが100μm以下であり、キャリア濃度が1×1018cm-3以上である、請求項21に記載の貼り合せ基板。
- 前記接合層(22)の露出面を覆うように形成された保護膜(23)を備える、請求項21に記載の貼り合せ基板。
- 前記単結晶半導体部材(1)において前記支持基材(20)と接合層(22)を介して接合される面上に形成された金属層をさらに備える、請求項21に記載の貼り合せ基板。
- 前記支持基材(20)には、前記接合層(22)を介して複数の前記単結晶半導体部材(1)が接合されている、請求項21に記載の貼り合せ基板。
- 前記単結晶半導体部材(1)を構成する材料は、炭化珪素および窒化物半導体のいずれかを含み、
前記支持基材(20)を構成する材料は、炭化珪素、アルミナ、サファイア、珪素、窒化珪素からなる群から選択される少なくとも1つを含む、請求項21に記載の貼り合せ基板。
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JP2013118211A (ja) * | 2011-12-01 | 2013-06-13 | Tokyo Electron Ltd | 基板収納容器 |
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