WO2011135670A1 - Method of manufacturing substrate with built-in part, and substrate with built-in part using same - Google Patents

Method of manufacturing substrate with built-in part, and substrate with built-in part using same Download PDF

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Publication number
WO2011135670A1
WO2011135670A1 PCT/JP2010/057459 JP2010057459W WO2011135670A1 WO 2011135670 A1 WO2011135670 A1 WO 2011135670A1 JP 2010057459 W JP2010057459 W JP 2010057459W WO 2011135670 A1 WO2011135670 A1 WO 2011135670A1
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WIPO (PCT)
Prior art keywords
connection
component
conductive layer
manufacturing
substrate
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PCT/JP2010/057459
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French (fr)
Japanese (ja)
Inventor
戸田光昭
清水良一
長谷川琢哉
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株式会社メイコー
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Priority to PCT/JP2010/057459 priority Critical patent/WO2011135670A1/en
Publication of WO2011135670A1 publication Critical patent/WO2011135670A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/568—Temporary substrate used as encapsulation process aid
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0266—Marks, test patterns or identification means
    • H05K1/0269—Marks, test patterns or identification means for visual or optical inspection
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09063—Holes or slots in insulating substrate not used for electrical connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20—Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036—Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/16—Inspection; Monitoring; Aligning
    • H05K2203/166—Alignment or registration; Control of registration
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/382—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal
    • H05K3/383—Improvement of the adhesion between the insulating substrate and the metal by special treatment of the metal by microetching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method of manufacturing a component-embedded substrate in which an electrical component or an electronic component is embedded in an insulating base material, and a component-embedded substrate using the same.
  • a component-embedded substrate is disclosed in Patent Document 1.
  • the component-embedded substrate described in Patent Document 1 is connected to an insulating base material, conductor circuits formed on both sides thereof, embedded in the insulating base material, and a terminal portion connected to a connection terminal portion provided on the substrate side. And an electronic component connected to the conductor circuit.
  • Patent Document 1 describes an example in which a connection terminal portion for connecting to a connection terminal of the component-embedded substrate is formed using a solder resist layer.
  • solder resist layer is formed by exposure, development, ultraviolet curing or thermal curing after screen printing. For this reason, adhesiveness with the prepreg which forms a board
  • the present invention is based on the above prior art, and can enhance the adhesion between an insulating base material such as a prepreg that forms a substrate and a conductive layer such as a copper foil, and these can be reliably laminated by pressing. It is an object of the present invention to provide a component built-in substrate manufacturing method and a component built-in substrate using the same.
  • a conductive layer is formed on a support plate, and the conductive layer is formed except for a connection region to be electrically connected to a connection terminal of an electrical or electronic component.
  • a connection region forming step of forming a mask layer covering the layer, a preparation step of providing a connection surface with the connection terminal in the connection region, a mask layer removal step of removing the mask layer, and the conductive layer on the conductive layer Disposing a resin insulating base material in a state in which the component is sandwiched between the conductive layer and a connection step in which the component is disposed and the connection surface of the connection region and the connection terminal are connected via a connection material.
  • the conductive layer and the insulating base material are pressed against each other, the pressing step of embedding the component in the insulating base material, and pattern formation for removing a part of the conductive layer to form a conductor pattern
  • a step of the press step Prior to facilities, to provide a method of manufacturing a component-embedded substrate, characterized in that it comprises a roughening treatment step of providing the connection surface rough rough surface than in the region other than the connection region of the conductive layer.
  • the preparation step is performed by placing a plate-shaped gold plating pad having a flat surface to be the connection surface on the connection region, and the roughening treatment step is performed after the preparation step. Is done.
  • the roughening treatment step is performed prior to forming the mask layer, and the preparatory step is such that the surface to be the connection surface is flat in the roughened connection region.
  • a plate-shaped gold plating pad is placed on the connection region.
  • the roughening step is performed prior to forming the mask layer, and the preparation step includes soft etching, microetching, acid cleaning, or plasma etching in the roughened connection region.
  • the connecting material is preferably solder or a conductive paste.
  • a spacer layer at a position corresponding to a position where the electrical or electronic component is to be placed before forming the mask layer.
  • a component built-in board using the manufacturing method of the component built-in board of Claim 2 Comprising: The said gold
  • a component-embedded substrate comprising a plating pad and the conductor pattern covering the gold plating pad.
  • the conductor pattern is formed in the pattern forming step.
  • the contact surface with the insulating base material is roughened.
  • the conductive layer and the insulating base material that have been pressed together in the pressing step have been subjected to a roughening treatment on the surface (pressure contact surface) of the conductive layer, so that the adhesive force is strong and it is difficult to peel off. Is done. Therefore, since the conductive pattern which is a part left after removing a part of the conductive layer also has a strong adhesion, it can be surely prevented from being accidentally separated from the insulating base material. In addition, this effect should just have roughened the surface of the conductive layer at the time of a press process. That is, if the surface of the conductive layer has been roughened by the pressing step, the above effect can be obtained.
  • connection region is flattened, it is possible to realize good solder wetting and spreading in the connection process.
  • the region for mounting the component is flattened, and the other region (the region that is stacked in contact with the insulating substrate) is roughened.
  • the connection material for example, solder
  • the adhesion with the insulating base material it is possible to improve the wetting and spreading property of the connection material (for example, solder) and the adhesion with the insulating base material. That is, the above effect can be obtained by making the conductive layer coexist with the roughened region and the flattened region.
  • connection terminal portion for connecting to the connection terminal of the component-embedded substrate can be formed in the planarized region, and solder can be formed in the roughened region. Can suppress the spread of wetness.
  • the conductor pattern when the conductor pattern is formed, the conductor pattern may be erroneously displaced by the etching process, but the gold plating pad serves as a so-called etching resist, and the connection material is exposed. There is no end. Therefore, the reliability regarding the connection of the mounted components is not lowered.
  • Such an effect is a problem peculiar to a transfer method for forming a circuit (conductor pattern) after component mounting, and the present invention is preferably applied to such a transfer method.
  • the conductive layer 2 is formed on the support plate 1.
  • the support plate 1 is, for example, a SUS plate.
  • the conductive layer 2 is a copper thin film made of, for example, copper plating.
  • a mask layer 3 is formed on the conductive layer 2.
  • the mask layer 3 is a laminate of a photosensitive film having chemical resistance, for example.
  • a photosensitive ink having chemical resistance may be applied to the conductive layer 2.
  • the mask layer 3 is formed except for a connection region 6 to be electrically connected to a connection terminal 5 included in an electric or electronic component 4 described later.
  • the connection region 6 is formed by exposing and developing the mask layer 3 and removing a predetermined portion of the mask layer 3.
  • the joining region 6 may be formed by removing the thermosetting ink as the mask layer 3.
  • FIG. 2 shows a connection region forming step.
  • region 6 is implemented.
  • This preparation step is performed by placing the gold plating pad 7 on the connection region 6.
  • the surface of the gold plating pad 7 becomes the connection surface 15.
  • the gold plating pad 7 is subjected to soft etching on a copper pad, and then gold plating treatment with a nickel thickness of 1 ⁇ m to 10 ⁇ m (preferably 5 ⁇ m) and a gold thickness of 0.01 ⁇ m to 1 ⁇ m (preferably 0.03 ⁇ m). It is a thing.
  • the soft etching the surface of the gold plating pad 7 is 0 ⁇ m to 1.5 ⁇ m in terms of surface roughness (Rz), and is thus formed flat.
  • the flattened connection surface 15 can be provided.
  • a method for planarizing the surface of the gold plating pad 7 micro etching, acid cleaning, or plasma etching may be used. Then, as shown in FIG. 4, a mask layer removing step for removing (peeling) the mask layer 3 is performed.
  • the surface 2a of the conductive layer 2 is roughened.
  • This roughening process is performed by etching the copper surface with respect to the surface 2a of the conductive layer 2 to form an organic film using a blackening reduction process, a bond film process, or a CZ process.
  • Its surface roughness (Rz) is 0.1 ⁇ m to 10 ⁇ m.
  • the bond film process is a process using a chemical solution manufactured by ATOTECH. This is a treatment for improving the resin adhesion by roughening the copper surface and forming an organometallic film.
  • the CZ process is a process using a chemical solution manufactured by MEC. This is for improving the roughening of the copper surface and the resin adhesion.
  • connection process is performed. Specifically, the connection surface 15 (surface of the gold plating pad 7) of the connection region 6 and the electrical or electronic component 4 are electrically connected. Specifically, the connection terminal 5 and the connection region 6 of the component 4 are connected via the connection material 8.
  • the connection material 8 is, for example, solder. 8a is a solder reflow. Thereby, the component 4 is mounted on the conductive layer 2 and the component support 9 is formed.
  • a pressing process is performed. Specifically, after placing the resin insulating base material 10 with the component 4 sandwiched between the conductive layer 2, the conductive layer 2 and the insulating base material 10 are pressed against each other to insulate the component 4. Embedded in the substrate 10. Thereby, the laminated body 11 is formed.
  • the insulating base material 10 is a prepreg, for example.
  • a pattern forming process is performed as shown in FIG. Specifically, the conductive pattern 13 is formed by removing a part of the conductive layer 2. The conductor pattern 13 is formed by etching the conductor layer 2. The conductor pattern 13a at the portion connected to the gold plating pad 7 is formed as a circuit larger than the gold plating pad 7 by 0 ⁇ m to 500 ⁇ m (preferably 50 ⁇ m on one side). Further, what is shown in FIG. 8 is a component built-in substrate 14 according to the present invention. In addition, although the figure showed the example of the single-sided board
  • the conductor pattern 13 is formed in the pattern forming step.
  • the contact surface with the insulating base material 10 is roughened as described above. That is, in the pressing process, the conductive layer 2 and the insulating base material 10 that are in pressure contact with each other are in a state in which the surface of the conductive layer 2 (pressure contact surface) is roughened, and thus the adhesion is strong and difficult to peel off. So that it is pressed. Therefore, it is possible to reliably prevent the conductor pattern 13 from being accidentally separated from the insulating base material 10. In addition, this effect should just have roughened the surface of the conductive layer 2 at the time of a press process.
  • the surface roughening process is performed between the mask layer removing process and the connecting process, but the present invention is not limited to this.
  • the roughening treatment may be performed, for example, after the conductive layer 2 in the connection region forming process is formed on the support plate 1 and before the mask layer 3 is formed, or after the connection process is completed, the pressing process. You may go before.
  • connection surface 15 of the connection region 6 is flattened, good solder wetting and spreading can be realized in the connection process.
  • the region where the component 4 is mounted is flattened with respect to the conductive layer 2 on which the component 4 is mounted and is stacked with the insulating base material 10, and the other region (the contact layer with the insulating base material 10 is stacked).
  • the region in a roughened state, it is possible to improve the wettability of the solder and the adhesion to the insulating substrate 10. That is, the above effect can be obtained by making the roughened region and the flattened region coexist in the conductive layer 2.
  • the conductor pattern 13a when the conductor pattern 13a is formed, the conductor pattern 13a may be misaligned by an etching process.
  • the gold plating pad 7 serves as a so-called etching resist, and the connection material 8 is not exposed. Therefore, the reliability regarding the connection of the mounted components 4 is not lowered.
  • Such an effect is a problem peculiar to a transfer method for forming a circuit (conductor pattern 13a) after component mounting, and the present invention is preferably applied to such a transfer method.
  • the spacer layer 16 may be formed at a position corresponding to the position where the electrical or electronic component 4 is to be disposed. In this case, as shown in FIG. 9, the spacer layer 16 is disposed between the component 4 and the conductive layer 2 in the multilayer body 11.
  • the spacer layer 16 is made of the same material as a generally used solder resist.
  • the gold plating pad 7 may be provided at a place different from the connection region 6.
  • the gold plating pad 7 is detected by X-rays, thereby forming a through hole 17 at a position aligned with an electrical or electronic component.
  • the conductor pattern 13a can be formed. Further, it can be used for alignment necessary for forming other conductor patterns and the like.
  • FIGS. 1 to 8 Another example of the component-embedded substrate according to the present invention will be described below with reference to FIGS. The description of the same points as in the examples shown in FIGS. 1 to 8 is omitted.
  • the conductive layer 2 is formed on the support plate 1.
  • the entire surface of the conductive layer 2 is roughened.
  • a mask layer 3 and a connection region 6 are formed on the conductive layer 2. Up to FIG. 13 is the connection region forming step.
  • connection surface 15 of the connection region 6 is flattened.
  • This flattening process is directly performed on the roughened conductive layer 2. That is, in this example, a roughening process and a flattening process are directly performed on the surface of the conductive layer 2.
  • a mask layer removing step is performed as shown in FIG. Specifically, the mask layer 3 is removed (peeled).
  • connection process is performed. Specifically, the connection surface 15 of the connection region 6 and the electrical or electronic component 4 are electrically connected. Thereby, the component 4 is mounted on the conductive layer 2 and the component support 9 is formed.
  • a pressing process is performed. Specifically, the resin insulating base 10 and the conductive layer 2 are pressed. At the same time, the component 4 is embedded in the insulating base material 10 to form the laminate 11.
  • a pattern forming process is performed. Specifically, the conductive pattern 13 is formed by removing a part of the conductive layer 2.
  • the conductive layer 2 may be directly planarized and roughened without using the gold plating pad 7. Also by this, the improvement of the solder wettability and the adhesion to the insulating substrate 10 can be improved.

Abstract

Disclosed is a method of manufacturing a substrate with a built-in part, provided with: a connection area forming process for forming connection areas (6) on a conductive layer formed on a support plate; a preparation process for furnishing, on the connection areas (6), connection faces (15) for connecting to connection terminals (5) of an electronic part (4); a mask layer removing process for removing a mask layer; a connecting process for arranging the part (4) on the conductive layer, and connecting the connection faces (15) of the connection areas (6) and the connection terminals (5) with a connection material (8) interposed therebetween; a pressing process for arranging a resin insulation base-material (10) on the conductive layer in a state of having the part (4) sandwiched therebetween, and then, pressurizing the conductive layer and the insulation base material (10) to bury the part (4) in the insulation base material (10); and a pattern forming process for removing a part of the conductive layer to form a conductor pattern (13). The method of manufacturing a substrate with built-in parts is also provided, prior to carrying out the pressing process, with a roughing-up process for furnishing a rough surface that is rougher than the connection faces (15), at areas other than the connection areas (6) of the conductive layer.

Description

部品内蔵基板の製造方法及びこれを用いた部品内蔵基板Manufacturing method of component-embedded substrate and component-embedded substrate using the same
　本発明は、電気部品あるいは電子部品を絶縁基材内に埋設させた部品内蔵基板の製造方法及びこれを用いた部品内蔵基板に関するものである。 The present invention relates to a method of manufacturing a component-embedded substrate in which an electrical component or an electronic component is embedded in an insulating base material, and a component-embedded substrate using the same.
　部品内蔵基板が特許文献１に開示されている。特許文献１に記載の部品内蔵基板は、絶縁基材と、この両面に形成された導体回路と、絶縁基材の中に埋設され、その端子部が基板側に設けられた接続端子部と接続して導体回路に接続している電子部品とを備えたものである。この部品内蔵基板の接続端子と接続させるための接続端子部が、ソルダレジスト層を用いて形成されている例が特許文献１には記載されている。 A component-embedded substrate is disclosed in Patent Document 1. The component-embedded substrate described in Patent Document 1 is connected to an insulating base material, conductor circuits formed on both sides thereof, embedded in the insulating base material, and a terminal portion connected to a connection terminal portion provided on the substrate side. And an electronic component connected to the conductor circuit. Patent Document 1 describes an example in which a connection terminal portion for connecting to a connection terminal of the component-embedded substrate is formed using a solder resist layer.
　しかしながら、ソルダレジスト層は、スクリーン印刷後に露光、現像、紫外線硬化又は熱硬化で形成されている。このため、基板を形成するプリプレグとの密着性が低く、その界面で剥離しやすい。 However, the solder resist layer is formed by exposure, development, ultraviolet curing or thermal curing after screen printing. For this reason, adhesiveness with the prepreg which forms a board | substrate is low, and it is easy to peel at the interface.
特開２０１０－２７９１７号公報JP 2010-27917 A
　本発明は、上記従来技術を考慮したものであって、基板を形成するプリプレグ等の絶縁基材と銅箔等の導電層との密着性を高めてこれらをプレスにより確実に積層することができる部品内蔵基板の製造方法及びこれを用いた部品内蔵基板を提供することを目的とする。 The present invention is based on the above prior art, and can enhance the adhesion between an insulating base material such as a prepreg that forms a substrate and a conductive layer such as a copper foil, and these can be reliably laminated by pressing. It is an object of the present invention to provide a component built-in substrate manufacturing method and a component built-in substrate using the same.
　前記目的を達成するため、本発明では、支持板上に導電層を形成し、この導電層に電気又は電子的な部品が有する接続端子と電気的に接続すべき接続領域を除いて、前記導電層を覆うマスク層を形成する接続領域形成工程と、前記接続領域に前記接続端子との接続面を提供する準備工程と、前記マスク層を除去するマスク層除去工程と、前記導電層上に前記部品を配置し、前記接続領域の接続面と前記接続端子とを接続材料を介して接続する接続工程と、前記導電層との間に前記部品を挟み込んだ状態で樹脂製の絶縁基材を配置した後、前記導電層と前記絶縁基材とを互いに圧接して、前記部品を前記絶縁基材内に埋設するプレス工程と、前記導電層の一部を除去して導体パターンを形成するパターン形成工程とを備え、前記プレス工程の実施に先立ち、前記導電層における前記接続領域以外の領域に前記接続面よりも粗い粗面を提供する粗面化処理工程とを備えることを特徴とする部品内蔵基板の製造方法を提供する。 In order to achieve the above object, according to the present invention, a conductive layer is formed on a support plate, and the conductive layer is formed except for a connection region to be electrically connected to a connection terminal of an electrical or electronic component. A connection region forming step of forming a mask layer covering the layer, a preparation step of providing a connection surface with the connection terminal in the connection region, a mask layer removal step of removing the mask layer, and the conductive layer on the conductive layer Disposing a resin insulating base material in a state in which the component is sandwiched between the conductive layer and a connection step in which the component is disposed and the connection surface of the connection region and the connection terminal are connected via a connection material. After that, the conductive layer and the insulating base material are pressed against each other, the pressing step of embedding the component in the insulating base material, and pattern formation for removing a part of the conductive layer to form a conductor pattern A step of the press step Prior to facilities, to provide a method of manufacturing a component-embedded substrate, characterized in that it comprises a roughening treatment step of providing the connection surface rough rough surface than in the region other than the connection region of the conductive layer.
　好ましくは、前記準備工程は、前記接続面となるべき表面が平坦な板形状の金めっきパッドを前記接続領域に載置して実施され、前記粗面化処理工程は、前記準備工程の後に実施される。 Preferably, the preparation step is performed by placing a plate-shaped gold plating pad having a flat surface to be the connection surface on the connection region, and the roughening treatment step is performed after the preparation step. Is done.
　さらに好ましくは、前記粗面化処理工程は、前記マスク層を形成するに先立って実施され、前記準備工程は、粗面化処理された前記接続領域に、前記接続面となるべき表面が平坦な板形状の金めっきパッドを前記接続領域に載置して実施される。 More preferably, the roughening treatment step is performed prior to forming the mask layer, and the preparatory step is such that the surface to be the connection surface is flat in the roughened connection region. A plate-shaped gold plating pad is placed on the connection region.
　さらに好ましくは、前記粗面化処理工程は、前記マスク層を形成するに先立って実施され、前記準備工程は、粗面化処理された前記接続領域にソフトエッチング又はマイクロエッチング又は酸洗浄又はプラズマエッチングのいずれかを施す。 More preferably, the roughening step is performed prior to forming the mask layer, and the preparation step includes soft etching, microetching, acid cleaning, or plasma etching in the roughened connection region. Apply one of the following.
　また、前記接続材料は半田あるいは導電性ペーストであれば好ましい。 The connecting material is preferably solder or a conductive paste.
　また、前記マスク層を形成するに先立って、前記電気又は電子的な部品が配置されるべき位置に対応した位置にスペーサ層を形成すれば好ましい。 In addition, it is preferable to form a spacer layer at a position corresponding to a position where the electrical or electronic component is to be placed before forming the mask layer.
　さらに、本発明では、請求項２に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、前記接続領域で前記接続材料を介して前記接続端子と電気的に接続された前記金めっきパッドと、前記金めっきパッドを覆っている前記導体パターンとを備えたことを特徴とする部品内蔵基板を提供する。 Furthermore, in this invention, it is a component built-in board using the manufacturing method of the component built-in board of Claim 2, Comprising: The said gold | metal | money electrically connected with the said connection terminal through the said connection material in the said connection area | region. Provided is a component-embedded substrate comprising a plating pad and the conductor pattern covering the gold plating pad.
　本発明によれば、パターン形成工程で、導体パターンが形成される。この導体パターンは、絶縁基材との接触面が粗面化処理されている。すなわち、プレス工程にて、互いに圧接された導電層と絶縁基材は、導電層の表面（圧接面）が粗面化処理されているため、密着力が強く剥離しにくい状態となるように圧接される。したがって、導電層を一部除去して残った部分である導体パターンも密着力が強いものであるため、誤って絶縁基材から剥離してしまうことを確実に防止することができる。なお、この効果は、プレス工程時に導電層の表面が粗面化処理されていればよい。すなわち、プレス工程までに導電層の表面が粗面化処理されていれば、上記効果を得ることができる。 According to the present invention, the conductor pattern is formed in the pattern forming step. In this conductor pattern, the contact surface with the insulating base material is roughened. In other words, the conductive layer and the insulating base material that have been pressed together in the pressing step have been subjected to a roughening treatment on the surface (pressure contact surface) of the conductive layer, so that the adhesive force is strong and it is difficult to peel off. Is done. Therefore, since the conductive pattern which is a part left after removing a part of the conductive layer also has a strong adhesion, it can be surely prevented from being accidentally separated from the insulating base material. In addition, this effect should just have roughened the surface of the conductive layer at the time of a press process. That is, if the surface of the conductive layer has been roughened by the pressing step, the above effect can be obtained.
　また、本発明によれば、接続領域が平坦化処理されているため、接続工程では、良好な半田の濡れ広がりを実現できる。このように、部品が実装され、絶縁基材と積層される導電層に対し、部品を実装する領域を平坦化し、それ以外の領域（絶縁基材と接触して積層される領域）を粗面化された状態に形成することで、接続材料（例えば半田）の濡れ広がり性の向上と絶縁基材との密着性を高めることができる。すなわち、導電層に粗面化領域と平坦化領域とを併存させることで、上記効果は得られる。 Further, according to the present invention, since the connection region is flattened, it is possible to realize good solder wetting and spreading in the connection process. In this way, for the conductive layer that is mounted with the component and laminated with the insulating substrate, the region for mounting the component is flattened, and the other region (the region that is stacked in contact with the insulating substrate) is roughened. By forming it in the formed state, it is possible to improve the wetting and spreading property of the connection material (for example, solder) and the adhesion with the insulating base material. That is, the above effect can be obtained by making the conductive layer coexist with the roughened region and the flattened region.
　また、導電層に粗面化領域と平坦化領域とを併存させることで、平坦化領域にて部品内蔵基板の接続端子と接続させるための接続端子部を形成でき、粗面化領域にて半田の濡れ広がりを抑制できる。 In addition, by having the roughened region and the planarized region coexist in the conductive layer, a connection terminal portion for connecting to the connection terminal of the component-embedded substrate can be formed in the planarized region, and solder can be formed in the roughened region. Can suppress the spread of wetness.
　また、本発明によれば、導体パターンを形成する際にエッチング処理にて導体パターンが誤ってずれてしまうことがあるが、金めっきパッドがいわゆるエッチングレジストの役割を果たし、接続材料が露出してしまうことはない。したがって、実装された部品の接続に関する信頼性が低下することはない。このような効果は、部品実装後に回路（導体パターン）を形成する転写法特有の問題点であり、本発明はこのような転写法に適用することが好ましい。 In addition, according to the present invention, when the conductor pattern is formed, the conductor pattern may be erroneously displaced by the etching process, but the gold plating pad serves as a so-called etching resist, and the connection material is exposed. There is no end. Therefore, the reliability regarding the connection of the mounted components is not lowered. Such an effect is a problem peculiar to a transfer method for forming a circuit (conductor pattern) after component mounting, and the present invention is preferably applied to such a transfer method.
また、本発明によれば、スペーサ層を形成することにより、部品の接続端子と導電層の接続面とを接続する際に、部品の高さ変動を抑制することができる。 Further, according to the present invention, when the spacer layer is formed, fluctuations in the height of the component can be suppressed when the connection terminal of the component and the connection surface of the conductive layer are connected.
本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. スペーサ層を設けた場合の本発明に係る部品内蔵基板の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of the component built-in board | substrate based on this invention when a spacer layer is provided. 貫通孔を設けた場合の本発明に係る部品内蔵基板の製造方法を示す概略図である。It is the schematic which shows the manufacturing method of the component built-in board | substrate based on this invention when providing a through-hole. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order. 本発明に係る別の部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows the manufacturing method of another component built-in board which concerns on this invention in order.
　本発明に係る部品内蔵基板の一例を図１～図８に沿って以下に説明する。
　まず、図１に示すように、支持板１上に導電層２を形成する。支持板１は、例えばＳＵＳ板である。導電層２は、例えば銅めっき等からなる銅薄膜である。次に、図２に示すように、導電層２上にマスク層３を形成する。このマスク層３は、例えば耐薬品性を有する感光性フィルムのラミネートである。他に、耐薬品性のある感光性インキを導電層２に塗布してもよい。マスク層３には、後述する電気又は電子的な部品４が有する接続端子５と電気的に接続すべき接続領域６を除いて形成されている。この接続領域６は、マスク層３に対し露光及び現像処理が施され、マスク層３の所定部位が除去されることにより形成されている。接合領域６は、熱硬化性インキをマスク層３として、これを除去することにより形成してもよい。この図２が接続領域形成工程である。 An example of the component-embedded substrate according to the present invention will be described below with reference to FIGS.
First, as shown in FIG. 1, the conductive layer 2 is formed on the support plate 1. The support plate 1 is, for example, a SUS plate. The conductive layer 2 is a copper thin film made of, for example, copper plating. Next, as shown in FIG. 2, a mask layer 3 is formed on the conductive layer 2. The mask layer 3 is a laminate of a photosensitive film having chemical resistance, for example. In addition, a photosensitive ink having chemical resistance may be applied to the conductive layer 2. The mask layer 3 is formed except for a connection region 6 to be electrically connected to a connection terminal 5 included in an electric or electronic component 4 described later. The connection region 6 is formed by exposing and developing the mask layer 3 and removing a predetermined portion of the mask layer 3. The joining region 6 may be formed by removing the thermosetting ink as the mask layer 3. FIG. 2 shows a connection region forming step.
　そして、図３に示すように、接続領域６における電子等部品の接続端子と接続すべき接続面を提供する準備工程を実施する。この準備工程は、接続領域６に金めっきパッド７を載置して行われる。この金めっきパッド７の表面が接続面１５となる。金めっきパッド７は、銅製のパッドにソフトエッチングが施され、その後、ニッケル厚１μｍ～１０μｍ（好ましくは５μｍ）、金厚０．０１μｍ～１μｍ（好ましくは０．０３μｍ）の金めっき処理が施されたものである。ソフトエッチングされることにより、金めっきパッド７の表面は表面粗さ（Ｒｚ）で表わすと０μｍ～１．５μｍとなるので、平坦に形成されている。このような表面が平坦の金めっきパッド７を接続領域６に載置することにより、平坦化された接続面１５を提供できる。なお、金めっきパッド７の表面を平坦化処理する方法として、マイクロエッチング又は酸洗浄又はプラズマエッチングを用いてもよい。そして、図４に示すように、マスク層３を除去（剥離）するマスク層除去工程を実施する。 And as shown in FIG. 3, the preparatory process which provides the connection surface which should be connected with the connection terminal of electronic parts in the connection area | region 6 is implemented. This preparation step is performed by placing the gold plating pad 7 on the connection region 6. The surface of the gold plating pad 7 becomes the connection surface 15. The gold plating pad 7 is subjected to soft etching on a copper pad, and then gold plating treatment with a nickel thickness of 1 μm to 10 μm (preferably 5 μm) and a gold thickness of 0.01 μm to 1 μm (preferably 0.03 μm). It is a thing. By the soft etching, the surface of the gold plating pad 7 is 0 μm to 1.5 μm in terms of surface roughness (Rz), and is thus formed flat. By placing the gold-plated pad 7 having such a flat surface on the connection region 6, the flattened connection surface 15 can be provided. As a method for planarizing the surface of the gold plating pad 7, micro etching, acid cleaning, or plasma etching may be used. Then, as shown in FIG. 4, a mask layer removing step for removing (peeling) the mask layer 3 is performed.
　そして、図５に示すように、導電層２の表面２ａに粗面化処理を施す。この粗面化処理は、黒化還元処理やボンドフィルム処理やＣＺ処理を用い、導電層２の表面２ａに対して銅表面をエッチングし、有機皮膜を形成することによって行われる。その表面粗さ（Ｒｚ）は、０．１μｍ～１０μｍである。ここで、ボンドフィルム処理とは、ＡＴＯＴＥＣＨ社製造の薬液による処理のことである。銅表面の粗面化と有機金属皮膜の形成による樹脂密着性を向上させるための処理である。また、ＣＺ処理とは、メック社製造の薬液による処理のことである。銅表面の粗面化及び樹脂密着性を向上させるためのものである。 Then, as shown in FIG. 5, the surface 2a of the conductive layer 2 is roughened. This roughening process is performed by etching the copper surface with respect to the surface 2a of the conductive layer 2 to form an organic film using a blackening reduction process, a bond film process, or a CZ process. Its surface roughness (Rz) is 0.1 μm to 10 μm. Here, the bond film process is a process using a chemical solution manufactured by ATOTECH. This is a treatment for improving the resin adhesion by roughening the copper surface and forming an organometallic film. Further, the CZ process is a process using a chemical solution manufactured by MEC. This is for improving the roughening of the copper surface and the resin adhesion.
　次に、図６に示すように、接続工程を実施する。具体的には、接続領域６の接続面１５（金めっきパッド７の表面）と電気又は電子的な部品４とを電気的に接続する。具体的には、部品４の接続端子５と接続領域６とを接続材料８を介して接続される。接続材料８は、例えば半田である。８ａは半田リフローである。これにより、部品４が導電層２上に実装され、部品支持体９が形成される。 Next, as shown in FIG. 6, a connection process is performed. Specifically, the connection surface 15 (surface of the gold plating pad 7) of the connection region 6 and the electrical or electronic component 4 are electrically connected. Specifically, the connection terminal 5 and the connection region 6 of the component 4 are connected via the connection material 8. The connection material 8 is, for example, solder. 8a is a solder reflow. Thereby, the component 4 is mounted on the conductive layer 2 and the component support 9 is formed.
　そして、図７に示すように、プレス工程を実施する。具体的には、導電層２との間に部品４を挟み込んだ状態で樹脂製の絶縁基材１０を配置した後、導電層２と絶縁基材１０とを互いに圧接して、部品４を絶縁基材１０内に埋設する。これにより、積層体１１が形成される。絶縁基材１０は、例えばプリプレグである。 Then, as shown in FIG. 7, a pressing process is performed. Specifically, after placing the resin insulating base material 10 with the component 4 sandwiched between the conductive layer 2, the conductive layer 2 and the insulating base material 10 are pressed against each other to insulate the component 4. Embedded in the substrate 10. Thereby, the laminated body 11 is formed. The insulating base material 10 is a prepreg, for example.
　そして、図８に示すようにパターン形成工程を実施する。具体的には、導電層２の一部を除去して導体パターン１３が形成される。この導体パターン１３は、導体層２にエッチング処理を施されて形成される。金めっきパッド７と接続された部位の導体パターン１３ａは金めっきパッド７より０μｍ～５００μｍ大きい（好ましくは片側５０μｍ）回路として形成される。また、この図８に示したものが、本発明に係る部品内蔵基板１４である。なお、図では基板の片面側のみに導体パターン１３が形成された片面基板の例を示したが、両面基板としても当然適用できる。また、これらを組み合わせた多層基板としても当然適用できる。 Then, a pattern forming process is performed as shown in FIG. Specifically, the conductive pattern 13 is formed by removing a part of the conductive layer 2. The conductor pattern 13 is formed by etching the conductor layer 2. The conductor pattern 13a at the portion connected to the gold plating pad 7 is formed as a circuit larger than the gold plating pad 7 by 0 μm to 500 μm (preferably 50 μm on one side). Further, what is shown in FIG. 8 is a component built-in substrate 14 according to the present invention. In addition, although the figure showed the example of the single-sided board | substrate with which the conductor pattern 13 was formed only in the single side | surface side of a board | substrate, naturally it can apply also as a double-sided board | substrate. Of course, the present invention can also be applied to a multilayer substrate combining these.
　このように、パターン形成工程では、導体パターン１３が形成される。この導体パターン１３は、絶縁基材１０との接触面が上述したように粗面化処理されている。すなわち、プレス工程にて、互いに圧接された導電層２と絶縁基材１０は、導電層２の表面（圧接面）が粗面化処理されているため、密着力が強く剥離しにくい状態となるように圧接される。したがって、導体パターン１３が誤って絶縁基材１０から剥離してしまうことを確実に防止することができる。なお、この効果は、プレス工程時に導電層２の表面が粗面化処理されていればよい。上述した例では、マスク層除去工程と接続工程との間で粗面化処理を行ったが、これに限定されるものではない。粗面化処理は、例えば、接続領域形成工程中の導電層２を支持板１に形成した後であってマスク層３を形成する前に行ってもよいし、接続工程が完了した後プレス工程の前に行ってもよい。 Thus, the conductor pattern 13 is formed in the pattern forming step. As for this conductor pattern 13, the contact surface with the insulating base material 10 is roughened as described above. That is, in the pressing process, the conductive layer 2 and the insulating base material 10 that are in pressure contact with each other are in a state in which the surface of the conductive layer 2 (pressure contact surface) is roughened, and thus the adhesion is strong and difficult to peel off. So that it is pressed. Therefore, it is possible to reliably prevent the conductor pattern 13 from being accidentally separated from the insulating base material 10. In addition, this effect should just have roughened the surface of the conductive layer 2 at the time of a press process. In the example described above, the surface roughening process is performed between the mask layer removing process and the connecting process, but the present invention is not limited to this. The roughening treatment may be performed, for example, after the conductive layer 2 in the connection region forming process is formed on the support plate 1 and before the mask layer 3 is formed, or after the connection process is completed, the pressing process. You may go before.
　また、接続領域６の接続面１５が平坦化処理されているため、接続工程では、良好な半田の濡れ広がりを実現できる。このように、部品４が実装され、絶縁基材１０と積層される導電層２に対し、部品４を実装する領域を平坦化し、それ以外の領域（絶縁基材１０と接触して積層される領域）を粗面化された状態に形成することで、上記半田の濡れ広がり性の向上と絶縁基材１０との密着性を高めることができる。すなわち、導電層２に粗面化領域と平坦化領域とを併存させることで、上記効果は得られる。 Further, since the connection surface 15 of the connection region 6 is flattened, good solder wetting and spreading can be realized in the connection process. As described above, the region where the component 4 is mounted is flattened with respect to the conductive layer 2 on which the component 4 is mounted and is stacked with the insulating base material 10, and the other region (the contact layer with the insulating base material 10 is stacked). By forming the region) in a roughened state, it is possible to improve the wettability of the solder and the adhesion to the insulating substrate 10. That is, the above effect can be obtained by making the roughened region and the flattened region coexist in the conductive layer 2.
　また、導体パターン１３ａを形成する際にエッチング処理にて導体パターン１３ａが誤ってずれてしまうことがある。しかしながら、金めっきパッド７がいわゆるエッチングレジストの役割を果たし、接続材料８が露出してしまうことはない。したがって、実装された部品４の接続に関する信頼性が低下することはない。このような効果は、部品実装後に回路（導体パターン１３ａ）を形成する転写法特有の問題点であり、本発明はこのような転写法に適用することが好ましい。 In addition, when the conductor pattern 13a is formed, the conductor pattern 13a may be misaligned by an etching process. However, the gold plating pad 7 serves as a so-called etching resist, and the connection material 8 is not exposed. Therefore, the reliability regarding the connection of the mounted components 4 is not lowered. Such an effect is a problem peculiar to a transfer method for forming a circuit (conductor pattern 13a) after component mounting, and the present invention is preferably applied to such a transfer method.
　一方で、マスク層３を形成するに先立って、電気又は電子的な部品４が配置されるべき位置に対応した位置にスペーサ層１６を形成してもよい。この場合、図９に示すように、積層体１１において、部品４と導電層２との間にスペーサ層１６が配置される。このように、スペーサ層１６を形成することにより、部品４の接続端子５と導電層２の接続面１５とを接続する際に、部品４の高さ変動を抑制することができる。なお、スペーサ層１６は一般的に用いられているソルダレジストと同一の材料が用いられる。 On the other hand, prior to forming the mask layer 3, the spacer layer 16 may be formed at a position corresponding to the position where the electrical or electronic component 4 is to be disposed. In this case, as shown in FIG. 9, the spacer layer 16 is disposed between the component 4 and the conductive layer 2 in the multilayer body 11. Thus, by forming the spacer layer 16, when connecting the connection terminal 5 of the component 4 and the connection surface 15 of the conductive layer 2, variation in the height of the component 4 can be suppressed. The spacer layer 16 is made of the same material as a generally used solder resist.
　さらに一方で、図１０に示すように、金めっきパッド７を接続領域６とは別の場所に設けてもよい。この場合、支持板１を除去した後、金めっきパッド７をＸ線で検出することにより、電気又は電子的な部品と整合した位置に貫通孔１７を形成する。この貫通孔１７を基準とし、上記導体パターン１３ａを形成することができる。また、その他の導体パターン等を形成するのに必要な位置合わせ等に利用することができる。 On the other hand, as shown in FIG. 10, the gold plating pad 7 may be provided at a place different from the connection region 6. In this case, after the support plate 1 is removed, the gold plating pad 7 is detected by X-rays, thereby forming a through hole 17 at a position aligned with an electrical or electronic component. Using the through hole 17 as a reference, the conductor pattern 13a can be formed. Further, it can be used for alignment necessary for forming other conductor patterns and the like.
　本発明に係る部品内蔵基板の別の例を図１１～図１８に沿って以下に説明する。なお、上述した図１～図８で示した例と同様の点については、記載を省略する。 Another example of the component-embedded substrate according to the present invention will be described below with reference to FIGS. The description of the same points as in the examples shown in FIGS. 1 to 8 is omitted.
　まず、図１１に示すように、支持板１上に導電層２を形成する。次に、図１２に示すように、導電層２の表面全域を粗面化処理する。そして、図１３に示すように、導電層２上にマスク層３と接続領域６を形成する。この図１３までが接続領域形成工程である。 First, as shown in FIG. 11, the conductive layer 2 is formed on the support plate 1. Next, as shown in FIG. 12, the entire surface of the conductive layer 2 is roughened. Then, as shown in FIG. 13, a mask layer 3 and a connection region 6 are formed on the conductive layer 2. Up to FIG. 13 is the connection region forming step.
　そして、図１４に示すように準備工程を実施する。具体的には、接続領域６の接続面１５を平坦化処理する。この平坦化処理は、粗面化処理された導電層２に対して直接行われる。すなわち、この例では、導電層２の表面に直接粗面化処理及び平坦化処理が行われる。平坦化処理された金めっきパッド７を載置することにより、接続領域６を平坦化した上記の例とは、この点で異なっている。なお、この平坦化処理は、ソフトエッチング又はマイクロエッチング又は酸洗浄又はプラズマエッチングを適用できる。そして、図１５に示すようにマスク層除去工程を行う。具体的には、マスク層３を除去（剥離）する。 Then, a preparation process is performed as shown in FIG. Specifically, the connection surface 15 of the connection region 6 is flattened. This flattening process is directly performed on the roughened conductive layer 2. That is, in this example, a roughening process and a flattening process are directly performed on the surface of the conductive layer 2. This is different from the above example in which the connection region 6 is flattened by placing the flattened gold plating pad 7. Note that soft etching, micro etching, acid cleaning, or plasma etching can be applied to the planarization treatment. Then, a mask layer removing step is performed as shown in FIG. Specifically, the mask layer 3 is removed (peeled).
　次に、図１６に示すように、接続工程を実施する。具体的には、接続領域６の接続面１５と電気又は電子的な部品４とを電気的に接続する。これにより、部品４が導電層２上に実装され、部品支持体９が形成される。 Next, as shown in FIG. 16, a connection process is performed. Specifically, the connection surface 15 of the connection region 6 and the electrical or electronic component 4 are electrically connected. Thereby, the component 4 is mounted on the conductive layer 2 and the component support 9 is formed.
　そして、図１７に示すように、プレス工程を実施する。具体的には、樹脂製の絶縁基材１０と導電層２とを圧接する。これとともに、部品４が絶縁基材１０内に埋設され、積層体１１が形成される。 Then, as shown in FIG. 17, a pressing process is performed. Specifically, the resin insulating base 10 and the conductive layer 2 are pressed. At the same time, the component 4 is embedded in the insulating base material 10 to form the laminate 11.
　そして、図１８に示すように、パターン形成工程を実施する。具体的には、導電層２の一部を除去して導体パターン１３が形成される。 Then, as shown in FIG. 18, a pattern forming process is performed. Specifically, the conductive pattern 13 is formed by removing a part of the conductive layer 2.
　このように、金めっきパッド７を用いなくても、導電層２に直接平坦化処理及び粗面化処理を施してもよい。これによっても、半田の濡れ広がり性の向上と絶縁基材１０との密着性を高めることができる。 As described above, the conductive layer 2 may be directly planarized and roughened without using the gold plating pad 7. Also by this, the improvement of the solder wettability and the adhesion to the insulating substrate 10 can be improved.
１　支持板
２　導電層
２ａ　導電層の表面
３　マスク層
４　電気又は電子的な部品
５　接続端子
６　接続領域
７　金めっきパッド
８　接続材料
９　部品支持体
１０　絶縁基材
１１　積層体
１３　導体パターン
１４　部品内蔵基板
１５　接続面
１６　スペーサ層
１７　貫通孔 DESCRIPTION OF SYMBOLS 1 Support plate 2 Conductive layer 2a Conductive layer surface 3 Mask layer 4 Electrical or electronic component 5 Connection terminal 6 Connection region 7 Gold plating pad 8 Connection material 9 Component support 10 Insulating substrate 11 Laminated body 13 Conductive pattern 14 Component Built-in substrate 15 Connection surface 16 Spacer layer 17 Through hole

Claims (7)

  1. 　支持板上に導電層を形成し、この導電層に電気又は電子的な部品が有する接続端子と電気的に接続すべき接続領域を除いて、前記導電層を覆うマスク層を形成する接続領域形成工程と、
    　前記接続領域に前記接続端子との接続面を提供する準備工程と、
    　前記マスク層を除去するマスク層除去工程と、
    　前記導電層上に前記部品を配置し、前記接続領域の接続面と前記接続端子とを接続材料を介して接続する接続工程と、
    　前記導電層との間に前記部品を挟み込んだ状態で樹脂製の絶縁基材を配置した後、前記導電層と前記絶縁基材とを互いに圧接して、前記部品を前記絶縁基材内に埋設するプレス工程と、
    　前記導電層の一部を除去して導体パターンを形成するパターン形成工程と
    を備え、
    　前記プレス工程の実施に先立ち、前記導電層における前記接続領域以外の領域に前記接続面よりも粗い粗面を提供する粗面化処理工程とを備えることを特徴とする部品内蔵基板の製造方法。     Forming a connection region in which a conductive layer is formed on a support plate and a mask layer covering the conductive layer is formed except for a connection region to be electrically connected to a connection terminal of an electrical or electronic component on the conductive layer Process,
    Providing a connection surface with the connection terminal in the connection region;
    A mask layer removing step of removing the mask layer;
    A connecting step of arranging the component on the conductive layer and connecting the connection surface of the connection region and the connection terminal via a connection material;
    After placing the resin insulating substrate with the component sandwiched between the conductive layer, the conductive layer and the insulating substrate are pressed against each other, and the component is embedded in the insulating substrate. Pressing process to
    A pattern forming step of forming a conductor pattern by removing a part of the conductive layer,
    A method of manufacturing a component-embedded substrate, comprising: a roughening treatment step of providing a rough surface rougher than the connection surface in a region other than the connection region in the conductive layer prior to the pressing step.
  2. 　前記準備工程は、前記接続面となるべき表面が平坦な板形状の金めっきパッドを前記接続領域に載置して実施され、
    　前記粗面化処理工程は、前記準備工程の後に実施されることを特徴とする請求項１に記載の部品内蔵基板の製造方法。     The preparatory step is performed by placing a plate-shaped gold plating pad having a flat surface to be the connection surface in the connection region,
    The method for manufacturing a component-embedded board according to claim 1, wherein the roughening treatment step is performed after the preparation step.
  3. 　前記粗面化処理工程は、前記マスク層を形成するに先立って実施され、前記準備工程は、粗面化処理された前記接続領域に、前記接続面となるべき表面が平坦な板形状の金めっきパッドを前記接続領域に載置して実施されることを特徴とする請求項１に記載の部品内蔵基板の製造方法。 The roughening treatment step is performed prior to forming the mask layer, and the preparatory step is performed in the roughened connection region in a plate-shaped gold plate with a flat surface to be the connection surface. The method for manufacturing a component built-in substrate according to claim 1, wherein the plating pad is placed on the connection region.
  4. 　前記粗面化処理工程は、前記マスク層を形成するに先立って実施され、前記準備工程は、粗面化処理された前記接続領域にソフトエッチング又はマイクロエッチング又は酸洗浄又はプラズマエッチングのいずれかを施すことを特徴とする請求項１に記載の部品内蔵基板の製造方法。 The roughening treatment step is performed prior to forming the mask layer, and the preparation step is performed by performing soft etching, microetching, acid cleaning, or plasma etching on the roughened connection region. The method for manufacturing a component-embedded substrate according to claim 1, wherein the method is performed.
  5. 　前記接続材料は半田又は導電性ペーストであることを特徴とする請求項１に記載の部品内蔵基板の製造方法。 2. The method of manufacturing a component-embedded board according to claim 1, wherein the connection material is solder or conductive paste.
  6. 　前記マスク層を形成するに先立って、前記電気又は電子的な部品が配置されるべき位置に対応した位置にスペーサ層を形成することを特徴とする請求項１に記載の部品内蔵基板の製造方法。 2. The method of manufacturing a component-embedded substrate according to claim 1, wherein a spacer layer is formed at a position corresponding to a position where the electrical or electronic component is to be disposed prior to forming the mask layer. .
  7. 　請求項２に記載の部品内蔵基板の製造方法を用いた部品内蔵基板であって、
    　前記接続領域で前記接続材料を介して前記接続端子と電気的に接続された前記金めっきパッドと、
    　前記金めっきパッドを覆っている前記導体パターンとを備えたことを特徴とする部品内蔵基板。     A component-embedded substrate using the component-embedded substrate manufacturing method according to claim 2,
    The gold plating pad electrically connected to the connection terminal via the connection material in the connection region;
    A component-embedded substrate comprising: the conductor pattern covering the gold plating pad.
PCT/JP2010/057459 2010-04-27 2010-04-27 Method of manufacturing substrate with built-in part, and substrate with built-in part using same WO2011135670A1 (en)

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Cited By (1)

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JPH11163510A (en) * 1997-12-02 1999-06-18 Denso Corp Mounting structure for electronic component
JPH11195864A (en) * 1997-12-27 1999-07-21 Tdk Corp Manufacture of wiring board
JP2007317899A (en) * 2006-05-26 2007-12-06 Nitto Denko Corp Wiring circuit board, and manufacturing method thereof
JP2009267149A (en) * 2008-04-25 2009-11-12 Dainippon Printing Co Ltd Part built-in wiring board, and method for manufacturing part built-in wiring board
JP2010027917A (en) * 2008-07-22 2010-02-04 Meiko:Kk Circuit substrate with built in electric/electronic components and manufacturing method of the same

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JPH11163510A (en) * 1997-12-02 1999-06-18 Denso Corp Mounting structure for electronic component
JPH11195864A (en) * 1997-12-27 1999-07-21 Tdk Corp Manufacture of wiring board
JP2007317899A (en) * 2006-05-26 2007-12-06 Nitto Denko Corp Wiring circuit board, and manufacturing method thereof
JP2009267149A (en) * 2008-04-25 2009-11-12 Dainippon Printing Co Ltd Part built-in wiring board, and method for manufacturing part built-in wiring board
JP2010027917A (en) * 2008-07-22 2010-02-04 Meiko:Kk Circuit substrate with built in electric/electronic components and manufacturing method of the same

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WO2023209902A1 (en) * 2022-04-27 2023-11-02 株式会社メイコー Component mounting substrate

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