JP5659234B2 - Component built-in board - Google Patents

Component built-in board Download PDF

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JP5659234B2
JP5659234B2 JP2012532818A JP2012532818A JP5659234B2 JP 5659234 B2 JP5659234 B2 JP 5659234B2 JP 2012532818 A JP2012532818 A JP 2012532818A JP 2012532818 A JP2012532818 A JP 2012532818A JP 5659234 B2 JP5659234 B2 JP 5659234B2
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component
pad
conductive
insulating base
substrate
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JPWO2012032654A1 (en
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光昭 戸田
戸田  光昭
良一 清水
良一 清水
琢哉 長谷川
琢哉 長谷川
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Meiko Co Ltd
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Meiko Co Ltd
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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4602Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
    • H05K1/188Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or attaching to a structure having a conductive layer, e.g. a metal foil, such that the terminals of the component are connected to or adjacent to the conductive layer before embedding, and by using the conductive layer, which is patterned after embedding, at least partially for connecting the component
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • H05K1/111Pads for surface mounting, e.g. lay-out
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03Metal processing
    • H05K2203/0338Transferring metal or conductive material other than a circuit pattern, e.g. bump, solder, printed component

Description

本発明は、電気部品あるいは電子部品を絶縁基材内に埋設させた部品内蔵基板に関するものである。   The present invention relates to a component-embedded substrate in which an electrical component or an electronic component is embedded in an insulating base material.

部品内蔵基板が特許文献1に開示されている。特許文献1に記載の部品内蔵基板は、絶縁基材と、この両面に形成された導体回路と、電子部品とを備えたものである。この電子部品は、絶縁基材の中に埋設され、その端子部が基板側に設けられた接続端子部と接続して導体回路に接続している内蔵部品である。この部品内蔵基板の接続端子と接続させるための接続端子部が、ソルダレジスト層を用いて形成されている例が特許文献1には記載されている。   A component-embedded substrate is disclosed in Patent Document 1. The component-embedded substrate described in Patent Document 1 includes an insulating base, a conductor circuit formed on both sides, and an electronic component. This electronic component is a built-in component that is embedded in an insulating base material and has a terminal portion connected to a connection terminal portion provided on the substrate side and connected to a conductor circuit. Patent Document 1 describes an example in which a connection terminal portion for connecting to a connection terminal of the component-embedded substrate is formed using a solder resist layer.

しかしながら、ソルダレジスト層は、スクリーン印刷後に露光、現像、紫外線硬化又は熱硬化で形成されている。このため、隣り合う内蔵部品間にソルダレジスト層が形成されていると、内蔵部品間隔を狭めることが困難である。すなわち、基板表面に対する部品の高密度化を図ることが困難である。また、特許文献1のように転写法で基板を作製する場合、導体パターンは電子部品との接続部より大きく設計されるため、配線の高密度化も図ることが困難である。   However, the solder resist layer is formed by exposure, development, ultraviolet curing, or thermal curing after screen printing. For this reason, if a solder resist layer is formed between adjacent built-in components, it is difficult to reduce the interval between the built-in components. That is, it is difficult to increase the density of components with respect to the substrate surface. Further, when the substrate is manufactured by the transfer method as in Patent Document 1, it is difficult to increase the density of the wiring because the conductor pattern is designed larger than the connection portion with the electronic component.

特開2010−27917号公報JP 2010-27917 A

本発明は、上記従来技術を考慮したものであって、内蔵部品同士の間隔を狭めて配置することができ、したがって部品の高密度化(部品の実装密度の向上)を図り、さらには配線の高密度化も図ることができる部品内蔵基板を提供することを目的とする。   The present invention takes the above-described conventional technology into consideration, and can be arranged with a small interval between built-in components. Therefore, it is possible to increase the density of components (improving the mounting density of components) and to further improve the wiring. An object of the present invention is to provide a component-embedded substrate capable of increasing the density.

前記目的を達成するため、本発明では、板形状に形成された樹脂製の絶縁 基材と、該絶縁基材内に埋設された複数の電子又は電気的な部品と、該部品が接合材を介して一方の面に実装され、前記一方の面及び周側面が前記絶縁 基材に覆われた金からなる板状の導電パッドと、該導電パッドの他方の面に形成され、前記他方の面の外縁よりも内側に形成されている銅からなる導体パターンと、を備え、前記導電パッドは、前記部品に設けられた複数の接続端子に対し前記接合材を介して電気的に接続され、前記導体パターンの形成時におけるエッチングレジストとして機能することを特徴とする部品内蔵基板を提供する。 In order to achieve the above object, in the present invention, a resin-made insulating base material formed in a plate shape, a plurality of electronic or electrical components embedded in the insulating base material, and the parts serve as bonding materials. is mounted on one side through a plate-shaped conductive pads of gold said the one surface and the peripheral side surface covered with the insulating substrate, is formed on the other surface of the conductive pad, the other surface A conductive pattern made of copper formed on the inner side of the outer edge, and the conductive pad is electrically connected to the plurality of connection terminals provided in the component via the bonding material , Provided is a component-embedded substrate that functions as an etching resist when forming a conductor pattern .

好ましくは、前記導体パターンは、前記他方の面の一部を露出させて形成されていることを特徴としている。   Preferably, the conductor pattern is formed by exposing a part of the other surface.

また、好ましくは、各接続端子に接続されたそれぞれの前記導電パッドでパッドユニットが形成され、隣り合う前記パッドユニット間には前記絶縁基材のみが介在していることを特徴としている。
また、好ましくは、前記接続端子は前記部品の両端部に設けられ、前記パッドユニットはパッド対として前記導電パッドが対向して配設されていることを特徴としている。
Preferably, a pad unit is formed by each of the conductive pads connected to each connection terminal, and only the insulating base material is interposed between adjacent pad units.
Preferably, the connection terminals are provided at both end portions of the component, and the pad unit is disposed so that the conductive pads face each other as a pad pair.

さらに好ましくは、前記パッド対を形成する前記導電パッド間に前記部品と前記絶縁基材の表面との間隔を保持するためのスペーサが設けられていることを特徴としている。
また、前記接合材は半田であり、前記スペーサはソルダレジストであることを特徴としている。
More preferably, a spacer is provided between the conductive pads forming the pad pair to maintain a distance between the component and the surface of the insulating base.
Further, the bonding material is solder, and the spacer is a solder resist.

本発明の部品内蔵基板は、絶縁基材と、複数の部品と、導電パッドと、導体パターンとを備え、導体パターンは導電パッドの他方の面であるパターン形成面の外縁より小さい範囲に形成される。したがって、導電パッドの外縁を越えて導体パターンが形成されることはなく、各部品間の間隔は導電パッドの大きさで決定される。これにより、導電パッド間の間隔を狭めて配置することができるので、部品の実装密度を向上させることができる。このとき、導体パターンが他方の面(パターン形成面)の外縁より小さい範囲、すなわち他方の面の一部を露出させて形成されていれば、確実に部品の実装密度を向上させることができる。   The component-embedded substrate of the present invention includes an insulating base, a plurality of components, a conductive pad, and a conductive pattern, and the conductive pattern is formed in a range smaller than the outer edge of the pattern forming surface that is the other surface of the conductive pad. The Therefore, the conductor pattern is not formed beyond the outer edge of the conductive pad, and the interval between the components is determined by the size of the conductive pad. Thereby, since the space | interval between conductive pads can be arrange | positioned and it can arrange | position, the mounting density of components can be improved. At this time, if the conductor pattern is formed in a range smaller than the outer edge of the other surface (pattern forming surface), that is, a part of the other surface is exposed, the mounting density of the components can be reliably improved.

また、部品の接続端子にそれぞれ接続された導電パッドでパッド対を形成し、このパッド対間には絶縁基材のみが介在している。したがって、従来のようなソルダレジスト層が形成されていないので、パッド対間の間隔を狭めることができる。このため、部品の実装密度を向上させることができる。なお、パッド対を形成するのは抵抗やコンデンサ等の二端子部品の場合であり、接続端子がさらに多い場合の多端子部品(トランジスタ、IC、LSI等)の場合はそれぞれの接続端子に接続される導電パッドでパッドユニットを形成する。パッドユニットの場合でも、効果は同様である。   Further, a pad pair is formed by conductive pads respectively connected to the connection terminals of the component, and only the insulating base material is interposed between the pad pairs. Therefore, since the conventional solder resist layer is not formed, the space | interval between pad pairs can be narrowed. For this reason, the mounting density of components can be improved. A pad pair is formed in the case of a two-terminal component such as a resistor or a capacitor. In the case of a multi-terminal component (transistor, IC, LSI, etc.) with more connection terminals, it is connected to each connection terminal. A pad unit is formed with a conductive pad. The effect is the same in the case of the pad unit.

また、パッド対を形成する導電パッド間に部品と絶縁基材の表面との間隔を保持するためのスペーサを設けることで、部品の沈み込みを防止することができる。特に、接合材が半田である場合に有効である。スペーサはソルダレジストを用いることが好ましい。   Moreover, sinking of a component can be prevented by providing a spacer for maintaining a gap between the component and the surface of the insulating substrate between the conductive pads forming the pad pair. This is particularly effective when the bonding material is solder. The spacer is preferably a solder resist.

本発明に係る部品内蔵基板の概略断面図である。1 is a schematic cross-sectional view of a component built-in substrate according to the present invention. 図1のA−A視図である。It is an AA view of FIG. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention. 本発明に係る部品内蔵基板の製造方法を順番に示す概略図である。It is the schematic which shows in order the manufacturing method of the component built-in board which concerns on this invention.

図1に示すように、本発明に係る部品内蔵基板1は、板形状の絶縁基材2を備えている。この絶縁基材2は、樹脂製であり、例えばプリプレグである。この絶縁基材2に電子又は電気的な部品3が埋設されている。この部品3は、絶縁基材2内に複数埋設されている。絶縁基材2内には、さらに板状の導電パッド4が埋設されている。具体的には、導電パッド4の一方の面(部品実装面4a)及び周側面が絶縁基材2に覆われ、他方の面は絶縁基材2の表面と面一に形成されている。すなわち、導電パッド4の他方の面(後述するパターン形成面4b)は絶縁基材2から露出している。導電パッドは、例えば金めっきパッドである。   As shown in FIG. 1, a component-embedded substrate 1 according to the present invention includes a plate-shaped insulating base material 2. This insulating substrate 2 is made of resin, for example, a prepreg. An electronic or electrical component 3 is embedded in the insulating base 2. A plurality of the components 3 are embedded in the insulating base material 2. A plate-like conductive pad 4 is embedded in the insulating base 2. Specifically, one surface (component mounting surface 4 a) and the peripheral side surface of the conductive pad 4 are covered with the insulating base material 2, and the other surface is formed flush with the surface of the insulating base material 2. That is, the other surface (pattern forming surface 4 b described later) of the conductive pad 4 is exposed from the insulating substrate 2. The conductive pad is, for example, a gold plating pad.

上述した部品3は、この導電パッド4の一方の面(部品実装面4a)に実装されている。具体的には、部品3の両端部にそれぞれ設けられた接続端子5に対応して導電パッド4がそれぞれ配置され、接合材6を介して電気的に接続されている。接合材6は、例えば半田や導電性の接着剤が用いられる。また、同一の部品3を実装しているそれぞれの導電パッド4(それぞれの接続端子5と接続される2個一組の導電パッド4)でパッド対8が形成されている。なお、図の例では抵抗やコンデンサ等の二端子部品を例にしているが、トランジスタやIC、LSI等の接続端子がさらに多い多端子部品の場合、パッド対8はパッドユニットとなる。具体的には、パッドユニットは3個以上の導電パッド4で構成される。   The component 3 described above is mounted on one surface (component mounting surface 4 a) of the conductive pad 4. Specifically, the conductive pads 4 are respectively arranged corresponding to the connection terminals 5 provided at both ends of the component 3 and are electrically connected via the bonding material 6. As the bonding material 6, for example, solder or a conductive adhesive is used. Further, a pad pair 8 is formed by each conductive pad 4 (a set of two conductive pads 4 connected to each connection terminal 5) on which the same component 3 is mounted. In the example shown in the figure, a two-terminal component such as a resistor or a capacitor is taken as an example. However, in the case of a multi-terminal component having more connection terminals such as a transistor, IC, or LSI, the pad pair 8 is a pad unit. Specifically, the pad unit is composed of three or more conductive pads 4.

導電パット4の他方の面(パターン形成面4b)には、導体パターン7が形成されている。図1及び図2の例では、パターン形成面4bの外縁よりも内側に導体パターン7が形成されている。このように、パターン形成面4bの外縁と同等又は外縁より小さい範囲に導体パターン7が形成されるので、導電パッド4の外縁を越えて導体パターン7が形成されることはない。このため、各部品3間の間隔、すなわちパッド対8間の間隔は導電パッド4の大きさで決定される。つまり、導体パターン7が導電パッド4からはみ出て形成されていないので、導電パッド4(実際にはパッド対8)間の間隔を狭めて配置することができる。これにより、部品3の製品基板に対する実装密度を向上させることができる。   A conductor pattern 7 is formed on the other surface (pattern forming surface 4 b) of the conductive pad 4. In the example of FIGS. 1 and 2, the conductor pattern 7 is formed inside the outer edge of the pattern forming surface 4b. Thus, since the conductor pattern 7 is formed in a range equal to or smaller than the outer edge of the pattern forming surface 4b, the conductor pattern 7 is not formed beyond the outer edge of the conductive pad 4. For this reason, the interval between the components 3, that is, the interval between the pad pair 8 is determined by the size of the conductive pad 4. That is, since the conductor pattern 7 is not formed so as to protrude from the conductive pad 4, the distance between the conductive pads 4 (actually, the pad pair 8) can be narrowed. Thereby, the mounting density with respect to the product board | substrate of the components 3 can be improved.

このとき、図1や図2のように導体パターン7が他方の面(パターン形成面4b)の外縁より小さい範囲、すなわち他方の面の一部を露出させて形成されていれば、確実に部品3の実装密度を向上させることができる。また、図2で示すように、部品3間に導体パターン7と接続される配線部9を設けても、部品3と配線部9との間隔を狭めることができ、やはり部品3の実装密度を向上させることができる。また、配線部9を設ける位置も可能な限り導電パッド4に近付けることができるので、配線の高密度化も図ることができる。   At this time, as shown in FIGS. 1 and 2, if the conductor pattern 7 is formed in a range smaller than the outer edge of the other surface (pattern forming surface 4b), that is, a part of the other surface is exposed, the component is surely obtained. 3 can be improved. In addition, as shown in FIG. 2, even if the wiring portion 9 connected to the conductor pattern 7 is provided between the components 3, the interval between the component 3 and the wiring portion 9 can be reduced, and the mounting density of the components 3 is also reduced. Can be improved. In addition, since the position where the wiring portion 9 is provided can be as close to the conductive pad 4 as possible, the wiring density can be increased.

一方、隣り合うパッド対8の間には、絶縁基材2のみが介在している。すなわち、隣り合うパッド対8間には、従来のようなソルダレジスト層が形成されていない。このため、パッド対8間の間隔が狭められている。このような構造は、部品3の実装密度の向上に寄与している。また、パッド対8を形成している導電パッド4間、すなわち部品3の下側には、スペーサ10が設けられている(図では一部の部品3にのみスペーサ10を記載している)。このスペーサ10は、部品3と絶縁基材2の表面との間隔を保持するためのものである。このスペーサ10を設けることで、部品3の沈み込みを防止することができる。特に、接合材が半田である場合に有効である。スペーサ10は、ソルダレジストを用いることが好ましい。このスペーサ10の形状や高さを変更することで、部品の設置高さを制御することも可能である。   On the other hand, only the insulating base material 2 is interposed between the adjacent pad pairs 8. That is, a conventional solder resist layer is not formed between adjacent pad pairs 8. For this reason, the space | interval between the pad pair 8 is narrowed. Such a structure contributes to an improvement in the mounting density of the components 3. In addition, a spacer 10 is provided between the conductive pads 4 forming the pad pair 8, that is, below the component 3 (in the drawing, the spacer 10 is described only for some components 3). The spacer 10 is for maintaining a distance between the component 3 and the surface of the insulating base 2. By providing this spacer 10, the sinking of the component 3 can be prevented. This is particularly effective when the bonding material is solder. The spacer 10 is preferably a solder resist. By changing the shape and height of the spacer 10, it is possible to control the installation height of the parts.

本発明に係る部品内蔵基板の製造方法の一例を図3〜図9に沿って以下に説明する。
まず、図3に示すように、支持板11上に導電層12を形成する。支持板11は、例えばSUS板である。導電層2は、例えば銅めっき等からなる銅薄膜である。次に、図4に示すように、導電層12上に上述した導電パッド4を載置する。導電パッド4が金めっきパッドである場合、この導電パッド4は、銅製のパッドにソフトエッチングを施し、その後、ニッケル厚1μm〜10μm(好ましくは5μm)、金厚0.01μm〜1μm(好ましくは0.03μm)の金めっき処理を施して形成される。ソフトエッチングされることにより、導電パッド4の表面は表面粗さ(Rz)で表わすと0μm〜1.5μmとなるので、平坦に形成される。なお、金めっきパッド7の表面を平坦化処理する方法として、マイクロエッチング又は酸洗浄又はプラズマエッチングを用いてもよい。
An example of a method for manufacturing a component-embedded substrate according to the present invention will be described below with reference to FIGS.
First, as shown in FIG. 3, the conductive layer 12 is formed on the support plate 11. The support plate 11 is, for example, a SUS plate. The conductive layer 2 is a copper thin film made of, for example, copper plating. Next, as shown in FIG. 4, the above-described conductive pad 4 is placed on the conductive layer 12. When the conductive pad 4 is a gold-plated pad, the conductive pad 4 is subjected to soft etching on a copper pad, and then has a nickel thickness of 1 μm to 10 μm (preferably 5 μm) and a gold thickness of 0.01 μm to 1 μm (preferably 0 (0.03 μm) gold plating treatment. By the soft etching, the surface of the conductive pad 4 is 0 μm to 1.5 μm in terms of surface roughness (Rz), and is thus formed flat. As a method for planarizing the surface of the gold plating pad 7, micro etching, acid cleaning, or plasma etching may be used.

そして、図5に示すように、導電層12の表面に粗面化処理を施し、粗面12aを形成する。この粗面化処理は、黒化還元処理やボンドフィルム処理やCZ処理を用い、導電層2の表面に対して銅表面をエッチングし、有機皮膜を形成することによって行われる。その表面粗さ(Rz)は、例えば0.1μm〜10μmである。ここで、ボンドフィルム処理とは、ATOTECH社製造の薬液による処理のことである。銅表面の粗面化と有機金属皮膜の形成による樹脂密着性を向上させるための処理である。また、CZ処理とは、メック社製造の薬液による処理のことである。銅表面の粗面化及び樹脂密着性を向上させるためのものである。   Then, as shown in FIG. 5, the surface of the conductive layer 12 is roughened to form a rough surface 12a. This roughening treatment is performed by etching the copper surface with respect to the surface of the conductive layer 2 to form an organic film using a blackening reduction treatment, a bond film treatment, or a CZ treatment. The surface roughness (Rz) is, for example, 0.1 μm to 10 μm. Here, the bond film process is a process using a chemical solution manufactured by ATOTECH. This is a treatment for improving the resin adhesion by roughening the copper surface and forming an organometallic film. Further, the CZ process is a process using a chemical solution manufactured by MEC. This is for improving the roughening of the copper surface and the resin adhesion.

そして、図6に示すように、導電パッド4の部品実装面4aに接合材6を配置する。図では、接合材6が半田の例を示している。そして、図7に示すように、部品3の接続端子5と導電パッド4とを接合材6を介して電気的に接続する。図の例で具体的にいえば、リフローはんだ付けを行う。これにより、部品3が導電パッド4に実装される。このとき、上述した粗面12aは導電パッド4の側縁に接する位置まで形成されているので、導電パッド4を超えて半田が広がることを確実に防止できる。すなわち、粗面12aが半田の広がりを阻止する役割を果たす。したがって、従来用いていたようなソルダダムを形成する必要がない。ソルダダムが不要となったので、上述した隣り合うパッド対8間の間隔を狭めることができる。これにより、部品3を配置する間隔を狭めることができ、部品3の実装密度を向上させることができる。また、ソルダダムを形成するためのソルダレジスト形成工程が不要となるので、工程の短縮につながり、そのための材料も不要となるのでコストも削減できる。   Then, as shown in FIG. 6, the bonding material 6 is disposed on the component mounting surface 4 a of the conductive pad 4. In the figure, the bonding material 6 is an example of solder. Then, as shown in FIG. 7, the connection terminal 5 of the component 3 and the conductive pad 4 are electrically connected through a bonding material 6. Specifically, in the example of the figure, reflow soldering is performed. Thereby, the component 3 is mounted on the conductive pad 4. At this time, since the rough surface 12a described above is formed up to a position in contact with the side edge of the conductive pad 4, it is possible to reliably prevent the solder from spreading beyond the conductive pad 4. That is, the rough surface 12a plays a role of preventing the solder from spreading. Therefore, it is not necessary to form a solder dam as used conventionally. Since the solder dam is not necessary, the interval between the adjacent pad pairs 8 can be reduced. Thereby, the space | interval which arrange | positions the components 3 can be narrowed, and the mounting density of the components 3 can be improved. In addition, since a solder resist forming process for forming the solder dam is not required, the process is shortened, and a material for the process is not required, so that the cost can be reduced.

そして、図8に示すように、部品3を絶縁基材2内に埋設する。具体的には、導電層12と絶縁基材2との間に部品3を挟み込み、導電層12と絶縁基材2とを互いに圧接する。その後、支持板11を除去する。   Then, as shown in FIG. 8, the component 3 is embedded in the insulating base material 2. Specifically, the component 3 is sandwiched between the conductive layer 12 and the insulating base material 2, and the conductive layer 12 and the insulating base material 2 are pressed against each other. Thereafter, the support plate 11 is removed.

そして、図9に示すように、導電パッド4のパターン形成面4bに導体パターン7を形成する。具体的には、導電層2の一部を除去して導体パターン7を形成する。この導体パターン7は、導電層12にエッチング処理を施されて形成される。このとき、導電パッド4がエッチングレジストとなり、接合材6の露出を防止できる。さらには、実装された部品3の電気的な接続の信頼性が低下することも防止できる。この導体パターン7は、上述したように、パターン形成面4bの外縁と同等又はそれより小さい範囲に形成される。導体パターン7を形成すると同時に、配線部9を形成してもよい。このようにして、なお、図では基板の片面側のみに導体パターン7が形成された片面基板の例を示したが、両面基板としても当然適用できる。また、これらを組み合わせた多層基板としても当然適用できる。   Then, as shown in FIG. 9, the conductor pattern 7 is formed on the pattern formation surface 4 b of the conductive pad 4. Specifically, the conductive pattern 2 is formed by removing a part of the conductive layer 2. The conductor pattern 7 is formed by etching the conductive layer 12. At this time, the conductive pad 4 becomes an etching resist, and the exposure of the bonding material 6 can be prevented. Furthermore, it is possible to prevent the reliability of the electrical connection of the mounted component 3 from being lowered. As described above, the conductor pattern 7 is formed in a range equivalent to or smaller than the outer edge of the pattern forming surface 4b. The wiring portion 9 may be formed simultaneously with the formation of the conductor pattern 7. Thus, although the figure shows an example of a single-sided substrate in which the conductor pattern 7 is formed only on one side of the substrate, it is naturally applicable to a double-sided substrate. Of course, the present invention can also be applied to a multilayer substrate in which these are combined.

1 部品内蔵基板
2 絶縁基材
3 部品
4 導電パッド
4a 部品実装面(一方の面)
4b パターン形成面(他方の面)
5 接続端子
6 接合材
7 導体パターン
8 パッド対
9 配線部
10 スペーサ
11 支持板
12 導電層
12a 粗面
1 Component Embedded Board 2 Insulating Base Material 3 Component 4 Conductive Pad 4a Component Mounting Surface (One Surface)
4b Pattern formation surface (the other surface)
5 Connection Terminal 6 Bonding Material 7 Conductor Pattern 8 Pad Pair 9 Wiring Portion 10 Spacer 11 Support Plate 12 Conductive Layer 12a Rough Surface

Claims (6)

板形状に形成された樹脂製の絶縁基材と、
該絶縁基材内に埋設された複数の電子又は電気的な部品と、
該部品が接合材を介して一方の面に実装され、前記一方の面及び周側面が前記絶縁基材に覆われた金からなる板状の導電パッドと、
該導電パッドの他方の面に形成され、前記他方の面の外縁より内側に形成されている銅からなる導体パターンと、
前記導電パッドは、前記部品に設けられた複数の接続端子に対し前記接合材を介して電気的に接続され、前記導体パターンの形成時におけるエッチングレジストとして機能することを特徴とする部品内蔵基板。
A resin insulating base formed in a plate shape;
A plurality of electronic or electrical components embedded in the insulating substrate;
The component is mounted on one surface via a bonding material, and the plate-like conductive pad made of gold with the one surface and the peripheral side surface covered with the insulating base;
A conductor pattern made of copper formed on the other surface of the conductive pad and formed inside the outer edge of the other surface;
The component-embedded substrate, wherein the conductive pad is electrically connected to a plurality of connection terminals provided on the component via the bonding material, and functions as an etching resist when the conductor pattern is formed .
前記導体パターンは、前記他方の面の一部を露出させて形成されていることを特徴とする請求項1に記載の部品内蔵基板。   The component built-in board according to claim 1, wherein the conductor pattern is formed by exposing a part of the other surface. 各接続端子に接続されたそれぞれの前記導電パッドでパッドユニットが形成され、
隣り合う前記パッドユニット間には前記絶縁基材のみが介在していることを特徴とする請求項1に記載の部品内蔵基板。
A pad unit is formed with each of the conductive pads connected to each connection terminal,
The component built-in board according to claim 1, wherein only the insulating base material is interposed between the adjacent pad units.
前記接続端子は前記部品の両端部に設けられ、前記パッドユニットはパッド対として前記導電パッドが対向して配設されていることを特徴とする請求項3に記載の部品内蔵基板。   The component built-in board according to claim 3, wherein the connection terminals are provided at both ends of the component, and the conductive pads are arranged to face the pad unit as a pad pair. 前記パッド対を形成する前記導電パッド間に前記部品と前記絶縁基材の表面との間隔を保持するためのスペーサが設けられていることを特徴とする請求項4に記載の部品内蔵基板。   The component-embedded substrate according to claim 4, wherein a spacer is provided between the conductive pads forming the pad pair to maintain a distance between the component and the surface of the insulating base. 前記接合材は半田であり、前記スペーサはソルダレジストであることを特徴とする請求項5に記載の部品内蔵基板。   6. The component built-in substrate according to claim 5, wherein the bonding material is solder, and the spacer is a solder resist.
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WO2009001621A1 (en) * 2007-06-26 2008-12-31 Murata Manufacturing Co., Ltd. Manufacturing method for part built-in substrate

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