WO2011127720A1 - 一种半导体器件的制造方法 - Google Patents

一种半导体器件的制造方法 Download PDF

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WO2011127720A1
WO2011127720A1 PCT/CN2010/077384 CN2010077384W WO2011127720A1 WO 2011127720 A1 WO2011127720 A1 WO 2011127720A1 CN 2010077384 W CN2010077384 W CN 2010077384W WO 2011127720 A1 WO2011127720 A1 WO 2011127720A1
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layer
metal
gate electrode
interface layer
thickness
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韩锴
王文武
王晓磊
陈世杰
陈大鹏
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Institute of Microelectronics of CAS
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01332—Making the insulator
    • H10D64/01336—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid
    • H10D64/01338—Making the insulator on single crystalline silicon, e.g. chemical oxidation using a liquid with a treatment, e.g. annealing, after the formation of the conductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/667—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
    • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 

Definitions

  • the present invention generally relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device for removing oxygen atoms in an interface layer in a high-k/metal gate device.
  • SiO 2 As a gate dielectric and heavily doped polysilicon as a gate electrode material in the fabrication of MOS devices.
  • Si0 2 gate dielectric in MOS transistors is approaching its limits. For example, in the 65 nm process, the thickness of the Si0 2 gate dielectric has dropped to 1.2 nm, which is about 5 silicon atomic layer thicknesses. If it continues to shrink, leakage current and power consumption will increase dramatically. At the same time, problems such as doping of boron atoms, polysilicon depletion effects, and excessive gate resistance caused by polysilicon gate electrodes will become more and more serious. For technologies at 32 nm and below, the dramatic increase in leakage current and power consumption will be urgently addressed by the development of new materials, processes, and new device structures.
  • an improved technique is to use a "high-k/metal gate” structure.
  • major semiconductor companies in the international arena have begun to develop "high-k/metal gate” technology for 32 nanometers and below.
  • Intel disclosed that the leakage current of the device is reduced by one tenth after the high-k gate dielectric material is used.
  • the interface layer is thickened during the annealing process due to the annealing process that must be employed.
  • a gate dielectric of EOT Equivalent Oxide Thickness
  • the gate dielectric EOT even needs to reach 0.7 nm or even 0.5 nm or less, while the interface layer Si0 2 thickness in the ordinary high k/metal gate process reaches 0.5-0.7 nm.
  • the present invention provides a method of fabricating a semiconductor device, the method comprising: providing a semiconductor substrate; forming an interface layer, a gate dielectric layer, and a gate electrode on the substrate; forming a metal oxygen absorption on the gate electrode
  • the device is thermally annealed to cause the metal oxygen gettering layer to absorb oxygen in the interface layer to reduce the thickness of the interface layer.
  • the metal oxygen gettering layer is formed by selecting an element from the group consisting of: Al, Be, La Y.
  • the metal oxygen gettering layer has a thickness of about 1 to 5 nm.
  • a metal oxygen gettering layer having an effect of absorbing oxygen in the interface layer is formed on the gate electrode to prevent oxygen in the external atmosphere from entering the interface layer during the annealing process, thereby preventing the Si0 2 interface layer.
  • the thickness is increased, and the oxygen absorption technique is utilized, so that the thickness of the Si0 2 interface layer having a thickness of 0.5-lnm is reduced to 0.5 nm or less during the annealing process, and even completely removed, effectively reducing the EOT of the device.
  • FIGS. 2-5 are schematic views showing respective stages of fabrication of a semiconductor device in accordance with a first embodiment of the present invention
  • the present invention generally relates to methods of fabricating semiconductor devices.
  • the following disclosure provides many different embodiments or examples for implementing different structures of the present invention.
  • the components and arrangements of the specific examples are described below. Of course, they are merely examples and are not intended to limit the invention.
  • the present invention may repeat reference numerals and/or letters in different examples. This repetition is for the purpose of brevity and clarity and does not in itself indicate the relationship between the various embodiments and/or arrangements discussed.
  • the present invention provides examples of various specific processes and materials, but one of ordinary skill in the art will recognize the applicability of other processes and/or the use of other materials.
  • the first feature described below on the second feature may include an embodiment in which the first and second features are formed in direct contact, and may further include additional features formed in the first and second features. Between the embodiments, such that the first and second features may not be directly connected Touch.
  • the substrate 101 includes a silicon substrate (e.g., a wafer) in a crystal structure, and the substrate 101 may further include other basic semiconductor or compound semiconductors such as Si, Ge, GeSi, GaAs, InP, SiC or diamond. Wait.
  • the substrate 101 can include various doping configurations in accordance with design requirements well known in the art (e.g., p-type or n-type substrates).
  • the substrate 101 may include an epitaxial layer that may be altered by stress to enhance performance, and may include a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • an interface layer 102, a gate dielectric layer 103, and a gate electrode 104 are formed on the substrate 101. as shown in picture 2.
  • the interface layer 102 may be formed on the substrate 101 in a manner of thermal growth.
  • the interface layer 102 is Si0 2 , and may also be an oxynitride layer having a thickness of about 0.7 nm.
  • a gate dielectric layer 103 and a gate electrode 104 are formed on the interface layer 102.
  • the gate dielectric layer 103 is a high-k gate dielectric layer 103.
  • a high-k gate dielectric layer 103 such as a high-k dielectric material Hf0 2 , HfSiO x , HfZrO x , HfLaO x , HfLaON x , and La 2 0 3 , is grown on the interface layer 102 by an ALD technique. The thickness is about 0.5 nm to 3 nm.
  • a gate electrode 104 is deposited on the high-k gate dielectric layer 103.
  • the gate electrode may be a multilayer structure and may include metals, metal compounds, and metal silicides, and combinations thereof.
  • the gate electrode is a metal gate 104 having a thickness of about 5 nm to 50 nm, and may include Hf, TiN, TaN, MoN, TiAlN, ⁇ 1 ⁇ , HfCN x , HfC, TiC, TaC, Ru, Re, Pt, Ru0 2 , TaRu x , HfRu, and combinations thereof.
  • a metal oxygen gettering layer 105 is formed on the gate electrode 104.
  • the metal oxygen gettering layer 105 may be formed by a method such as deposition or co-sputtering to have a thickness of about 1 to 5 nm, preferably 2 nm.
  • the metal oxygen gettering layer may include Al, Be, La, and Y.
  • the device structure is thermally annealed to cause the metal oxygen gettering layer 105 to absorb oxygen in the interface layer 102 to reduce the thickness of the interface layer 102.
  • the annealing process can be temperature and time controlled, such as lowering the annealing temperature and extending the annealing time, so that the metal in the metal oxygen gettering layer diffuses into the entire gate electrode 104, even the gate dielectric layer 103, for adjustment.
  • the effective work function which achieves the effect of adjusting the threshold voltage of the NMOS device and the PMOS device.
  • the annealing process can oxidize the oxygen gettering layer 105 to a metal oxide, making the thickness of the interface layer 102 small, as shown in FIG.
  • the heat treatment temperature is about 300 to 1000 ° C, preferably 400 ° C
  • the time is about 1 to 300 s, preferably 60 s.
  • a subsequent fabrication process can be performed on the device, including: patterning the metal oxygen gettering layer 105, the gate electrode 104 and the gate dielectric layer 103, and the interface layer 102 to form a gate stack, and stacking the gates
  • the sidewalls form sidewalls, and the source and drain regions are formed.
  • source/drain shallow junction regions may be formed to form the final semiconductor device structure.
  • a metal oxygen gettering layer 105 is formed on the gate electrode 104, and the oxygen gettering layer 105 is formed of a metal such as Al, Be, La or Y, and then thermally annealed, and the annealing time is appropriately selected during the annealing process.
  • temperature, the annealing time and temperature are selected according to the mutual thickness of the oxygen absorbing layer and the gate dielectric layer, and in the embodiment of the present invention, the annealing temperature is selected to be 600 ° C and the annealing time is 20 s.
  • one annealing or multiple annealing may be selected as needed.
  • the metal in the metal oxygen absorbing layer is diffused into the entire gate electrode 104, even the gate dielectric layer 103, in order to adjust the effective work function, thereby achieving the effect of adjusting the threshold voltage of the NMOS device and the PMOS device.
  • diffusion of metal Al, La, Y into the entire metal gate and/or high-k gate dielectric layer can also adjust the effective work function of the NMOS device; while A1 and Be diffuse into the metal gate and/or high-k gate dielectric layer. Adjust the effective work function of the PMOS device.
  • the Gibbs free energy generated by the selected metal becomes much larger than Si, it means that the oxide of these metals is more stable and easier to form than the silicon oxide in the interface layer 102. Therefore, in the high temperature process, the interface layer Si0 The oxygen in 2 is driven to form a metal oxide with these oxygen gettering layers 105, resulting in the thickness of the interface layer 102 becoming smaller or even disappearing, effectively reducing the EOT.
  • the metal oxide 112 or the unsaturated metal oxide can prevent the oxygen in the external atmosphere from entering the interface during the annealing process of the subsequent process.
  • Layer 102 prevents or reduces the potential for increased thickness of interface layer 102, thereby avoiding an increase in EOT and also reducing EOT.

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

一种半导体器件的制造方法
技术领域
本发明通常涉及半导体器件的制造方法， 具体来说， 涉及去除高 k/金 属栅器件中界面层中氧原子的半导体器件的制造方法。 背景技术
在微电子技术发展的几十年来， 逻辑芯片制造商在制造 MOS器件时， 一直釆用 Si02作为栅介质， 釆用重掺杂的多晶硅作为栅电极材料。 但是， 随着特征尺寸的不断缩小， MOS晶体管中的 Si02栅介质已临近了极限。例 如， 在 65纳米工艺中， Si02栅介质的厚度已降至 1.2纳米， 约为 5个硅原 子层厚度， 如果再继续缩小， 漏电流和功耗将急剧增加。 同时， 由多晶硅 栅电极引起的掺杂硼原子扩散、 多晶硅耗尽效应、 以及过高的栅电阻等问 题也将变的越来越严重。 对于 32纳米及以下各技术代， 急剧增加的漏电流 和功耗等问题将急待新材料、 新工艺、 及新器件结构的开发来解决。
为降低漏电流和功耗， 有一种改进技术是釆用"高 k/金属栅"结构。 目 前， 国际范围内的各主要半导体公司都已开始着手面向 32纳米及以下技术 代的"高 k/金属栅"技术的开发。 Intel披露出在釆用高 k栅介质材料后， 器 件的漏电流降为原来的十分之一。 但是， 在高 k/金属栅工艺中， 由于必须 釆用的退火工艺， 致使界面层在退火工艺中变厚。 但由于在 45nm 以下的 CMOS 器件存在着非常严重的短沟道效应， 需要 EOT ( Equivalent Oxide Thickness, 等效氧化层厚度） 不超过 lnm的栅介质来提高对沟道的控制能 力， 所以厚的界面层 Si02是不可接受的。 尤其在 32纳米及 22纳米工艺技 术中， 栅极介质 EOT甚至需要达到 0.7纳米甚至 0.5纳米以下， 而普通高 k/金属栅工艺中界面层 Si02厚度就达到了 0.5-0.7纳米。
因此， 需要提出一种能够有效减小 EOT, 特别是减小界面层厚度的半 导体器件制造方法。 发明内容
本发明提供了一种半导体器件的制造方法， 所述方法包括： 提供半导 体衬底； 在所述衬底上形成界面层、 栅介质层和栅电极； 在所述栅电极上 形成金属氧吸除层； 对所述器件进行热退火处理， 以使所述金属氧吸除层 吸除界面层中的氧， 使界面层的厚度减小。 其中， 所述金属氧吸除层从包 含下列元素的组中选择元素来形成： Al、 Be、 La Y。 所述金属氧吸除层 的厚度为大约为 l-5nm。
通过釆用本发明所述的方法， 在栅电极上形成具有吸除界面层中氧的 作用的金属氧吸除层， 阻止退火过程中外界氛围里的氧进入界面层， 防止了 Si02界面层的厚度增加， 并利用氧吸除技术，使得原本厚度达 0.5-lnm的 Si02 界面层在退火过程中厚度减少为 0.5纳米以下， 甚至完全去除， 有效地减小了 器件的 EOT。 附图说明
图 1示出了根据本发明的第一实施例的半导体器件的制造方法的流程图； 图 2-5示出了根据本发明的第一实施例的半导体器件各个制造阶段的示意 图； 具体实施方式
本发明通常涉及制造半导体器件的方法。 下文的公开提供了许多不同 的实施例或例子用来实现本发明的不同结构。 为了简化本发明的公开， 下 文中对特定例子的部件和设置进行描述。 当然， 它们仅仅为示例， 并且目 的不在于限制本发明。 此外， 本发明可以在不同例子中重复参考数字和 /或 字母。 这种重复是为了简化和清楚的目的， 其本身不指示所讨论各种实施 例和 /或设置之间的关系。 此外， 本发明提供了的各种特定的工艺和材料的 例子， 但是本领域普通技术人员可以意识到其他工艺的可应用于性和 /或其 他材料的使用。 另外， 以下描述的第一特征在第二特征之 "上，，的结构可以 包括第一和第二特征形成为直接接触的实施例， 也可以包括另外的特征形 成在第一和第二特征之间的实施例， 这样第一和第二特征可能不是直接接 触。
根据本发明的第一实施例， 参考图 1 , 图 1示出了根据本发明的半导体器 件的制造方法的流程图。 在步骤 S11 , 提供半导体衬底， 参考图 2。 在本实 施例中， 衬底 101 包括位于晶体结构中的硅衬底 （例如晶片 ) , 衬底 101 还可以包括其他基本半导体或化合物半导体， 例如 Si、 Ge、 GeSi、 GaAs、 InP、 SiC或金刚石等。 根据现有技术公知的设计要求 （例如 p型衬底或者 n型衬底） ， 衬底 101 可以包括各种掺杂配置。 此外， 可选地， 衬底 101 可以包括外延层， 可以被应力改变以增强性能， 以及可以包括绝缘体上硅 ( SOI ) 结构。
在步骤 S12 , 在所述衬底 101上形成界面层 102、 栅介质层 103和栅电 极 104。如图 2所示。可以热生长的方式在所述衬底 101上形成界面层 102, 在本发明实施例中， 界面层 102为 Si02 , 也可以为氮氧化物层， 其厚度为 大约 0.7nm。 而后， 如图 3所示， 在所述界面层 102上形成栅介质层 103和栅 电极 104。 优选地， 所述栅介质层 103为高 k栅介质层 103。 具体来说， 首先， 在所述界面层 102上利用 ALD技术生长高 k栅介质层 103 , 例如高 k介质材 料 Hf02、 HfSiOx、 HfZrOx、 HfLaOx、 HfLaONx和 La203 , 其厚度为大约 0.5nm-3nm。 然后， 在所述高 k栅介质层 103上沉积栅电极 104。 所述栅电极 可以为多层结构， 可包括金属、 金属化合物和金属硅化物及其他们的组合。 在本发明实施例中， 所述栅电极为金属栅极 104厚度为大约 5nm至 50nm , 可以包括 Hf 、 TiN、 TaN、 MoN、 TiAlN、 ΜοΑ1Ν、 HfCNx、 HfC、 TiC、 TaC、 Ru、 Re、 Pt、 Ru02、 TaRux、 HfRu及其组合。
而后在步骤 S13 , 在所述栅电极 104上形成金属氧吸除层 105。 如图 4 所示，可以通过例如沉积或者共溅射等方法形成所述金属氧吸除层 105 ,其 厚度为大约 l-5nm, 优选为 2nm。 所述金属氧吸除层可以包括 Al、 Be、 La 和 Y。
在步骤 S14 , 对所述器件结构进行热退火处理， 以使所述金属氧吸除层 105吸除界面层 102 中的氧， 使界面层 102的厚度减小。 可以对退火工艺 进行温度和时间的控制， 如降低退火温度和延长退火时间， 以使金属氧吸 除层中的金属扩散进入整个栅电极 104, 甚至栅介质层 103 中， 以便调节 有效功函数， 从而实现调节 NMOS器件和 PMOS器件阔值电压的效果。 此 外， 退火工艺可以使氧吸除层 105氧化为金属氧化物， 使界面层 102厚度 变小， 如图 5 所示。 在本实施例中， 热处理温度为大约 300-1000°C, 优选 为 400°C, 时间为大约 l-300s, 优选为 60s。
而后， 可以对所述器件进行后续制造工艺， 包括： 对所述金属氧吸除 层 105、 栅电极 104和栅介质层 103 以及界面层 102进行图形化， 以形成 栅堆叠， 以及在栅堆叠的侧壁形成侧墙， 以及形成源极区和漏极区， 在形 成源极区和漏极区之前， 可以先形成源 /漏浅结区， 从而形成最终的半导体 器件结构。
以上对利用氧吸除层 105减小界面层 102厚度的方法进行了描述。 根 据本发明的实施例， 在栅电极 104上形成金属氧吸除层 105 , 氧吸除层 105 由 Al、 Be、 La或 Y等金属形成， 而后进行热退火， 在退火过程中合理选 择退火时间和温度， 根据吸氧层和栅介质层的相互厚度选择退火时间和温 度， 在本发明的实施例中选择退火温度为 600°C, 退火时间为 20s。 此外， 可以根据需要选择一次退火或者多次退火。 最终使金属吸氧层中的金属扩 散进入整个栅电极 104, 甚至栅介质层 103 , 以便调节有效功函数， 从而实 现调节 NMOS器件和 PMOS器件阔值电压的效果。 例如， 金属 Al、 La、 Y 扩散到整个金属栅和 /或高 k栅介质层中可以也调节 NMOS器件的有效功函 数；而 A1和 Be扩散到金属栅和 /或高 k栅介质层中可以调节 PMOS器件的 有效功函数。 同时由于所选用的金属生成吉布斯自由能变远大于 Si, 这意 味着这些金属的氧化物比界面层 102 中硅的氧化物更加稳定和容易形成， 因此， 在高温过程中， 界面层 Si02中的氧被驱动与这些氧吸除层 105形成 金属氧化物， 从而导致界面层 102厚度变小， 甚至消失， 有效减小了 EOT。 另外， 在合理控制退火温度和时间的氧吸除层 105 氧化为金属氧化物 112 后， 金属氧化物 112或为不饱和金属氧化物， 可以阻止后续工艺的退火过程 中外界氛围里的氧进入界面层 102,防止或减小界面层 102的厚度增加的可能， 从而避免 EOT的增加， 也减小了 EOT。
虽然关于示例实施例及其优点已经详细说明，应当理解在不脱离本发明的 精神和所附权利要求限定的保护范围的情况下 ,可以对这些实施例进行各种变 化、 替换和修改。 对于其他例子， 本领域的普通技术人员应当容易理解在保持 本发明保护范围内的同时， 工艺步骤的次序可以变化。
此外， 本发明的应用范围不局限于说明书中描述的特定实施例的工艺、机 构、 制造、 物质组成、 手段、 方法及步骤。 从本发明的公开内容， 作为本领域 的普通技术人员将容易地理解， 对于目前已存在或者以后即将开发出的工艺、 机构、 制造、 物质组成、 手段、 方法或步骤， 其中它们执行与本发明描述的对 应实施例大体相同的功能或者获得大体相同的结果，依照本发明可以对它们进 行应用。 因此， 本发明所附权利要求旨在将这些工艺、机构、制造、物质组成、 手段、 方法或步骤包含在其保护范围内。

Claims

权 利 要 求
1. 一种半导体器件的制造方法， 所述方法包括：
提供半导体衬底；
在所述衬底上形成界面层、 栅介质层和栅电极；
在所述栅电极上形成金属氧吸除层；
对所述器件进行热退火处理， 以使所述金属氧吸除层吸除界面层中的 氧， 使界面层的厚度减小。
2. 根据权利要求 1所述的方法， 其中所述金属氧吸除层从包含下列元 素的组中选择元素来形成： Al、 Be、 ！^和丫。
3. 根据权利要求 1 所述的方法， 其中所述金属氧吸除层的厚度为 l-5nm。
4. 根据权利要求 1 所述的方法， 其中所述热退火处理的温度为 300-1000°C。
5.根据权利要求 4所述的方法，其中所述热退火处理的时间为 l-300s。
6. 根据权利要求 1所述的方法， 其中所述栅介质层从包含下列元素的 组中选择元素来形成： Hf02、 HfSiOx、 HfZrOx, HfLaOx、 HfLaONx和 La203 及其组合。
7. 根据权利要求 1所述的方法， 其中所述栅电极从包含下列元素的组 中选择元素来形成： Hf 、 TiN、 TaN、 MoN、 TiAlN、 ΜοΑ1Ν、 HfCNx、 HfC、 TiC、 TaC、 Ru、 Re、 Pt、 Ru02、 TaRux、 Hf u及其组合。
8. 根据权利要求 1所述的方法， 其中所述金属氧吸除层通过沉积或共 溅射方式形成。
PCT/CN2010/077384 2010-04-14 2010-09-28 一种半导体器件的制造方法 Ceased WO2011127720A1 (zh)

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