WO2011124002A1 - 一种半导体结构及其制造方法 - Google Patents

一种半导体结构及其制造方法 Download PDF

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WO2011124002A1
WO2011124002A1 PCT/CN2010/001439 CN2010001439W WO2011124002A1 WO 2011124002 A1 WO2011124002 A1 WO 2011124002A1 CN 2010001439 W CN2010001439 W CN 2010001439W WO 2011124002 A1 WO2011124002 A1 WO 2011124002A1
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band gap
wide band
layer
silicon
semiconductor layer
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French (fr)
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尹海洲
朱慧珑
骆志炯
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to GB1121918.5A priority Critical patent/GB2484420A/en
Priority to CN201090000830.XU priority patent/CN202917448U/zh
Publication of WO2011124002A1 publication Critical patent/WO2011124002A1/zh
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3218—Phosphides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3221—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3404—Deposited materials, e.g. layers characterised by the chemical composition being Group IVA materials
    • H10P14/3411—Silicon, silicon germanium or germanium

Definitions

  • the present invention relates to semiconductor fabrication technology, and more particularly to a semiconductor structure and a method of fabricating the same. Background technique
  • SCE Severe short channel effect
  • Ultrathin silicon-on-insulator is a typical technique used to suppress short channel effects.
  • a silicon oxide 102 as an insulating layer is interposed between the silicon substrate 101 and the top silicon 103, which is called a buried oxide layer (BOX).
  • BOX buried oxide layer
  • the ultra-thin silicon channel provided by the ultra-thin silicon-on-insulator device limits the depth of the source and drain regions, improves the gate-to-channel control, and suppresses the short channel effect.
  • Silicon wafer bonding technology is currently commonly used to fabricate ultra-thin silicon-on-insulator.
  • the fabrication of ultra-thin insulating silicon by wafer bonding technology is highly demanding, and it is easy to cause lattice defects on the contact surface during wafer bonding, resulting in low yield.
  • the thickness of the ultra-thin silicon layer is difficult to control, the uniformity of the top silicon 103 on the buried oxide layer is poor.
  • a semiconductor structure comprising: a silicon substrate; a wide band gap semiconductor layer formed on the silicon substrate; and a silicon layer formed on the wide band gap semiconductor layer.
  • a method of fabricating a semiconductor structure comprising: growing a wide band gap semiconductor layer on a silicon substrate; and growing a silicon layer on the wide band gap semiconductor layer.
  • the wide band gap semiconductor layer may be formed of any one or a combination of the following: GaP, GaAs, AlAs.
  • the wide band gap semiconductor layer comprises at least one layer, wherein the wide band gap semiconductor
  • the thickness of the layer is 5 to 50 nm.
  • the thickness of the silicon layer is 5 to 20 nm.
  • the wide bandgap semiconductor layer is formed of a wide bandgap semiconductor material having a band gap width greater than 1.5 ev. Further, the difference between the lattice constant of the wide band gap semiconductor material and the lattice constant of Si is 2% or less.
  • the technical solution adopted by the embodiment of the invention solves the problem that the silicon on the ultra-thin insulator has high manufacturing requirements and low yield, and the semiconductor device manufactured by using the embodiment of the invention can suppress the short channel effect of the device. , improve electrical and physical properties.
  • FIG. 1 is a schematic structural view of a silicon-on-insulator of the prior art
  • FIG. 2 is a schematic view of a semiconductor structure in accordance with an embodiment of the present invention.
  • Figure 3 is the relationship between the band gap and the lattice constant of a common semiconductor material
  • FIG. 4 is a flow chart of a method of fabricating a semiconductor structure in accordance with an embodiment of the present invention. detailed description
  • the semiconductor structure and the manufacturing method thereof provided by the embodiments of the present invention solve the problem that the silicon structure on the ultra-thin insulator is high in requirements and the yield is low, and the short channel effect is well suppressed.
  • FIG. 2 shows a schematic structural view of a semiconductor structure 200 in accordance with an embodiment of the present invention.
  • the semiconductor structure 200 includes a silicon substrate 201, one or more wide band gap semiconductor layers 202 formed on a silicon substrate, and silicon formed on one or more of the wide band gap semiconductor layers 202.
  • Layer 203 The thickness of one or more of the wide band gap semiconductor layers 202 is preferably 5 to 50 nm, and the thickness of the silicon layer 203 is preferably 5 to 20 nm.
  • the top silicon layer 203 may also be referred to as top layer silicon.
  • Figure 3 shows the relationship between the band gap and the lattice constant of a common semiconductor material.
  • the lattice constant of silicon is 5.43 A, and the band gap is 1. leV. Therefore, a material having a lattice constant close to that of silicon and having a band gap width larger than that of silicon is selected to form a wide band gap semiconductor layer 202, such as GaP, GaAs, AlAs, or the like. Or their compositions.
  • an intermediate wide band gap semiconductor layer is formed using GaP.
  • the lattice constant of GaP is very close to Si and has a high band gap width. Generally, we think that the semiconductor material with a band gap width exceeding 1.5 ev is a wide band gap semiconductor. Material.
  • the difference between the lattice constant of the wide band gap semiconductor material and the lattice constant of Si is not more than 2%.
  • the lattice constant of Si is 5.43A, so the lattice constant of the wide band gap semiconductor material we choose is preferably between 5.3A and 5.5A, which can better avoid lattice defects caused by epitaxial growth.
  • the semiconductor material having a large lattice constant is selected, which is also related to the thickness of the wide band gap semiconductor layer and the top silicon to be formed.
  • the difference between the lattice constant of the wide band gap semiconductor material and Si is large, the wide band gap semiconductor The layer and the top layer of silicon should not be too thick to avoid lattice defects.
  • Embodiments of the present invention use a wide bandgap semiconductor material in place of an oxide layer in silicon on a substrate in which a semiconductor device is fabricated.
  • the ultrathin silicon channel formed by the device limits the depth of the source and drain regions and improves the gate-to-ditch.
  • the control capability of the track thereby suppressing the short channel effect of the semiconductor device.
  • the lattice constant of the wide band gap semiconductor material used in the embodiment of the present invention is very close to that of silicon, thereby ensuring a better lattice structure at the contact interface.
  • each wide band gap semiconductor layer 202 may be provided, and each of the wide band gap semiconductor layers may be composed of the above wide band gap material or a combination thereof.
  • the wide band gap material has a crystal structure in which strain is generated to match the crystal structure of the semiconductor substrate material. With the semiconductor structure formed by the embodiment of the present invention, since the wide band gap semiconductor layer has a crystal structure, it is more advantageous for source/drain epitaxial growth of the semiconductor device than the amorphous state of the oxide layer in the silicon on the ultrathin insulator.
  • the embodiment of the present invention is not limited thereto, and for example, a multilayer wide band gap semiconductor layer may be formed, and the material of each layer may be different.
  • the materials of the respective layers may be GaP, GaAs, AlAs, etc., respectively, or a combination thereof.
  • the use of a semiconductor material having a large band gap width as a part of the semiconductor device substrate enables the semiconductor device to have a small leakage current.
  • step S401 a GaP layer 202 is epitaxially grown on a silicon substrate 201.
  • GaP layer in addition to growing the GaP layer, other wide band gap semiconductor layers such as GaAs, AlAs, etc., or combinations thereof may be grown; and wide band gap semiconductor layers may also be grown by other techniques, such as Deposition techniques and the like well known to those skilled in the art.
  • a wide band gap semiconductor layer can be grown, or multiple layers can be grown.
  • the wide band gap semiconductor layer has a thickness of 5 to 50 nm.
  • the total thickness of the multilayer wide band gap semiconductor layer is 5 to 50 nm.
  • different materials, GaP, GaAs, AlAs, etc., or a combination thereof may be grown per layer, and the same material may be grown.
  • the thickness of the wide band gap semiconductor layer can be easily controlled by the method adopted in the embodiment of the present invention, and can be rooted It is adjusted as needed to better suppress the short channel effect of the device.
  • a silicon layer 203 having a thickness of 5 to 20 nm is grown on the GaP layer 202. It is also possible to form a silicon layer by epitaxial growth or deposition techniques.
  • the thickness of the top silicon of silicon on ultra-thin insulators is generally less than 30 nm, and the uniformity of the top silicon is not easily controlled.
  • the top silicon layer is grown by epitaxy or deposition techniques to provide better control of the thickness of the top silicon layer and better uniformity of the top silicon layer compared to wafer bonding techniques.
  • the manufacturing method of the semiconductor structure employed in the embodiment of the present invention avoids the problem of a large number of lattice defects of the contact surface due to atomic squeeze in the wafer bonding technique.
  • the embodiment of the present invention uses a method of epitaxial growth or deposition to form a wide band gap semiconductor layer and a top layer silicon, which can well control the thickness of the wide band gap semiconductor layer and the top layer silicon.
  • the semiconductor structure fabrication method according to the present invention does not require wafer bonding, but requires only inexpensive and easy to operate epitaxial or deposition growth, which can significantly reduce process complexity and cost.
  • the thickness of the grown top layer silicon can be precisely controlled and has better uniformity than the top layer silicon formed by polishing.
  • the epitaxially grown silicon layer has a more regular lattice structure, which contributes to the subsequent growth of source and drain regions.
  • the thickness of the wide band gap semiconductor layer formed by epitaxial growth can be made thinner than the buried oxide layer of silicon on the ultrathin insulator, so that the short channel effect can be further suppressed.

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Description

一种半导体结构及其制造方法 技术领域
本发明涉及半导体制造技术， 尤其涉及一种半导体结构及其制造方法。 背景技术
现代集成电路制造中的普遍趋势是生产尺寸越来越小的半导体器件， 例如存储单 元。
虽然制造纳米尺度的晶体管允许将更多的晶体管集成在单个晶片上， 从而能够在 更小的区域中形成更大的电路系统， 然而晶体管尺寸的不断缩小导致沟道长度的减 小， 从而引起愈发严重的短沟道效应 （SCE)。
超薄绝缘体上硅（UTSOI)是用于抑制短沟道效应的一种典型技术。如图 1所示， 在绝缘体上硅结构 100中， 硅衬底 101和顶层硅 103之间有一层作为绝缘层的二氧化 硅 102， 称为埋氧层（BOX)。采用超薄绝缘体上硅的器件所提供的超薄硅沟道限制了 源区和漏区的深度， 提高了栅对沟道的控制能力， 抑制了短沟道效应。
目前一般利用晶片键合技术制作超薄绝缘体上硅。通过晶片键合技术制造超薄绝 缘体上硅对工艺要求很高， 在晶片键合中容易造成接触面上的晶格缺陷， 从而导致良 品率低。此外， 由于超薄硅层的制造很难控制厚度， 因此，位于埋氧层上的顶层硅 103 的均匀性较差。 发明内容
因此， 希望提供一种半导体结构及其制作方法， 其具有与超薄绝缘体上硅类似 的抑制短沟道效应的功能， 并且性能更加稳定， 且更加易于制造。
根据本发明的一个方面， 提供了一种半导体结构， 包括： 硅衬底； 形成于所述 硅衬底上的宽带隙半导体层； 以及形成于所述宽带隙半导体层上的硅层。
根据本发明的另一方面， 提供了一种制造半导体结构的方法， 包括： 在硅衬底 上生长宽带隙半导体层； 和在所述宽带隙半导体层上生长硅层。
在上述方案的基础上， 优选地， 其中所述宽带隙半导体层可以由以下任一种或 多种的组合形成： GaP、 GaAs、 AlAs。
优选地， 其中所述所述宽带隙半导体层包括至少一层， 其中所述宽带隙半导体 层的厚度是 5〜50nm。
优选地， 其中所述硅层的厚度是 5〜20nm。
所述宽带隙半导体层由宽带隙半导体材料形成， 所述宽带隙半导体材料的带隙 宽度大于 1.5ev。 并且， 宽带隙半导体材料的晶格常数与 Si的晶格常数的差值小于等于 2%。
通过本发明实施例所采用的技术方案， 解决了超薄绝缘体上硅制造要求高且良品 率低的问题， 并且采用本发明实施例制造的半导体器件， 能够很好的抑制器件的短沟 道效应， 提高电学性能和物理性能。 附图说明
参考附图， 以示例而非限制的方式来描述实施例， 附图中相似的附图标记表示 相应的或类似的元件， 其中：
图 1是现有技术的绝缘体上硅的结构示意图；
图 2是根据本发明实施例的半导体结构的示意图；
图 3是常用半导体材料的带隙与晶格常数之间的关系；
图 4是根据本发明实施例的半导体结构的制造方法流程图。 具体实施方式
本发明的实施例提供的半导体结构及其制作方法， 其形成的半导体结构解决了超 薄绝缘体上硅工艺要求高且良品率低的问题， 并且较好地抑制了短沟道效应。
图 2示出了根据本发明实施例的一种半导体结构 200的结构示意图。 如图 2所示， 该半导体结构 200包括硅衬底 201、 形成于硅衬底上的一层或多层宽带隙半导体层 202， 以及形成于一层或多层宽带隙半导体层 202上的硅层 203。 其中， 一层或多层宽带隙半 导体层 202的厚度优选为 5〜50nm， 硅层 203的厚度优选为 5〜20nm。 顶部硅层 203也可 以称为顶层硅。
图 3示出了常用半导体材料的带隙与晶格常数之间的关系。 硅的晶格常数为 5.43A, 带隙为 1. leV, 因此选择与硅的晶格常数接近， 并且带隙宽度大于硅的材料来 形成宽带隙半导体层 202， 例如 GaP、 GaAs、 AlAs等， 或它们的组合物。 在本发明的 实施例中， 采用 GaP形成中间的宽带隙半导体层。 GaP的晶格常数与 Si非常接近， 并且 具有很高的带隙宽度。通常我们认为带隙宽度超过 1.5ev的半导体材料为宽带隙半导体 材料。 此外优选地， 宽带隙半导体材料的晶格常数与 Si的晶格常数的差值不大于 2%。 例如， Si的晶格常数为 5.43A , 因此我们选择的宽带隙半导体材料晶格常数最好在 5.3A〜5.5 A之间， 能够较好地避免在外延生长中引起的晶格缺陷。 具体地选择晶格常 数为多大的半导体材料， 还与需要形成的宽带隙半导体层以及顶层硅的厚度有关， 通 常如果宽带隙半导体材料的晶格常数与 Si的差值较大， 则宽带隙半导体层以及顶层硅 不宜过厚， 以免引起晶格缺陷。
本发明的实施例在制造半导体器件的衬底中采用宽带隙半导体材料替代绝缘体 上硅中的氧化层， 器件形成的超薄硅沟道限制了源区和漏区的深度， 能够提高栅对沟 道的控制能力， 从而抑制了半导体器件的短沟道效应。 并且本发明实施例采用的宽带 隙半导体材料的晶格常数与硅非常接近， 从而能够保证接触界面上较好的晶格结构。
尽管图中仅示出了一个宽带隙半导体层 202， 但是可以设置一层或多层宽带隙半 导体层 202， 每层宽带隙半导体层可以由上述宽带隙材料或其组合物构成。 所述宽带 隙材料具有晶体结构， 其中产生应变以便与半导体衬底材料的晶体结构相匹配。 通过 本发明实施例形成的半导体结构， 由于宽带隙半导体层为晶体结构， 与超薄绝缘体上 硅中的氧化层的非晶态相比， 则更有利于半导体器件的源 /漏的外延生长。
本发明的实施例并不局限于此， 例如可以形成多层宽带隙半导体层， 每层的材料 可以不同。 各层的材料可以分别是 GaP、 GaAs、 AlAs等， 或它们的组合物。
采用带隙宽度较大的半导体材料作为半导体器件衬底的一部分， 能够使半导体器 件具有较小的漏电流。
图 4示出了根据本发明的实施例制造半导体结构的方法的流程图。 在步骤 S401 , 在硅衬底 201上外延生长 GaP层 202。
本领域普通技术人员可知， 除了生长 GaP层之外， 还可以生长其他的宽带隙半导 体层， 例如 GaAs、 AlAs等， 或者是它们的组合物； 还可以通过其他技术生长宽带隙半 导体层， 例如本领域普通技术人员熟知的淀积技术等。
可以生长一层宽带隙半导体层， 也可以生长多层。 在一层宽带隙半导体层的情况 下， 优选地， 该宽带隙半导体层的厚度是 5〜50nm。 在多层宽带隙半导体层的情况下， 优选地， 该多层宽带隙半导体层的总厚度是 5〜50nm。 在生长多层宽带隙半导体层的 情况下， 可以每层生长不同的材料， GaP、 GaAs、 AlAs等， 或它们的组合物， 也可以 生长相同的材料。
通过本发明实施例采用的方法， 宽带隙半导体层的厚度很容易进行控制， 可以根 据需要调节， 从而能够较好地抑制器件的短沟道效应。
然后， 在步骤 S402, 在 GaP层 202上生长一层厚度为 5〜20nm的硅层 203。 同样也 可以用外延生长或淀积技术生成硅层。 超薄绝缘体上硅的顶层硅厚度一般小于 30nm， 顶层硅的均匀性很不容易控制。 通过外延或淀积技术生长顶部硅层， 与晶片键合技术 相比能够很好地控制顶部硅层的厚度， 并且顶部硅层的均匀性更好。
在硅衬底上生长宽带隙半导体层， 在一层宽带隙半导体层上生长其他宽带隙半导 体层， 以及在宽带隙半导体层上生长硅层的外延、 淀积方法是本领域技术人员所熟知 的， 故此省略对其的详细说明， 以免不必要地模糊本发明的主旨。
本发明实施例采用的半导体结构的制造方法， 避免了晶片键合技术中由于原子挤 压造成的接触面大量的晶格缺陷的问题。 本发明实施例采用外延生长或淀积方法形成 宽带隙半导体层以及顶层硅的方法， 能够很好的控制宽带隙半导体层以及顶层硅的厚 度。
根据本发明的半导体结构制造方法不需要晶片键合， 而只需要成本低廉且易于操 作的外延或淀积生长， 可以显著降低工艺复杂度和成本。 生长的顶层硅的厚度可以被 精确地控制， 并且具有比抛光形成的顶层硅更好的均匀性。 同时， 外延生长的硅层具 有更加规则的晶格结构， 有助于后续的源、 漏区生长。 此外， 与超薄绝缘体上硅的埋 氧层相比， 外延生长形成的宽带隙半导体层的厚度可以很薄， 因此可以进一步抑制短 沟道效应。
以上结合本发明的实施例描述了本发明， 但是本领域的技术人员可以理解， 在 不背离所附权利要求的范围的前提下， 可以进行其他改变或改造， 仍属于本发明的保 护范围。

Claims

^
1、 一种半导体结构， 包括：
硅衬底；
形成于所述硅衬底上的宽带隙半导体层； 以及
形成于所述宽带隙半导体层上的硅层。
2、 根据权利要求 1所述的半导体结构， 其中所述宽带隙半导体层由以下任一种 或多种的组合形成： GaP、 GaAs、 AlAs。
3、根据权利要求 1所述的半导体结构，其中所述宽带隙半导体层包括至少一层。
4、 根据权利要求 1所述的半导体结构， 其中所述宽带隙半导体层的厚度是 5〜
50nm。
5、 根据权利要求 1所述的半导体结构， 其中所述硅层的厚度是 5〜20nm。
6、 根据权利要求 1所述的半导体结构， 所述宽带隙半导体层由宽带隙半导体材 料形成， 所述宽带隙半导体材料的带隙宽度大于 1.5ev。
7、 根据权利要求 1至 6中任一项所述的半导体结构， 形成所述宽带隙半导体层的 半导体材料的晶格常数与 Si的晶格常数的差值小于等于 2%。
8、 一种制造半导体结构的方法， 包括- 在硅衬底上生长宽带隙半导体层； 和
在所述宽带隙半导体层上生长硅层。
9、 根据权利要求 8所述的方法， 所述在硅衬底上生长宽带隙半导体层具体为- 在硅衬底上生长由以下任一种或多种的组合形成的宽带隙半导体层： GaP、 GaAs、 AlAso
10、 根据权利要求 8所述的方法， 所述在硅衬底上生长宽带隙半导体层包括： 在所述硅衬底上生长至少一层宽带隙半导体层。
11、 根据权利要求 8所述的方法， 其中所述宽带隙半导体层的厚度是 5〜50nm。
12、 根据权利要求 8所述的方法， 其中所述硅层的厚度是 5〜20nm。
13、根据权利要求 8所述的方法，所述宽带隙半导体层由宽带隙半导体材料形成， 所述宽带隙半导体材料的带隙宽度大于 1.5ev。
14、 根据权利要求 8至 13中任一项所述的方法， 形成所述宽带隙半导体层的半导 体材料的晶格常数与 Si的晶格常数的差值小于等于 2%。
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