WO2011121969A1 - 画像表示装置およびシャッタ眼鏡 - Google Patents
画像表示装置およびシャッタ眼鏡 Download PDFInfo
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- WO2011121969A1 WO2011121969A1 PCT/JP2011/001806 JP2011001806W WO2011121969A1 WO 2011121969 A1 WO2011121969 A1 WO 2011121969A1 JP 2011001806 W JP2011001806 W JP 2011001806W WO 2011121969 A1 WO2011121969 A1 WO 2011121969A1
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- signal
- shutter
- eye
- control signal
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
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- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B30/00—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images
- G02B30/20—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes
- G02B30/22—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the stereoscopic type
- G02B30/24—Optical systems or apparatus for producing three-dimensional [3D] effects, e.g. stereoscopic images by providing first and second parallax images to an observer's left and right eyes of the stereoscopic type involving temporal multiplexing, e.g. using sequentially activated left and right shutters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
- G09G3/288—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels
- G09G3/291—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes
- G09G3/294—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels using AC panels controlling the gas discharge to control a cell condition, e.g. by means of specific pulse shapes for lighting or sustain discharge
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/30—Image reproducers
- H04N13/332—Displays for viewing with the aid of special glasses or head-mounted displays [HMD]
- H04N13/341—Displays for viewing with the aid of special glasses or head-mounted displays [HMD] using temporal multiplexing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N13/00—Stereoscopic video systems; Multi-view video systems; Details thereof
- H04N13/30—Image reproducers
- H04N13/398—Synchronisation thereof; Control thereof
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/06—Details of flat display driving waveforms
- G09G2310/066—Waveforms comprising a gently increasing or decreasing portion, e.g. ramp
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/001—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background
- G09G3/003—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes using specific devices not provided for in groups G09G3/02 - G09G3/36, e.g. using an intermediate record carrier such as a film slide; Projection systems; Display of non-alphanumerical information, solely or in combination with alphanumerical information, e.g. digital display on projected diapositive as background to produce spatial visual effects
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N2213/00—Details of stereoscopic systems
- H04N2213/008—Aspects relating to glasses for viewing stereoscopic images
Definitions
- the present invention relates to an image display device and shutter glasses that stereoscopically display right-eye images and left-eye images that are alternately displayed on a display device in time order using shutter glasses.
- a typical plasma display panel (hereinafter abbreviated as “panel”) as a display device has a large number of discharge cells formed between a front substrate and a rear substrate arranged to face each other.
- a plurality of pairs of display electrodes composed of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other.
- a dielectric layer and a protective layer are formed so as to cover the display electrode pairs.
- the back substrate has a plurality of parallel data electrodes formed on the glass substrate on the back side, a dielectric layer is formed so as to cover the data electrodes, and a plurality of barrier ribs are formed thereon in parallel with the data electrodes. ing. And the fluorescent substance layer is formed in the surface of a dielectric material layer, and the side surface of a partition.
- the front substrate and the rear substrate are arranged opposite to each other and sealed so that the display electrode pair and the data electrode are three-dimensionally crossed.
- a discharge gas containing xenon is sealed, and a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other.
- ultraviolet rays are generated by gas discharge in each discharge cell, and the phosphors of each color of red (R), green (G) and blue (B) are excited and emitted by the ultraviolet rays. Display an image.
- the subfield method is generally used as a method for driving the panel.
- one field is divided into a plurality of subfields, and gradation display is performed by causing each discharge cell to emit light or not emit light in each subfield.
- Each subfield has an initialization period, an address period, and a sustain period.
- an initialization waveform is applied to each scan electrode, and an initialization discharge is generated in each discharge cell.
- wall charges necessary for the subsequent address operation are formed, and priming particles (excited particles for generating the discharge) for generating the address discharge stably are generated.
- the scan pulse is sequentially applied to the scan electrodes, and the address pulse is selectively applied to the data electrodes based on the image signal to be displayed.
- an address discharge is generated between the scan electrode and the data electrode of the discharge cell to emit light, and a wall charge is formed in the discharge cell.
- the number of sustain pulses based on the luminance weight determined for each subfield is alternately applied to the display electrode pairs composed of the scan electrodes and the sustain electrodes.
- a sustain discharge is generated in the discharge cell that has generated the address discharge, and the phosphor layer of the discharge cell emits light (hereinafter referred to as “lighting” that the discharge cell emits light by the sustain discharge, and “non-emitting”. Also written as “lit”.)
- each discharge cell is made to emit light with the luminance according to the luminance weight.
- each discharge cell of the panel is caused to emit light with a luminance corresponding to the gradation value of the image signal, and an image is displayed in the image display area of the panel.
- 3D image A method of displaying a three-dimensional (3 dimension: hereinafter referred to as “3D”) image (hereinafter referred to as “3D image”) that can be stereoscopically viewed using such a panel has been studied.
- One 3D image is composed of one right-eye image and one left-eye image.
- the right-eye image and the left-eye image are alternately arranged in time order.
- the user views the 3D image displayed on the panel using special glasses called shutter glasses including a shutter for the right eye and a shutter for the left eye.
- the shutter glasses receive a control signal transmitted from the image display unit included in the image display device, and the left and right shutters are synchronized with each of the field for displaying the right-eye image and the field for displaying the left-eye image. Open and close alternately. That is, during the period when the right-eye image is displayed on the panel, the right-eye shutter is opened (a state that transmits visible light) and the left-eye shutter is closed (a state that blocks visible light). During the period in which the left-eye image is displayed, the left-eye shutter is opened and the right-eye shutter is closed. Accordingly, the user can observe the right-eye image only with the right eye, can observe the left-eye image with only the left eye, and can stereoscopically view the 3D image displayed on the panel.
- the shutter glasses do not operate normally.
- the shutter glasses may stop operating when one of the shutters is shut off, or stop operating when both shutters are shut off, depending on the timing at which the control signal is shut off. In such a case, the user cannot normally stereoscopically view the 3D image displayed on the panel.
- the present invention displays the image by alternately repeating the right eye field for displaying the right eye image signal and the left eye field for displaying the left eye image signal, and the first control signal synchronized with the right eye field and the left eye field.
- the image display device includes an image display unit that transmits the first control signal, and shutter glasses having a right-eye shutter and a left-eye shutter that transmit and block visible light, and the shutter glasses receive the first control signal.
- a shutter control circuit that stores first timing information for a plurality of fields based on the first control signals for a plurality of fields and generates a second control signal based on the stored first timing information for the plurality of fields; 2 Transmission of visible light through the right-eye shutter and the left-eye shutter using the control signal And controlling the cutoff.
- the right-eye shutter and the left-eye shutter can be normally controlled even if the control signal to be received is temporarily lost. Accordingly, a user who views a 3D image displayed on the image display unit through the shutter glasses temporarily receives a control signal for the shutter glasses transmitted from the image display device and received by the shutter glasses by a shielding object or the like. Even if it is obstructed, the 3D image displayed on the image display unit can be stereoscopically viewed normally.
- the shutter control circuit includes a clock generation unit, a counter unit that performs counting based on a clock generated by the clock generation unit and is reset by the received first control signal, and a first control.
- a storage unit for storing the output signal of the counter unit when receiving a signal for a plurality of fields as first timing information, and a timing setting for setting the second timing information based on the first timing information for the plurality of fields stored in the storage unit
- a control signal generation unit that generates the second control signal by comparing the second timing information set by the timing setting unit and the output of the counter unit.
- both the right-eye shutter and the left-eye shutter are visible when the shutter control circuit loses more than half of the first control signals for a plurality of fields. It is also possible to adopt a configuration in which the light is transmitted.
- the image display unit in the present invention may be configured using a plasma display panel.
- the present invention displays the image by alternately repeating the right eye field for displaying the right eye image signal and the left eye field for displaying the left eye image signal, and the first control signal synchronized with the right eye field and the left eye field.
- Shutter glasses having a right eye shutter and a left eye shutter that receive a first control signal and transmit and block visible light, and are used for viewing an image displayed on an image display unit that transmits
- a shutter control circuit is provided that stores first timing information for a plurality of fields based on a first control signal for fields, and generates a second control signal based on the stored first timing information for a plurality of fields. Transmits and blocks visible light in the right-eye shutter and left-eye shutter using signals Characterized in that the Gosuru.
- the right eye shutter and the left eye shutter can be normally controlled. Accordingly, a user who views a 3D image displayed on the image display unit through the shutter glasses temporarily receives a control signal for the shutter glasses transmitted from the image display device and received by the shutter glasses by a shielding object or the like. Even if it is obstructed, the 3D image displayed on the image display unit can be stereoscopically viewed normally.
- the shutter control circuit includes a clock generation unit, a counter unit that performs counting based on a clock generated by the clock generation unit and is reset by the received first control signal, and a first control signal. And a timing setting unit for setting the second timing information based on the first timing information for a plurality of fields stored in the storage unit. And a control signal generation unit that generates a second control signal by comparing the second timing information set by the timing setting unit and the output of the counter unit.
- both the right eye shutter and the left eye shutter emit visible light. It may be configured to transmit.
- FIG. 1 is an exploded perspective view showing a structure of a panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 2 is an electrode array diagram of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 3 is a circuit block diagram of the plasma display device according to the embodiment of the present invention.
- FIG. 4 schematically shows drive voltage waveforms applied to the respective electrodes of the panel used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- FIG. 5 is a diagram schematically showing a subfield configuration, a first control signal, and shutter glasses opening / closing operations of the plasma display apparatus in accordance with the exemplary embodiment of the present invention.
- FIG. 6 is a circuit block diagram of a shutter control circuit provided in the shutter glasses of the plasma display device according to the embodiment of the present invention.
- FIG. 7 is a timing chart showing the operation of the shutter glasses of the plasma display device according to the embodiment of the present invention.
- FIG. 1 is an exploded perspective view showing the structure of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention.
- a plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21.
- a dielectric layer 25 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 26 is formed on the dielectric layer 25.
- the protective layer 26 is made of a material mainly composed of magnesium oxide (MgO).
- a plurality of data electrodes 32 are formed on a glass rear substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon.
- a phosphor layer 35 that emits light of each color of red (R), green (G), and blue (B) is provided on the side surface of the partition wall 34 and on the dielectric layer 33.
- the front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect with each other with a minute discharge space interposed therebetween. And the outer peripheral part is sealed with sealing materials, such as glass frit. Then, for example, a mixed gas of neon and xenon is sealed in the discharge space inside as a discharge gas.
- the discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. Thus, a plurality of discharge cells are formed on the panel 10.
- discharge is generated in these discharge cells, and the phosphor layer 35 of the discharge cells emits light (lights the discharge cells), thereby displaying a color image on the panel 10.
- One pixel is composed of three discharge cells that emit blue (B) light.
- the structure of the panel 10 is not limited to the above-described structure, and for example, the panel may be provided with stripe-shaped partition walls in which the partition walls are arranged only in the vertical direction (column direction).
- FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device according to the embodiment of the present invention.
- the panel 10 includes n scan electrodes SC1 to SCn (scan electrode 22 in FIG. 1) extended in the horizontal direction (row direction) and n sustain electrodes SU1 to SUn (sustain electrodes in FIG. 1). 23) are arranged, and m data electrodes D1 to Dm (data electrodes 32 in FIG. 1) extending in the vertical direction (column direction) are arranged.
- FIG. 3 is a circuit block diagram of plasma display device 100 in accordance with the exemplary embodiment of the present invention.
- the plasma display device 100 shown in the present embodiment includes an image display unit 40 and shutter glasses 50.
- the image display unit 40 is necessary for the panel 10, the image signal processing circuit 41, the data electrode drive circuit 42, the scan electrode drive circuit 43, the sustain electrode drive circuit 44, the timing generation circuit 45, the control signal transmission unit 46, and each circuit block.
- a power supply circuit (not shown) for supplying power is provided.
- the image signal processing circuit 41 assigns a gradation value to each discharge cell based on the input image signal.
- the gradation value is converted into image data indicating light emission / non-light emission for each subfield (data corresponding to light emission / non-light emission corresponding to digital signals “1” and “0”). That is, the image signal processing circuit 41 converts the image signal for each field into image data indicating light emission / non-light emission for each subfield.
- each gradation value of R, G, and B is assigned to each discharge cell based on the R signal, the G signal, and the B signal.
- the input image signal includes a luminance signal (Y signal) and a saturation signal (C signal, RY signal and BY signal, or u signal and v signal, etc.)
- the luminance signal and saturation signal Based on the degree signal, R signal, G signal, and B signal are calculated, and thereafter, R, G, and B gradation values (gradation values expressed in one field) are assigned to each discharge cell. Then, the R, G, and B gradation values assigned to each discharge cell are converted into image data indicating light emission / non-light emission for each subfield.
- the input image signal is a stereoscopic image signal having a right-eye image signal and a left-eye image signal.
- the image signal is displayed on the panel 10, the right-eye image signal and the left-eye image signal are displayed.
- the image signal is alternately input to the image signal processing circuit 41 for each field. Therefore, the image signal processing circuit 41 converts the right eye image signal into right eye image data, and converts the left eye image signal into left eye image data.
- the timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal.
- the generated timing signal is supplied to each circuit block (image signal processing circuit 41, data electrode drive circuit 42, scan electrode drive circuit 43, sustain electrode drive circuit 44, etc.). Further, the timing generation circuit 45 outputs a first control signal synchronized with the right-eye field and the left-eye field to the control signal transmission unit 46 for controlling the opening / closing of the shutter of the shutter glasses 50.
- the control signal transmission part 46 has light emitting elements 47, such as LED (Light Emitting Diode). Then, the first control signal is encoded and converted into a serial signal, and the light emitting element 47 is used to convert the serial signal into, for example, an optical signal such as infrared rays and transmit it.
- light emitting elements 47 such as LED (Light Emitting Diode).
- the timing generation circuit 45 generates the first control signal
- the control signal transmission unit 46 converts the first control signal into an optical signal and transmits it to the shutter glasses 50.
- the data electrode driving circuit 42 converts the data for each subfield constituting the image data including the right-eye image data and the left-eye image data into signals corresponding to the data electrodes D1 to Dm. Then, based on the signal and the timing signal supplied from the timing generation circuit 45, the data electrodes D1 to Dm are driven. In the address period, an address pulse is generated and applied to each of the data electrodes D1 to Dm.
- Scan electrode drive circuit 43 includes a ramp waveform generation circuit, a sustain pulse generation circuit, and a scan pulse generation circuit (not shown in FIG. 3), and generates a drive voltage waveform based on a timing signal supplied from timing generation circuit 45. Then, the voltage is applied to each of scan electrode SC1 to scan electrode SCn.
- the ramp waveform generation circuit generates an initialization waveform to be applied to scan electrode SC1 through scan electrode SCn based on the timing signal during the initialization period.
- the sustain pulse generating circuit generates a sustain pulse applied to scan electrode SC1 through scan electrode SCn based on the timing signal during the sustain period.
- the scan pulse generating circuit includes a plurality of scan electrode driving ICs (scan ICs), and generates scan pulses to be applied to scan electrode SC1 to scan electrode SCn based on a timing signal in an address period.
- Sustain electrode drive circuit 44 includes a sustain pulse generation circuit and a circuit for generating voltage Ve (not shown in FIG. 3), and generates and maintains a drive voltage waveform based on the timing signal supplied from timing generation circuit 45.
- the voltage is applied to each of electrode SU1 through sustain electrode SUn.
- a sustain pulse is generated based on the timing signal and applied to sustain electrode SU1 through sustain electrode SUn.
- the image display unit 40 displays the 3D image on the panel 10 by alternately repeating the right-eye field for displaying the right-eye image signal and the left-eye field for displaying the left-eye image signal in time order, and for the right eye.
- a first control signal synchronized with the field and the left eye field is generated, converted into an optical signal, and transmitted to the shutter glasses 50.
- the shutter glasses 50 include a shutter control circuit 52, a right-eye shutter 56R, and a left-eye shutter 56L.
- the shutter control circuit 52 receives the first control signal converted into the optical signal by using the light receiving element 53 such as a photodiode, and reproduces the first control signal.
- the right-eye shutter 56R and the left-eye shutter 56L are optical shutters configured using, for example, liquid crystal, and can be opened and closed independently.
- the shutter glasses 50 open / close operations (transmit visible light) of the right-eye shutter 56R and the left-eye shutter 56L based on the first control signal transmitted from the control signal transmitter 46 and received and reproduced by the shutter control circuit 52.
- the shutter glasses 50 in the present embodiment do not directly use the first control signal reproduced by the shutter control circuit 52 for controlling the right-eye shutter 56R and the left-eye shutter 56L.
- the shutter control circuit 52 generates a second control signal based on the reproduced first control signal. Then, the shutter glasses 50 control the right-eye shutter 56R and the left-eye shutter 56L using the second control signal.
- the shutter glasses 50 have the right eye shutter 56R and the left eye shutter 56L that receive the first control signal and transmit and block visible light.
- the material constituting the right-eye shutter 56R and the left-eye shutter 56L is not limited to liquid crystal. Any material can be used for the shutter as long as it can switch between blocking and transmitting visible light at high speed.
- the image display unit 40 performs gradation display by the subfield method.
- the subfield method one field is divided into a plurality of subfields on the time axis, and a luminance weight is set for each subfield.
- Each subfield has an initialization period, an address period, and a sustain period.
- An image is displayed on the panel 10 by controlling light emission / non-light emission of each discharge cell for each subfield.
- the luminance weight represents a ratio of the luminance magnitudes displayed in each subfield, and the number of sustain pulses corresponding to the luminance weight is generated in the sustain period in each subfield. Therefore, for example, the subfield with the luminance weight “8” emits light with a luminance about eight times that of the subfield with the luminance weight “1”, and emits light with about four times the luminance of the subfield with the luminance weight “2”. Accordingly, various gradations can be displayed by selectively causing each subfield to emit light in a combination corresponding to the image signal, and an image can be displayed on the panel 10.
- the image signal input to the plasma display device 100 is a stereoscopic image signal that alternately repeats the right-eye image signal and the left-eye image signal for each field. Then, a right-eye field for displaying a right-eye image signal and a left-eye field for displaying a left-eye image signal are alternately displayed in time order on the panel 10 to display a stereoscopic image composed of a right-eye image and a left-eye image. A visual image (3D image) is displayed on the panel 10.
- the number of 3D images displayed per unit time (for example, 1 second) is half of the field frequency (the number of fields generated per second). For example, if the field frequency is 60 Hz, there are 30 right-eye images and left-eye images displayed per second, so 30 3D images are displayed on the panel 10 per second. . Therefore, in the present embodiment, the field frequency is set to twice the normal frequency (for example, 120 Hz) to reduce image flicker that is likely to occur when an image with a low field frequency is displayed.
- the user views the 3D image displayed on the panel 10 through the shutter glasses 50 that independently open and close the right-eye shutter 56R and the left-eye shutter 56L in synchronization with the right-eye field and the left-eye field.
- the user can observe the right-eye image only with the right eye and the left-eye image with only the left eye, so that the 3D image displayed on the panel 10 can be stereoscopically viewed.
- the right-eye field and the left-eye field differ only in the image signal to be displayed, and the field configuration such as the number of subfields constituting one field, the luminance weight of each subfield, and the arrangement of subfields is as follows. The same. Therefore, hereinafter, when it is not necessary to distinguish between “for right eye” and “for left eye”, the field for right eye and the field for left eye are simply abbreviated as fields.
- the right-eye image signal and the left-eye image signal are simply abbreviated as image signals.
- the field configuration is also referred to as a subfield configuration.
- Each field of the right eye field and the left eye field has a plurality of subfields, and each subfield has an initialization period, an address period, and a sustain period.
- an initializing operation is performed in which initializing discharge is generated in the discharge cells and wall charges necessary for the address discharge in the subsequent address period are formed on each electrode.
- the initializing operation includes only a forced initializing operation that forcibly generates an initializing discharge in a discharge cell regardless of whether or not there is a previous discharge, and a discharge cell that has generated an address discharge in the address period of the immediately preceding subfield. There is a selective initialization operation for generating an initialization discharge.
- a scan pulse is applied to the scan electrode 22 and an address pulse is selectively applied to the data electrode 32, an address discharge is selectively generated in the discharge cells to emit light, and a sustain discharge is generated in the subsequent sustain period.
- An address operation for forming wall charges to be generated in the discharge cells is performed.
- the number of sustain pulses obtained by multiplying the luminance weight of each subfield by a predetermined proportional constant is alternately applied to the scan electrode 22 and the sustain electrode 23, and the discharge cell in which the address discharge is generated in the immediately preceding address period A sustain operation is performed to generate a sustain discharge and emit light from the discharge cell.
- This proportionality constant is the luminance magnification. For example, when the luminance magnification is two, the sustain pulse is applied to the scan electrode 22 and the sustain electrode 23 four times in the sustain period of the subfield having the luminance weight “2”. Therefore, the number of sustain pulses generated in the sustain period is 8.
- Each subfield of subfield SF1 to subfield SF5 has a luminance weight of (16, 8, 4, 2, 1).
- the subfield SF1 generated at the beginning of the field is set to the subfield having the largest luminance weight, and thereafter, the luminance weight is set to each subfield so that the luminance weight is sequentially reduced.
- the subfield SF5 generated at the end of the field is set as the subfield having the smallest luminance weight.
- the forced initialization operation is performed in the initialization period of the subfield SF1 that occurs at the beginning of the field, and the selective initialization operation is performed in the initialization period of the subfields SF2 to SF5.
- the light emission not related to the image display is only the light emission due to the discharge of the forced initialization operation in the subfield SF1. Therefore, the black luminance, which is the luminance of the black display region where no sustain discharge occurs, is only weak light emission in the forced initialization operation, and an image with high contrast can be displayed on the panel 10.
- the number of subfields constituting one field and the luminance weight of each subfield are not limited to the above values.
- the structure which switches a subfield structure based on an image signal etc. may be sufficient.
- FIG. 4 is a diagram showing drive voltage waveforms applied to each electrode of panel 10 used in plasma display apparatus 100 in the embodiment of the present invention.
- FIG. 4 shows scan electrode SC1 that performs the address operation first in the address period, scan electrode SCn that performs the address operation last in the address period, sustain electrode SU1 to sustain electrode SUn, and data electrode D1 to data electrode Dm. The drive voltage waveform to be applied is shown.
- FIG. 4 shows drive voltage waveforms from the subfield SF1 to the middle of the subfield SF3.
- the subfield SF1 is a subfield for performing a forced initialization operation
- the subfield SF2 and the subfield SF3 are subfields for performing a selective initialization operation. Therefore, the waveform shape of the drive voltage applied to the scan electrode 22 in the initialization period is different between the subfield SF1, the subfield SF2, and the subfield SF3.
- the driving voltage waveforms in the other subfields are substantially the same as the driving voltage waveforms in the subfields SF2 and SF3 except that the number of sustain pulses generated in the sustain period is different.
- Scan electrode SCi, sustain electrode SUi, and data electrode Dk in the following represent electrodes selected based on image data (data indicating light emission / non-light emission for each subfield) from among the electrodes.
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm and sustain electrode SU1 through sustain electrode SUn.
- Voltage Vi1 is applied to scan electrode SC1 through scan electrode SCn, and a ramp waveform voltage that gradually increases from voltage Vi1 to voltage Vi2 is applied.
- Voltage Vi1 is set to a voltage lower than the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn, and voltage Vi2 is set to a voltage exceeding the discharge start voltage with respect to sustain electrode SU1 through sustain electrode SUn.
- the initialization operation in the initialization period of the subfield SF1 that is, the forced initialization operation for forcibly generating the initialization discharge in all the discharge cells is completed.
- voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn, and voltage Vc is applied to each of scan electrode SC1 through scan electrode SCn.
- a negative scan pulse having a negative voltage Va is applied to the scan electrode SC1 in the first row where the address operation is performed first.
- an address pulse of a positive voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm.
- the voltage difference at the intersection between the data electrode Dk of the discharge cell to which the address pulse of the voltage Vd is applied and the scan electrode SC1 is the difference between the externally applied voltage (voltage Vd ⁇ voltage Va) and the wall voltage on the data electrode Dk and the scan electrode.
- the difference from the wall voltage on SC1 is added.
- the voltage difference between data electrode Dk and scan electrode SC1 exceeds the discharge start voltage, and a discharge is generated between data electrode Dk and scan electrode SC1.
- the voltage difference between sustain electrode SU1 and scan electrode SC1 is the difference between the externally applied voltages (voltage Ve ⁇ voltage Va), and sustain electrode SU1.
- the difference between the upper wall voltage and the wall voltage on the scan electrode SC1 is added.
- the sustain electrode SU1 and the scan electrode SC1 are not easily discharged but are likely to be discharged. Can do.
- a discharge generated between the data electrode Dk and the scan electrode SC1 can be triggered to generate a discharge between the sustain electrode SU1 and the scan electrode SC1 in the region intersecting the data electrode Dk.
- an address discharge is generated in the discharge cell to emit light, positive wall voltage is accumulated on scan electrode SC1, negative wall voltage is accumulated on sustain electrode SU1, and negative polarity is also formed on data electrode Dk.
- the wall voltage is accumulated.
- the above address operation is sequentially performed in the order of scan electrode SC2, scan electrode SC3,..., Scan electrode SCn until reaching the discharge cell in the n-th row, and the address period of subfield SF1 is completed.
- address discharge is selectively generated in the discharge cells to emit light, and wall charges are formed in the discharge cells.
- the voltage difference between scan electrode SCi and sustain electrode SUi exceeds the discharge start voltage, and a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. Then, the phosphor layer 35 emits light by the ultraviolet rays generated by this discharge. In addition, due to this discharge, negative wall voltage is accumulated on scan electrode SCi, and positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.
- sustain pulses of the number obtained by multiplying the luminance weight by a predetermined luminance magnification are alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.
- the voltage that is the base potential is maintained while the voltage 0 (V) is applied to sustain electrode SU1 through sustain electrode SUn and data electrode D1 through data electrode Dm.
- a ramp waveform voltage that gradually rises from 0 (V) toward voltage Vr is applied to scan electrode SC1 through scan electrode SCn.
- a selective initialization operation is performed in which a drive voltage waveform in which the first half of the initialization period in the subfield SF1 is omitted is applied to each electrode.
- voltage Ve is applied to sustain electrode SU1 through sustain electrode SUn
- voltage 0 (V) is applied to data electrode D1 through data electrode Dm.
- a scan waveform SC1 to scan electrode SCn are applied with a ramp waveform voltage that gradually falls from a voltage (for example, voltage 0 (V)) that is less than the discharge start voltage to a negative voltage Vi4 that exceeds the discharge start voltage.
- a weak initializing discharge is generated in a discharge cell that has generated a sustain discharge in the sustain period of the immediately preceding subfield (subfield SF1 in FIG. 4). Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. Further, since a sufficient positive wall voltage is accumulated on the data electrode Dk due to the sustain discharge generated in the immediately preceding sustain period, an excessive portion of the wall voltage is discharged, and the wall on the data electrode Dk is discharged. The voltage is adjusted to a wall voltage suitable for the write operation.
- the initialization operation in the subfield SF2 is selectively performed in the discharge cell in which the address operation is performed in the address period of the immediately preceding subfield, that is, in the discharge cell in which the sustain discharge is generated in the sustain period of the immediately preceding subfield.
- a selective initializing operation for generating initializing discharge is performed.
- a drive voltage waveform similar to that in the address period of the subfield SF1 is applied to each electrode, and an address operation for accumulating wall voltage on each electrode of the discharge cell to emit light is performed.
- the number of sustain pulses corresponding to the luminance weight is alternately applied to scan electrode SC1 through scan electrode SCn and sustain electrode SU1 through sustain electrode SUn.
- a sustain discharge is generated in the discharge cell that has generated the address discharge.
- each subfield of subfield SF3 to subfield SF5 In the initialization period and address period of each subfield of subfield SF3 to subfield SF5, the same drive voltage waveform as that in the initialization period and address period of subfield SF2 is applied to each electrode. In the sustain period of each subfield of subfield SF3 to subfield SF5, the same drive voltage waveform as that of subfield SF2 is applied to each electrode except for the number of sustain pulses generated in the sustain period.
- the gradient of the rising ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn in the initializing period of subfield SF1 is set to 1.5 (V / ⁇ sec), and the gradient of the falling ramp waveform voltage is ⁇ 2 .5 (V / ⁇ sec), and the ramp waveform voltage applied to scan electrode SC1 through scan electrode SCn during the initialization period of subfield SF2 through subfield SF5 has a gradient of ⁇ 2.5 (V / ⁇ sec). Is set. Further, after the generation of the sustain pulse in the sustain period (the end of the sustain period), the gradient waveform voltage rising from the voltage 0 (V) toward the voltage Vr has its gradient set to 10 (V / ⁇ sec).
- each voltage value, gradient, and the like are preferably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.
- FIG. 5 is a diagram schematically showing the subfield configuration of the plasma display device 100, the first control signal, and the opening / closing operation of the shutter glasses 50 in the embodiment of the present invention.
- FIG. 5 shows the drive voltage waveform applied to the scan electrode SCn that performs the address operation last in the address period, the first control signal, and the opening / closing operations of the right-eye shutter 56R and the left-eye shutter 56L.
- FIG. 5 shows six fields.
- a right eye field and a left eye field are alternately generated.
- the first field, the third field, and the fifth field are right-eye fields, and the right-eye image signal is displayed on the panel 10.
- the second field, the fourth field, and the sixth field are fields for the left eye, and the left-eye image signal is displayed on the panel 10.
- a user who observes a 3D image displayed on the panel 10 through the shutter glasses 50 recognizes an image (right-eye image and left-eye image) displayed in two fields as a single 3D image. Therefore, the number of images displayed on the panel 10 per second is observed by the user as half the number of fields displayed per second. For example, when the field frequency of the 3D image displayed on the panel (the number of fields generated per second) is 60 Hz, the user observes 30 3D images per second. Therefore, in order to display 60 3D images per second, the field frequency must be set to 120 Hz, which is twice 60 Hz. Therefore, in this embodiment, the field frequency (the number of fields generated per second) is set to twice the normal frequency (for example, 120 Hz) so that the user can smoothly observe the 3D moving image. ing.
- Each field of the right eye field and the left eye field has five subfields (subfield SF1, subfield SF2, subfield SF3, subfield SF4, and subfield SF5).
- luminance weights (16, 8, 4, 2, 1) are set in the subfields SF1 to SF5, respectively.
- one field is constituted by five subfields in which the luminance weight is set in each subfield so that the luminance weight is sequentially decreased in the order in which the subfields are generated. That is, the subfield having the largest luminance weight is generated at the beginning of the field, the subfield having the second largest luminance weight is generated, the subfield having the third largest luminance weight is generated, and the fourth subfield is generated. The subfield with the fourth largest luminance weight is generated, and the subfield with the smallest luminance weight is generated at the end of the field.
- the reason why each subfield is generated and the panel 10 is driven is as follows.
- the phosphor layer 35 used in the panel 10 has afterglow characteristics depending on the material constituting the phosphor.
- This afterglow is a phenomenon in which the phosphor continues to emit light after the end of discharge.
- the intensity of afterglow is proportional to the luminance when the phosphor emits light, and the higher the luminance when the phosphor emits light, the stronger the afterglow.
- afterglow decays with a time constant according to the characteristics of the phosphor, and the luminance gradually decreases with time. However, afterglow persists for several milliseconds after the end of the sustain discharge.
- Light emission generated in a subfield with a large luminance weight is higher in luminance than light emission generated in a subfield with a small luminance weight. Therefore, the afterglow due to light emission generated in a subfield with a large luminance weight has higher luminance and the time required for attenuation than the afterglow due to light emission generated in a subfield with a small luminance weight.
- the afterglow leaking into the subsequent field increases compared to when the final subfield is a subfield with a small luminance weight.
- the afterglow generated in one field leaks into the subsequent field, the afterglow is It is observed by the user as unnecessary light emission not related to the image signal. This phenomenon is crosstalk.
- the image display quality is image display quality for a user who views a 3D image through the shutter glasses 50.
- a subfield having the largest luminance weight is generated at the beginning of the field, and thereafter, the luminance weight is decreased in the order in which the subfields are generated, and the last subfield of the field is changed to the subfield having the smallest luminance weight, and the next field is reached. It is desirable to reduce the leakage of afterglow as much as possible.
- the subfield SF1 is set to the subfield having the largest luminance weight, and the luminance weights are sequentially reduced in the subsequent subfields.
- the shutter glasses 50 open / close the right eye shutter 56R and the left eye shutter 56L based on the first control signal.
- the timing generation circuit 45 synchronizes the first control signal for opening the right-eye shutter 56R (hereinafter abbreviated as “first right-open signal Sro1”) in synchronization with the start of the writing period of the subfield SF1 of the right-eye field. Output. Further, the timing generation circuit 45 outputs a first control signal for closing the right eye shutter 56R (hereinafter abbreviated as “first right closing signal Src1”) in synchronization with the start of the left eye field. Further, the timing generation circuit 45 synchronizes the first control signal for opening the left-eye shutter 56L (hereinafter abbreviated as “first left-open signal Slo1”) with the start of the writing period of the sub-field SF1 of the left-eye field. And output. The timing generation circuit 45 outputs a first control signal for closing the left-eye shutter 56L (hereinafter abbreviated as “first left-closing signal Slc1”) in synchronization with the start of the right-eye field.
- the control signal transmission unit 46 transmits each of the first control signals (first right open signal Sro1, first right close signal Src1, first left open signal Slo1, first left close signal Slc1), a header portion, a code portion, And converting the serial signal into an optical signal and transmitting it to the shutter glasses 50.
- the header portion indicates that a series of subsequent serial signals is the first control signal.
- the code portion is provided to identify whether the first control signal is the first right open signal Sro1, the first right close signal Src1, the first left open signal Slo1, or the first left close signal Slc1.
- the timing portion is provided to indicate the timing for performing the control specified in the code portion.
- header portion and the timing portion are not necessarily provided independently, and may be configured as a serial signal that is also used as the code portion.
- FIG. 6 is a circuit block diagram of the shutter control circuit 52 provided in the shutter glasses 50 of the plasma display device 100 according to the embodiment of the present invention.
- the shutter control circuit 52 includes a clock generation unit 61, a control signal reception unit 62, a counter unit 63, a storage unit 64, a timing setting unit 65, and a control signal generation unit 66.
- the clock generator 61 generates a clock signal (hereinafter referred to as “clock CK”) for operating the shutter control circuit 52 of the shutter glasses 50 and supplies it to each part of the shutter control circuit 52.
- clock CK a clock signal
- the light receiving element 53 receives the first control signal converted into the optical signal transmitted from the control signal transmitting unit 46 via the light emitting element 47, and converts it into an electrical serial signal.
- the control signal receiving unit 62 receives the first control signal received by the light receiving element 53 and converted from an optical signal to an electrical serial signal.
- the clock CK of the clock generator 61 is input to the control signal receiver 62 as a synchronization signal. Then, the control signal receiving unit 62 decodes the first control signal into a first right open signal Sro1, a first right close signal Src1, a first left open signal Slo1, and a first left close signal Slc1, and outputs them. .
- the control signal reception unit 62 includes the first right-open signal Sro1, the first Each of the right closing signal Src1, the first left opening signal Slo1, and the first left closing signal Slc1 is synchronized with the clock CK, and is shaped into a pulse width of one clock cycle of the clock CK and output.
- the counter unit 63 includes a counter 71, a coincidence circuit 72, a selector 73, an AND gate 74, a delay 75, and an OR gate 76.
- the counter 71 is a counter (upcounter) that receives the clock CK of the clock generator 61 as a synchronization signal and increases the count value in synchronization with the clock CK, and outputs the count value.
- the counter 71 receives a signal output from the OR gate 76 as a reset signal, and the count value is reset by the reset signal.
- the counter 71 has a bit length sufficient to count (count) the clock CK over one cycle of control of the right-eye shutter 56R and the left-eye shutter 56L.
- the one cycle is a period from the opening operation of the right-eye shutter 56R and the left-eye shutter 56L to the next opening operation, which is substantially a period corresponding to two fields. For example, if one cycle of control is a maximum of 16 msec (a period corresponding to two fields of a video signal having a field frequency of 120 Hz) and one cycle of the clock CK is 1 ⁇ sec, the bit length of the counter 71 is 14 bits (maximum, It is possible to count up to 16383).
- bit length of the counter 71 is 7 bits. Therefore, the minimum value of the output of the counter 71 is “0”, and the maximum value is “127”.
- the coincidence circuit 72 has two input terminals, and outputs an “H” level signal when the signals inputted to the respective input terminals are equal to each other.
- “0” is input to one input terminal, and the output of the counter 71 is input to the other input terminal. Therefore, the coincidence circuit 72 outputs the “H” level when the output of the counter 71 reaches the minimum value “0”.
- the selector 73 has two input terminals and outputs a signal input to any one of the input terminals based on the selector signal. “127” equal to the maximum value of the output of the counter 71 is input to one input terminal of the selector 73, and the output of the counter 71 is input to the other input terminal.
- the selector 73 receives the output signal of the coincidence circuit 72 as a selector signal. Then, the selector 73 selects the output signal of the counter 71 if the output signal of the coincidence circuit 72 is “L” level, and selects “127” if the output signal of the coincidence circuit 72 is “H” level. Output.
- the AND gate 74 performs a logical product operation of two inputs and one output. That is, if both of the two input signals are at “H” level, an “H” level signal is output, and if at least one of the two input signals is at “L” level, an “L” level signal is output.
- the AND gate 74 receives the output signal of the coincidence circuit 72 at one input terminal and a signal (inverted signal) obtained by logically inverting the clock CK at the other input terminal. Therefore, the AND gate 74 outputs an “H” level signal if both the output signal of the coincidence circuit 72 and the inverted signal of the clock CK are “H” level, and “L” if at least one of them is “L” level. ”Level signal is output.
- the output signal of the AND gate 74 is referred to as a shift clock Ssft.
- the delay 75 is a commonly used latch circuit, to which a second left closing signal Slc2 described later is input, and an inverted signal of the clock CK is input as a synchronization signal.
- the delay 75 latches the second left closing signal Slc2 with the inverted signal of the clock CK, and delays and outputs the second left closing signal Slc2 by 1 ⁇ 2 period of the clock CK.
- OR gate 76 performs a 2-input 1-output OR operation. That is, if both of the two input signals are at “L” level, an “L” level signal is output, and if at least one of the two input signals is at “H” level, an “H” level signal is output.
- the OR gate 76 receives the output signal of the delay 75 at one input terminal, and receives the first left closed signal Slc1 output from the control signal receiving unit 62 at the other input terminal. Therefore, in the OR gate 76, both the second left closed signal Slc2 delayed by 1 ⁇ 2 period of the clock CK output from the delay 75 and the first left closed signal Slc1 output from the control signal receiving unit 62 are “L”. "L” level signal is output if "" level, and "H” level signal is output if at least one is “H” level.
- the output signal of the OR gate 76 is input to the counter 71 as a reset signal.
- the storage unit 64 includes an OR gate 81a, an OR gate 81b, an OR gate 81c, an OR gate 81d, a data latch 82a, a data latch 82b, a data latch 82c, a data latch 82d, a shift register 83a, a shift register 83b, and a shift register 83c. And a shift register 83d.
- the OR gate 81a, the OR gate 81b, the OR gate 81c, and the OR gate 81d perform a 2-input 1-output logical sum operation in the same manner as the OR gate 76.
- the shift clock Ssft output from the AND gate 74 is input to one input terminal, and the first right open signal Sro1 output from the control signal receiving unit 62 is input to the other input terminal. Yes.
- the OR gate 81a outputs the result of these logical sum operations as a clock signal used for the data latch 82a.
- the shift clock Ssft output from the AND gate 74 is input to one input terminal, and the first right closing signal Src1 output from the control signal receiving unit 62 is input to the other input terminal. Yes.
- the OR gate 81b outputs the result of the logical sum operation as a clock signal used for the data latch 82b.
- the shift clock Ssft output from the AND gate 74 is input to one input terminal, and the first left open signal Slo1 output from the control signal receiving unit 62 is input to the other input terminal. Yes.
- the OR gate 81c outputs the result of the logical sum operation as a clock signal used for the data latch 82c.
- the shift clock Ssft output from the AND gate 74 is input to one input terminal, and the first left closed signal Slc1 output from the control signal receiving unit 62 is input to the other input terminal. Yes.
- the OR gate 81d outputs the result of the logical sum operation as a clock signal used for the data latch 82d.
- the data latch 82a, data latch 82b, data latch 82c, and data latch 82d are commonly used latch circuits.
- the data latch 82a receives the signal output from the selector 73 (the output signal of the counter 71 or the numerical value “127”), and the output signal of the OR gate 81a as a synchronization signal.
- the data latch 82a latches the signal output from the selector 73 with the synchronization signal output from the OR gate 81a, and outputs it as first timing information.
- the data latch 82b receives the signal output from the selector 73, and receives the output signal of the OR gate 81b as a synchronization signal.
- the data latch 82b latches the signal output from the selector 73 with the synchronization signal output from the OR gate 81b, and outputs it as first timing information.
- the data latch 82c receives the signal output from the selector 73, and receives the output signal of the OR gate 81c as a synchronization signal.
- the data latch 82c latches the signal output from the selector 73 with the synchronization signal output from the OR gate 81c, and outputs it as first timing information.
- the data latch 82d receives the signal output from the selector 73, and receives the output signal of the OR gate 81d as a synchronization signal.
- the data latch 82d latches the signal output from the selector 73 with the synchronization signal output from the OR gate 81d, and outputs it as first timing information.
- the coincidence circuit 72 outputs an “H” level signal. Therefore, the selector 73 selects and outputs “127” equal to the maximum value of the output of the counter 71, and the AND gate 74 outputs the shift clock Ssft. If the output of the counter 71 is a numerical value other than “0”, the coincidence circuit 72 outputs an “L” level signal. Therefore, the selector 73 selects and outputs the output signal of the counter 71, and the output signal of the AND gate 74 becomes "L" level.
- the data latch 82a latches “127” equal to the maximum value of the output of the counter 71, and outputs it as first timing information. Further, when the “L” level signal is output from the AND gate 74, the output signal of the counter 71 is latched at the timing when the first right-open signal Sro1 is output from the control signal receiving unit 62, and is then output as the first timing. Output as information.
- the data latch 82b latches “127” equal to the maximum value of the output of the counter 71, and outputs it as first timing information. Further, when an “L” level signal is output from the AND gate 74, the output signal of the counter 71 is latched at the timing when the first right closing signal Src1 is output from the control signal receiving unit 62, and the first timing signal is output to the first timing. Output as information.
- the data latch 82c latches “127” equal to the maximum value of the output of the counter 71, and outputs it as first timing information.
- the output signal of the counter 71 is latched at the timing when the first left-open signal Slo1 is output from the control signal receiving unit 62, and the first output signal is output to the first timing. Output as information.
- the data latch 82d latches “127” equal to the maximum value of the output of the counter 71 and outputs it as first timing information. Further, when the “L” level signal is output from the AND gate 74, the output signal of the counter 71 is latched at the timing when the first left closing signal Slc1 is output from the control signal receiving unit 62, and is then output as the first timing. Output as information.
- the shift register 83a, the shift register 83b, the shift register 83c, and the shift register 83d are commonly used shift register circuits, and are configured by connecting a plurality of latch circuits in series (cascade). Then, in synchronization with the input synchronization signal, the input signal is moved by one latch circuit (shifted by one stage) and output. Therefore, the shift register 83a, the shift register 83b, the shift register 83c, and the shift register 83d can delay the input signal by the number of latch circuits that constitute each shift register. At this time, as many shift signals as the number of latch circuits constituting the shift register are stored in the shift register. For example, if the number of latch circuits constituting each shift register is 10, each shift register can output the input signal with a delay of 10 periods of the synchronization signal input to the shift register. At this time, ten input signals are stored in the shift register.
- each shift register of the shift register 83a, the shift register 83b, the shift register 83c, and the shift register 83d is configured by two or more latch circuits. The description will be made on the assumption that the circuit is composed of eight latch circuits. Therefore, the plurality of first control signals over a plurality of fields received by the shutter glasses is “2” or more.
- the shift clock Ssft output from the AND gate 74 is input to the shift register 83a, shift register 83b, shift register 83c, and shift register 83d as a synchronization signal.
- the first timing information output from the data latch 82a is input to the shift register 83a. Therefore, the signal output from the shift register 83a is a signal obtained by delaying the first timing information output from the data latch 82a by eight periods of the shift clock Ssft.
- the first timing information output from the data latch 82b is input to the shift register 83b. Therefore, the signal output from the shift register 83b is a signal obtained by delaying the first timing information output from the data latch 82b by eight cycles of the shift clock Ssft.
- the first timing information output from the data latch 82c is input to the shift register 83c. Therefore, the signal output from the shift register 83c is a signal obtained by delaying the first timing information output from the data latch 82c by eight periods of the shift clock Ssft.
- the first timing information output from the data latch 82d is input to the shift register 83d. Therefore, the signal output from the shift register 83d is a signal obtained by delaying the first timing information output from the data latch 82d by eight periods of the shift clock Ssft.
- the timing setting unit 65 includes a data selector 84a, a data selector 84b, a data selector 84c, and a data selector 84d.
- the data selector 84a, the data selector 84b, the data selector 84c, and the data selector 84d have a plurality of storage circuits and a majority circuit inside, and the largest number of data (the most frequent among the plurality of data stored in the storage circuit). Value) and output. For example, if the data selector has 10 storage circuits and 6 “10” s and 4 “20” s are stored in each storage circuit, the data selector is “10”, which has the larger number. Select to output. When there are a plurality of mode values, the data having the largest value is selected and output. For example, if the data selector has 10 storage circuits and 5 “10” s and 5 “20” s are stored in each storage circuit, the data selector has a larger numerical value of “20”. Select to output.
- the data selectors 84a, 84b, 84c, and 84d are provided in the shift registers 83a, 83b, 83c, and 83d. Assume that the same number of memory circuits as the number of latch circuits provided therein are provided. For example, if each shift register is composed of eight latch circuits, each data selector has eight memory circuits, and the majority decision is made with the eight data stored in the memory circuit. . Each time the new data is output from the shift register, each data selector updates the data stored in the storage circuit one by one from the oldest one.
- the first timing information output from the shift register 83a is input to the data selector 84a.
- the data selector 84a stores the eight pieces of first timing information output from the shift register 83a, selects the mode value among them, and outputs it as the second timing information.
- the first timing information output from the shift register 83b is input to the data selector 84b.
- the data selector 84b stores the eight pieces of first timing information output from the shift register 83b, selects the mode value among them, and outputs it as the second timing information.
- the first timing information output from the shift register 83c is input to the data selector 84c.
- the data selector 84c stores the eight pieces of first timing information output from the shift register 83c, selects the mode value among them, and outputs it as the second timing information.
- the first timing information output from the shift register 83d is input to the data selector 84d.
- the data selector 84d stores the eight pieces of first timing information output from the shift register 83d, selects the mode value among them, and outputs it as the second timing information.
- the control signal generator 66 includes a match circuit 91a, a match circuit 91b, a match circuit 91c, a match circuit 91d, an AND gate 92R, an AND gate 92L, a JK flip-flop 93R, a JK flip-flop 93L, an amplifier 94R, and an amplifier 94L.
- the coincidence circuit 91a, the coincidence circuit 91b, the coincidence circuit 91c, and the coincidence circuit 91d have two input terminals, and output an “H” level signal when the signals input to the respective input terminals are equal to each other.
- coincidence circuit 91a the second timing information output from the data selector 84a is input to one input terminal, and the output of the counter 71 is input to the other input terminal. Accordingly, coincidence circuit 91a outputs “H” level when the output of counter 71 becomes equal to the second timing information output from data selector 84a.
- the signal output from the coincidence circuit 91a is a second control signal for opening the right-eye shutter 56R (hereinafter referred to as “second right-open signal Sro2”).
- the coincidence circuit 91b In the coincidence circuit 91b, the second timing information output from the data selector 84b is input to one input terminal, and the output of the counter 71 is input to the other input terminal. Therefore, the coincidence circuit 91b outputs “H” level when the output of the counter 71 becomes equal to the second timing information output from the data selector 84b.
- the signal output from the coincidence circuit 91b is a second control signal for closing the right-eye shutter 56R (hereinafter referred to as “second right closing signal Src2”).
- the coincidence circuit 91c In the coincidence circuit 91c, the second timing information output from the data selector 84c is input to one input terminal, and the output of the counter 71 is input to the other input terminal. Therefore, the coincidence circuit 91c outputs “H” level when the output of the counter 71 becomes equal to the second timing information output from the data selector 84c.
- the signal output from the coincidence circuit 91c is a second control signal for opening the left-eye shutter 56L (hereinafter referred to as “second left-open signal Slo2”).
- the coincidence circuit 91d In the coincidence circuit 91d, the second timing information output from the data selector 84d is input to one input terminal, and the output of the counter 71 is input to the other input terminal. Therefore, the coincidence circuit 91d outputs “H” level when the output of the counter 71 becomes equal to the second timing information output from the data selector 84d.
- the signal output from the matching circuit 91d is a second control signal for closing the left-eye shutter 56L (hereinafter referred to as “second left-closing signal Slc2”).
- the AND gate 92R and the AND gate 92L perform a logical product operation of two inputs and one output in the same manner as the AND gate 74.
- the AND gate 92R a signal obtained by logically inverting the second right open signal Sro2 is input to one input terminal, and the second right close signal Src2 is input to the other input terminal. Therefore, the AND gate 92R outputs an “H” level signal if the second right open signal Sro2 is at “L” level and the second right close signal Src2 is at “H” level, otherwise “L”. ”Level signal is output.
- the AND gate 92R is a circuit provided to give priority to the second right open signal Sro2.
- the AND gate 92L a signal obtained by logically inverting the second left open signal Slo2 is input to one input terminal, and the second left close signal Slc2 is input to the other input terminal. Therefore, the AND gate 92L outputs an “H” level signal if the second left open signal Slo2 is at “L” level and the second left close signal Slc2 is at “H” level, otherwise “L”. ”Level signal is output.
- the AND gate 92L is a circuit provided to give priority to the second left open signal Slo2.
- the JK flip-flop 93R and the JK flip-flop 93L are generally used JK flip-flop circuits. That is, when an “L” level signal is input to the input terminal J and an “H” level signal is input to the input terminal K, the output signal becomes the “L” level. Further, when an “H” level signal is input to the input terminal J and an “L” level signal is input to the input terminal K, the output signal becomes the “H” level. When an “L” level signal is input to each of the input terminal J and the input terminal K, the output signal maintains the previous state. When an “H” level signal is input to each of the input terminal J and the input terminal K, the output signal is a signal obtained by logically inverting the previous state.
- the JK flip-flop 93R In the JK flip-flop 93R, the second right open signal Sro2 output from the coincidence circuit 91a is input to the input terminal J, and the output signal of the AND gate 92R is input to the input terminal K. Therefore, the JK flip-flop 93R sets the output signal to the “H” level when the second right open signal Sro2 becomes the “H” level. Further, the JK flip-flop 93R is configured such that when the output of the AND gate 92R is at “H” level, that is, when the second right closing signal Src2 is at “H” level and the second right opening signal Sro2 is at “L” level, The output signal is set to “L” level. The output signal of the JK flip-flop 93R does not change when the second right open signal Sro2 is at "L” level and the second right close signal Src2 is at “L” level.
- the JK flip-flop 93L In the JK flip-flop 93L, the second left open signal Slo2 output from the coincidence circuit 91c is input to the input terminal J, and the output signal of the AND gate 92L is input to the input terminal K. Therefore, the JK flip-flop 93L sets the output signal to the “H” level when the second left open signal Slo2 becomes the “H” level.
- the JK flip-flop 93L is configured such that when the output of the AND gate 92L is at “H” level, that is, when the second left closing signal Slc2 is at “H” level and the second left opening signal Slo2 is at “L” level, The output signal is set to “L” level.
- the output signal of the JK flip-flop 93L does not change when the second left open signal Slo2 is at “L” level and the second left close signal Slc2 is at “L” level.
- a signal (inverted signal) obtained by logically inverting the clock CK is input to the JK flip-flop 93R and JK flip-flop 93L as a synchronization signal. Therefore, the outputs of the JK flip-flop 93R and JK flip-flop 93L are signals delayed by a half cycle of the clock CK.
- the amplifier 94R and the amplifier 94L are voltage amplifiers, and generate voltages necessary for controlling the shutter of the shutter glasses 50.
- the right eye shutter 56R and the left eye shutter 56L provided in the shutter glasses 50 are normally white liquid crystal shutters (transmitting visible light when no control voltage is applied). Therefore, the right-eye shutter 56R and the left-eye shutter 56L are in a state of blocking visible light when a control voltage VCL (for example, voltage 30 (V)) is applied, and are not applied with the control voltage VCL ( For example, when a voltage of 0 (V) is applied), visible light is transmitted.
- VCL for example, voltage 30 (V)
- the amplifier 94R amplifies the output of the JK flip-flop 93R up to a voltage VCL necessary for driving the right-eye shutter 56R.
- V voltage 0
- the amplifier 94R outputs a voltage 0 (V) when the output of the JK flip-flop 93R is “H” level, and the JK flip-flop 93R When the output is at the “L” level, the voltage VCL is output to close the right-eye shutter 56R.
- the amplifier 94L amplifies the output of the JK flip-flop 93L up to a voltage VCL necessary for driving the left-eye shutter 56L.
- V voltage 0
- the amplifier 94L outputs a voltage 0 (V) when the output of the JK flip-flop 93L is “H” level, and the JK flip-flop 93L When the output is at the “L” level, the voltage VCL is output to close the left-eye shutter 56L.
- the shutter control circuit 52 includes the clock generation unit 61, the counter unit 63 that increases the count value based on the clock CK generated by the clock generation unit 61 and is reset by the received first control signal,
- the storage unit 64 that stores the output signal of the counter unit 63 when receiving the control signal for a plurality of fields as the first timing information, and the second timing information based on the first timing information for the plurality of fields stored in the storage unit 64.
- a timing setting unit 65 to be set, and a control signal generation unit 66 that compares the second timing information set by the timing setting unit 65 with the output of the counter 71 to generate a second control signal.
- FIG. 7 is a timing chart showing the operation of the shutter glasses 50 of the plasma display device 100 according to the embodiment of the present invention.
- FIG. 7 shows an output signal of each circuit block in the shutter control circuit 52, and timing when the shutter glasses 50 are operating correctly in synchronization with the first control signal transmitted from the control signal transmission unit 46. A chart is shown.
- the output of the counter 71 when the control signal receiving unit 62 outputs the first right open signal Sro1. Is “10”, the output of the counter 71 when the control signal receiving unit 62 outputs the first right closing signal Src1 is “50”, and the control signal receiving unit 62 outputs the first left opening signal Slo1.
- the output of the counter 71 is “60” and the output of the counter 71 when the control signal receiving unit 62 outputs the first left-close signal Slc1 is “100”.
- the control signal receiving unit 62 outputs the “100” when the counter 71 outputs “100”.
- the first left closing signal Slc1 is output.
- the first left closing signal Slc1 is input to the OR gate 76, the first left closing signal Slc1 is input from the OR gate 76 to the counter 71 as a reset signal. Thereby, the counter 71 is reset in synchronization with the clock CK, and the output signal of the counter 71 becomes “0”.
- the coincidence circuit 72 When the counter 71 outputs “0”, the coincidence circuit 72 outputs “H” level. As a result, the output signal of the selector 73 is switched to “127” from the output signal of the counter 71. At the same time, the AND gate 74 outputs the shift clock Ssft in synchronization with the inverted signal of the clock CK.
- the shift register 83a takes in the output signal of the data latch 82a as new first timing information. If the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the output signal of the data latch 82a is “10”. Therefore, the shift register 83a takes in “10” as new first timing information. At the same time, the shift register 83a shifts the first timing information stored in the shift register 83a one stage at a time (data is moved by one latch circuit). If the counter 71 is operating correctly in synchronization with the first control signal, all the first timing information stored in the shift register 83a is “10”. Therefore, “10” is output from the shift register 83a.
- the shift register 83b takes in the output signal of the data latch 82b as new first timing information. If the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the output signal of the data latch 82b is “50”. Therefore, the shift register 83b takes in “50” as new first timing information. At the same time, the shift register 83b shifts the first timing information stored in the shift register 83b by one stage (data is moved by one latch circuit). If the counter 71 is operating correctly in synchronization with the first control signal, all the first timing information stored in the shift register 83b is “50”. Therefore, “50” is output from the shift register 83b.
- the shift register 83c takes in the output signal of the data latch 82c as new first timing information. If the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the output signal of the data latch 82c is “60”. Therefore, the shift register 83c captures “60” as new first timing information. At the same time, the shift register 83c shifts the first timing information stored in the shift register 83c one step at a time (data is moved by one latch circuit). If the counter 71 is operating correctly in synchronization with the first control signal, the first timing information stored in the shift register 83c is all “60”. Therefore, “60” is output from the shift register 83c.
- the shift register 83d captures the output signal of the data latch 82d as new first timing information. If the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the output signal of the data latch 82d is “100”. Therefore, the shift register 83d captures this “100” as new first timing information. At the same time, the shift register 83d shifts the first timing information stored in the shift register 83d one step at a time (data is moved by one latch circuit). If the counter 71 is operating correctly in synchronization with the first control signal, the first timing information stored in the shift register 83d is all “100”. Therefore, “100” is output from the shift register 83d.
- the signal output from the shift register 83a is always “10”, and the shift register 83b
- the output signal is always “50”
- the signal output from the shift register 83c is always “60”
- the signal output from the shift register 83d is always “100”.
- Each numerical value shown in FIG. 7 is represented by a decimal number, but since “127” is equal to the maximum value in the counter 71, “127” in the meaning of the maximum value in the counter 71 is “FFF” in FIG. ".
- the shift clock Ssft output from the AND gate 74 is input as a synchronization signal to the data latch 82b via the OR gate 81b, and is input as a synchronization signal to the data latch 82c via the OR gate 81c. Via the data latch 82d. Therefore, when the shift clock Ssft is output from the AND gate 74, the data latch 82b, the data latch 82c, and the data latch 82d latch “127” output from the selector 73 as a new input signal.
- the output signal of the data latch 82b is “50” and the output signal of the data latch 82c is “60”.
- the output signal of the data latch 82d is “100”. Therefore, at the timing when the shift clock Ssft is output from the AND gate 74, the output signal of the data latch 82b is temporarily switched from “50” to “127 (FFF in FIG. 7)”, and the output signal of the data latch 82c is “ 60 ”is temporarily switched to“ 127 (FFF in FIG. 7) ”, and the output signal of the data latch 82d is temporarily switched from“ 100 ”to“ 127 (FFF in FIG. 7) ”.
- the output signal of the counter 71 increases from “0” by “1” in synchronization with the clock CK.
- the output signal of the coincidence circuit 72 becomes “L” level
- the output signal of the AND gate 74 also becomes “L” level
- the output signal of the selector 73 is switched from “127” to the output signal of the counter 71.
- the control signal receiving unit 62 will be opened to the first right when the output signal of the counter 71 is “10”.
- the signal Sro1 is output.
- the first right open signal Sro1 output from the control signal receiving unit 62 is input as a synchronization signal to the data latch 82a via the OR gate 81a. Therefore, the data latch 82a latches the output signal “10” of the counter 71, which is the output signal of the selector 73, as new first timing information.
- the output signal of the data latch 82a is switched from “127 (FFF in FIG. 7)” to “10”.
- the coincidence circuit 91a compares the second timing information output from the data selector 84a with the output signal of the counter 71. As described above, if the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the second timing information output from the data selector 84a is “10”. When the output signal 71 is “10”, the coincidence circuit 91a outputs an “H” level signal.
- the control signal receiving unit 62 is the first when the output signal of the counter 71 is “50”. 1 Outputs a right closing signal Src1.
- the first right closing signal Src1 output from the control signal receiving unit 62 is input as a synchronization signal to the data latch 82b via the OR gate 81b. Therefore, the data latch 82b latches the output signal “50” of the counter 71, which is the output signal of the selector 73, as new first timing information. As a result, the output signal of the data latch 82b is switched from “127 (FFF in FIG. 7)” to “50”.
- the coincidence circuit 91b compares the second timing information output from the data selector 84b with the output signal of the counter 71. As described above, if the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the second timing information output from the data selector 84b is “50”. When the output signal 71 is “50”, the coincidence circuit 91b outputs an “H” level signal.
- the control signal receiving unit 62 is the first when the output signal of the counter 71 is “60”. 1 Left open signal Slo1 is output.
- the first left open signal Slo1 output from the control signal receiving unit 62 is input as a synchronization signal to the data latch 82c via the OR gate 81c. Therefore, the data latch 82c latches the output signal “60” of the counter 71, which is the output signal of the selector 73, as new first timing information. As a result, the output signal of the data latch 82c is switched from “127 (FFF in FIG. 7)” to “60”.
- the coincidence circuit 91c compares the second timing information output from the data selector 84c with the output signal of the counter 71. As described above, if the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the second timing information output from the data selector 84c is “60”. When the output signal 71 is “60”, the coincidence circuit 91 c outputs an “H” level signal.
- the control signal receiving unit 62 is the first when the output signal of the counter 71 is “100”. 1
- the left closing signal Slc1 is output.
- the first left closing signal Slc1 output from the control signal receiving unit 62 is input as a synchronization signal to the data latch 82d via the OR gate 81d. Therefore, the data latch 82d latches the output signal “100” of the counter 71, which is the output signal of the selector 73, as new first timing information.
- the output signal of the data latch 82d is switched from “127 (FFF in FIG. 7)” to “100”.
- the coincidence circuit 91d compares the second timing information output from the data selector 84d with the output signal of the counter 71. As described above, if the counter 71 is operating correctly in synchronization with the first control signal transmitted from the control signal transmitter 46, the second timing information output from the data selector 84d is “100”. When the output signal 71 is “100”, the coincidence circuit 91d outputs an “H” level signal.
- this signal is input as the second left closing signal Slc2 to the input terminal K of the JK flip-flop 93L via the AND gate 92L, when the output signal from the coincidence circuit 91d becomes “H” level, The output signal of the JK flip-flop 93L becomes “L” level. As a result, the output signal of the amplifier 94L becomes the voltage VCL (for example, voltage 30 (V)), and the left-eye shutter 56L changes from a state of transmitting visible light to a state of blocking visible light.
- VCL for example, voltage 30 (V)
- the second left closing signal Slc2 output from the coincidence circuit 91d is input as a reset signal to the counter 71 via the delay 75 and the OR gate 76. Therefore, the counter 71 is reset by the second left closing signal Slc2, and the output signal of the counter 71 becomes “0” again.
- the first left closing signal Slc1 and the second left closing signal Slc2 have substantially the same timing. Occurs.
- the shutter control circuit 52 repeats the same operation as described above. Then, by repeating these operations, the shutter control circuit 52 controls the state of transmitting visible light and the state of blocking visible light in the right-eye shutter 56R and the left-eye shutter 56L.
- the optical signal transmitted from the light emitting element 47 and received by the light receiving element 53 is temporarily blocked by a shield or the like, and is received from the control signal transmitting unit 46 to be received by the control signal receiving unit 62. Even if the transmitted first control signal is temporarily lost, the second timing information output from the data selector 84a to the data selector 84d is changed unless the majority decision result is changed in the data selector 84a to the data selector 84d. do not do. If the second timing information output from the data selector 84a to the data selector 84d is correct, the coincidence circuit 91a to the coincidence circuit 91d output the second control signal at the correct timing.
- the shutter control circuit 52 even if the first control signal to be received by the control signal receiving unit 62 is temporarily lost, the second timing information output from the data selector 84a to the data selector 84d is changed.
- the coincidence circuit 91a to the coincidence circuit 91d can output the second control signal at the correct timing and normally control the right-eye shutter 56R and the left-eye shutter 56L. Therefore, the user normally stereoscopically views the 3D image displayed on the panel 10 even if the optical signal transmitted from the light emitting element 47 and received by the light receiving element 53 is temporarily blocked by a shield or the like. be able to.
- each shift register of the shift register 83a, shift register 83b, shift register 83c, and shift register 83d in the storage unit 64 includes eight latch circuits, and eight pieces of first timing information.
- the period for storing the eight pieces of first timing information corresponds to 12 fields. Accordingly, in this configuration, in the shutter control circuit 52, if the first control signal to be received by the control signal receiving unit 62 is lost over a period of 10 fields or more, the data latch 82a, the data latch 82b, the data latch 82c, the data All signals output from the latch 82d are “127”, and more than half of the information stored in the shift registers 83a, 83b, 83c, and 83d is “127”.
- the majority decision results in the data selector 84a, data selector 84b, data selector 84c, and data selector 84d are all “127”, and the data selector 84a, data selector 84b, data selector 84c, and data selector 84d output from the data selector 84d.
- the 2 timing information is all “127”.
- the output signal of the counter 71 becomes “127”
- the output signals of the coincidence circuit 91a, the coincidence circuit 91b, the coincidence circuit 91c, and the coincidence circuit 91d are all at the “H” level. Therefore, both the output of JK flip-flop 93R and the output of JK flip-flop 93L are at “H” level.
- the output signals of the amplifier 94R and the amplifier 94L become voltage 0 (V), and both the right-eye shutter 56R and the left-eye shutter 56L are in a state of transmitting visible light.
- the counter 71 is reset by the output signal from the coincidence circuit 91d, the output signal becomes “0” again, and the value is incremented by “1” from “0” in synchronization with the clock CK.
- the output signals of the coincidence circuit 91a, the coincidence circuit 91b, the coincidence circuit 91c, and the coincidence circuit 91d are all at the “L” level. Therefore, both the output of JK flip-flop 93R and the output of JK flip-flop 93L maintain the previous state and become “H” level.
- the output signals of the amplifier 94R and the amplifier 94L maintain the voltage 0 (V), and the right-eye shutter 56R and the left-eye shutter 56L both maintain a state of transmitting visible light.
- the first control signal to be received by the control signal receiving unit 62 is over a long period of time (the result of majority decision in the data selector 84a, the data selector 84b, the data selector 84c, and the data selector 84d is If all of them are lost (until they all become “127”), the right-eye shutter 56R and the left-eye shutter 56L are both maintained in a state of transmitting visible light. Therefore, in the shutter glasses 50, it is possible to prevent the operation from stopping when one shutter is closed, or the operation from stopping when both shutters are closed. Can be kept from being blocked.
- the shutter glasses 50 store the first timing information for a plurality of fields based on the received first control signal for a plurality of fields, and the first timings for the stored plurality of fields.
- a shutter control circuit 52 that generates a second control signal based on the information is provided, and transmission and blocking of visible light in the right-eye shutter 56R and the left-eye shutter 56L are controlled using the second control signal.
- the right-eye shutter 56R and the left-eye shutter 56L can be normally controlled. Therefore, a user who views a 3D image displayed on the panel 10 through the shutter glasses 50 receives an optical signal for controlling the shutter glasses transmitted from the plasma display device 100 and received by the shutter glasses 50 as a shield or the like. 3D image displayed on the panel 10 can be normally stereoscopically viewed even if it is temporarily blocked by.
- the shutter glasses 50 stop operating when one of the shutters is closed, or stop operating when both shutters are closed. Therefore, it is possible to prevent the user from being in a state where one or both fields of view remain blocked.
- a clock CK which is a synchronization signal necessary for operating each circuit in the shutter control circuit 52, is generated in the clock generator 61 built in the shutter glasses 50. Therefore, in the shutter glasses 50, even if the first control signal to be received is lost, the clock CK can be stably generated, and each circuit in the shutter control circuit 52 can be stably operated.
- each shift register of the shift register 83a, shift register 83b, shift register 83c, and shift register 83d in the storage unit 64 includes eight latch circuits, and eight pieces of first timing information.
- the present invention is not limited to this configuration.
- the shutter control circuit 52 by increasing the number of latch circuits constituting the shift register, when the first control signal to be received by the control signal receiving unit 62 is lost, the right-eye shutter 56R and the left-eye shutter 56L are provided. The time that can be normally controlled can be extended.
- the shutter control circuit 52 by reducing the number of latch circuits constituting the shift register, the right eye shutter 56R and the left eye shutter after the first control signal to be received by the control signal receiving unit 62 is lost. It is possible to reduce the time required to open the 56L together.
- the counter 71 is described as a counter (up counter) that increases the count value in synchronization with the clock CK of the clock generator 61.
- the counter 71 is the clock CK of the clock generator 61. It is also possible to configure as a counter (down counter) that decreases the count value in synchronization with the counter. In that case, each set value in the shutter control circuit 52 may be reset according to the down counter.
- the number of subfields constituting one field is not limited to the above number.
- the number of gradations that can be displayed on the panel 10 can be further increased.
- the luminance weight of the subfield is set to a power of “2”, and the luminance weight of each subfield of subfield SF1 to subfield SF5 is set to (16, 8, 4, 2, 1).
- the example to do was explained.
- the luminance weight set in each subfield is not limited to the above numerical values. For example, by giving redundancy to the combination of subfields that determine the gradation as (12, 7, 3, 2, 1), etc., it is possible to perform coding while suppressing the occurrence of a moving image pseudo contour.
- the number of subfields constituting one field, the luminance weight of each subfield, and the like may be appropriately set according to the characteristics of panel 10 and the specifications of plasma display apparatus 100.
- each circuit block shown in the embodiment of the present invention may be configured as an electric circuit that performs each operation shown in the embodiment, or a microcomputer that is programmed to perform the same operation. May be used.
- the drive circuit described above is merely an example, and the configuration of the drive circuit is not limited to the configuration described above.
- the specific numerical values shown in the embodiment of the present invention are set based on the characteristics of the panel 10 having a screen size of 50 inches and the number of display electrode pairs 24 of 1024. It is just an example. The present invention is not limited to these numerical values, and each numerical value is desirably set optimally in accordance with the characteristics of the panel and the specifications of the plasma display device. Each of these numerical values is allowed to vary within a range where the above-described effect can be obtained. Further, the number of subfields and the luminance weight of each subfield are not limited to the values shown in the embodiment of the present invention, and the subfield configuration may be switched based on an image signal or the like. Good.
- the present invention provides an image display device that stereoscopically displays right-eye images and left-eye images that are alternately displayed on a display device in time order when a control signal to be received by the shutter glasses is temporarily lost. Even when the right eye shutter and the left eye shutter are normally controlled, the user can stereoscopically display the display image. When the control signal to be received by the shutter glasses is missing, one or both of them can be displayed. Since the operation can be prevented from being stopped in a state where the shutter is closed, it is useful as an image display device and shutter glasses.
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Abstract
Description
図1は、本発明の実施の形態におけるプラズマディスプレイ装置に用いるパネル10の構造を示す分解斜視図である。ガラス製の前面基板21上には、走査電極22と維持電極23とからなる表示電極対24が複数形成されている。そして、走査電極22と維持電極23とを覆うように誘電体層25が形成され、その誘電体層25上に保護層26が形成されている。
21 前面基板
22 走査電極
23 維持電極
24 表示電極対
25,33 誘電体層
26 保護層
31 背面基板
32 データ電極
34 隔壁
35 蛍光体層
41 画像信号処理回路
42 データ電極駆動回路
43 走査電極駆動回路
44 維持電極駆動回路
45 タイミング発生回路
46 制御信号発信部
47 発光素子
50 シャッタ眼鏡
52 シャッタ制御回路
53 受光素子
56R 右目用シャッタ
56L 左目用シャッタ
61 クロック発生部
62 制御信号受信部
63 カウンタ部
64 記憶部
65 タイミング設定部
66 制御信号生成部
71 カウンタ
72,91a,91b,91c,91d 一致回路
73 セレクタ
74,92R,92L ANDゲート
75 ディレイ
76,81a,81b,81c,81d ORゲート
82a,82b,82c,82d データラッチ
83a,83b,83c,83d シフトレジスタ
84a,84b,84c,84d データセレクタ
93R,93L JKフリップフロップ
94R,94L 増幅器
100 プラズマディスプレイ装置
Claims (7)
- 右目用画像信号を表示する右目用フィールドと左目用画像信号を表示する左目用フィールドとを交互に繰り返して画像を表示するとともに前記右目用フィールドおよび前記左目用フィールドに同期した第1制御信号を発信する画像表示部と、前記第1制御信号を受信するとともに可視光を透過および遮断する右目用シャッタおよび左目用シャッタを有するシャッタ眼鏡とを備えた画像表示装置であって、
前記シャッタ眼鏡は、受信した複数フィールド分にわたる前記第1制御信号にもとづく複数フィールド分の第1タイミング情報を記憶するとともに、記憶した複数フィールド分の前記第1タイミング情報にもとづき第2制御信号を生成するシャッタ制御回路を備え、
前記第2制御信号を用いて前記右目用シャッタおよび前記左目用シャッタにおける可視光の透過および遮断を制御する
ことを特徴とする画像表示装置。 - 前記シャッタ制御回路は、
クロック発生部と、
前記クロック発生部で発生したクロックにもとづき計数を行うとともに受信した前記第1制御信号でリセットされるカウンタ部と、
前記第1制御信号を受信したときの前記カウンタ部の出力信号を第1タイミング情報として複数フィールド分記憶する記憶部と、
前記記憶部で記憶した複数フィールド分の第1タイミング情報にもとづき第2タイミング情報を設定するタイミング設定部と、
前記タイミング設定部が設定した第2タイミング情報と前記カウンタ部の出力とを比較して前記第2制御信号を生成する制御信号生成部とを備えた
ことを特徴とする請求項1に記載の画像表示装置。 - 前記シャッタ制御回路は、複数フィールド分にわたる前記第1制御信号のうち、半数以上の前記第1制御信号が欠落したときに、前記右目用シャッタおよび前記左目用シャッタをともに可視光を透過する状態にする
ことを特徴とする請求項1に記載の画像表示装置。 - 前記画像表示部は、プラズマディスプレイパネルを用いて構成されている
ことを特徴とする請求項1に記載の画像表示装置。 - 右目用画像信号を表示する右目用フィールドと左目用画像信号を表示する左目用フィールドとを交互に繰り返して画像を表示するとともに前記右目用フィールドおよび前記左目用フィールドに同期した第1制御信号を発信する画像表示部に表示される画像の鑑賞に用いられ、前記第1制御信号を受信するとともに可視光を透過および遮断する右目用シャッタおよび左目用シャッタを有するシャッタ眼鏡であって、
受信した複数フィールド分にわたる前記第1制御信号にもとづく複数フィールド分の第1タイミング情報を記憶するとともに、記憶した複数フィールド分の前記第1タイミング情報にもとづき第2制御信号を生成するシャッタ制御回路を備え、
前記第2制御信号を用いて前記右目用シャッタおよび前記左目用シャッタにおける可視光の透過および遮断を制御する
ことを特徴とするシャッタ眼鏡。 - 前記シャッタ制御回路は、
クロック発生部と、
前記クロック発生部で発生したクロックにもとづき計数を行うとともに受信した前記第1制御信号でリセットされるカウンタ部と、
前記第1制御信号を受信したときの前記カウンタ部の出力信号を第1タイミング情報として複数フィールド分記憶する記憶部と、
前記記憶部で記憶した複数フィールド分の第1タイミング情報にもとづき第2タイミング情報を設定するタイミング設定部と、
前記タイミング設定部が設定した第2タイミング情報と前記カウンタ部の出力とを比較して前記第2制御信号を生成する制御信号生成部とを備えた
ことを特徴とする請求項5に記載のシャッタ眼鏡。 - 前記シャッタ制御回路は、複数フィールド分にわたる前記第1制御信号のうち、半数以上の前記第1制御信号が欠落したときに、前記右目用シャッタおよび前記左目用シャッタをともに可視光を透過する状態にする
ことを特徴とする請求項5に記載のシャッタ眼鏡。
Priority Applications (4)
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JP2012508074A JP5360292B2 (ja) | 2010-03-29 | 2011-03-28 | 画像表示装置およびシャッタ眼鏡 |
EP11762218A EP2555041A1 (en) | 2010-03-29 | 2011-03-28 | Image display device and shutter spectacles |
CN2011800067010A CN102713727A (zh) | 2010-03-29 | 2011-03-28 | 图像显示装置及快门眼镜 |
US13/637,892 US20130016194A1 (en) | 2010-03-29 | 2011-03-28 | Image display device and shutter spectacles |
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JP2010074670 | 2010-03-29 | ||
JP2010-074670 | 2010-03-29 |
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US (1) | US20130016194A1 (ja) |
EP (1) | EP2555041A1 (ja) |
JP (1) | JP5360292B2 (ja) |
KR (1) | KR20120099296A (ja) |
CN (1) | CN102713727A (ja) |
WO (1) | WO2011121969A1 (ja) |
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CN110223644B (zh) * | 2018-03-02 | 2020-08-04 | 京东方科技集团股份有限公司 | 显示装置、虚拟现实设备及驱动方法 |
CN113727088B (zh) * | 2020-05-26 | 2023-12-19 | 上海三思电子工程有限公司 | 3d眼镜控制系统、方法、装置、存储介质及终端 |
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JPH10322726A (ja) * | 1997-05-15 | 1998-12-04 | Sanyo Electric Co Ltd | プラズマディスプレイパネルを用いた時分割メガネ方式の立体映像表示方法 |
JP2001320734A (ja) * | 2000-05-12 | 2001-11-16 | Sony Corp | 立体画像表示装置 |
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TW334520B (en) * | 1995-02-24 | 1998-06-21 | Matsushita Electric Ind Co Ltd | Display device Liquid crystal display |
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US20010043266A1 (en) * | 2000-02-02 | 2001-11-22 | Kerry Robinson | Method and apparatus for viewing stereoscopic three- dimensional images |
JP2002199416A (ja) * | 2000-12-25 | 2002-07-12 | Nippon Hoso Kyokai <Nhk> | 立体画像表示方法及び立体画像表示装置 |
JP5029608B2 (ja) * | 2006-08-02 | 2012-09-19 | 日本電気株式会社 | 画像処理装置及び表示装置並びに画像表示システム |
US8223162B2 (en) * | 2006-08-30 | 2012-07-17 | Nec Corporation | Image processing apparatus, image processing method, program thereof, display device, and image display system |
CN101589328A (zh) * | 2007-11-20 | 2009-11-25 | 松下电器产业株式会社 | 图像显示装置及其显示方法、程序、集成电路、眼镜式头戴式显示器、汽车、双筒望远镜和台式显示器 |
KR101446559B1 (ko) * | 2008-03-24 | 2014-10-06 | 삼성전자주식회사 | 3차원 영상 시청을 위한 신호생성방법 및 이를 적용한영상시청장치 |
JP2009259512A (ja) * | 2008-04-15 | 2009-11-05 | Panasonic Corp | プラズマディスプレイ装置 |
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TWI408947B (zh) * | 2009-02-13 | 2013-09-11 | Mstar Semiconductor Inc | 影像調整裝置及影像調整方法 |
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2011
- 2011-03-28 KR KR1020127019923A patent/KR20120099296A/ko not_active Application Discontinuation
- 2011-03-28 JP JP2012508074A patent/JP5360292B2/ja not_active Expired - Fee Related
- 2011-03-28 US US13/637,892 patent/US20130016194A1/en not_active Abandoned
- 2011-03-28 CN CN2011800067010A patent/CN102713727A/zh active Pending
- 2011-03-28 WO PCT/JP2011/001806 patent/WO2011121969A1/ja active Application Filing
- 2011-03-28 EP EP11762218A patent/EP2555041A1/en not_active Withdrawn
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JPH10322726A (ja) * | 1997-05-15 | 1998-12-04 | Sanyo Electric Co Ltd | プラズマディスプレイパネルを用いた時分割メガネ方式の立体映像表示方法 |
JP2001320734A (ja) * | 2000-05-12 | 2001-11-16 | Sony Corp | 立体画像表示装置 |
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KR20120099296A (ko) | 2012-09-07 |
CN102713727A (zh) | 2012-10-03 |
US20130016194A1 (en) | 2013-01-17 |
JPWO2011121969A1 (ja) | 2013-07-04 |
EP2555041A1 (en) | 2013-02-06 |
JP5360292B2 (ja) | 2013-12-04 |
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