WO2011116524A1 - 具有低栅电阻的沟槽型半导体功率器件及其制备方法 - Google Patents

具有低栅电阻的沟槽型半导体功率器件及其制备方法 Download PDF

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WO2011116524A1
WO2011116524A1 PCT/CN2010/071303 CN2010071303W WO2011116524A1 WO 2011116524 A1 WO2011116524 A1 WO 2011116524A1 CN 2010071303 W CN2010071303 W CN 2010071303W WO 2011116524 A1 WO2011116524 A1 WO 2011116524A1
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trench
layer
gate
buried
source
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PCT/CN2010/071303
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French (fr)
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苏冠创
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香港商莫斯飞特半导体有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41766—Source or drain electrodes for field effect devices with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4941—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a barrier layer between the silicon and the metal or metal silicide upper layer, e.g. Silicide/TiN/Polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66727—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the source electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon

Definitions

  • the present invention relates to a cell structure and device configuration of a power semiconductor device. More particularly, the present invention relates to a novel and improved cell structure and device configuration of a trench type semiconductor power device having a low gate resistance.
  • FIGS. 1A and 1B a top view and a side cross-sectional view of a conventional Mosfet device 10 formed on an n+ type semiconductor substrate 15 having a first conductivity type drain region (for example, an n+ substrate forming a bottom surface).
  • the trench type Mosfet cell is formed on a first conductivity type epitaxial layer 20 (e.g., an N epitaxial layer) having a lower doping concentration than the substrate.
  • a P-type body 25 of a second conductivity type (for example, a PP body 25) is formed in the epitaxial layer 20, and the P-type body 25 surrounds a source region 30 having a first conductivity type (for example, an N+ source) District 30).
  • Each Mosfet cell further includes a polysilicon gate 35 located in a trench insulated from the surrounding epitaxial layer 20 and having a gate oxide layer 40.
  • An NSG and BPSG layer 45 insulates the Mosfet from the top, the NSG and BPSG layer 45 also has a gate metal opening that contacts the gate contact metal layer 50 with the trench type polysilicon gate 35, the NSG and BPSG layer 45 There is also a source contact opening that brings the source metal into contact with the source region.
  • the gate metal layer 50 is located between the source pad layers 55, and the gate metal formed as a "gate" to lower the internal gate resistance is in contact with the gate pad layer 70 in the lower right corner.
  • Source pad layer 55 and gate pad layer 70 are connected to leadframe 90 by gold source leads 75 and gate leads 80 having a diameter of no more than two thousandths of an inch.
  • the source metal is divided into several pieces, which will increase the Ron value of the device due to the increase in surface conduction resistance.
  • the Mosfet trench is filled with a high conductivity material (for example, a refractory metal), so that the internal gate is relatively small, which is suitable for fast switching;
  • An insulating material (such as silicon dioxide) of the trench wall serves as a gate oxide layer.
  • a layer of polysilicon is then formed over the insulating material to provide cushioning for stress relief.
  • the trench is then filled with a high melting point metal such as tungsten.
  • the Mosfet device shown in Figure 2 has a large limitation. As the cell pitch decreases, the width of the trench becomes narrower and narrower. However, the trench gate needs to accommodate the gate oxide layer, polysilicon, and poorly soluble metal, which makes the trench opening of the gate not too small, and the minimum opening size does not allow the trench width to become too narrow, thus limiting the cell. density.
  • a layer of lining is first added to the trench by forming an insulating material (e.g., silicon dioxide) overlying the trench walls.
  • an insulating material e.g., silicon dioxide
  • a polysilicon layer is formed on the insulating material as a buffer layer for stress relief.
  • the top of the trench gate is then filled with a refractory metal such as tungsten.
  • a trench type semiconductor power device having a low gate resistance is characterized in that the semiconductor power device has a buried trench gate of a titanium/titanium nitride/tungsten plug, has a protective insulating layer on the top, and is buried
  • the input trench gate is arranged with a standard trench gate with a buried trench gate, or 10 standard trench gates with a buried trench gate; buried
  • the number of gated gates is inversely proportional to the width of the standard trench gate of the cell and inversely proportional to the desired gate resistance.
  • the semiconductor power device is prepared by:
  • the Mosfet device includes a source contact trench and a buried gate plug trench, the source contact trench having a first formation by oxide etching of oxide layers, ie, BPSG and NSG layers.
  • the oxide trench; the source contact trench and the buried gate plug trench further include a silicon trench formed by silicon etching after oxide etching; and then titanium/titanium nitride is used respectively
  • the layer and the tungsten layer respectively fill the source contact trench and the buried gate trench plug, and then etch the surface layer to remove surface tungsten and the surface of the undoped oxide layer and the BPSG layer.
  • the low-resistance metal layer is composed of titanium/aluminum-copper alloy or titanium/titanium-titanium/aluminum-copper alloy to ensure good electrical contact, and then, The metal is etched such that the metal layer forms a source metal pad layer and a gate metal pad layer and is in electrical contact with the source body trench plug and the buried gate trench plug, respectively.
  • It can reduce the internal gate resistance without affecting the cell density, making it simple and suitable for mass production. It can be used in various trench type MOSFETs, such as P-type and N-type low voltage devices and high voltage devices, P-type and N-type IGBTs, and even high-voltage integrated circuits.
  • Figure 1A is a side cross-sectional view of the prior art
  • Figure 1B is a plan view of the prior art
  • FIG. 2 is a side cross-sectional view of a gate trench filled with a hard metal in the prior art
  • FIG. 3 is a cross-sectional view of a gate trench with a high conductivity layer on top of the prior art
  • FIG. 4 is a cross-sectional view of a prior art gate trench filled with a high conductivity
  • 5A, 5B, 5C, 5D, 5E, 5F, 5G, and 5H are schematic views of the steps of the preparation method of the present invention.
  • Figure 1 15-n+ type semiconductor substrate; 20-epitaxial layer; 25-P type body; 30-source region; 35-polysilicon gate; 40-gate oxide layer; 45-NSG and BPSG layers; 50-gate metal layer; 55-source metal pad; 70-gate pad; 75-source lead; 80-gate lead; 90-lead frame.
  • Fig. 3 7b-trench type gate; 9-silicide layer; 10-interlayer insulating film.
  • a buried trench type gate 250 having a titanium/titanium nitride/tungsten plug is formed, and an NSG layer 270 is formed on the top.
  • the buried trench gate 250 is arranged with a standard trench gate with a buried trench gate or 10 standard trench gates with a buried trench gate.
  • the number of buried trench gates 250 is inversely proportional to the width of the standard trench gate of the cell and inversely proportional to the desired gate resistance.
  • the gate resistance is not limited by the small cell pitch.
  • a trench mask is used to form a plurality of trenches 208 in the epitaxial layer 210 on the base layer 205.
  • the trench is sacrificially oxidized to eliminate the silicon layer that is destroyed by the plasma during the grooving process.
  • An oxide layer 215 is then formed, followed by a polysilicon layer 218 to fill the trench and cover the top surface, followed by doping using an N+ type dopant.
  • the polysilicon layer 218 is etched and then implanted into a P-type body using a P-type dopant. Subsequently, the temperature is raised to diffuse the P-type body 225 into the epitaxial layer 210.
  • a source mask 228 is employed and then a source is implanted using an N-type dopant.
  • the temperature is raised to cause it to diffuse to the source region 230.
  • an undoped oxide NSG layer and a BPSG layer 240 are deposited on the top surface.
  • Contact etching is performed by oxidative etching of BPSG and NSG layer 240 using a contact mask to form a contact opening, and then etching the silicon so that the contact opening penetrates deeper into the source as shown Region 230, P-type body 225, and gate trenches and buried trench gates 220.
  • the source body contact trench and the buried gate trench plug are separately filled using a titanium/titanium nitride layer 245 and a tungsten layer 250, respectively. Thereafter, the surface layer is etched to remove the surface tungsten element and the surface titanium/titanium nitride element on the top of the ILD.
  • FIG. 5F another NSG layer 270 is formed on top of the device.
  • an intermetallic mask is used and dry oxide etching is performed to remove the NSG layer 270 at the top of the source contact plug 260.
  • a layer of low resistance metal 280 is deposited on the top surface.
  • the low-resistance metal layer may be composed of a titanium/aluminum-copper alloy or a titanium/titanium-titanium/aluminum-copper alloy to ensure good electrical contact, and then metal etching is performed to form a metal layer to form a source metal pad layer 55 and a gate electrode.
  • the metal pad layer 70 is in electrical contact with the source body trench plug 260 and the buried gate trench plug 250, respectively.
  • the semiconductor power device is prepared by:
  • the device includes a source body contact trench 260 and a buried gate plug trench 250 having first oxide etch by oxide layers, ie, BPSG and NSG layers.
  • the formed oxide trench; the source contact trench 260 and the buried gate plug trench 250 further comprise a silicon trench formed by silicon etching after oxide etching; then titanium is used respectively / Titanium nitride layer 245 and tungsten layer 246 fill the source body contact trench and the buried gate 250 trench plug, respectively, and then etch the surface layer to remove the undoped oxide layer and BPSG a surface tungsten element on the top of layer 240 and a surface titanium/titanium nitride element;
  • a low resistance metal layer 280 on the top surface of the device, the low resistance metal layer being composed of titanium/aluminum copper alloy or titanium/titanium nitride/aluminum copper alloy to ensure good electrical contact, and then Metal etching is performed such that the metal layer forms the source metal pad layer 55 and the gate metal pad layer 70 and is in electrical contact with the source body trench plug 260 and the buried gate trench plug 250, respectively.

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Description

具有低栅电阻的沟槽型半导体功率器件及其制备方法 技术领域
本发明涉及功率半导体器件的单元结构和器件配置。 更具体地，本发明涉及一种具有低栅电阻的沟槽型半导体功率器件的新型改进单元结构和器件配置。
背景技术
形成用于高密度沟槽型金属氧化物半导体场效应晶体管（Mosfet）器件的沟槽型栅极和栅道的传统技术正面临着技术难题，当沟槽宽度减小时不良内部栅极电阻会增高以致开关速度变慢。狭窄的沟槽宽度，由于沟槽区的掺杂多晶硅减少，会导致很高的栅极电阻。 高栅极电阻会对器件的开关性能造成不利影响，同时还降低产品的可靠性。
参考图1A和1B，在具有第一导电率型的漏区的n+型半导体衬底15（例如形成底面的n+衬底）上形成的普通Mosfet器件10的俯视图和侧剖视图。 沟槽型Mosfet单元在一个第一导电率型的外延层20（例如N外延层）上形成，外延层20具有比衬底低的掺杂浓度。在外延层20中形成一个第二导电率型的P型体25（例如一个PP型体25），P型体25环绕着一个具有第一导电率类型的源极区30（例如一个N+源极区30）。 每个Mosfet单元进一步包括一个多晶硅栅极35，该多晶硅栅极35位于与周围的外延层20绝缘的沟槽中，并具有一个栅极氧化层40。 一个NSG和BPSG层45使Mosfet与顶部绝缘，该NSG和BPSG层45还具有一个栅极金属开口，使栅极接触金属层50与沟槽型的多晶硅栅极35接触，该NSG和BPSG层45还具有一个源极体接触开口，使源极金属与源极区接触。
缺点：当沟槽宽度变小时，沟槽区的掺杂多晶硅减少，栅极电阻会提高，特别是对于中心区的沟槽，从而影响器件的开关速度。
图1B：栅极金属层50位于源极垫层55之间，形成为“栅道”以降低内部栅极电阻的栅极金属与在右下角的栅极垫层70接触。 源极垫层55和栅极垫层70通过直径不大于千分之二英寸的金源极引线75和栅极引线80连接到引线框90。
缺点：源极金属被分为几片，由于表面传导电阻的增加，因而会提高器件的Ron值。
美国专利 6,737,323 揭示了一种沟槽型Mosfet，如图2所示，该Mosfet的沟槽填以高导电率材料（例如难熔金属）所以内部栅极比较小，适合于快速开关；制作上，沟槽盖沟槽壁的绝缘材料（例如二氧化硅）作为栅极氧化层， 然后在绝缘材料上形成一层多晶硅，为消除应力的提供缓冲。 然后使用高熔点金属（例如钨）填满沟槽。 如图2所示的Mosfet器件具有一个很大的限制。 当单元间距减小时，沟槽的宽度会变得越来越窄。 但是，沟槽栅极需要容下栅极氧化层、多晶硅和难溶金属，这使得栅极的沟槽开口不能太小，最小的开口尺寸不允许沟槽宽度变得太窄，因此限制了单元密度。
美国专利 6,930,355，图3： 每个沟槽型栅极7b中的多晶硅层的上部进行硅化处理，以形成硅化物层9。然后形成层间绝缘膜10。
缺点：(i) 工艺难；(ii) 阈值电压难以控制US006930355美国专利US20060273382，图4：
首先通过形成一层覆盖沟槽壁的绝缘材料（例如二氧化硅）为沟槽增加一层衬层。
其次在绝缘材料上形成一多晶硅层，作为消除应力的缓冲层。 然后使用难熔金属（例如钨）填充沟槽型栅极的顶部。
缺点：由于沟槽型栅极开口的尺寸限制，沟槽的宽度受到限制，从而限制了单元密度。
 技术问题
本发明的目的是提供一种具有低栅电阻的沟槽型半导体功率器件及其制备方法，在沟槽型功率Mosfet设计和制造领域中，仍需要提供一种新型的单元结构和器件配置，以解决上述难题和设计限制。 特别是，需要在降低栅极电阻的同时不限制沟槽型半导体功率器件的单元密度的提高。
技术解决方案
本发明的具有低栅电阻的沟槽型半导体功率器件，其特征在于，该半导体功率器件具有钛/氮化钛/钨插头的埋入式沟槽型栅极，在顶部具有保护绝缘层，埋入式沟槽型栅极的布置是一个标准沟槽栅极配有一个埋入式沟槽型栅极，或者是10个标准沟槽栅极配有一个埋入式沟槽型栅极；埋入式沟槽型栅极的数目与单元的标准沟槽型栅极的宽窄成反比，与所需的栅极电阻值成反比。
该半导体功率器件的制备方法为：
a.使用一个沟槽掩模，以便在基层上的外延层中形成多个沟槽；
b.对沟槽进行一次牺牲性氧化，以消除在开槽过程中被等离子破坏的硅层；然后形成一层栅极氧化层，随后沉积一个多晶硅层，以填充沟槽并覆盖顶面，接着使用N+型掺杂剂进行掺杂；对多晶硅层进行浸蚀，然后使用P型掺杂剂植入P型体，随后，提高温度，以便使P型体扩散到外延层中；
c.采用源极掩模，使用N型掺杂剂植入源极，随后，提高温度，以使其扩散到源极区；
d.在顶面上沉积一个非掺杂氧化物层和BPSG层，采用一个接触掩模，通过对非掺杂氧化物层和BPSG层进行氧化浸蚀来进行接触腐蚀处理，以便形成接触开口，然后对硅进行浸蚀，以便使接触开口更深地穿过源极区进入到P型体、以及栅道沟槽和埋入式沟槽栅极中；
e.该Mosfet器件包括一个源极体接触沟槽和埋层栅道插塞沟槽，该源极体接触沟槽具有首先通过对氧化物层即BPSG和NSG层进行氧化物浸蚀而形成的氧化物沟槽；源极体接触沟槽和埋层栅道插塞沟槽还包括一个通过在氧化物浸蚀之后进行的硅浸蚀而形成的硅沟槽；然后分别使用钛/氮化钛层和钨层对源极体接触沟槽和埋入式栅极沟槽插塞分别进行填充，之后，对表层进行浸蚀，以去除非掺杂氧化物层和BPSG层顶部的表面钨元素和表面钛/氮化钛元素；
f.在该器件的顶部形成第二NSG层，采用金属间掩模并进行干燥氧化物浸蚀，以便去除源极接触插塞顶部的第二NSG层；
g.去除光刻胶层；
h.在该器件的顶面上沉积一层低电阻金属层，低电阻金属层由钛/铝铜合金或钛/氮化钛/铝铜合金构成，以保证形成良好的电接触，然后，进行金属浸蚀，使金属层形成源极金属垫层和栅极金属垫层并分别与源极体沟槽插塞和埋入式栅极沟槽插塞电接触。
 有益效果
可以降低内部栅极电阻，同时不影响提高单元密度，制作简单，适用于量产。可用于各种沟槽型金属氧化物半导体场效应晶体管，如P型和N型低压器件和高压器件，P型和N型IGBT以至高压集成电路等。
 附图说明
图1A是现有技术的侧剖视图；
图1B是现有技术的俯视图；
图2是现有技术中填有难镕金属的栅极沟槽的侧剖视图；
图3是现有技术中顶部带有高电导率层的栅极沟槽剖视图；
图4是现有技术中填有高导点率的栅极沟槽的剖视图；
图5A、图5B、图5C、图5D、图5E、图5F、图5G、图5H是本发明制备方法的各步骤示意图。
以上的图中有：
图1中：15－n+型半导体衬底；20－外延层；25－P型体；30－源极区；35－多晶硅栅极；40－栅极氧化层； 45－NSG和BPSG层；50－栅极金属层；55－源极金属垫层；70－栅极垫层；75－源极引线；80－栅极引线；90－引线框。
图3中：7b－沟槽型栅极；9－硅化物层；10－层间绝缘膜。
图5中：205－基层；208－沟槽；210－外延层； 215－氧化层；218－多晶硅层；225－P型体；228－源极掩模；230－源极区；240－BPSG和NSG层；220－埋入式沟槽栅极；245－钛/氮化钛层；25－钨层；270－NSG层；260－源极接触插塞；275－光刻胶层；280－低电阻金属层；55－源极金属垫层；70－栅极金属垫层；250－埋入式栅极沟槽插塞。
本发明的实施方式
本发明的具有低栅电阻的沟槽型半导体功率器件，为了降低栅极电阻，形成了具有钛/氮化钛/钨插头的埋入式沟槽型栅极250，在顶部具有NSG层270，埋入式沟槽型栅极250的布置是一个标准沟槽栅极配有一个埋入式沟槽型栅极，或者是10个标准沟槽栅极配有一个埋入式沟槽型栅极；埋入式沟槽型栅极250的数目与单元的标准沟槽型栅极的宽窄成反比，与所需的栅极电阻值成反比。 采用本新发明，栅极电阻不受小的单元间距的限制。
下列图（图5A到图5H）中的X向剖视图的工艺流程用于展示本发明的思想：
在图5A中，使用一个沟槽掩模以便在基层205上的外延层210中形成多个沟槽208。
在图5B中，对沟槽进行牺牲性氧化，以消除在开槽过程中被等离子破坏的硅层。 然后形成一层氧化层215，随后沉积一个多晶硅层218，以填充沟槽并覆盖顶面，接着使用N+型掺杂剂进行掺杂。 对多晶硅层218进行浸蚀，然后使用P型掺杂剂植入一个P型体。随后，提高温度，以便使P型体225扩散到外延层210中。
在图5C中，采用一个源极掩模228，然后使用N型掺杂剂植入一个源极。
随后，提高温度，以使其扩散到源极区230。
在图5D中，在顶面上沉积一个非掺杂氧化物NSG层和一个BPSG层240。采用一个接触掩模，通过对BPSG和NSG层240进行氧化浸蚀来进行接触腐蚀处理，以便形成接触开口，然后对硅进行浸蚀，以便使接触开口更深地进入到如图所示的源极区230、P型体225、以及栅道沟槽和埋入式沟槽栅极220中。
在图5E中，分别使用钛/氮化钛层245和钨层250对源极体接触沟槽和埋入式栅极沟槽插塞分别进行填充。之后，对表层进行浸蚀，以去除ILD顶部的表面钨元素和表面钛/氮化钛元素。
在图5F中，在器件的顶部形成另一个NSG层270。 在图5F中，采用一个金属间掩模并进行干燥氧化物浸蚀，以便去除源极接触插塞260顶部的NSG层270。
在图5G中，去除了光刻胶层275。
在图5H中，在顶面上沉积一层低电阻金属层280。低电阻金属层可由钛/铝铜合金或钛/氮化钛/铝铜合金构成，以保证形成良好的电接触，然后，进行金属浸蚀，使金属层形成源极金属垫层55和栅极金属垫层70并分别与源极体沟槽插塞260和埋入式栅极沟槽插塞250电接触。
该半导体功率器件的制备方法为：
a.使用一个沟槽掩模，以便在基层205上的外延层210中形成多个沟槽208；
b.对沟槽208进行一次牺牲性氧化，以消除在开槽过程中被等离子破坏的硅层；然后形成一层栅极氧化层215，随后沉积一个多晶硅层218，以填充沟槽并覆盖顶面，接着使用N+型掺杂剂进行掺杂；对多晶硅层218进行浸蚀，然后使用P型掺杂剂植入P型体225，随后，提高温度，以便使P型体225扩散到外延层210中；
c.采用源极掩模228，使用N型掺杂剂植入源极，随后，提高温度，以使其扩散到源极区230；
d.在顶面上沉积一个非掺杂氧化物层和BPSG层240，采用一个接触掩模，通过对非掺杂氧化物层和BPSG层240进行氧化浸蚀来进行接触腐蚀处理，以便形成接触开口，然后对硅进行浸蚀，以便使接触开口更深地穿过源极区230进入到P型体225、以及栅道沟槽和埋入式沟槽栅极220中；
e.该器件包括一个源极体接触沟槽260和埋层栅道插塞沟槽250，该源极体接触沟槽260具有首先通过对氧化物层即BPSG和NSG层进行氧化物浸蚀而形成的氧化物沟槽；源极体接触沟槽260和埋层栅道插塞沟槽250还包括一个通过在氧化物浸蚀之后进行的硅浸蚀而形成的硅沟槽；然后分别使用钛/氮化钛层245和钨层246对源极体接触沟槽和埋入式栅极250沟槽插塞分别进行填充，之后，对表层进行浸蚀，以去除非掺杂氧化物层和BPSG层240顶部的表面钨元素和表面钛/氮化钛元素；
f.在该器件的顶部形成第二NSG层270，采用金属间掩模并进行干燥氧化物浸蚀，以便去除源极接触插塞260顶部的第二NSG层270；
g.去除光刻胶层275；
h.在该器件的顶面上沉积一层低电阻金属层280，低电阻金属层由钛/铝铜合金或钛/氮化钛/铝铜合金构成，以保证形成良好的电接触，然后，进行金属浸蚀，使金属层形成源极金属垫层55和栅极金属垫层70并分别与源极体沟槽插塞260和埋入式栅极沟槽插塞250电接触。

Claims (2)

  1. 一种具有低栅电阻的沟槽型半导体功率器件，其特征在于，该半导体功率器件具有钛/氮化钛/钨插头的埋入式沟槽型栅极（250），在顶部具有NSG层270，埋入式沟槽型栅极（250）的布置是一个标准沟槽栅极配有一个埋入式沟槽型栅极，或者是10个标准沟槽栅极配有一个埋入式沟槽型栅极；埋入式沟槽型栅极（250）的数目与单元的标准沟槽型栅极的宽窄成反比，与所需的栅极电阻值成反比。
  2. 一种具有低栅电阻的沟槽型半导体功率器件的制备方法，其特征在于该半导体功率器件的制备方法为：
    a.使用一个沟槽掩模，以便在基层（205）上的外延层（210）中形成多个沟槽（208）；
    b.对沟槽（208）进行一次牺牲性氧化，以消除在开槽过程中被等离子破坏的硅层；然后形成一层栅极氧化层（215），随后沉积一个多晶硅层（218），以填充沟槽并覆盖顶面，接着使用N+型掺杂剂进行掺杂；对多晶硅层（218）进行浸蚀，然后使用P型掺杂剂植入P型体（225），随后，提高温度，以便使P型体（225）扩散到外延层（210）中；
    c.采用源极掩模（228），使用N型掺杂剂植入源极，随后，提高温度，以使其扩散到源极区（230）；
    d.在顶面上沉积一个非掺杂氧化物层和BPSG层（240），采用一个接触掩模，通过对非掺杂氧化物层和BPSG层（240）进行氧化浸蚀来进行接触腐蚀处理，以便形成接触开口，然后对硅进行浸蚀，以便使接触开口更深地穿过源极区（230）进入到P型体（225）、以及栅道沟槽和埋入式沟槽栅极（220）中；
    e.该Mosfet器件包括一个源极体接触沟槽（260）和埋层栅道插塞沟槽（250），该源极体接触沟槽（260）具有首先通过对氧化物层即BPSG和NSG层进行氧化物浸蚀而形成的氧化物沟槽；源极体接触沟槽（260）和埋层栅道插塞沟槽（250）还包括一个通过在氧化物浸蚀之后进行的硅浸蚀而形成的硅沟槽；然后分别使用钛/氮化钛层（245）和钨层（246）对源极体接触沟槽和埋入式栅极（250）沟槽插塞分别进行填充，之后，对表层进行浸蚀，以去除非掺杂氧化物层和BPSG层（240）顶部的表面钨元素和表面钛/氮化钛元素；
    f.在该器件的顶部形成NSG层（270），采用金属间掩模并进行干燥氧化物浸蚀，以便去除源极接触插塞（260）顶部的NSG层（270）；
    g.去除光刻胶层（275）；
    h.在该器件的顶面上沉积一层低电阻金属层（280），低电阻金属层由钛/铝铜合金或钛/氮化钛/铝铜合金构成，以保证形成良好的电接触，然后，进行金属浸蚀，使金属层形成源极金属垫层（55）和栅极金属垫层（70）并分别与源极体沟槽插塞（260）和埋入式栅极沟槽插塞（250）电接触。
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CN101345259A (zh) * 2007-07-13 2009-01-14 半导体元件工业有限责任公司 垂直型mos晶体管及其方法

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CN101345259A (zh) * 2007-07-13 2009-01-14 半导体元件工业有限责任公司 垂直型mos晶体管及其方法

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017068749A1 (en) * 2015-10-19 2017-04-27 Toyota Jidosha Kabushiki Kaisha Semiconductor device and manufacturing method thereof
CN114628247A (zh) * 2022-05-12 2022-06-14 北京芯可鉴科技有限公司 Igbt器件的制造方法及igbt器件

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