Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
  • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
  • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/62—Capacitors having potential barriers
  • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D1/00—Resistors, capacitors or inductors
  • H10D1/60—Capacitors
  • H10D1/68—Capacitors having no potential barriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
  • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
  • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
  • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors
  • H10D84/217—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors of only conductor-insulator-semiconductor capacitors

Definitions

• Embodiments of the subject matter described herein generally relate to semiconductor components, and more particularly relate to decoupling capacitors used in connection with such components.
• decoupling capacitors or “decaps”
• the ground node is connected to a lightly- or moderately-doped N-well and biased in accumulation. In this way, the low N- well resistance improves high-frequency response of the component while providing the desired decoupling characteristics.
• a decoupling capacitor in accordance with various embodiments includes a pair of metal-oxide-semiconductor (MOS) capacitors formed in wells of opposite plurality, wherein each MOS capacitor has a set of well-ties and a high-dose implant.
• MOS metal-oxide-semiconductor
• a second conductive material e.g., polycrystalline silicon or silicide
• a second insulating material e.g. silicon nitride
• a high permittivity oxide is used as part of the insulating material of the MOS capacitor.
• the top conductor of each MOS capacitor is electrically coupled to the well-ties of the other MOS capacitor, and the well-ties and/or the high-dose implants of the MOS capacitors exhibit asymmetry with respect to their dopant polarities.
• a method of forming a decoupling capacitor in accordance with one embodiment includes: providing a substrate having a first dopant polarity and defining a first well region; forming a second well region adjacent the first well region within the substrate, the second well region having a second dopant polarity opposite the first dopant polarity; forming a first high-dose implant within the first well region; forming a second high-dose implant within the second well region; forming a first set of well-ties in the first well; forming a second set of well-ties in the second well; forming one or more oxide layers over each or both of the first high-dose implant and the second high-dose implant; forming a first conductor over the first well region and a second conductor over the second well region; interconnecting the first set of well-ties and the second conductor to define a first electrical node; and interconnecting the second set of well-ties and the first conductor to define a second electrical node; wherein at least one of the first high-
• FIG. 1 is a conceptual layout view of a decoupling capacitor (decap) design in accordance with one embodiment ;
• FIG. 2 is a conceptual cross-sectional view of region A-A' of FIG. 1;
• FIG. 3 is a conceptual cross-sectional view of region B-B' of FIG. 1;
• FIG. 4 is a conceptual cross-sectional view of Region A-A' of FIG. 1 in accordance with an alternate embodiment
• FIG. 5 is a conceptual cross-sectional view of Region B-B' of FIG. 1 in accordance with an alternate embodiment
• FIG. 6 is a conceptual cross-sectional view of Region A-A' of FIG. 1 in accordance with an alternate embodiment
• FIG. 7 is a conceptual cross-sectional view of Region B-B' of FIG. 1 in accordance with an alternate embodiment
• FIG. 8 is a conceptual layout view showing multiple adjacent decoupling capacitors used in various embodiments.
• FIG. 9 is a schematic diagram showing an equivalent circuit for the embodiment depicted in FIG. 1;
• FIG. 10 is a graph showing the relationship between impedance and frequency for an exemplary decap embodiment.
• FIG. 11 is a graph showing the relationship between charge donation and dopant concentration in an exemplary embodiment.
• an exemplary decoupling capacitor (or "decap") 100 in the context of a CMOS structure is generally formed in the vicinity of one or more nearby logic regions 101, which may include any number of conventional semiconductor logic components.
• Decap 100 which functions to decouple regions 101 from each other, includes two conductors (typically, polysilicon conductors) 106 and 108 positioned over corresponding wells 102 and 104.
• well 104 is a P- substrate well (i.e., a well formed from a portion of the P- substrate), and well 102 is an N-well (i.e., an N-type well formed within the P- substrate).
• the P- region shown in the illustrated embodiment corresponds to a substrate (e.g., a silicon, GaAs, or other suitable semiconductor substrate), this structure also functions as a "well” for the purpose of forming diffused regions (e.g., well-ties), and thus it is common in the art to refer to this structure as a "substrate/well” or a "substrate well.”
• a substrate e.g., a silicon, GaAs, or other suitable semiconductor substrate
• this structure also functions as a "well” for the purpose of forming diffused regions (e.g., well-ties), and thus it is common in the art to refer to this structure as a "substrate/well” or a "substrate well.”
• conductor 106 is bordered on two sides (or at any other suitable locations along its periphery) by two N+ diffusion regions 110 and 1 12 formed within N- well 102.
• conductor 108 is bordered by a P+ diffusion region 1 14 and an N+ diffusion region 1 16.
• diffusion regions 1 10, 112, 1 14, and 1 16 are rectangular and have substantially the same area, shape, and orientation.
• N+ diffusion region 1 10, N+ diffusion region 1 12, and conductor 108 are tied to a supply voltage node (or "VDD") 150, while P+ diffusion region 114, N+ diffusion region 116, and conductor 106 are tied to ground node (or "ground”) 152.
• MOS capacitor 300 (illustrated in FIG. 3) is therefore biased in accumulation, whereas MOS capacitor 200 (illustrated in FIG. 2) is biased in depletion.
• MOS capacitor 200 (illustrated in FIG. 2) is biased in depletion.
• the various conductive traces, electrodes, and/or other contacts used to provide electrical connectivity between these structures are not shown in the figures.
• an implant region 202 (in this case, a high-dose, low energy implant) is formed within N-well 102 between N+ diffusion regions 110 and 112, adjacent to conductor 106.
• implant region 204 is formed between P+ and N+ diffusion regions 114 and 116 within P- substrate well 104 and adjacent to conductor 108.
• Implant regions 202 and 204 may be formed from the same high-dose implant, or from different high-dose implants, and may be N-type or P-type species implants, depending upon the desired behavior. In one embodiment, an N-Type implant having a surface concentration of approximately 3E19/cm 3 is employed.
• the implant conditions may be selected such that an active surface dopant concentration of at least lE19/cm 3 is achieved.
• a high active surface dopant concentration reduces the size of the depletion region when the MOS capacitor is biased in depletion, thereby increasing the high frequency capacitance.
• the high-dose implant also reduces series resistance, further improving the high frequency decoupling of the decap.
• diffusion regions 110, 1 12, 1 14, and 1 16 act as well-ties, i.e., coupling their respective wells to either VDD 150 or ground 152, while the asymmetrical P+ diffusion region 114 effectively protects against latch-up of the decap and nearby logic 101.
• a well capacitance 210 is formed between N-well 102 and P-substrate well 104. This capacitance 210 contributes to decoupling of the circuit.
• decap 100 can be characterized as two MOS capacitors formed in wells having opposite polarity and having at least one pair of asymmetrical well-ties (or being asymmetrical in some other respect.) That is, one MOS capacitor 200 is formed by conductor 106, an oxide 203, and N-well 102, while another MOS capacitor 300 is formed by conductor 108, oxide 203 (or an oxide layer different from oxide 203), and P- substrate well 104.
• Well-tie regions 1 10, 1 12, 1 14, and 116 are asymmetrical in that MOS capacitor 300 includes diffusions (1 14 and 1 16) of opposite polarity, while MOS capacitor 200 includes diffusions (1 10 and 1 12) of the same polarity.
• FIGS. 4 and 5 depict an alternate embodiment of MOS capacitors 200 and 300, respectively, wherein the implant within N-well 102 is a P+ implant 404, and the asymmetry of well-ties is provided by a P+ implant 402 within N-well 102.
• MOS capacitor 300 includes two P+ well-ties 114 and 502. MOS capacitor 200 is therefore biased in accumulation in this embodiment, whereas MOS capacitor 300 is biased in depletion.
• implant 202 may be a depleted, N-type implant, while implant 504 is a P-type implant.
• both MOS capacitors 200 and 300 are biased in depletion mode.
• the illustrated designs are advantageous in that all or substantially all of standard cell transistors within nearby logic regions 101 experience the same one-dimensional well-proximity effect. Furthermore, because decap 100 can be placed relatively close to regions 101, the density of the overall design and the effectiveness of the decoupling are improved vis-a-vis traditional decap methods.
• a particular decap 100 may be configured as a mirrored instance of itself reflected along either the x or y axes. This can be seen in FIG. 8, which shows the placement of exemplary decaps 100 within standard cell rows at arbitrary locations and with standard cell heights. Region 802, for example, depicts a set of three adjacent decaps 100 placed with their longitudinal axes oriented parallel to each other (and the y-axis). Conversely, region 804 shows two adjacent decaps 100 oriented with co-linear longitudinal axes (also parallel to the y-axis).
• wells 102 and 104 are continuous and substantially straight over distances extending beyond multiple transistors, e.g. hundreds of nanometers or microns or larger, such that layout-dependent WPE is minimized. Because decaps 100 electrically couple wells 102 and 104 to VDD and the ground node, respectively, for the surrounding logic circuitry 101, dedicated well contacts for logic circuitry 101 are not necessary.
• Well capacitance 210 will therefore include contributions from wells 102 and 104 in the regions of logic circuitry 101, which may amount to significant low-frequency capacitances, e.g. 0.1-100 fF, depending on the size of wells 102 and 104.
• Filler cells 806 and 808 may be provided for abutting columns to extend and merge the adjacent MOS capacitors of the same polarity of decaps 100, so as to increase decoupling capacitance density per area.
• the various embodiments shown above can be manufactured in a variety of ways, including standard CMOS processing steps and photolithography well known in the art.
• the high-dose, low-energy implants 202 and 204 can be made before gate processing. These dopants can then be activated during source and drain anneal, or in a separate anneal step.
• FIG. 9 presents an equivalent circuit 900 for the embodiment depicted in FIGS. 1-3.
• circuit 900 includes a capacitance CN corresponding to MOS capacitor 200, a capacitance Cj corresponding to the junction capacitance between N-well 102 and P- substrate well 104 (i.e., capacitor 210), and a capacitance Cp corresponding to MOS capacitor 300.
• Circuit 900 also includes a resistance R corresponding to the resistance of N-well 102 and a number of metal contacts to silicon (CAB), a resistance RNP corresponding to the CAB resistance and the resistance of implanted region 204, and a resistance Rpp corresponding to the CAB and P- substrate well 104 resistance.
• CAB metal contacts to silicon
• FIG. 10 depicts the impedance of the circuit (curve 1003) vs. the impedance of a conventional decap circuit (curve 1001) as function of frequency.
• the conventional decap is a single MOS capacitor in an n-well biased in accumulation formed with a conventional process.
• the conventional decap has the same layout area footprint as the embodiment pictured in FIGS. 1-3, it requires greater spacing to logic circuitry 101 and introduces WPE variation to the neighboring transistors.
• FIG. 1 1 depicts the change in charge donation (at 100GHz), normalized to that of the conventional decap, vs. surface dopant concentration in the decap implant regions (i.e., regions 202 and 204).

Landscapes

• Semiconductor Integrated Circuits (AREA)
• Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Priority Applications (4)

Applications Claiming Priority (2)

Publications (1)

Family

ID=43937842

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (5)

Citations (5)

Family Cites Families (7)

• 2010
  • 2010-02-12 US US12/705,185 patent/US8227846B2/en active Active
• 2011
  • 2011-02-11 EP EP11704012.1A patent/EP2534690B1/en active Active
  • 2011-02-11 JP JP2012553032A patent/JP2013520016A/ja active Pending
  • 2011-02-11 KR KR1020127023803A patent/KR101697720B1/ko not_active Expired - Fee Related
  • 2011-02-11 CN CN2011800087480A patent/CN102754214A/zh active Pending
  • 2011-02-11 WO PCT/US2011/024522 patent/WO2011106176A1/en not_active Ceased

Patent Citations (5)

Also Published As

Similar Documents

Legal Events