WO2011091774A1 - Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission - Google Patents

Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission Download PDF

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Publication number
WO2011091774A1
WO2011091774A1 PCT/DE2010/000094 DE2010000094W WO2011091774A1 WO 2011091774 A1 WO2011091774 A1 WO 2011091774A1 DE 2010000094 W DE2010000094 W DE 2010000094W WO 2011091774 A1 WO2011091774 A1 WO 2011091774A1
Authority
WO
WIPO (PCT)
Prior art keywords
pulse
bus
transmission
active
voltage
Prior art date
Application number
PCT/DE2010/000094
Other languages
German (de)
English (en)
Inventor
Petar Tomic
Klaus Adler
Roland Seifert
Harald Kemmann
Ingo Laskiwitz
Original Assignee
Gira Giersiepen Gmbh & Co. Kg
Tapko Technologies Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gira Giersiepen Gmbh & Co. Kg, Tapko Technologies Gmbh filed Critical Gira Giersiepen Gmbh & Co. Kg
Priority to EP10708889.0A priority Critical patent/EP2529521B1/fr
Priority to PCT/DE2010/000094 priority patent/WO2011091774A1/fr
Priority to ES10708889T priority patent/ES2434340T3/es
Priority to RU2012136546/07A priority patent/RU2524206C2/ru
Priority to CN201080062770.9A priority patent/CN102742232B/zh
Publication of WO2011091774A1 publication Critical patent/WO2011091774A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40045—Details regarding the feeding of energy to the node from the bus
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
    • H02J13/00—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network
    • H02J13/00006—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment
    • H02J13/00007—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using the power network as support for the transmission
    • H02J13/00009—Circuit arrangements for providing remote indication of network conditions, e.g. an instantaneous record of the open or closed condition of each circuitbreaker in the network; Circuit arrangements for providing remote control of switching means in a power distribution network, e.g. switching in and out of current consumers by using a pulse code signal carried by the network characterised by information or instructions transport means between the monitoring, controlling or managing units and monitored, controlled or operated power network element or electrical equipment using the power network as support for the transmission using pulsed signals
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B90/00—Enabling technologies or technologies with a potential or indirect contribution to GHG emissions mitigation
    • Y02B90/20—Smart grids as enabling technology in buildings sector
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
    • Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
    • Y04S40/00—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them
    • Y04S40/12—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment
    • Y04S40/121—Systems for electrical power generation, transmission, distribution or end-user application management characterised by the use of communication or information technologies, or communication or information technology specific aspects supporting them characterised by data transport means between the monitoring, controlling or managing units and monitored, controlled or operated electrical equipment using the power network as support for the transmission

Definitions

  • the invention relates to a transmission stage in a bus node of a bus network, in particular in a bus node of an EIB network, which is coupled to a bus line, for generating a transmission signal corresponding bit signal, and a method for generating a bit signal from a transmission signal, wherein the transmission signal from a sequence of transmission pulses.
  • Bus nodes should on the one hand ensure a combination between the control units contained in them, mostly microprocessors, on the other hand also ensure the voltage supply of this control unit and also of connected application circuits, such as relays, sensors, buttons, displays and the like via the bus.
  • a bus node in this sense therefore contains a transmitter, a receiver and a power supply for the internal circuit and possibly also for the application circuits.
  • Figure 1 shows the configuration of a bus with multiple bus nodes.
  • the power supply includes one or more power supplies, however, whose output impedance must be increased to prevent the transmission frequencies of the bus communication from the power supplies from being attenuated to the point of cancellation in the worst case.
  • intermediate impedance converter which are preferably designed as throttle modules.
  • the requirements for a transmission stage when used in an EIB network are specified in the Konnex manual, version 2.0. Based on these requirements, the finished bus devices are certified.
  • FIG. 2 shows in the partial image (a) a bit sequence from an EIB example telegram which is generated in accordance with a sequence of pulses of a transmission signal, in the partial image (b) the details of a single bit pulse.
  • Bus + is the nominal bus voltage
  • bus represents the common potential for the further considerations, ie the ground potential.
  • the EIB signal of a single transmit pulse is a time-limited and in the duration synchronized with the transmit pulse voltage drop Ua, hereinafter referred to as an active pulse designated, defined from the nominal bus voltage Bus +.
  • an active pulse designated, defined from the nominal bus voltage Bus +.
  • a defined voltage increase Ue then follows beyond the nominal bus voltage Bus +, which initiates the so-called compensation pulse.
  • Bus nodes in their function as transmitters generate these signals accordingly.
  • the same amount of energy that a transmit pulse extracts from the bus with the active pulse should be re-injected during the equalize pulse.
  • At least one control circuit is provided, which outputs the transmission signal at least to the circuit for generating the active pulse.
  • Such a transmission stage is described in DE 10 2006 011 595 B4.
  • the replica of an active pulse in accordance with the currently applied bus DC voltage, wherein the amplitude of the active pulse is predetermined by the amplitude of a transmission signal voltage generated in the transmission stage.
  • the energy loss caused by the active pulse is stored in a capacitive storage element.
  • a voltage is built up on the memory element which is higher than the bus DC voltage. It is in the circuit for generating the active pulse
  • a control circuit is provided in the circuit for generating the equalizing pulse, the control circuits communicating with one another in order to pass on the transmitted signal.
  • the object of the present invention is to further develop this known transmission stage and to ensure by optimized signal shaping that the extracted energy as far as possible can be returned to the bus.
  • the pulse depth of the active pulse is determined by a predetermined reference voltage in a transmission stage, which is independent of the size of the DC voltage component of the bit signal or bus signal. This makes it possible, as it were, to obtain advance knowledge of how much energy the active pulse will subtract, so that the decay behavior of the equalizing pulse can be defined by the adapted dimensioning of a timing element (eg a differentiating circuit).
  • a timing element eg a differentiating circuit.
  • the presence of a circuit for generating a balance pulse is only one option that is not mandatory for realizing the invention.
  • the reference voltage may be a supply voltage provided by a voltage supply of the bus node or else an intermediate voltage which is generated in a voltage supply of the bus node.
  • the pulse depth of the active pulse is kept constant by negative feedback of the AC voltage component of the bit signal, which further contributes to be able to determine the exact deducted in the active pulse energy.
  • a circuit for generating the equalizing pulse when a circuit for generating the equalizing pulse is present, it has at least two energy storage, which are connected in parallel at the beginning of the transmission pulse and charge during the duration of the transmission pulse to the currently present bus voltage and at the end of the transmission pulse be connected in series, wherein the total voltage is connected via the series-connected energy storage on the bus.
  • a single control circuit is provided, which drives the circuit for generating the active pulse and the circuit for generating the equalizing pulse. This simplifies the actual circuitry and becomes possible because the equalizing pulse is synchronized directly with the transmit pulse.
  • a method for generating a bit signal corresponding to a transmission signal comprising a train of transmission pulses, which for each transmission pulse consists of an active pulse and an equalizing pulse following the active pulse comprises the steps of generating the active pulse and generating the equalizing pulse and thereby characterized in that the pulse depth of the active pulse is determined by a predetermined reference voltage, and it is preferred that the pulse depth of the active pulse is kept constant by negative feedback of the AC voltage component of the bit signal.
  • the generation of the equalizing pulse, the provision of at least two energy storage, the parallel switching of the energy storage at the beginning of a transmission pulse, so that the energy storage are charged during the duration of the transmission pulse to the currently present bus voltage, and the in-series switching of Energy storage of the transmission pulse includes.
  • the invention describes the use of a transmission stage according to one of claims 1 to 6 in an application-specific integrated circuit (ASIC), which could then also comprise other circuit parts, for example receiver, power supply and the like.
  • ASIC application-specific integrated circuit
  • FIG. 1 shows an example of a configuration of a bus.
  • FIG. 2 shows in the partial image (a) a bit sequence from an EIB example telegram and in the partial image (b) the details of a bit pulse from the bit sequence.
  • FIG. 3 shows a block diagram of a transmission stage according to an exemplary embodiment of the present invention.
  • Figure 4 shows an embodiment of a circuit for generating the active pulse to be used in a transmission stage according to the present invention.
  • Figure 5 shows a circuit for generating the equalizing pulse to be used in a transmitting stage according to the present invention.
  • FIG. 6 shows an example of a complete transmission stage according to the present invention together with the control circuit.
  • FIG. 3 shows a block diagram of a transmission stage in a bus node according to an embodiment of the present invention.
  • a circuit A for generating the active pulse and a circuit B for generating the subsequent to the active pulse equalizing pulse are driven by a single control circuit C, which shows a transmission signal, for simplicity as a single transmit pulse U send , both to the circuit A for Generating the active pulse and outputs to the circuit B for generating the equalizing pulse.
  • the control unit issuing the signal U send is shown in the drawing. figure not shown.
  • the transmission stage can be realized without the circuit B for generating the equalizing pulse.
  • Figure 4 shows an example of a circuit for generating the active pulse for a transmission stage according to the present invention.
  • the transistor Q3 constitutes a transmitting transistor as an emitter follower which is switched by a driving circuit formed of transistors Q1 and Q2.
  • the transmission signal U S end is applied to the base of the transistor Q2.
  • the transistor Q2 In the idle state, ie without existing transmit pulse, the transistor Q2 is blocked and, since no current can flow through the resistor R5, as a result, the transistor Q3. Since the transistor Q2 is blocked, no current can flow in the base-emitter circuit of the transistor Ql, it is therefore also blocked, although at the base of the resistance divider formed from the resistors Rl and R2 via the protective resistor R3, a control voltage Ub is applied.
  • the transistor Ql is thus prepared for opening.
  • the capacitor Cl is used for negative feedback of the AC voltage component of the bus signal.
  • the capacitor transmits the falling edge at t 0 as a negative voltage to the resistor divider Rl, R2. If this reaches the value of -Ub plus the accumulating voltage drops across the base-emitter path of the transistor Ql and the emitter-collector saturation voltage of the transistor Q2, the transistor Ql blocks and, as a consequence, the transistor Q3, so that the bus voltage Bus + does not can fall further.
  • the values of the resistors R1, R2 and R2 must be high on the one hand, so as not to load the bus line too much, but on the other hand, too low, at the moment Send pulse U se nd to ensure a safe opening of the transistor Ql.
  • the pulse depth of the active pulse is determined by U re f and the voltage divider Rl, R2, in addition to the voltage drops across the now active transistors Ql and Q2. If the value of the resistor R3 is not set too high, the voltage drop due to the very low base current of the transistor Ql can be neglected.
  • U re f may be the supply voltage for connected applications, or even the intermediate voltage that is generated at a power supply for bus node, as described for example in PCT / DE2010 / 000017.
  • the reference voltage U re f can be used directly if it has the required value to achieve the desired pulse depth. It can also be processed by a Zener diode or a voltage regulator. For these embodiments, the resistor R2 can be omitted.
  • FIG. 5 shows a circuit for generating the equalizing pulse.
  • the circuit At rest, ie without a transmit pulse U sen d, which acts at the base of the transistor Q6, the circuit is de-energized due to the locked transistor Q6 and as a result, the locked transistor Q5.
  • the transistor Q6 opens.
  • the capacitor C2 charges via the resistor R7 and the diode D2 to the currently existing bus voltage Bus +, which prevails during the active pulse on.
  • the resistor Rl 1 and through the diode D6 a base current for the transistor Q5, which now also opens.
  • the capacitor C4 Via the diode D5 and the resistor R9, the capacitor C4 also charges to the currently existing bus voltage.
  • the capacitors C2 and C4 are connected in parallel at the beginning during the active pulse. Also, a current flows through the diode D4 and through the resistor R8, but if the resistor R8 is selected to be relatively high impedance, this current is negligible and loads the bus only slightly.
  • the transistor Q4 is turned off and, since the cathodes of the two diodes D4 and D5 have approximately the same potential, the capacitor C3 is practically discharged.
  • the transistor Q5 is also turned off.
  • the diodes D4 and D5 are arranged opposite polarity, so that this route also carries no electricity.
  • a current now flows from the charged capacitor C4 via the collector-base path of the transistor Q4, the discharged capacitor C3 and the resistor R8.
  • the transistor Q4 opens.
  • the two capacitors C4 and C2 are now connected in series. Their total voltage is higher than the bus voltage Bus +, so that now a relatively high current flows towards the bus, which is limited by the resistor R9.
  • the capacitor C3 is now continuously charged via the resistor R8 until the transistor Q4 blocks again.
  • FIG. 6 shows the combination of the circuits according to FIG. 4 and FIG. 5.
  • the transistor Q2 assumes the function of the transistor Q6 from the circuit according to FIG. 5, so that the transmit pulse U sen d is applied both to the circuit for generating the active pulse and to the circuit for generating the equalizing pulse is given.
  • a decoupling diode Dl is provided, which separates the two circuits functionally from each other.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un étage d'émission dans un nœud de bus d'un réseau de bus, en particulier dans un nœud de bus d'un réseau EIB, lequel nœud est couplé à une ligne du bus (Bus+, Bus-), servant à générer un signal binaire qui correspond à un signal d'émission comportant une série d'impulsions d'émission et qui se compose pour chaque impulsion d'émission d'une impulsion active, qui a une durée Δt = t1 - t0, t0 indiquant le début de l'impulsion active et t1 la fin de l'impulsion active, et une profondeur d'impulsion Ua, et d'une impulsion compensatrice contiguë à l'impulsion active. L'étage d'émission est équipé : - d'un circuit (A) pour générer l'impulsion active; - en option, d'un circuit (B) pour générer l'impulsion compensatrice; et - au moins d'un circuit de commande (C) qui délivre en sortie le signal d'émission (Usend) au moins au circuit (A) afin de générer l'impulsion active. L'étage d'émission se caractérise en ce que la profondeur d'impulsion (Ua) de l'impulsion active est définie par une tension de référence (Uref) prédéterminée qui est indépendante de la grandeur de la composante continue du signal binaire.
PCT/DE2010/000094 2010-01-29 2010-01-29 Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission WO2011091774A1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP10708889.0A EP2529521B1 (fr) 2010-01-29 2010-01-29 Etage d'emission dans un noeud d'un reseau de bus pour generer un signal de bit correspondant a un signal a transmettre et procede correspondant
PCT/DE2010/000094 WO2011091774A1 (fr) 2010-01-29 2010-01-29 Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission
ES10708889T ES2434340T3 (es) 2010-01-29 2010-01-29 Etapa de emisión en un nodo de bus de una red en bus para generar una señal de bit correspondiente a una señal de emisión y procedimiento para generar una señal de bit a partir de una señal de emisión
RU2012136546/07A RU2524206C2 (ru) 2010-01-29 2010-01-29 Передающий каскад в шинном узле шинной сети для выработки соответствующего передаваемому сигналу битового сигнала и способ выработки битового сигнала из передаваемого сигнала
CN201080062770.9A CN102742232B (zh) 2010-01-29 2010-01-29 总线网络的总线节点中的用于生成对应于发送信号的位信号的发送级以及用于从发送信号中生成位信号的方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/DE2010/000094 WO2011091774A1 (fr) 2010-01-29 2010-01-29 Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission

Publications (1)

Publication Number Publication Date
WO2011091774A1 true WO2011091774A1 (fr) 2011-08-04

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PCT/DE2010/000094 WO2011091774A1 (fr) 2010-01-29 2010-01-29 Etage d'émission dans un nœud de bus d'un réseau de bus servant à générer un signal binaire correspondant à un signal d'émission et procédé pour générer un signal binaire à partir d'un signal d'émission

Country Status (5)

Country Link
EP (1) EP2529521B1 (fr)
CN (1) CN102742232B (fr)
ES (1) ES2434340T3 (fr)
RU (1) RU2524206C2 (fr)
WO (1) WO2011091774A1 (fr)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996031012A1 (fr) * 1995-03-30 1996-10-03 Siemens Aktiengesellschaft Technique de generation d'informations de tension alternative pour un systeme de bus, et unite de transmission pour l'application de cette technique
WO1998004027A1 (fr) * 1996-07-17 1998-01-29 Siemens Aktiengesellschaft Coupleur de bus pour emission sans translateur
EP0909497B1 (fr) * 1996-07-04 2003-08-20 Siemens Aktiengesellschaft Coupleur de bus comportant un circuit emetteur commande en amplitude

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1062757A1 (ru) * 1982-08-05 1983-12-23 Рижское Производственное Объединение "Вэф" Им.В.И.Ленина Устройство дл передачи и контрол сигналов

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1996031012A1 (fr) * 1995-03-30 1996-10-03 Siemens Aktiengesellschaft Technique de generation d'informations de tension alternative pour un systeme de bus, et unite de transmission pour l'application de cette technique
EP0909497B1 (fr) * 1996-07-04 2003-08-20 Siemens Aktiengesellschaft Coupleur de bus comportant un circuit emetteur commande en amplitude
WO1998004027A1 (fr) * 1996-07-17 1998-01-29 Siemens Aktiengesellschaft Coupleur de bus pour emission sans translateur

Also Published As

Publication number Publication date
CN102742232B (zh) 2015-04-29
EP2529521A1 (fr) 2012-12-05
RU2524206C2 (ru) 2014-07-27
EP2529521B1 (fr) 2013-10-09
RU2012136546A (ru) 2014-03-10
CN102742232A (zh) 2012-10-17
ES2434340T3 (es) 2013-12-16

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