WO2011036828A1 - Procédé pour la fabrication de dispositif à semi-conducteurs, dispositif à semi-conducteurs fabriqué selon le procédé - Google Patents

Procédé pour la fabrication de dispositif à semi-conducteurs, dispositif à semi-conducteurs fabriqué selon le procédé Download PDF

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WO2011036828A1
WO2011036828A1 PCT/JP2010/003443 JP2010003443W WO2011036828A1 WO 2011036828 A1 WO2011036828 A1 WO 2011036828A1 JP 2010003443 W JP2010003443 W JP 2010003443W WO 2011036828 A1 WO2011036828 A1 WO 2011036828A1
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film
metal
metal film
forming
silicon
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Japanese (ja)
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仙石直久
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パナソニック株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4983—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET with a lateral structure, e.g. a Polysilicon gate with a lateral doping variation or with a lateral composition variation or characterised by the sidewalls being composed of conductive, resistive or dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Definitions

  • the present invention relates to a method of manufacturing a semiconductor device and a semiconductor device using the same, and more particularly to a semiconductor device having a gate electrode or a fuse element in which a metal and polysilicon are stacked.
  • FIG. 18 shows a transistor formation process according to a first conventional example using a metal gate having a MIPS (Metal Inserted Poly-Si Stack) structure (see, for example, Patent Document 1).
  • MIPS Metal Inserted Poly-Si Stack
  • an element isolation region 102 that divides an NFET (N-type Field Effect Transistor) region and a PFET (P-type Field EffectTransistor) region is formed on a semiconductor substrate 101 made of silicon. Selectively form.
  • a gate insulating film 103 is formed on the semiconductor substrate 101, and then, by a PVD (Physical Vapor-Deposition) method, the work function value is large on the entire surface of the gate insulating film 103 and suitable for the gate metal of the PFET.
  • a titanium nitride (TiN) film 104 is deposited.
  • wet etching is performed with the PFET region covered with a resist mask to remove the TiN film 104 in the NFET region.
  • a polysilicon film 105 is deposited on the entire surface of the semiconductor substrate 101.
  • a metal film 113 and a cap insulating film 114 are sequentially deposited on the polysilicon film 105.
  • a metal electrode made of polysilicon / TiN is formed in the PFET region by a lithography method and an etching method, and a polysilicon electrode is formed in the NFET region.
  • Patent Document 1 a so-called polymetal structure in which a metal film 113 is formed on a polysilicon film 105 is employed. Thereafter, although not shown, extension implantation is performed on the upper portion of the semiconductor substrate 101 using the patterned gate electrode as a mask.
  • a sidewall 106 is formed on the side surface of the gate electrode, and source / drain implantation is performed on the semiconductor substrate 101 using the formed sidewall 106 and gate electrode as a mask.
  • a nickel (Ni) film is deposited on the entire surface of the semiconductor substrate 101, and the deposited Ni film is subjected to heat treatment to form a Ni silicide film 107 on the active region in a self-aligned manner.
  • an interlayer insulating film 108 is deposited on the semiconductor substrate 101 so as to cover the gate electrode. After that, a contact plug 109 that is electrically connected to the metal film 113 of the gate electrode is formed in the interlayer insulating film 108.
  • a metal gate using a metal having a composition different from that of the PFET can be formed for the NFET.
  • the characteristics are significantly deteriorated as compared with the NFET. Only the PFET to be used is a metal gate, so that the process change is minimized.
  • the TiN film is known to be a material suitable as a metal for a PFET because the work function value is about the midgap of silicon (midgap) or higher (close to the valence band). Note that in an NFET, Fermi level pinning does not occur even when a poly-Si / high-k gate structure is used. Therefore, even if a poly-Si / high-k structure is used, the operation characteristics are not deteriorated as much as a PFET.
  • the interface resistance between the metal material (TiN film 104) constituting the metal gate and the polysilicon film 105 is high. Since a metal gate electrode material such as TiN has a Fermi level within the band gap of silicon (Si), when TiN or the like is brought into contact with polysilicon, a Schottky having either N-type or P-type polarity. Joining. Thereby, although it depends on the dopant concentration of the polysilicon film 105, the interface resistance tends to increase. Furthermore, in addition to the formation of the Schottky junction, it also strongly depends on the manufacturing process, and a high resistance layer may be formed between the metal and the polysilicon, thereby increasing the interface resistance. When the interface resistance is high, the transistor is not charged / discharged quickly, which hinders the high-speed operation of the FET.
  • Patent Document 2 and Patent Document 3 disclose that the metal film 113 penetrates through the metal film 113 in the contact hole opening process when the contact plug 109 to the gate electrode is formed, as shown in FIG. Etching is performed up to the polysilicon film 105 under the film 113.
  • Etching is performed up to the polysilicon film 105 under the film 113.
  • Ti titanium
  • TiN titanium nitride
  • W tungsten
  • an object of the present invention is to reduce the interface resistance between a metal film having a MIPS structure and a contact plug.
  • a semiconductor device is configured to directly contact a first metal film in a MIPS structure and a second metal film in a polymetal structure.
  • the first method for manufacturing a semiconductor device includes a step (a) of forming a first insulating film on a semiconductor region, and a first method on the first insulating film.
  • the first metal film is formed on the first insulating film, and the first silicon film is formed on the formed first metal film. Subsequently, an opening for exposing the first metal film is formed in the first silicon film, and a second metal film is formed on at least the bottom surface and the wall surface of the formed opening.
  • the first metal film in the lowermost layer and the second metal film on the first silicon film are in direct contact with each other, and therefore the interface resistance between the first silicon film and the first metal film. Therefore, the device can be operated at high speed.
  • the second metal film is formed so as to embed an opening on the first silicon film, and is formed after the step (e).
  • the method may further include a step (f) of forming a gate electrode by patterning the second metal film, the first silicon film, and the first metal film.
  • the second metal film is formed so as to embed an opening on the first silicon film
  • the method may further comprise a step (h) of forming a gate electrode by forming a third metal film on the first silicon film.
  • the step (h) may include a step of forming a metal silicide on the first silicon film by heat-treating the third metal film.
  • a semiconductor film made of silicon germanium may be used instead of the second metal film.
  • the second metal film is formed on the first silicon film including the bottom surface and the wall surface of the opening, and the step (e).
  • step (f) of patterning the second metal film, the first silicon film, the first metal film, and the first insulating film, and a second metal film on the patterned first silicon film And a step (h) of forming a gate electrode by forming a metal silicide film on top of the first silicon film from which the second metal film has been removed. Also good.
  • a second silicon film is formed on the first silicon film including the bottom surface and the wall surface of the opening between step (d) and step (e).
  • the step (e) includes the step of forming a second metal film on the second silicon film, and then performing a heat treatment to form the second metal film and the second silicon film.
  • the second silicon film can be substituted by leaving the first silicon film without completely etching the first silicon film.
  • the opening is an opening groove formed so as to expose the first insulating film, and is formed after step (e). Patterning the second metal film, the first silicon film, the first metal film, and the first insulating film so as to face each other with the opening groove interposed therebetween, so that the second metal film is made of the first silicon film.
  • the method may further include a step (f) of forming a fuse element remaining on the upper surface, the bottom surface of the opening groove, and the wall surface.
  • the first method of manufacturing the semiconductor device includes a second silicon film on the first silicon film including the bottom surface and the wall surface of the opening groove between the steps (d) and (e).
  • the step (e) further includes forming a second metal film on the second silicon film, and then performing a heat treatment to form the second metal film and the second metal film.
  • a step of forming a metal silicide film from the silicon film may be included.
  • the opening may be formed so as to expose the first insulating film.
  • a step (a) of forming a first insulating film on a semiconductor region and a first metal film on the first insulating film are formed.
  • Step (b) forming a first silicon film on the first metal film (c), patterning the first silicon film and the first metal film, thereby forming the gate electrode
  • the first metal film is formed on the first insulating film, and the first silicon film is formed on the formed first metal film.
  • a gate electrode is formed by patterning the first silicon film and the first metal film, and a second metal film is formed on the semiconductor region so as to cover the gate electrode.
  • the formed second metal film is heat-treated to form a metal silicide film on the top and side portions of the first silicon film.
  • the lowermost first metal film and the metal silicide film formed on the upper and side portions of the first silicon film are in direct contact with each other, so that the first silicon film and the first metal film are in contact with each other. Since it is not affected by the interfacial resistance, the device can be operated at high speed.
  • the second semiconductor device manufacturing method includes a step (g) of performing first extension implantation in the semiconductor region using the gate electrode as a mask between the step (d) and the step (e), and the step (f). Thereafter, at least one of the step (h) of performing the second extension implantation into the semiconductor region using the gate electrode on which the metal silicide film is formed as a mask may be provided.
  • a first semiconductor device includes a semiconductor region, a first insulating film formed on the semiconductor region, a first metal film formed on the first insulating film, A silicon film having an opening, a second metal film formed on the silicon film, and an opening in the silicon film, the first metal film and the second metal film. And a third metal film for electrically connecting the metal film.
  • the first metal film in the lowermost layer and the second metal film on the silicon film are in direct contact with each other by the third metal film.
  • the device is not affected by the interface resistance between the first metal film and the first metal film, so that the device can be operated at high speed.
  • the second metal film may be a metal silicide film.
  • the second metal film and the third metal film may be metal silicide films.
  • the first metal film, the silicon film, the second metal film, and the third metal film may constitute a gate electrode.
  • a second semiconductor device is formed by interposing an insulating film on a semiconductor region, and at least two stacked layers in which a first metal film, a silicon film, and a second metal film are sequentially stacked.
  • a structure and a third metal film that electrically connects the stacked structures are provided, and a fuse element is formed from the stacked structure and the third metal film.
  • the third metal film may be a metal silicide film.
  • the first metal film in the lowermost layer and the second metal film on the silicon film are in direct contact with each other. Since it is not affected by the interface resistance with the metal film 1, the device can be operated at high speed.
  • FIG. 1 is a cross-sectional view showing a semiconductor device according to the first embodiment of the present invention.
  • 2A to 2F are cross-sectional views in order of steps showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3A is a plan view of FIG.
  • FIG. 3B is a plan view in FIG.
  • FIG. 3C is a cross-sectional view of one step showing the method for manufacturing a semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a cross-sectional view showing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 5A to FIG. 5F are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 6B are cross-sectional views in order of steps showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 7 is a sectional view showing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 8A to FIG. 8F are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 9 is a plan view of FIG.
  • FIG. 10 is a sectional view showing a semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 11A to FIG. 11F are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 12A is a plan view of FIG. FIG. 12B and FIG.
  • FIG. 12C are cross-sectional views in order of steps showing the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention.
  • FIG. 13A is a plan view showing a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 13B is a cross-sectional view taken along line XIIIb-XIIIb in FIG.
  • FIG. 14A to FIG. 14F are cross-sectional views in order of steps showing the method for manufacturing a semiconductor device according to the fifth embodiment of the present invention.
  • FIG. 15 is a plan view of FIG.
  • FIG. 16 is a cross-sectional view showing a semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 17F are cross-sectional views in order of steps showing the method for manufacturing a semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 18A to FIG. 18F are cross-sectional views in order of steps showing a method for manufacturing a semiconductor device according to the first conventional example.
  • FIG. 19 is a sectional view showing a semiconductor device according to a second conventional example.
  • the semiconductor device according to the first embodiment is a P-type field effect transistor (PFET), for example, a gate electrode 9 formed on a semiconductor substrate 1 made of silicon (Si). have.
  • the gate electrode 9 is formed so as to straddle the semiconductor region (active region) partitioned by the element isolation 2 formed on the semiconductor substrate 1.
  • the gate electrode 9 includes a gate insulating film 3 including a high-k film, a titanium nitride (TiN) film 4, a polysilicon film 5, a metal film 7, and an insulating film 8 that are sequentially formed on the semiconductor substrate 1. Yes.
  • a side wall 10 is formed on the side surface of the gate electrode 9, and the gate electrode 9 including the side wall 10 is covered with an interlayer insulating film 11.
  • an interlayer insulating film 11 In the interlayer insulating film 11, a contact plug 12 connected to the metal film 7 of the gate electrode 9 is provided in the vicinity of the contact portion of the metal film 7 with the TiN film 4.
  • a part of the metal film 7 formed on the polysilicon film 5 in the gate electrode 9 penetrates the region on the element isolation 2 of the polysilicon film 5 and the TiN film 4. It is a point that touches directly.
  • the metal film 7 for forming the polymetal gate and the TiN film 4 for forming the metal gate are in direct contact with each other through the through-hole, the interface resistance between the polysilicon film 5 and the TiN film 4 is Therefore, the PFET can be operated at high speed.
  • the contact portion of the metal film 7 with the TiN film 4 is formed by two through holes.
  • the metal film 7 may be in contact by at least one through hole. That's fine.
  • element isolation 2 is selectively formed on a semiconductor substrate 1 made of silicon.
  • threshold-control ion implantation Vt implantation
  • the semiconductor region partitioned by element isolation 2 in the semiconductor substrate 1 to activate the semiconductor region to be an active region.
  • the surface oxide film on the semiconductor substrate 1 is removed.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the gate insulating film 3, and HfSiO having a thickness of 3.0 nm by chemical vapor deposition (CVD) is formed thereon.
  • CVD chemical vapor deposition
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the gate insulating film 3 is not limited to a high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 which is a gate metal film having a thickness of 10 nm is deposited on the gate insulating film 3 by, for example, a CVD method.
  • a non-doped polycrystal having a thickness of 80 nm is deposited on the TiN film 4.
  • a silicon film 5 is deposited.
  • a p-type dopant is ion-implanted (gate implantation) into the polysilicon film 5.
  • a PFET is targeted, and a TiN film 4 that is an effective metal material for the PFET having an effective work function value of about 4.6 eV or more is used as the gate metal.
  • a metal material having a large effective work function such as TaN or TaCNO can be used.
  • a so-called Cap film is deposited on the gate insulating film 3, that is, on the HfSiON film to increase the effective work function value of the gate electrode 9 such as an AlO film, and subsequently a metal such as TiN is deposited on the Cap film.
  • a film may be deposited.
  • NFET N-type field effect transistor
  • TaC which is a material having a small effective work function
  • LaO film is used as the NFET Cap material, the value of the effective work function of the gate electrode in the NFET can be similarly reduced.
  • the TiN film 4 is exposed to at least one place (here, two places) of the upper part of the element isolation 2 in the polysilicon film 5 by lithography and dry etching.
  • a first contact hole 5a is formed.
  • the first contact hole 5 a may be formed only in the polysilicon film 5, or may be formed in the upper part or all of the TiN film 4 under the polysilicon film 5 (that is, penetrated).
  • a metal film 7 made of W / TiN / Ti it is desirable that the Ti film and the TiN film are deposited up to the bottom of the first contact hole 5a by using a film forming method with high directivity.
  • the W film is desirably formed by a CVD method or an atomic layer deposition (ALD) method.
  • W / TiN / Ti is used as the metal film 7, the present invention is not limited to this, and a W / WN x film known as a polymetal gate electrode material may be used. Further, the W film is deposited to a thickness of 50 nm or more, and the deposited W film is planarized by a chemical mechanical polishing (CMP) method or an etch back method to form a more uniform W film having a desired film thickness. 5 may be formed. Further, at this time, all the metal film 7 on the polysilicon film 5 may be removed, and a W / TiN / Ti film or a W / WN x film may be formed again on the polysilicon film 5. In this way, a gate electrode in which the upper surface of the metal film 7 is flattened can be obtained.
  • CMP chemical mechanical polishing
  • an insulating film 8 made of silicon nitride (SiN) is deposited on the metal film 7 by low pressure CVD.
  • the lower TiN film 4 is a gate metal electrode film and functions as a metal film that determines the effective work function of the gate electrode 9.
  • the upper metal film 7 made of W / TiN / Ti is a metal film constituting a so-called polymetal gate electrode, and is basically not involved in the modulation of the effective work function of the gate electrode 9. It serves to reduce sheet resistance.
  • FIG. 3A shows a planar configuration in the process of FIG. As shown in FIG. 3A, a first contact hole 5a is formed in the polysilicon film 5 in a region to be a gate electrode 9 in a later step, and a metal film penetrating from the metal film 7 to the TiN film 4 is formed. 7 is embedded.
  • the insulating film 8 to the TiN film 4 are patterned by lithography and dry etching. Subsequently, cleaning is performed to remove the resist mask and the gate insulating film 3, thereby obtaining the gate electrode 9.
  • the planar configuration after this step is shown in FIG.
  • a metal film 7 is embedded in the upper part of the element isolation 2 in the gate electrode 9 constituting the PFET.
  • P-type extension (Ext) implantation is performed on the active region of the semiconductor substrate 1 using the patterned gate electrode 9 as a mask. Thereafter, sidewalls 10 made of SiN or the like are formed on each side surface of the gate electrode 9. Subsequently, source / drain (S / D) implantation is performed on the active region of the semiconductor substrate 1 using the formed sidewall 10 and the gate electrode 9 as a mask. Thereafter, heat treatment is performed to activate the implanted impurities.
  • a nickel (Ni) film for example, is deposited on the entire surface of the semiconductor substrate 1, and the deposited Ni film is heat-treated to form a Ni silicide film on the active region in a self-aligned manner.
  • Ni nickel
  • an interlayer insulating film 11 is deposited on the semiconductor substrate 1 so as to cover the gate electrode 9.
  • a second contact hole 11a exposing the metal film 7 is formed above the gate electrode 9 in the interlayer insulating film 11 and in the vicinity of the first contact hole 5a.
  • a contact plug 12 is formed by burying a contact metal made of W / TiN / Ti or the like in the formed second contact hole 11a.
  • the path from the contact plug 12 to the TiN film 4 which is the lower gate metal layer constituting the gate electrode 9 is conventionally the metal film 7 which is the metal layer of the polymetal gate electrode and the gate metal.
  • a polysilicon film 5 is always present between the TiN film 4.
  • the upper metal film 7 and the lower TiN film 4 are in direct contact with each other through the first contact hole 5a, and therefore, between the metal film 7 and the TiN film 4.
  • the polysilicon film 5 is not interposed. As a result, the influence of the interface resistance between the polysilicon film 5 and the TiN film 4 is eliminated, so that the delay time of the PFET can be shortened.
  • the semiconductor device according to the second embodiment is different from the semiconductor device according to the first embodiment in that a Ni silicide film 13 is provided instead of the metal film 7 which is a metal layer of the polymetal gate electrode. It is.
  • the Ni silicide film 13 and the TiN film 4 for forming the metal gate are in direct contact with each other through the metal film 7 embedded in the through hole (first contact hole). Since it is not affected by the interface resistance with the TiN film 4, the PFET can be operated at high speed.
  • an element isolation 2 is selectively formed on an upper portion of a semiconductor substrate 1 made of silicon.
  • threshold-control ion implantation Vt implantation
  • Vt implantation threshold-control ion implantation
  • the surface oxide film on the semiconductor substrate 1 is removed.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the gate insulating film 3, and an HfSiO film having a thickness of 3.0 nm is deposited thereon by a CVD method.
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the gate insulating film 3 is not limited to a high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 which is a gate metal film having a thickness of 10 nm is deposited on the gate insulating film 3 by, for example, a CVD method.
  • a non-doped polycrystal having a thickness of 80 nm is deposited on the TiN film 4.
  • a silicon film 5 is deposited.
  • the PFET is targeted, and the TiN film 4 that is an effective metal material for the PFET having an effective work function value of about 4.6 eV or more is used for the gate metal.
  • a metal material having a large effective work function such as TaN or TaCNO can be used.
  • a so-called Cap film is deposited on the gate insulating film 3, that is, on the HfSiON film to increase the effective work function value of the gate electrode 9 such as an AlO film, and subsequently a metal such as TiN is deposited on the Cap film.
  • a film may be deposited.
  • the TiN film 4 is exposed to at least one place (here, two places) of the upper part of the element isolation 2 in the polysilicon film 5 by lithography and dry etching.
  • a first contact hole 5a is formed.
  • the first contact hole 5a may be formed only in the polysilicon film 5, or may be formed in the upper part or the whole (through) of the TiN film 4 below the polysilicon film 5.
  • a metal film 7 made of W / TiN / Ti it is desirable that the Ti film and the TiN film are deposited up to the bottom of the first contact hole 5a by using a film forming method with high directivity.
  • the W film is desirably formed by a CVD method or an atomic layer deposition (ALD) method.
  • W / TiN / Ti is used as the metal film 7
  • the present invention is not limited to this, and a W / WN x film known as a polymetal gate electrode material may be used.
  • the present invention is not limited to the above metals, and may be a single layer film of other metal materials, for example, tantalum nitride (TaN) or a laminated film containing TaN.
  • the Schottky barrier height of each metal film ie, Ni silicide film 13 and TiN film 4 having lower resistance than that of the polysilicon film 5 and in contact with each of the upper and lower ends is higher than that of the polysilicon film 5.
  • a low semiconductor material for example, SiGe film may be used.
  • the metal film 7 is polished by the CMP method to expose the polysilicon film 5 therebelow.
  • the metal film 7 on the polysilicon film 5 is removed by polishing, but the metal film 7 buried in the first contact hole 5a remains as it is.
  • the polysilicon film 5 to the TiN film 4 are patterned by lithography and dry etching. Subsequently, cleaning is performed to remove the resist mask and the gate insulating film 3, thereby obtaining the gate electrode 9.
  • P-type extension (Ext) implantation is performed on the active region of the semiconductor substrate 1 using the patterned gate electrode 9 as a mask. Thereafter, sidewalls 10 made of SiN or the like are formed on each side surface of the gate electrode 9. Subsequently, source / drain (S / D) implantation is performed on the active region of the semiconductor substrate 1 using the formed sidewall 10 and the gate electrode 9 as a mask. At this time, impurities are also implanted into the polysilicon film 5 constituting the gate electrode 9. Thereafter, heat treatment is performed to activate the implanted impurities.
  • a nickel (Ni) film for example, is deposited on the entire surface of the semiconductor substrate 1 by sputtering or vacuum evaporation, and the deposited Ni film is subjected to heat treatment, A Ni silicide film 13 is formed in a self-aligned manner on the polysilicon film 5 and the active region, thereby obtaining a transistor structure.
  • an interlayer insulating film 11 is deposited on the semiconductor substrate 1 so as to cover the gate electrode 9.
  • a second contact hole 11 a exposing the Ni silicide film 13 is formed above the gate electrode 9 in the interlayer insulating film 11 and in the vicinity of the metal film 7.
  • a contact plug 12 is formed by burying a contact metal made of W / TiN / Ti or the like in the formed second contact hole 11a.
  • the upper Ni silicide film 13 and the lower TiN film 4 are in direct contact with each other via the metal film 7 embedded in the first contact hole 5a.
  • the polysilicon film 5 is not interposed between the Ni silicide film 13 and the TiN film 4.
  • the influence of the interface resistance between the polysilicon film 5 and the TiN film 4 is eliminated, so that the delay time of the PFET can be shortened.
  • FIG. 7 the same components as those shown in FIG. 1 and FIG.
  • the semiconductor device according to the third embodiment is different from the semiconductor device according to the second embodiment in that the first contact hole 5 a formed in the polysilicon film 5 constituting the gate electrode 9 is formed by the metal film 7. Instead, the metal thin film 14 made of tantalum nitride (TaN) is provided on the bottom surface and the wall surface of the first contact hole 5a. In FIG. 7, the interlayer insulating film that covers the gate electrode 9 and the contact plug formed in the interlayer insulating film are omitted.
  • the Ni silicide film 13 and the TiN film 4 for forming the metal gate are in direct contact with each other through the metal thin film 14 formed in the first contact hole 5a, the polysilicon film 5 and the TiN film 4 are contacted. Therefore, the PFET can be operated at high speed.
  • element isolation 2 is selectively formed on a semiconductor substrate 1 made of silicon.
  • threshold-control ion implantation Vt implantation
  • the semiconductor region partitioned by element isolation 2 in the semiconductor substrate 1 to activate the semiconductor region to be an active region.
  • the surface oxide film on the semiconductor substrate 1 is removed.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the gate insulating film 3, and an HfSiO film having a thickness of 3.0 nm is deposited thereon by a CVD method.
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the gate insulating film 3 is not limited to a high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 which is a gate metal film having a thickness of 10 nm is deposited on the gate insulating film 3 by, for example, a CVD method.
  • a non-doped polycrystal having a thickness of 80 nm is deposited on the TiN film 4.
  • a silicon film 5 is deposited.
  • the PFET is targeted, and the TiN film 4 that is an effective metal material for the PFET having an effective work function value of about 4.6 eV or more is used as the gate metal.
  • a metal material having a large effective work function such as TaN or TaCNO can be used.
  • a so-called Cap film is deposited on the gate insulating film 3, that is, on the HfSiON film to increase the effective work function value of the gate electrode 9 such as an AlO film, and then a metal such as TiN is deposited on the Cap film.
  • a film may be deposited.
  • an NFET, TaC or the like which is a material having a small effective work function value can be used.
  • a LaO film is used as the NFET Cap material, the value of the effective work function of the gate electrode in the NFET can be similarly reduced.
  • the TiN film 4 is exposed to at least one place (here, two places) of the upper part of the element isolation 2 in the polysilicon film 5 by lithography and dry etching.
  • a first contact hole 5a is formed.
  • the first contact hole 5a may be formed only in the polysilicon film 5, or may be formed in the upper part or the whole (through) of the TiN film 4 below the polysilicon film 5.
  • TaN having a film thickness of 5 nm is formed on the polysilicon film 5 along the bottom surface and the wall surface of each first contact hole 5a by sputtering or the like.
  • a metal thin film 14 is deposited.
  • the metal thin film 14 to be deposited can use a metal material (for example, a TiN film) that does not form silicide with the polysilicon film 5 instead of TaN.
  • the metal thin film 14 is a low-resistance material as compared with the polysilicon film 5 and the height of the Schottky barrier of each metal film (that is, the Ni silicide film 13 and the TiN film 4) that is in contact with each other at the upper end and the lower end.
  • a semiconductor material lower than that of the polysilicon film 5 may be used.
  • the metal thin film 14 to the TiN film 4 are patterned by lithography and dry etching. Subsequently, cleaning is performed to remove the resist mask and the gate insulating film 3, thereby obtaining the gate electrode 9.
  • the planar configuration after this step is shown in FIG. As shown in FIG. 9, a metal thin film 14 is formed along the wall surface of the first contact hole 5a in the gate electrode 9 constituting the PFET.
  • P type extension (Ext) implantation is performed on the active region of the semiconductor substrate 1 using the patterned gate electrode 9 as a mask. Thereafter, sidewalls 10 made of SiN or the like are formed on each side surface of the gate electrode 9. At this time, the metal thin film 14 formed on the upper surface of the polysilicon film 5 is scraped away by dry etching when forming the sidewall 10 and disappears. On the other hand, the first contact hole 5a is filled with an insulating film 10a when the sidewall 10 is formed. In addition, the metal thin film 14 should just be removed by the Ni silicide formation process which is a post process.
  • an offset sidewall is formed between the gate electrode 9 and the sidewall 10
  • it may be removed when the offset sidewall is formed.
  • source / drain (S / D) implantation is performed on the active region of the semiconductor substrate 1 using the formed sidewall 10 and the gate electrode 9 as a mask.
  • impurities are also implanted into the polysilicon film 5 constituting the gate electrode 9.
  • heat treatment is performed to activate the implanted impurities.
  • a nickel (Ni) film for example, is deposited on the entire surface of the semiconductor substrate 1 by sputtering or vacuum evaporation, and the deposited Ni film is heat-treated, A Ni silicide film 13 is formed in a self-aligned manner on the polysilicon film 5 and the active region, thereby obtaining a transistor structure.
  • an interlayer insulating film is deposited on the semiconductor substrate 1 so as to cover the gate electrode 9.
  • a second contact hole exposing the Ni silicide film 13 is formed above the gate electrode 9 in the interlayer insulating film and in the vicinity of the metal thin film 14.
  • a contact metal made of W / TiN / Ti or the like is embedded in the formed second contact hole to form a contact plug.
  • the upper Ni silicide film 13 and the lower TiN film 4 are in direct contact with each other through the metal thin film 14 formed in the first contact hole 5a.
  • the polysilicon film 5 is not interposed between the Ni silicide film 13 and the TiN film 4. As a result, the influence of the interface resistance between the polysilicon film 5 and the TiN film 4 is eliminated, so that the delay time of the PFET can be shortened.
  • FIG. 10 the same components as those shown in FIG. 1 and FIG.
  • the semiconductor device according to the fourth embodiment is different from the semiconductor device according to the third embodiment in that the first contact hole formed in the polysilicon film 5 constituting the gate electrode 9 has a bottom surface and a wall surface.
  • the metal thin film 14 to be provided is a Ni silicide film, and the Ni silicide film provided on the bottom surface and the wall surface is provided integrally with the Ni silicide film 18 above the polysilicon film 5.
  • the interlayer insulating film covering the gate electrode 9 and the contact plug formed in the interlayer insulating film are omitted.
  • the PFET can be operated at high speed.
  • element isolation 2 is selectively formed on a semiconductor substrate 1 made of silicon.
  • threshold-control ion implantation Vt implantation
  • the semiconductor region partitioned by element isolation 2 in the semiconductor substrate 1 to activate the semiconductor region to be an active region.
  • the surface oxide film on the semiconductor substrate 1 is removed.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the gate insulating film 3, and an HfSiO film having a thickness of 3.0 nm is deposited thereon by a CVD method.
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the gate insulating film 3 is not limited to a high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 which is a gate metal film having a thickness of 10 nm is deposited on the gate insulating film 3 by, for example, a CVD method.
  • a non-doped polycrystal having a thickness of 80 nm is deposited on the TiN film 4.
  • a silicon film 5 is deposited.
  • the PFET is targeted, and the TiN film 4 that is an effective metal material for the PFET having an effective work function value of about 4.6 eV or more is used as the gate metal.
  • a metal material having a large effective work function such as TaN or TaCNO can be used.
  • a so-called Cap film is deposited on the gate insulating film 3, that is, on the HfSiON film to increase the effective work function value of the gate electrode 9 such as an AlO film, and then a metal such as TiN is deposited on the Cap film.
  • a film may be deposited.
  • an NFET, TaC or the like which is a material having a small effective work function value can be used.
  • a LaO film is used as the NFET Cap material, the value of the effective work function of the gate electrode in the NFET can be similarly reduced.
  • the TiN film 4 is exposed to at least one place (here, two places) of the upper portion of the element isolation 2 in the polysilicon film 5 by lithography and dry etching.
  • a first contact hole 5a is formed.
  • the first contact hole 5a may be formed only in the polysilicon film 5, or may be formed in the upper part or the whole (through) of the TiN film 4 below the polysilicon film 5. In the case of this embodiment, it is possible to leave the polysilicon film 5 without penetrating it.
  • a polysilicon thin film 16 having a thickness of 3 nm is formed on the polysilicon film 5 along the bottom and wall surfaces of the first contact holes 5a by the CVD method. accumulate. If the polysilicon film 5 is not penetrated, the polysilicon thin film 16 need not be deposited.
  • a Ni film 17 having a thickness of 5 nm is deposited on the polysilicon thin film 16 by sputtering or the like.
  • a first heat treatment is performed at a temperature of 300 ° C. for 30 seconds to cause the Ni film 17 to undergo silicidation reaction with the polysilicon thin film 16 and part of the polysilicon film 5.
  • a Ni silicide (Ni 2 Si) film 18 is formed from the Ni film 17.
  • the unreacted Ni film 17 is removed by washing with a hydrogen peroxide aqueous solution (SPM).
  • SPM hydrogen peroxide aqueous solution
  • a second heat treatment is further performed at a temperature of 450 ° C. for about 30 seconds to change the composition of the Ni silicide film 18 to NiSi.
  • the metal silicide formed on the polysilicon film 5 and inside the first contact hole 5a is Ni silicide.
  • the present invention is not limited to this, and Co silicide (CoSi 2 ) or Ti Other metal silicides such as silicide (TiSi 2 ) may be used.
  • the Ni film 17 is a single-layer film, but a TiN film may be deposited on the Ni film 17 as a barrier film.
  • the Ni 2 Si film is formed.
  • the NiSi film may be formed from the beginning by increasing the heat treatment temperature, and further, Ni 3 Si 4 or NiSi 2 or the like may be formed. Also good.
  • the Ni film 17 may be a partial reaction or a total reaction.
  • the Ni silicide film 18 to the TiN film 4 are patterned by lithography and dry etching. Subsequently, cleaning is performed to remove the resist mask and the gate insulating film 3, thereby obtaining the gate electrode 9.
  • the planar configuration after this step is shown in FIG.
  • a Ni silicide film 18 is formed along the wall surface of the first contact hole 5a in the gate electrode 9 constituting the PFET.
  • P type extension (Ext) implantation is performed on the active region of the semiconductor substrate 1 using the patterned gate electrode 9 as a mask. Thereafter, sidewalls 10 made of SiN or the like are formed on each side surface of the gate electrode 9. At this time, the insulating film 10a when the sidewall 10 is formed is buried in the first contact hole 5a.
  • source / drain (S / D) implantation is performed on the active region of the semiconductor substrate 1 using the formed sidewall 10 and gate electrode 9 as a mask. At this time, impurities are also implanted into the polysilicon film 5 constituting the gate electrode 9. Thereafter, heat treatment is performed to activate the implanted impurities.
  • a nickel (Ni) film is deposited on the entire surface of the semiconductor substrate 1 by a sputtering method or a vacuum evaporation method, and the deposited Ni film is subjected to a heat treatment to form an upper portion of the polysilicon film 5 and the active region.
  • a transistor structure is obtained by forming the Ni silicide film 18 on the top in a self-aligned manner. In this second silicidation step, the Ni silicide film 18 is formed thick on the top of the gate electrode 9.
  • an interlayer insulating film is deposited on the semiconductor substrate 1 so as to cover the gate electrode 9.
  • a second contact hole exposing the Ni silicide film 18 is formed on the interlayer insulating film above the gate electrode 9 and in the vicinity of the first contact hole 5a.
  • a contact metal made of W / TiN / Ti or the like is embedded in the formed second contact hole to form a contact plug.
  • the upper Ni silicide film 18 and the lower TiN film 4 are in direct contact with each other through the first contact hole 5a, whereby the Ni silicide film 18 and the TiN film are contacted. 4, the polysilicon film 5 is no longer interposed. As a result, the influence of the interface resistance between the polysilicon film 5 and the TiN film 4 is eliminated, so that the delay time of the PFET can be shortened.
  • the semiconductor device according to the fifth embodiment is a fuse element, which is formed on a semiconductor substrate 1 made of silicon, for example, and is opposed to the groove 5A. It has two electrodes 9A formed. Each electrode 9 ⁇ / b> A is formed on an insulating film 3 ⁇ / b> A on the element isolation 2 formed on the semiconductor substrate 1.
  • Each electrode 9A is composed of an insulating film 3A, a TiN film 4, a polysilicon film 5 and a Ni silicide film 18 which are sequentially formed on the semiconductor substrate 1.
  • the Ni silicide film 18 is formed across the upper surface and the opposing surface of the two electrodes 9A facing each other, and functions as a substantial fuse.
  • element isolation 2 is selectively formed on a semiconductor substrate 1 made of silicon.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the insulating film 3A, and a HfSiO film having a thickness of 3.0 nm is deposited thereon by a CVD method.
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the insulating film 3A is not limited to the high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 having a thickness of 10 nm is deposited on the insulating film 3A by, for example, a CVD method, and then a non-doped polysilicon film 5 having a thickness of 80 nm is deposited on the TiN film 4. .
  • a trench 5A exposing the insulating film 3A is formed in the polysilicon film 5 and the TiN film 4 by lithography and dry etching.
  • the gate electrode 9 can function as a fuse element.
  • a polysilicon thin film 16 having a film thickness of 3 nm is deposited on the polysilicon film 5 along the bottom surface and the wall surface of the trench 5A by the CVD method.
  • a Ni film 17 having a thickness of 5 nm is deposited on the polysilicon thin film 16 by sputtering or the like.
  • a first heat treatment is performed at a temperature of 300 ° C. for 30 seconds to cause the Ni film 17 to undergo silicidation reaction with the polysilicon thin film 16 and part of the polysilicon film 5.
  • a Ni silicide (Ni 2 Si) film 18 is formed from the Ni film 17.
  • the unreacted Ni film 17 is removed by washing with a hydrogen peroxide aqueous solution (SPM).
  • SPM hydrogen peroxide aqueous solution
  • a second heat treatment is further performed at a temperature of 450 ° C. for about 30 seconds to change the composition of the Ni silicide film 18 to NiSi.
  • the metal silicide formed on the polysilicon film 5 and inside the trench 5A is Ni silicide.
  • the present invention is not limited to this, and Co silicide (CoSi 2 ) or Ti silicide (TiSi 2).
  • Other metal silicides may be used.
  • the Ni film 17 is a single-layer film, but a TiN film may be deposited on the Ni film 17 as a barrier film.
  • the Ni 2 Si film is formed.
  • the NiSi film may be formed from the beginning by increasing the heat treatment temperature, and further, Ni 3 Si 4 or NiSi 2 or the like may be formed. Also good.
  • the Ni film 17 may be a partial reaction or a total reaction.
  • the present invention is not limited to a metal silicide such as a Ni 2 Si film, and a TiN film that is not silicided may be used in place of the polysilicon thin film 16 and the Ni film 17.
  • FIG. 15 shows a planar configuration in this process. As shown in FIG. 15, the Ni silicide film 18 is etched in a region larger than the plane area of the trench 5A.
  • FIG. 14F the Ni silicide film 18 to the TiN film 4 are patterned by lithography and dry etching. Subsequently, a fuse element is obtained by performing cleaning to remove the resist mask and the insulating film 3A.
  • FIG.14 (f) is the figure which formed to the side wall after this.
  • the groove 5A between the electrodes 9A penetrates in the vertical direction in the figure.
  • the fuse element can be functioned (fused) with a desired amount of current.
  • an interlayer insulating film is deposited on the semiconductor substrate 1 so as to cover the electrode 9A.
  • a contact hole exposing the Ni silicide film 18 is formed above each electrode 9A in the interlayer insulating film.
  • a contact plug made of W / TiN / Ti or the like is embedded in the formed contact hole to form a contact plug.
  • the gate electrode 9 is a PFET according to the fourth embodiment, in which the first contact hole 5a is formed in the polysilicon film 5. And a semiconductor device having the fuse element according to the fifth embodiment can be formed at the same time.
  • the semiconductor device according to the sixth embodiment is a PFET, and includes a gate electrode 9B formed on a semiconductor substrate 1 made of, for example, silicon.
  • the gate electrode 9B is provided on the semiconductor region defined by the element isolation 2 formed on the semiconductor substrate 1, and includes a gate insulating film 3 including a high-k film, a TiN film 4 and a polysilicon film 5, and A Ni silicide film 18 is formed on the upper and side portions of the polysilicon film 5.
  • the Ni silicide film 18 formed on the side of the polysilicon film 5 in the gate electrode 9B is in direct contact with the TiN film 4 below the polysilicon film 5. is there.
  • the Ni silicide film 18 for forming the polymetal gate and the TiN film 4 for forming the metal gate are in direct contact with each other via the Ni silicide film 18 formed on the side of the polysilicon film 5. Since it is not affected by the interface resistance between the polysilicon film 5 and the TiN film 4, the PFET can be operated at high speed.
  • element isolation 2 is selectively formed on a semiconductor substrate 1 made of silicon.
  • threshold-control ion implantation Vt implantation
  • the semiconductor region partitioned by element isolation 2 in the semiconductor substrate 1 to activate the semiconductor region to be an active region.
  • the surface oxide film on the semiconductor substrate 1 is removed.
  • a thermal oxide film having a thickness of 1.5 nm is formed on the semiconductor substrate 1 as the gate insulating film 3, and an HfSiO film having a thickness of 3.0 nm is deposited thereon by a CVD method.
  • a high dielectric constant insulating film made of HfSiON / SiO 2 is formed by performing surface nitriding treatment.
  • the gate insulating film 3 is not limited to a high dielectric constant insulating film, and may be a SiO 2 film or a SiON film.
  • a TiN film 4 which is a gate metal film having a thickness of 10 nm is deposited on the gate insulating film 3 by, for example, a CVD method.
  • a non-doped polycrystal having a thickness of 80 nm is deposited on the TiN film 4.
  • a silicon film 5 is deposited.
  • the polysilicon film 5 and the TiN film 4 are patterned by lithography and dry etching.
  • the gate electrode 9B is obtained by cleaning to remove the resist mask.
  • the gate insulating film 3 is not removed during cleaning, but is left on the semiconductor substrate 1.
  • LDD Lightly Doped Drain
  • a Ni film 17 having a thickness of 5 nm is deposited on the entire surface including the gate electrode 9B on the gate insulating film 3 by sputtering or the like.
  • a first heat treatment is performed at a temperature of 300 ° C. for 30 seconds to cause the Ni film 17 to undergo a silicidation reaction with the exposed portion of the polysilicon film 5, thereby forming Ni.
  • a Ni silicide (Ni 2 Si) film 18 is selectively formed from the film 17. That is, since the gate insulating film 3 is formed on the semiconductor substrate 1, the Ni silicide film 18 is not formed on the semiconductor substrate 1, and Ni is formed only on the upper surface and the side surface of the gate electrode 9B from which the polysilicon film 5 is exposed. A silicide film 18 is formed. Subsequently, the unreacted Ni film 17 is removed by washing with a hydrogen peroxide aqueous solution (SPM).
  • SPM hydrogen peroxide aqueous solution
  • the gate insulating film 3 on the side of the gate electrode 9B is removed using an aqueous solution such as hydrogen fluoride (HF). Thereafter, a second heat treatment is further performed at a temperature of 450 ° C. for about 30 seconds to change the composition of the Ni silicide film 18 to NiSi. Note that it is not always necessary to convert the Ni 2 Si film to the NiSi film.
  • the metal silicide is Ni silicide, the present invention is not limited to this, and other metal silicides such as Co silicide or Ti silicide may be used.
  • the Ni film 17 is a single-layer film, but a TiN film may be deposited on the Ni film 17 as a barrier film.
  • the Ni 2 Si film is formed.
  • the NiSi film may be formed from the beginning by increasing the heat treatment temperature, and further, Ni 3 Si 4 or NiSi 2 or the like may be formed. Also good.
  • the Ni film 17 may be a partial reaction or a total reaction.
  • the sixth embodiment is also characterized in that the width of the gate electrode 9B in the gate length direction is increased by the Ni silicide film 18.
  • the gate electrode 9B and the Ni silicide film 18 are used as a mask.
  • An extension (Ext) injection is performed. That is, the Ni silicide film 18 formed on the side of the gate electrode 9B on the gate length direction side serves as an offset sidewall.
  • the Ext implant is formed farther from the side surface of the gate electrode 9B than the LDD implant of the I / O transistor.
  • sidewalls 10 made of SiN or the like are formed on each side surface of the gate electrode B9.
  • source / drain (S / D) implantation is performed on the active region of the semiconductor substrate 1 using the formed sidewall 10 and the gate electrode 9B as a mask.
  • impurities are also implanted into the polysilicon film 5 constituting the gate electrode 9.
  • heat treatment is performed to activate the implanted impurities.
  • a nickel (Ni) film is deposited on the entire surface of the semiconductor substrate 1 by a sputtering method or a vacuum evaporation method, and the deposited Ni film is subjected to a heat treatment so as to be formed on the polysilicon film 5 and the active region.
  • Ni silicide film 18 By forming the Ni silicide film 18 in a self-aligned manner, the transistor structure shown in FIG. 16 is obtained.
  • an interlayer insulating film is deposited on the semiconductor substrate 1 so as to cover the gate electrode 9B.
  • a contact hole exposing the Ni silicide film 18 is formed above the gate electrode 9B in the interlayer insulating film.
  • a contact plug made of W / TiN / Ti or the like is embedded in the formed contact hole to form a contact plug.
  • the upper Ni silicide film 18 and the lower TiN film 4 are in direct contact with each other on the side of the polysilicon film 5, thereby causing the Ni silicide film 18 and the TiN film 4 to be in contact with each other.
  • the polysilicon film 5 is not interposed between the two. As a result, the influence of the interface resistance between the polysilicon film 5 and the TiN film 4 is eliminated, so that the delay time of the PFET can be shortened.
  • Ni silicide film 18 formed on both sides of the polysilicon film 5 can be used as an offset sidewall, that is, as an implantation mask.
  • the first metal film in the lowermost layer and the second metal film on the silicon film are in direct contact with each other. Therefore, the device can be operated at high speed.
  • it is useful for a semiconductor device having a gate electrode in which a metal and polysilicon are laminated, and a fuse. It can also be applied to devices.

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Abstract

La présente invention concerne un procédé pour la fabrication de dispositif à semi-conducteurs, selon lequel un film isolant de grille (3) est formé sur un substrat semi-conducteur (1), ensuite un film de TiN (ç) et un film de silicium polycristallin (5) sont formés successivement sur le film isolant de grille (3), ensuite un orifice de contact (5a) est formé dans le film de silicium polycristallin (5) de sorte que le film de TiN (4) soit exposé depuis l'orifice de contact (5a), et ensuite un film métallique (7) est formé sur au moins la surface inférieure et la surface de paroi du premier orifice de contact (5a) dans le film de silicium polycristallin (5).
PCT/JP2010/003443 2009-09-28 2010-05-21 Procédé pour la fabrication de dispositif à semi-conducteurs, dispositif à semi-conducteurs fabriqué selon le procédé WO2011036828A1 (fr)

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JP2009222354A JP2011071402A (ja) 2009-09-28 2009-09-28 半導体装置の製造方法及びそれを用いた半導体装置

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Publication number Priority date Publication date Assignee Title
JP2006237372A (ja) * 2005-02-25 2006-09-07 Toshiba Corp 半導体装置
JP2009302320A (ja) * 2008-06-13 2009-12-24 Renesas Technology Corp 半導体装置およびその製造方法
WO2009157113A1 (fr) * 2008-06-24 2009-12-30 パナソニック株式会社 Dispositif semi-conducteur et son procédé de fabrication

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006237372A (ja) * 2005-02-25 2006-09-07 Toshiba Corp 半導体装置
JP2009302320A (ja) * 2008-06-13 2009-12-24 Renesas Technology Corp 半導体装置およびその製造方法
WO2009157113A1 (fr) * 2008-06-24 2009-12-30 パナソニック株式会社 Dispositif semi-conducteur et son procédé de fabrication

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