Classifications

• • G—PHYSICS
  • G10—MUSICAL INSTRUMENTS; ACOUSTICS
  • G10K—SOUND-PRODUCING DEVICES; METHODS OR DEVICES FOR PROTECTING AGAINST, OR FOR DAMPING, NOISE OR OTHER ACOUSTIC WAVES IN GENERAL; ACOUSTICS NOT OTHERWISE PROVIDED FOR
  • G10K11/00—Methods or devices for transmitting, conducting or directing sound in general; Methods or devices for protecting against, or for damping, noise or other acoustic waves in general
  • G10K11/18—Methods or devices for transmitting, conducting or directing sound
  • G10K11/26—Sound-focusing or directing, e.g. scanning
  • G10K11/34—Sound-focusing or directing, e.g. scanning using electrical steering of transducer arrays, e.g. beam steering
  • G10K11/341—Circuits therefor
  • G10K11/346—Circuits therefor using phase variation
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
  • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
  • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
  • G01S7/52017—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00 particularly adapted to short-range imaging
  • G01S7/52019—Details of transmitters
  • G01S7/5202—Details of transmitters for pulse systems

Definitions

• the present invention relates to transmitter circuitry for an ultrasound system, and, in particular, to circuitry for providing sub-beam formed transmit signals for an ultrasound system.
• a conventional ultrasound system includes a processor/controller 10 and analog front end (AFE) 20, as well as a user interface (not shown), such as a video display and computer keyboard and mouse.
• AFE analog front end
• a user interface such as a video display and computer keyboard and mouse.
• a digital beam former 12 which provide multiple digital transmit data signals 13 defining the transmitted beam profile, and receives, in return, multiple digital receive data signals 33 representing the received energy profile. Any desired beam forming is performed within the beam former circuitry 12.
• the transmission path of the AFE 20 includes multiple channels of digital-to-analog conversion (DAC) circuitry 22 and multiple transducer amplifier driver circuits 24.
• the transmit data signals 13 are converted to corresponding analog signals 23 for driving the driver circuits 24.
• Each of the resulting driver output signals 25 drives a respective transducer within the transducer array 28, and is conveyed via a transmit/receive switch 26, in accordance with well- known principles.
• reflected ultrasound energy received by the transducer array 28 is converted to corresponding analog electrical signals 27 which are conveyed via the transmit/receive switch 26 to respective time variable gain amplifier (TVGA) circuits 30.
• the resulting amplified signals 31 are converted by multiple channels of analog-to- digital conversion (ADC) circuitry 32 to produce the receive data signals 33.
• ADC analog-to- digital conversion
• Such ultrasound imaging systems operate in this manner to provide beam forming necessary for the desired image resolution and quality.
• the beam forming functions are typically implemented in the digital domain to achieve the desired flexibility and
• Multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system is provided in which sub-beam signals are formed by delaying sub-beam pulse pattern data in accordance with sub-beam pulse delay data and multiple clock signals.
• multi-channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system includes: pulse control circuitry to provide a plurality of sub-beam pulse control signals including a plurality of sub-beam pulse pattern data, a plurality of sub-beam pulse delay data and a plurality of clock signals; and
• signal pulse generating circuitry coupled to the pulse control circuitry and responsive to the pluralities of sub-beam pulse pattern data, sub-beam pulse delay data and clock signals by providing a plurality of serial sub-beam signal pulses, wherein one or more respective ones of the plurality of sub-beam serial signal pulses correspond to at least a portion of the plurality of sub- beam pulse pattern data and are time delayed in relation to the pluralities of sub-beam pulse delay data and clock signals.
• multichannel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system includes:
• clock selection circuitry responsive to a first portion of a plurality of sub-beam pulse delay data and a plurality of clock signals by providing a selected one of the plurality of clock signals
• delay circuitry coupled to the clock selection circuitry and responsive to a second portion of the plurality of sub-beam pulse delay data and the selected one of the plurality of clock signals by providing a delayed clock signal corresponding to and temporally delayed in relation to the selected one of the plurality of clock signals;
• data storage circuitry coupled to the delay circuitry and responsive to a plurality of sub- beam pulse pattern data and the delayed clock signal by storing the plurality of sub-beam pulse pattern data and retrieving respective portions of the stored plurality of sub-beam pulse pattern data in accordance with the delayed clock signal.
• multichannel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system includes:
• pulse controller means for providing a plurality of sub-beam pulse control signals including a plurality of sub-beam pulse pattern data, a plurality of sub-beam pulse delay data and a plurality of clock signals;
• signal pulse generator means for receiving the pluralities of sub-beam pulse pattern data, sub-beam pulse delay data and clock signals and in response thereto providing a plurality of serial sub-beam signal pulses, wherein one or more respective ones of the plurality of sub-beam serial signal pulses correspond to at least a portion of the plurality of sub-beam pulse pattern data and are time delayed in relation to the pluralities of sub-beam pulse delay data and clock signals.
• multi- channel pulser driver circuitry for a sub-beam forming transmitter of an ultrasound system includes:
• clock selector means for receiving a first portion of a plurality of sub-beam pulse delay data and in response thereto selecting among a plurality of clock signals to provide a selected one of the plurality of clock signals;
• delay means for receiving a second portion of the plurality of sub-beam pulse delay data and in response thereto delaying the selected one of the plurality of clock signals to provide a delayed clock signal corresponding to and temporally delayed in relation to the selected one of the plurality of clock signals;
• Figure 1 is a functional block diagram of the transmit and receive channels of a conventional beam forming ultrasound system.
• Figure 2 is a functional block diagram of transmit and receive channels of an ultrasound system implementing sub-beam forming in accordance with one or more embodiments of the presently claimed invention.
• Figure 3 is a functional block diagram of eight channels of an ultrasound system having a sub-beam forming transmitter in accordance with one or more embodiments of the presently claimed invention.
• FIG. 4 is a functional block diagram of a driver circuit for a signal pulser for driving an ultrasound transducer in accordance with one or more embodiments of the presently claimed invention.
• Figure 5 is a functional block diagram of an exemplary embodiment of one of the pulse driver channels of the circuitry of Figure 4.
• signal may refer to one or more currents, one or more voltages, or a data signal.
• any part of such circuitry may alternatively be implemented using one or more appropriately programmed processors, depending upon the signal frequencies or data rates to be processed.
• the functional blocks are not necessarily indicative of the division between hardware circuitry.
• one or more of the functional blocks e.g., processors, memories, etc.
• the functional blocks may be implemented in a single piece of hardware (e.g., a general purpose signal processor, random access memory, hard disk drive, etc.).
• any programs described may be standalone programs, may be incorporated as subroutines in an operating system, may be functions in an installed software package, etc.
• an ultrasound system employing sub-beam forming in accordance with one or more embodiments of the presently claimed invention simplifies the signal interface between the global digital beam former circuitry of the processor/controller 100 and the AFE 200.
• the global digital beam former 102 divides the total number N of channels into many smaller groups of n channels, or "sub-beams", which provide multiple sub-beams of transmit data signals 103 and receive multiple sub-beams of receive data signals 215.
• these N/n data signals 103 are used to provide N sub-beam signals 203 by N/n sub-beam former circuits 202a.
• the sub-beam signals 203 serve as analog drive signals for the driver circuits 206, which provide the drive signals 207 for the transducer array.
• the receive signals 209 from the transducer array 210 are amplified by time variable gain amplifiers 210, and the resulting amplified signals 211 are converted by ADC circuits 212 to produce corresponding digital signals 213.
• These digital signals 213 are processed by sub-beam forming receiver circuits 214 (the subject matter of which is disclosed and one or more embodiments of which are claimed in a co-pending patent application) to provide the N/n receive data signals 215.
• Such sub-beam forming in accordance with one or more embodiments of the presently claimed invention reduces overall system complexity and power consumption. For example, whereas conventional beam forming is performed in the digital domain, e.g., using a field programmable gate array (FPGA), e.g., as part of the global digital beam former 102, with a large number of interpolation computations consuming significant power, sub-beam forming in accordance with one or more embodiments of the presently claimed invention is performed in analog and mixed signal domains to achieve high accuracy while consuming less power.
• FPGA field programmable gate array
• each sub-beam former circuit 202a in the transmit signal path of the AFE 200 receives transmit beam form control signals 103a, 103b, including sub-beam forming profile data, global beam offset data, calibration compensation data, sparse selection data and transmit initiation, or "fire up,” control data, as well as a clock signal 103c.
• the clock signal 103c drives a phase locked loop (PLL) circuit 222, which provides various clock signals having different frequencies and phases, as needed.
• PLL phase locked loop
• the sub-beam former circuit 202a receives beam forming requirements as defined by the sub-beam forming profile data signal Btx 103a, and converts them to multiple waveforms t ⁇ , tl, ... , t7 203a with programmable signal amplitudes and time delays. For example, a waveform with a signal duration of 200 ns can be pre-stored in the sub-beam former circuit 202a, and the sub-beam forming profile data specify that the waveforms be successively delayed by 1 ns and reduced in amplitude by one percent. As a result, following assertion of the fire up signal Bst 103b, the sub-beam former circuit 202a will provide the eight signals 203a such that
• tl(n) 0.99*t0(n-lns)
• t2(n) 0.98*t0(n-2ns)
• ..., t7(n) 0.93*t0(n-7ns).
• modifications to the signal amplitudes can be done in the driver circuits 206a, e.g., in accordance with programmable positive 217p and negative 217n power supply voltages (discussed in more detail below).
• the sub-beam formed signals 203a drive the driver circuits 206a, which provide the drive signals 207a for their respective transducers (as discussed above).
• the sub- beam former circuitry 202a provides one or more control signals 217c to power management circuitry 216 for the drive circuits 206a.
• the power management circuitry 216 controls positive 217p and negative 217n power supply voltages for the driver circuits 206a.
• the driver circuits 206a use class G amplifiers for which their power supply voltages 217p, 217n are controlled by the power management circuitry 216, thereby providing amplitude control for the transducer drive signals 207a.
• the driver circuits 206a can be implemented in the form of simple pulse generators, multi-level pulse generators, or other classes of amplifiers (e.g., class A/B).
• the sub-beam former 202a With the sub-beam former 202a operating at sufficiently high frequency, it can be operated to provide multiple pulses to implement a pulse width modulation (PWM) function to generate arbitrary waveforms, or code excited pulses to provide more energy to the ultrasound target.
• PWM pulse width modulation
• Calibration can be provided within the sub-beam former 202a to improve control efficiency and allow for signal losses through the signal paths to the transducers.
• Such calibration can include calibration for time delays and amplitude variations. For example, operating differences will always exist to some degree among the various transducers, driver amplifiers and other circuit elements (both active and passive).
• the calibration process (e.g., as part of manufacturing test) can include capturing these differences and converting them to offset data for storage within the sub-beam former 202a, thereby allowing adjustments to be made to the beam profile based on these offset data to provide more accurate beam forming performance.
• sparse beam forming can be provided by driving subsets of transducers, such as even or odd or individually selected transducers.
• the amplitudes for selected ones of the various waveforms produced can be defined as zero (or some other predetermined low value).
• the driver circuit 206aa can be implemented using two-level drivers or pulse generators (pulsers), substantially as shown.
• Firing control circuitry 242 in accordance with a transmit enable signal 103c, provides a start control signal 243a to provide pulse signals through eight pairs of shift register channels 250, and a load control signal 243b for a finite state machine (FSM) 248 which provides control and converts incoming data into the proper format.
• Serial interface circuitry 244 receives pulse and control data and a corresponding clock signal 103d, and converts the serial data to parallel data 245 to be loaded into the FSM 248.
• the FSM 248 provides pulse pattern data 249a (e.g., 128 bits) and delay profile data 249b (e.g., 17 bits) for the data channels 250, and a control signal 249c for a PLL circuit 246.
• the PLL circuit 246 receives reference and bias signals 103e, and generates a multiphase clock signal 247 at the over sampling frequency fc (e.g., 160 MHz with eight phases in an exemplary embodiment).
• fc the over sampling frequency
• the data channels 250 receive the pulse pattern 249a and delay profile 249b data, and are controlled by the fire control signal 243a and selected phases of the multi -phase clock signal 247 (discussed in more detail below).
• Each data channel 250 provides two output bits P (PO, Pl, P2, ... , P7), N (NO, Nl , N2, ... , N7) for the pulser driver circuit driving its respective transducer. These two bits allow four levels of pulser control, three of which are used when driving bipolar pulsers.
• Each pair of signals Pn, Nn can be delayed with equal timing; however, the eight signal pairs P0/N0, Pl/Nl, ..., P7/N7 are generally delayed by different timing intervals in accordance with beam forming requirements as discussed above (e.g., signal pair Pl/Nl delayed by 1.5 ns relative to signal pair P0/N0).
• each data channel 250 provides up to 64 pulses for each control bit P, N, thereby allowing for PWM or code excited multi-pulse signals.
• the serial interface 244 allows different delay profile data to be received and loaded into the FSM 248 for different beam patterns.
• the transmit enable signal 103c allows all data channels 250 to be fired
• Calibration can be provided by storing calibration data within the FSM 248 or within dedicated memory (not shown).
• an exemplary embodiment 250aa of one of the data channels 250 includes a multiplexer 262, shift registers 264p, 264n, a counter 266, and logic circuitry 268, 270, 272, all interconnected substantially as shown.
• the pulse pattern data 249a are split between and loaded into the shift registers 264p, 264n.
• the delay profile data 249b provides control bits to the multiplexer 262 for selecting one of the phases of the multi-phase clock signal 247 (e.g., three bits for selecting among eight phases), and bits (e.g., 14) for loading the counter 266. Accordingly, the counter 266 controls the coarse delay, while the multiphase clock signal 247 controls the fine delay.
• the selected clock signal phase 263 drives the counter 266 as well as the programmable divider 265.
• the divider 265 scales the clock 263 to a lower frequency clock 265a controlled by a preloaded scaling factor for the programmable pulse firing frequency.
• the counter 266 output 267 is kept at a logic "0" before each firing, controlled by a "fire” control signal 243a. Following assertion of the "fire" control signal 243a, the counter 266 starts counting. After the coarse delay interval as determined by the loaded counter data has passed, the asserted terminal count output 267 enables the divided clock 265a to pass via the AND gate 272 as the clock signal 273 for the shift registers 264p, 264n.
• the input AND gate 268 and feedback inverter 270 disable the counter clock 269, keeping the counter 266 output terminal asserted until the "fire" control signal 243a is de- asserted). Accordingly, at the end of the delay interval defined by the coarse and fine delays, the control bits 25 lap, 25 Ian for the pulser are clocked out by the enabled clock signal 273 in accordance with the bit patterns loaded into the shift registers 264p, 264n.
• Another counter 274 counts fired pulses. When it reaches the predetermined length, its terminal count output 274a is asserted, thereby disabling the clock signal 273 through the inverter 275 and the AND gate 272.

Landscapes

• Engineering & Computer Science (AREA)
• Physics & Mathematics (AREA)
• Acoustics & Sound (AREA)
• Multimedia (AREA)
• Computer Networks & Wireless Communication (AREA)
• General Physics & Mathematics (AREA)
• Radar, Positioning & Navigation (AREA)
• Remote Sensing (AREA)
• Ultra Sonic Daignosis Equipment (AREA)
• Measurement Of Velocity Or Position Using Acoustic Or Ultrasonic Waves (AREA)

Priority Applications (3)

Applications Claiming Priority (2)

Publications (2)

Family

ID=43450187

Family Applications (1)

Country Status (6)

Cited By (1)

Families Citing this family (12)

Family Cites Families (22)

• 2009
  • 2009-07-15 US US12/503,438 patent/US8171333B2/en active Active
• 2010
  • 2010-07-15 EP EP10800516.6A patent/EP2453802A4/en not_active Withdrawn
  • 2010-07-15 WO PCT/US2010/042066 patent/WO2011008914A2/en active Application Filing
  • 2010-07-15 JP JP2012522880A patent/JP5714010B2/ja active Active
  • 2010-07-15 TW TW099123245A patent/TWI435711B/zh active
  • 2010-07-15 CN CN201080040565.2A patent/CN102481139B/zh active Active

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events