Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
  • H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
  • H04L25/03828—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties
  • H04L25/03866—Arrangements for spectral shaping; Arrangements for providing signals with specified spectral properties using scrambling

Definitions

• the invention relates to a frame synchronization scrambling code technology and a descrambling code technology in a communication protocol, in particular to a scrambling device for parallel frame synchronization in a synchronous digital transmission system (SDH)/fiber synchronous network (SONET) and its descrambling Code device.
• SDH synchronous digital transmission system
• SONET fiber synchronous network
• the receiving end uses the 1/0 change on the line to recover the receiving clock of the line through the phase-locked loop, realizes bit synchronization, and transmits the synchronization information through the frame flag, thereby realizing frame synchronization and thus byte synchronization. Only when bit synchronization and frame synchronization are implemented, the receiving end can correctly extract valid user data.
• the user information that needs to be transmitted during the communication process is ever-changing. If the user data contains a long sequence of 0 or even 1 connection, the receiving phase-locked loop may lose lock and enter the hold state, and the clock quality will be degraded, resulting in data recovery. There is a problem of error or even error. If the user data contains the same information as the frame flag, the receiving frame synchronization state machine may enter an error state or repeatedly oscillate during initialization, and there is a problem that correct frame synchronization cannot be performed.
• Scrambling codes are techniques commonly used in digital communications. The purpose is to make the data transmitted on the digital lines random, so that the above problems can be effectively avoided.
• the randomized line data can ensure that there is enough 1/0 change on the line to recover the clock, and try to avoid the frame flag in the user information field.
• the scrambling code implementation performs a linear operation on the pseudo-random sequence and the information to be transmitted, and generates the scrambled data, that is, the pseudo-random sequence generator is used to generate the randomization effect of the output line data; the receiving end uses the same pseudo-random sequence. In the opposite operation, the original data, that is, the process of descrambling, can be recovered.
• the scrambling code can be implemented in software or hardware.
• the pseudo-random sequence is usually composed of a pseudo-random code (M) sequence.
• M pseudo-random code
• the pseudo-random sequence refers to a string of numbers generated by an arithmetic operation according to a certain calculation function, and the number of strings is a string of numbers close to a sequence of random numbers.
• a binary sequence is typically generated from a pseudo-random sequence for scrambling/descrambling calculations.
• the frame synchronization scrambling code at the transmitting end, XORs the transmitted data information with an M sequence to ensure that the transmitted sequences 1 and 0 after the scrambling are randomly changed.
• the same M sequence is used to inversely calculate the received information stream to recover the original information stream.
• Frame Synchronization Scrambling Code The state information of the M sequence needs to be transmitted.
• the transmission domain SDH system uses A1A2 as a frame synchronization pattern, also called a framing byte, to achieve frame synchronization between the transmitting and receiving parties.
• the synchronization signal is also used as the synchronization information of the self-synchronizing scrambling/descrambling circuit.
• the scrambling circuit and the descrambling circuit are both set to 1, and the initial value is returned to the initial state of all ones, and
• the scrambling code is started at the same position, and the scrambling code is started after the first line segment overhead to ensure synchronization between the transmitting end and the receiving end.
• the first is to express the scrambling code formula in a serial circuit manner, and then decompose the parallel bit stream into superposition of each single-bit serial scrambling code, and use the matrix method or directly perform iterative calculation.
• To obtain the circuit structure of parallel scrambling/descrambling For different parallel input bit widths, separate calculations are needed to obtain the corresponding parallel scrambling/descrambling circuit structure. After the parallel bit width becomes larger, such as 256 bits or more, cumbersome iterative derivation and combined logic are required.
• the link which results in a large delay of the circuit, may not meet the required processing frequency of the parallel signal, and is not suitable for high-speed circuits of 40G or more.
• the parallel bit stream is a kind of parallel data, and the parallel data is distinguished from the serial data, so-called serial data refers to: data processed according to a single bit; so-called parallel data refers to: data processed according to multiple bits.
• Serial data is transmitted on the communication line, but in the processing of the chip, successive n bits are intercepted in the serial data for processing, that is, the serial data is converted into n-bit parallel data.
• the existing serial/parallel conversion refers to the meaning here.
• the disadvantages of using the existing parallel scrambling/descrambling circuit are: On the one hand, for different parallel data input bit widths, it is necessary to separately design corresponding parallel scrambling/descrambling circuit structures, universally applicable. The range is small, it is not universal, which is not conducive to popularization. On the other hand, the M sequence that is not preset is required to perform real-time operation with parallel data. The input bit width of parallel data is larger, and the iteration used for real-time operation is The more complicated, the computational complexity of this iterative real-time operation is 4 ⁇ , resulting in slow operation, resulting in low efficiency and low processing frequency of the parallel scrambling/descrambling circuit. Summary of the invention
• the main object of the present invention is to provide a scrambling device for parallel frame synchronization and a descrambling device thereof, which can respectively implement scrambling code and decoding, and are not only suitable for parallel data of various input bit widths, and have versatility. , using the promotion; and reducing the computational complexity, improving the working efficiency and processing frequency of the scrambling device and its descrambling device.
• a scrambling device for parallel frame synchronization comprising: a storage unit, a control unit, and an exclusive OR unit;
• control unit configured to sequentially read a pseudo-random sequence in the storage unit, and obtain content corresponding to the parallel data in the pseudo-random sequence
• a storage unit configured to store the pseudo random sequence preset, and the pseudo random sequence And inputting an exclusive OR unit corresponding to the parallel data;
• an exclusive OR unit configured to perform an exclusive OR process on the parallel data sequentially input from the pseudo random sequence acquired from the storage unit, and output the scrambled data.
• the content corresponding to the parallel data in the pseudo-random sequence is specifically: the Q-bit content corresponding to the parallel data in the pseudo-random sequence; the pseudo-random in a state where the bit width of the parallel data is Q
• the length of the sequence is TXQ, which is composed of a pseudo-random code M sequence of Q bits; wherein T is a repeated cycle period of the M sequence.
• the control unit is further configured to cycle according to the T under the control of the frame synchronization signal, and sequentially acquire the M sequence of the Q bits corresponding to the parallel data in the pseudo random sequence.
• the XOR unit is further configured to perform XOR processing on the parallel data sequentially input with the M sequence of the Q bit corresponding to the parallel data in the pseudo random sequence until the completion of the TXQ The traversal of the M sequence of bits.
• the control unit is specifically an address generator; the storage unit is specifically an M sequence generator.
• a descrambling code device for parallel frame synchronization comprising: a storage unit, a control unit, and an exclusive OR unit;
• control unit configured to sequentially read the pseudo random sequence in the storage unit, and obtain content corresponding to the scrambled data in the pseudo random sequence
• a storage unit configured to store the pseudo-random sequence set in advance, and input content corresponding to the scrambled data in the pseudo-random sequence into an exclusive OR unit;
• an XOR unit configured to perform XOR processing on the scrambled data sequentially input from the content corresponding to the scrambled data in the pseudo random sequence acquired from the storage unit, and output the descrambled Obtained parallel data.
• the content corresponding to the scrambled data in the pseudo-random sequence is specifically: the pseudo-random sequence corresponds to the scrambled data in a state where the bit width of the data after the scrambling code is Q. Q bit content;
• the pseudo random sequence has a length T x Q and is composed of M sequences of Q bits; wherein T is a repeated cycle period of the M sequence.
• the control unit is further configured to, according to the T, perform a loop according to the T synchronization, and sequentially acquire the M sequence of the Q bit corresponding to the scrambled data in the pseudo random sequence.
• the XOR unit is further configured to sequentially perform the X-sequence data of the Q-bit corresponding to the scrambled data in the pseudo-random sequence. Processing until the traversal of the M sequence of T x Q bits is completed.
• the control unit is specifically an address generator; the storage unit is specifically an M sequence generator.
• the invention realizes a scrambling device for parallel frame synchronization and a descrambling device thereof, which can respectively implement scrambling code and decoding.
• the device includes a control unit for using a pseudo random sequence in the storage unit. Performing sequential reading, and acquiring content corresponding to the parallel data in the pseudo-random sequence; the storage unit is configured to store the pre-set pseudo-random sequence, and input the content corresponding to the parallel data in the pseudo-random sequence into the exclusive OR unit; The unit is configured to sequentially process the parallel data sequentially input, and sequentially perform XOR processing on the content corresponding to the parallel data in the pseudo random sequence acquired from the storage unit, and then output the scrambled data.
• the XOR unit for performing XOR processing on the scrambled number of the sequential input, and outputting Parallel data obtained after descrambling.
• the scrambling code and decoding of the parallel frame synchronization can be respectively realized, and the arbitrary bit width is realized.
• the scrambling/descrambling of parallel frame synchronization is not only suitable for parallel data of various bit widths, but also has universality and utilization, and reduces computational complexity, and improves the work of the scrambling device and its descrambling device. Efficiency and processing frequency.
• the combination logic is less, the implementation is simple, and the processing delay is less, which is more suitable for parallel scrambling and descrambling codes with large bit width and high speed.
• FIG. 1 is a schematic structural diagram of a scrambling device/descrambling code device for parallel frame synchronization according to the present invention
• FIG. 2 is a schematic structural diagram of an embodiment of a scrambling device/descrambling code device for parallel frame synchronization according to the present invention
• Fig. 3 is a block diagram showing the configuration of an embodiment of a 256-bit parallel scrambling device/descrambling code device for an STM-256 signal.
• DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic idea of the present invention is: When used as a scrambling device, after the parallel data is input into the scrambling device, the control unit reads the content corresponding to the parallel data in the pseudo-random sequence from the storage unit; The data in the unit is different or different, and the scrambled data is obtained.
• the input is the scrambled data
• the control unit reads the content corresponding to the scrambled data in the pseudo-random sequence from the storage unit, and performs XOR with the scrambled data.
• the XOR processing is performed in the unit to obtain the descrambled parallel data code stream.
• the present invention When used as a scrambling device or a descrambling device, it is composed of three functional units, an exclusive OR unit, a control unit, and a storage unit.
• the pre-set pseudo-random sequence stored in the storage unit is the same whether used as a scrambling device or a descrambling device; control at the control unit Under the system, the data sequentially read from the storage unit is the same, that is, when the XOR processing is performed in the XOR unit, a part of the contents of the pseudo random sequence used is the same.
• the descrambling code device of the present invention can perform descrambling processing on the scrambled data processed by the scrambled device, thereby recovering the parallel data code of the original input scrambling device after the descrambling code processing. flow. Since the present invention is used as a scrambling device or a descrambling device, it is composed of three functional units, an exclusive OR unit, a control unit, and a storage unit. Therefore, in order to describe the cartridge, the system architecture of the device is represented by FIG. The specific implementation of each unit when used as a different device is separately explained.
• a scrambling device for parallel frame synchronization includes: a storage unit, a control unit, and an exclusive OR unit.
• the control unit is configured to sequentially read the pseudo-random sequence in the storage unit, and obtain content corresponding to the parallel data in the pseudo-random sequence.
• the storage unit is configured to store a pre-set pseudo-random sequence, and input the content corresponding to the parallel data in the pseudo-random sequence into the exclusive OR unit.
• the XOR unit is configured to, after sequentially processing, the parallel data sequentially input, and the XOR data corresponding to the parallel data in the pseudo random sequence acquired from the storage unit, and output the scrambled data.
• the content corresponding to the parallel data in the pseudo-random sequence is specifically: Q-bit content corresponding to the parallel data in the pseudo-random sequence.
• the pseudo-random sequence has a length of T x Q and is composed of M sequences of Q bits; where T is a repeated cycle of the M sequence.
• the value of Q is related to the rate of serial data and the processing speed of the chip, for example, it can be 256 bits.
• the present invention saves the pre-calculated pseudo-random sequence in the storage unit in advance.
• the prior art pseudo-random sequence is not pre-calculated and stored, and is obtained by an instant operation. Therefore, the invention can reduce the computational complexity, so that the apparatus of the present invention processes the cartridge, has high processing efficiency, can be applied to a device having a larger bit width and a higher speed of parallel data; and does not limit the bit width of the parallel data.
• the characteristic equation of the M sequence is more versatile and can be adapted to a variety of communication protocols.
• the control unit is further configured to cycle according to T under the control of the frame synchronization signal, and sequentially acquire the M sequence of the Q bit corresponding to the parallel data in the pseudo random sequence.
• the XOR unit is further configured to perform XOR processing on the sequentially input parallel data in sequence with the M sequence of the Q bit corresponding to the parallel data in the pseudo random sequence until the traversal of the M sequence of the TXQ bit is completed, and the output is disturbed.
• the data after the code is further configured to perform XOR processing on the sequentially input parallel data in sequence with the M sequence of the Q bit corresponding to the parallel data in the pseudo random sequence until the traversal of the M sequence of the TXQ bit is completed, and the output is disturbed.
• control unit is specifically an address generator;
• storage unit is specifically an M sequence generator.
• a descrambling code device for parallel frame synchronization comprising: a storage unit, a control unit, and acquiring content corresponding to the scrambled data in the pseudo-random sequence.
• a storage unit configured to store a pre-set pseudo-random sequence, and input the content corresponding to the scrambled data in the pseudo-random sequence into the XOR unit.
• the XOR unit is configured to perform XOR processing on the scrambled data sequentially input and the content corresponding to the scrambled data in the pseudo random sequence acquired from the storage unit, and output the parallel data obtained after the descrambling. .
• the content corresponding to the parallel data in the pseudo random sequence is read from the storage unit, and the pseudo random sequence is read from the storage unit when used as the descrambling device.
• the content corresponding to the data after the code is the same, so that the descrambling device of the present invention can perform descrambling processing on the scrambled data processed by the scrambled device, thereby After the descrambling code is processed, the parallel data code stream of the original input scrambling device is restored.
• the pseudo-random sequence is followed by the scrambling code
• the corresponding content of the data is specifically: the Q-bit content corresponding to the scrambled data in the pseudo-random sequence.
• the pseudo random sequence has a length of T x Q and is composed of M sequences of Q bits; wherein T is a repeated cycle of the M sequence.
• control unit is further configured to cycle according to T under the control of the frame synchronization signal, and sequentially acquire the M sequence of the Q bit corresponding to the scrambled data in the pseudo random sequence.
• the XOR unit is further configured to perform XOR processing on the scrambled data sequentially input in sequence with the M sequence of the Q bit corresponding to the scrambled data in the pseudo random sequence until the completion of the T The traversal of the X-bit M sequence, outputting the parallel data obtained after descrambling.
• control unit is specifically an address generator;
• storage unit is specifically an M sequence generator.
• the address generator and the M sequence generator involved in the present invention as a scrambling device or a descrambling device are as shown in Fig. 2.
• the present invention includes the following:
• the principle of the technical solution of the present invention is as follows:
• the characteristic polynomial of the scrambling code is J 7 + X 6 + 1 , that is, a pseudo-random sequence of 2 7 -1 or 127-bit period is used.
• the essence of the frame synchronization scrambling code is that in the order of data bit transmission, each data bit is XORed with the M sequence generator output bits and then transmitted on the communication line.
• the descrambling circuit also XORs the scrambled data bits with the same M sequence generator output bits in a corresponding order to find the original data bit stream.
• the M-sequence linear shift register will be assigned an initial value, typically giving an all-one value.
• the M sequence has a repetition period of T, and each complete M sequence is M[0, T-1].
• R sequence with a length of T x Q and a content of Q M sequences combined, that is:
• R[0,TQ-1] ⁇ M[0,T-1] 0 , M[0,Tl] l5 M[0,T-1] 2 , M[0,T-1] 3 .... .
• M[0,T-1] Q ⁇
• the sequentially input Q-bit data bits are XORed with the corresponding Q-bit contents in the R sequence, that is, DR[0, Q-1], Di A R[Q , 2Q-l] , D 2 A R[2Q, 3Q-1] , ..., D T 1 A R[(T-1)Q, TQ-1] , all the contents of the R sequence are traversed once, A large scrambling cycle has been completed.
• the next scrambling process is to repeat the above process until the scrambling of the current frame is completed.
• the descrambling process and the scrambling process are handled in exactly the same way.
• the parallel frame synchronization scrambling device/descrambling code device designed by the present invention is realized based on the above theoretical principle. As shown in Fig. 1, it is composed of three units: a control unit, a storage unit, and an exclusive OR unit, as shown in Fig. 1.
• the control unit takes out a part of the content of the corresponding M sequence from the storage unit, and then differentiates in the XOR unit to obtain the scrambled data.
• the input is scrambled data
• the control unit extracts the same part of the M sequence from the storage unit and the scrambled data is XORed in the XOR unit to obtain descrambling.
• Parallel data stream The parallel frame synchronization scrambling device/descrambling code device of the present invention does not limit the bit width of the input parallel data and the characteristic equation of the M sequence, and for the higher bit width and longer scrambling code sequence, only the control unit and the storage unit are added. Capacity and complexity.
• the scrambling code and descrambling function can be realized at a lower rate, and is suitable for the SDH/SONET transmission system and other communication systems adopting the frame synchronization scrambling scheme.
• the control unit in FIG. 1 may be specifically an address generator, and the storage unit may be specifically an M-sequence generator, as shown in FIG. 2, where the parallel data bit width q, M is the highest order of the characteristic equation of r.
• the effective address line of the address generator output is r root, and the controlled address range is 1-2.
• the address of the control output is 1 address, and then according to the beat of the input clock, the address is incremented by one at each valid data until the highest address is 2 7 -1 , and then returns to the 1 address, in turn cycle.
• the M sequence generator is generally implemented by RAM or ROM, and the effective data space is q 2 r -1 bits.
• the M sequence is in the order of bits generated by the pseudo-random code, starting from the M1 bit to the M2 bit, and sequentially filling, a total of The M sequences of q lengths are filled.
• Each address output by the controller corresponds to a range of q bits, and the size of the 2-1 address space corresponds to q, corresponding to the complete q +1 sequence of 2-1 length.
• the M sequence generator extracts the valid M sequence content from the index address, and performs exclusive processing with the input parallel data/scrambled data to obtain valid scrambled data. / Parallel data recovered after descrambling.
• the system operates at a 155.52MHz clock frequency and implements scrambling with a 256-bit parallel width.
• the M sequencer consists of a ROM, since the characteristic polynomial of the SDH scrambling code is
• X 7 + X 6 + 1 uses a pseudo-random sequence of 2 7 -1, which is a 127-bit period, so its capacity is: (2 7 - 1 x 256 ) bits, 2 7 - 1 is the depth of the storage space; The width of the storage space, which contains 256 127-bit pseudo-random sequences.
• M represents the entire 127-bit pseudo-random sequence
• ml, m2, ... represent the content of the corresponding bit position of the pseudo-random sequence.
• the deserializer performs clock recovery, synchronous acquisition, serial/parallel conversion, and outputs parallel data with a word width of 256 bits and a synchronous clock (CLK).
• the deframer generates the first 256-bit word aligned frame sync indication signal and the 256-bit parallel data after frame synchronization in the STM-256 frame structure by detecting the A1A2 framing byte in the signal.
• the address generator calculates the row and column address in the SDH frame structure, and obtains the scrambled ROM table address based on the row and column address. When the frame synchronization indication occurs, the row address and the column address point to the initial position of the frame structure, and the column address is incremented by 1 under the driving of the synchronization indication.
• the column address points to the frame.
• the first ⁇ ll of the structure, and the row address is incremented by 1.
• the row address and the column address point to the beginning of the frame structure again.
• the ROM table address points to address 0, since 9 x N bytes of the 1st line of the STM-N segment overhead are unscrambled, when the row address is 0 and the column address is > 9
• the ROM table address starts to traverse the entire ROM periodically from the address ADDROxOO to ADDR0x7E, and simultaneously outputs the M-sequence content stored in the corresponding address ROM and the 256-bit parallel data to obtain the scrambled STM. -256 data frames, until the row address > 8 and the column address > 8639, the lookup table address is redirected to address 0. This completes the scrambling process of the entire frame, and the descrambling process is similar to the above scrambling code.

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• 2009
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