WO2010150668A1 - Capacitance type input device and production method thereof - Google Patents

Capacitance type input device and production method thereof Download PDF

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Publication number
WO2010150668A1
WO2010150668A1 PCT/JP2010/059926 JP2010059926W WO2010150668A1 WO 2010150668 A1 WO2010150668 A1 WO 2010150668A1 JP 2010059926 W JP2010059926 W JP 2010059926W WO 2010150668 A1 WO2010150668 A1 WO 2010150668A1
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WIPO (PCT)
Prior art keywords
film
transparent conductive
input device
conductive member
transparent
Prior art date
Application number
PCT/JP2010/059926
Other languages
French (fr)
Japanese (ja)
Inventor
浩幸 菅原
Original Assignee
ジオマテック株式会社
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Publication date
Application filed by ジオマテック株式会社 filed Critical ジオマテック株式会社
Priority to JP2011519751A priority Critical patent/JP5503651B2/en
Priority to KR1020117030738A priority patent/KR101464818B1/en
Priority to CN201080027537.7A priority patent/CN102804108B/en
Publication of WO2010150668A1 publication Critical patent/WO2010150668A1/en

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    • G06F3/01Input arrangements or combined input and output arrangements for interaction between user and computer
    • G06F3/03Arrangements for converting the position or the displacement of a member into a coded form
    • G06F3/041Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0443Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a single layer of sensing electrodes
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    • G06F3/04142Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means using force sensing means to determine a position the force sensing means being located peripherally, e.g. disposed at the corners or at the side of a touch sensing plate
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    • G06F3/044Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means
    • G06F3/0446Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means by capacitive means using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes
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    • G06F2203/04111Cross over in capacitive digitiser, i.e. details of structures for connecting electrodes of the sensing pattern where the connections cross each other, e.g. bridge structures comprising an insulating layer, or vias through substrate

Definitions

  • the present invention relates to a capacitance-type input device and a method for manufacturing the same, and more particularly to a capacitance-type input device that has high transparency and suppresses power consumption and a method for manufacturing the same.
  • the touch panel type input device detects an input operation position in the operation area when an input operation is performed on the operation area with a stylus pen or a finger, and outputs an input signal indicating the input operation position to the external processing device.
  • touch panel type input devices such as resistance film type, capacitance type, electromagnetic induction type, ultrasonic surface acoustic wave type, infrared scanning type, etc.
  • Resistive film type input devices that are relatively inexpensive are the mainstream.
  • the resistance film type input device has a problem that the operating temperature range is narrow and it is vulnerable to changes with time because of the structure in which the film is pressed and short-circuited in a two-layer structure of film and glass. Further, it has a problem that it is vulnerable to impact and has a short life. In addition, there are problems such as a decrease in accuracy associated with an increase in the area of the input device and inferior transparency due to the need for two metal thin films.
  • the capacitance type input device forms an electrolysis on the entire surface of the input device, and detects the position by changing the surface charge of the portion in contact with or close to the user's finger, so it is resistant to dust and water. It is durable and has high resolution. In addition, since the response speed is high and it reacts only to a conductor such as a finger, there is an advantage that there is no malfunction when another object (such as clothes) contacts.
  • Patent Documents 1 and 2 As such a capacitance-type input device, in Patent Documents 1 and 2, electrode patterns are extended in a direction intersecting each other on a single substrate to form a grid-like electrode pattern, and the user's finger There has been proposed a technique for detecting an input position by detecting that the capacitance between the electrodes changes when the electrode contacts or approaches.
  • a touch panel type input device is disposed on an image display device, and is operated by an operator viewing an image displayed on the image display device and touching the touch panel type input device. Therefore, since it is necessary to visually check the image displayed on the image display device from the operation surface side of the touch panel type input device, the touch panel type input device is required to have high transparency. Therefore, a material having excellent transparency has been used as a material for a substrate and an electrode pattern of a touch panel type input device.
  • Patent Document 2 also discloses an input device that is made of a transparent material (transparent conductive film).
  • the capacitance-type input device needs to constantly flow current, the power consumption greatly depends on the resistance value of the entire device. Therefore, when the transparent conductive film is patterned in the touch panel type input device, the transparent conductive film has a larger resistance value than that of the metal, so that there is a problem that the voltage for operating the input unit is increased and the power consumption is increased. .
  • the capacitance type input device increases the power consumption when the transparent conductive film is patterned as described above.
  • a metal thin film having a low resistance value has been used as a wiring pattern used for connection to an external device in order to reduce power consumption even slightly. Therefore, in the touch panel type input device that requires transparency, the electrode pattern and the conductive member of the intersection are made of a transparent conductive film, while the wiring pattern is made of a metal thin film, and the electrode pattern and the conductive part of the intersection are made.
  • the member and the wiring pattern are made of different materials. Therefore, there is a problem that a wiring pattern film forming process and an electrode pattern film forming process are separately required, and the manufacturing process tends to be complicated.
  • An object of the present invention is to provide a touch panel type input device having high transparency and low power consumption in a capacitance type input device. Another object of the present invention is to provide an inexpensive capacitive input device by making the capacitive input device with a simple configuration and a simplified manufacturing process.
  • the visibility of human vision with respect to an image viewed through an input device is expressed as transparency. That is, even if the light is blocked by what is invisible because it is fine and the amount of light transmission is slightly reduced, it is expressed as transparent when there is no effect on the image visibility.
  • the subject includes an input unit in which an input operation is performed, and an output unit for outputting a signal from the input unit, and the input unit and
  • the output unit is a capacitance-type input device provided on the same surface of a transparent substrate, and the output unit electrically connects the connection terminal that outputs the signal, the input unit, and the connection terminal.
  • the contact is formed continuously with the second transparent conductive film and disposed at a position intersecting with the conductive member.
  • the conductive member, the connection terminal, and the wiring pattern are formed of the same conductor film, and the conductor film is a single layer of a metal layer or a multilayer including at least one metal layer,
  • the conductive member is solved by being formed in a linear shape.
  • the conductive member that electrically connects the first transparent conductive film is constituted by a conductor film including a metal layer (metal thin film) having a resistance value smaller than that of the transparent conductive film.
  • a conductor film including a metal layer (metal thin film) having a resistance value smaller than that of the transparent conductive film.
  • the power consumption of the capacitive input device can be reduced.
  • all electrode patterns are formed using a transparent conductive film in order to ensure transparency in the operation region of the capacitive input device.
  • the resistance value of the transparent conductive film depends on the thickness. Even when the thickness is about several tens of nanometers or more, the transparent conductive film has a resistivity of about 1.5 ⁇ 10 ⁇ 4 ⁇ cm.
  • the metal layer is conductive by one layer or a multilayer including at least one metal layer. By configuring the body membrane, power consumption can be reduced.
  • the conductor film is a single layer of the metal layer, and the width of the conductive member in the second direction is 4 to 10 ⁇ m.
  • the conductor film is formed of only the metal layer, if the width of the conductive member is 4 to 10 ⁇ m, the conductive member cannot be visually recognized by human vision. Therefore, the operator does not visually recognize the conductive member, and the transparency of the operation area of the capacitive input device can be ensured.
  • the conductive film is only a metal layer, if the width of the conductive member is larger than 10 ⁇ m, the conductive member is slightly visible to the operator, but if it is smaller than 4 ⁇ m, the patterning accuracy by etching or the like is improved. Since it falls, it is not preferable.
  • the conductor film is composed of a plurality of layers in which metal layers and metal oxide layers are alternately stacked, and the metal oxide layer is formed on the viewer side in the conductor film. It is suitable if it is made.
  • a metal oxide layer on the operator's viewing side, it is possible to reduce the reflectance of the conductor film by utilizing light interference between the respective layers.
  • a fine shape such as a conductive member may be visible depending on the direction of reflected light even if it is not visually recognized by transmitted light, but this problem can be solved by reducing the reflectance. Then, when a plurality of metal layers and metal oxide layers are stacked, the reflectance can be further reduced.
  • the “viewing side” refers to the side that the operator visually recognizes in the capacitive input device.
  • the side (surface) in which the input part and the output part were formed on the transparent substrate it refers to the uppermost layer of the conductor film.
  • the side (back surface) where the input part and the output part are not formed it indicates the lowest layer of the conductor film.
  • the width of the conductive member in the second direction is 7 to 40 ⁇ m.
  • the width of the conductive member is preferably 7 to 40 ⁇ m.
  • the transparency is further improved, so that even when the width of the conductive member is increased, the conductive member is hardly visually recognized.
  • the width of the conductive member is larger than 40 ⁇ m, the conductive member is slightly visible but is not preferable.
  • it is smaller than 7 ⁇ m the patterning accuracy by etching or the like is lowered, which is not preferable.
  • the material of the metal layer is selected from silver, silver alloy, copper, copper alloy, MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound). Any of the above metals is preferred. Since these metal materials have small resistance values, static electricity with low power consumption can be obtained by making the conductive member, the connection terminal, and the wiring pattern into a single layer made of the above-mentioned metal thin film or a multiple layer containing the above-mentioned metal thin film. A capacitive input device can be obtained. Further, since the resistance value is small, the wiring pitch can be narrowed, and as a result, the frame area (output portion) where the wiring pattern is disposed can be narrowed.
  • the wiring pitch can be reduced, the wiring pattern can be increased with the same installation area, and the input signal can be detected with high positional accuracy.
  • the metal material is suitable for manufacturing the capacitive input device of the present invention because it can be easily processed by etching.
  • the material of the metal layer is selected from silver, silver alloy, copper, copper alloy, and MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound).
  • the metal oxide layer contains an indium composite oxide.
  • the insulating film may be disposed only at the intersection between the first electrode pattern and the second electrode pattern. According to this configuration, since the conductive member is formed on the transparent substrate, the insulation between the first electrode pattern and the second electrode pattern can be maintained only by forming the insulating film only at the intersection thereafter. . Therefore, when each part (each member) is laminated and formed, it can be formed more easily.
  • the conductive member is formed last. Is done. At this time, since the conductive member must electrically connect only the first transparent conductive film, all portions other than the portion where the first transparent conductive film and the conductive member are connected must be covered with an insulating film. There is. Therefore, according to this configuration, since the range in which the insulating film is provided is limited only to the intersection between the first electrode pattern and the second electrode pattern, protection is provided on the first electrode pattern and the second electrode pattern. Only the film is formed.
  • the configuration in FIG. 4 unlike the configuration in which the transparent conductive film is first formed on the transparent substrate (configuration in FIG. 4), the configuration in FIG. There is no need to provide a contact hole, and there is no need to perform fine patterning such as passing a conductive member through the contact hole. Therefore, a relatively simple configuration can be obtained, and as a result, the yield is improved when forming the input portion of the capacitive input device.
  • the subject includes an input unit where an input operation is performed, and an output unit for outputting a signal from the input unit, A method of manufacturing a capacitive input device in which the input unit and the output unit are provided on the same surface of a transparent substrate, wherein a transparent conductive film is formed on the entire surface of the transparent substrate.
  • connection portions of the electrode pattern were formed of a transparent conductive film, but the connection terminals and the wiring pattern were formed of a metal thin film having a low resistance value. Therefore, the manufacturing process can be simplified by forming the conductive member, the connection terminal, and the wiring pattern with a conductive film made of the same material as in the present invention. Furthermore, since the conductive member that electrically connects the plurality of first transparent conductive films is formed of a conductive film, the resistance value of the electrode pattern is reduced, so that a capacitive input device with low power consumption is provided. can do.
  • the subject includes an input unit where an input operation is performed, and an output unit for outputting a signal from the input unit,
  • a method of manufacturing a capacitance-type input device in which the input unit and the output unit are provided on the same surface of a transparent substrate, wherein a single layer or at least one layer of a metal layer is formed on the entire surface of the transparent substrate.
  • Conductive film formed by etching a linear conductive member to be formed A turning step, an insulating film forming step for forming an insulating film on the entire surface of the transparent substrate, and a plurality of first members disposed adjacent to each other in the second direction in the insulating film.
  • An insulating film patterning step for removing a portion other than a position that insulates the connecting portion formed continuously with the two transparent conductive films and disposed at a position intersecting with the conductive member; and the entire surface on the transparent substrate A transparent conductive film forming step of forming a transparent conductive film, and etching the first transparent conductive film, the plurality of second transparent conductive films, and the connection portion with respect to the transparent conductive film. And the transparent conductive film patterning step to be formed.
  • the width of the conductive member in the second direction is 4 It is preferable to form so as to be ⁇ 10 ⁇ m. In this way, when the conductive member that electrically connects the first transparent conductive film is formed of a conductor film made of only a metal layer, the conductive member becomes difficult to be visually recognized by setting the width to 4 to 10 ⁇ m. It is possible to provide a capacitive input device having transparency in the input unit.
  • the conductor film forming step includes a step of forming a metal oxide layer first or last in the conductor film forming step, the step of forming the metal layer, and the metal oxide layer. It is preferable to alternately include the step of forming a film.
  • a metal oxide layer as the uppermost layer or the lowermost layer in the conductor film, a highly transparent conductor film can be obtained. At this time, it is necessary to provide a metal oxide layer at least on the viewing side.
  • by alternately laminating metal layers and metal oxide layers in the conductor film it is possible to obtain a conductor film having a lower reflectivity by utilizing interference of light between the layers. As a result, it is possible to provide a capacitance-type input device with high transparency of the input unit and the output unit.
  • the width of the conductive member in the second direction is 7 to 40 ⁇ m. In this way, by forming the metal oxide layer in the uppermost layer or the lowermost layer in the conductor film and making the width of the conductive member in the above range, the conductive member can be made difficult to visually recognize, so that more transparent A high capacitance type input device can be provided.
  • the capacitance-type input device of the present invention by forming a conductive member that electrically connects the first transparent conductive film with a conductive film including at least one or more metal layers, the electrical conductivity of the conductive member is increased. As a result, it is possible to provide a capacitance-type input device with reduced resistance and, as a result, reduced power consumption. Further, by using the same material for the conductive member, the connection terminal, and the wiring pattern, the manufacturing process can be greatly simplified. Further, when the conductive film is formed only of the metal layer, the visibility of the conductive member can be lowered by setting the width of the conductive member to 4 to 10 ⁇ m, and the capacitance type input device having high transparency. It can be.
  • the visibility of the conductor film is reduced. be able to.
  • the width of the conductive member formed of the conductive film configured as described above is set to 7 to 40 ⁇ m, the transparency of the input section can be ensured.
  • the insulating film only needs to be formed at the intersection of the electrode patterns, and the entire film thickness can be reduced. As a result, since the influence of interference colors is reduced, a highly transparent capacitive input device can be provided.
  • FIG. 1 is a schematic perspective view of an input device equipped with a capacitive input device according to an embodiment of the present invention. It is a pattern diagram of the capacitive input device according to the embodiment of the present invention. It is explanatory drawing which expanded partially the pattern figure of the capacitive input device which concerns on Embodiment 1 of this invention.
  • FIG. 4 is a schematic cross-sectional view corresponding to the line AA of FIG. 3 according to Embodiment 1 of the present invention. It is explanatory drawing which expanded partially the pattern figure of the electrostatic capacitance type input device which concerns on Embodiment 2 of this invention.
  • FIG. 6 is a schematic cross-sectional view corresponding to line BB in FIG. 5 according to Embodiment 2 of the present invention.
  • FIG. 5 is a graph showing optical characteristics according to Example 1-1 to Example 1-4 of the present invention.
  • FIG. 7 is a graph showing optical characteristics according to Example 2-1 to Example 2-5 of the present invention.
  • a capacitance-type input device will be described with reference to the drawings.
  • the materials, arrangements, configurations, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
  • FIG. 1 is a schematic perspective view of an input device equipped with a capacitive input device
  • FIG. 2 is a pattern diagram of the capacitive input device.
  • 3 and 4 relate to the first embodiment of the present invention.
  • FIG. 3 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device.
  • FIG. 4 corresponds to the AA line in FIG.
  • FIG. 5 and FIG. 6 relate to Embodiment 2 of the present invention
  • FIG. 5 is a partially enlarged explanatory view of the pattern diagram of the capacitance type input device
  • FIG. 7 is a graph showing optical characteristics according to Examples 1-1 to 1-4
  • FIG. 8 is an optical diagram according to Examples 2-1 to 2-5. It is a graph which shows a characteristic.
  • a capacitive input device 1 is used as an input device 100 by being configured in combination with an image display device 2 as shown in FIG.
  • the input device 100 includes at least a capacitive input device 1, an image display device 2, and a flexible flat cable 3.
  • the capacitive input device 1 is disposed so as to overlap the viewing side of the image display device 2, that is, the side operated by the user, and the operator inputs the surface of the capacitive input device 1.
  • An input unit 1a for performing an input operation and an output unit 1b for outputting a signal from the input unit 1a to the outside are provided.
  • the flexible flat cable 3 for outputting the input signal is connected to the output part 1b of the capacitive input device 1.
  • the flexible flat cable 3 is connected to a detection drive circuit (detection unit) (not shown). Further, when the input device 100 is operated, the driving IC may be mounted with COG (Chip On Glass) as long as it does not affect the operation.
  • COG Chip On Glass
  • the image display device 2 mounted on the input device 100 can use a general liquid crystal panel, an organic EL panel, or the like, and displays a moving image or a still image.
  • the input device 100 employs a capacitance method that determines the position by measuring the ratio of the amount of current. The operation will be described below.
  • the input device 100 includes the capacitance type input device 1, and during the operation, the user visually recognizes an image displayed on the image display device 2 through the transparent capacitance type input device 1 and performs a corresponding input. Check the information. Information is input by touching a position corresponding to the instruction image displayed on the image display device 2 with a finger or the like on the capacitive input device 1. At this time, when a finger, which is a conductor, touches, the capacitance between the detection electrodes (the first electrode pattern 20 and the second electrode pattern 30) disposed on the capacitive input device 1 is increased. To have. As a result, the capacitance at the position touched by the finger is lowered, and the position is calculated by a detection drive circuit (detection unit) (not shown).
  • a detection drive circuit detection unit
  • the capacitance type input device 1 includes a first electrode pattern 20 extending in the x-axis direction and a second electrode pattern 30 extending in the y-axis direction on the transparent substrate 4. Is formed, whereby the input portion 1a is formed. Furthermore, the output part 1b is formed by forming the wiring patterns 50 and 60 connected to the electrode patterns and the connection terminals 50a and 60a provided in the wiring patterns 50 and 60, respectively.
  • FIG. 2 shows a part of the pattern of the capacitive input device 1.
  • the first transparent conductive film 21a (see FIG. 3) provided in the first electrode pattern 20 and the second transparent conductive film 31a provided in the second electrode pattern 30 are each formed in a substantially diamond shape.
  • the second transparent conductive films 31a adjacent to each other are continuously formed by the connection portions 31c at the apexes of the approximately rhombus, and as a result, the second electrode pattern 30 continuous in the y-axis direction is formed.
  • the first electrode pattern 20 and the second electrode pattern 30 intersect each other at the intersection 40, and both are electrically insulated.
  • the first electrode pattern 20 and the second electrode pattern 30 may have a vertical correspondence as shown in FIG. 2 or may be disposed on the transparent substrate 4 at a non-vertical corresponding angle.
  • the wiring patterns 50 and 60 include the first electrode pattern 20 (more specifically, the first transparent conductive film 21a) and the second electrode pattern 30 (more specifically, the second transparent conductive film 31a). On the other hand, it is preferable to make the contact as long as possible because the resistance can be reduced.
  • the wiring patterns 50 and 60 and the connection terminals 50a and 60a are formed of a conductor having a single metal layer or a multilayer including at least one metal layer on the transparent substrate 4 or the insulating film.
  • the wiring patterns 50 and 60 electrically connect the first electrode pattern 20 and the second electrode pattern 30 to the connection terminals 50a and 60a, respectively.
  • the connection terminals 50a and 60a are connected to the flexible flat cable 3. Connected.
  • the anisotropic conductive film (ACF) and the flexible flat cable 3 are superposed in this order on the connection terminals 50a and 60a, and heated to about 150 ° C. for thermocompression bonding.
  • ACF anisotropic conductive film
  • the connection method can be wire bonding, solder, laser welding, or the like.
  • FIG. 3 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device 1 according to the first embodiment
  • FIG. 4 is a schematic cross-sectional view corresponding to the line AA in FIG.
  • the transparent substrate 4 including the first transparent conductive film 21a and the second transparent conductive film 31a forming the pad portions 21 and 31 having a large area (in the present embodiment, diamond-shaped portions) and the intersecting portion 40 on the transparent substrate 4 including the first transparent conductive film 21a and the second transparent conductive film 31a forming the pad portions 21 and 31 having a large area (in the present embodiment, diamond-shaped portions) and the intersecting portion 40.
  • An insulating film (not shown) is formed on the entire surface.
  • the portion on the first transparent conductive film 21a is laminated on the insulating film 21b
  • the portion on the second transparent conductive film 31a is laminated on the insulating film 31b
  • the connecting portion 31c of the intersection 40 This part is referred to as an insulating film 41a.
  • a contact hole 22 having no insulating film is provided in the insulating film 21b.
  • the insulating film provided over the entire surface of the transparent substrate 4 is formed before the conductive member 51a and the like which will be described later, it is also provided below the wiring patterns 50 and 60. Therefore, in the first embodiment, when the insulating film is formed, the entire range on the transparent substrate 4 other than the contact hole 22 is covered with the insulating film.
  • a conductive member 51a is formed through the contact hole 22 so that the first transparent conductive films 21a formed adjacent to each other are electrically connected to each other on the insulating film 41a.
  • the electrically connected first electrode pattern 20 is formed. That is, the first transparent conductive films 21a of the pad portions 21 that are separated and adjacent to each other are electrically connected by being disposed so that the conductive member 51a bridges the insulating film 41a.
  • the conductive member 51a is in contact with the first transparent conductive film 21a at the contact portion 52a.
  • the entire surface of the transparent substrate 4 on which the respective films are stacked is covered with a protective film 71.
  • the capacitive input device 1 has a rhombus when the pad portions 21 and 31 including the first transparent conductive film 21a and the second transparent conductive film 31a are formed on the transparent substrate 4 as viewed from the operation surface side. Is formed.
  • the shape of the pad parts 21 and 31 is not limited to a rhombus, and a shape such as a hexagon that can cover the transparent substrate 4 uniformly without a gap can be employed.
  • the length of one side is preferably 4 to 8 mm.
  • the first transparent conductive film 21a that forms the pad portion 21 is formed adjacent to and spaced from each other, while the second transparent conductive film 31a that forms the pad portion 31 passes through the connection portion 31c at the intersection 40.
  • the adjacent second transparent conductive film 31a is continuously formed to form the first electrode pattern 20 and the second electrode pattern 30, respectively.
  • the connecting portion 31c preferably has a width (length in the x-axis direction in FIG. 3) of 50 to 200 ⁇ m.
  • the first transparent conductive films 21a adjacent to each other may be continuous at the intersection 40, and the second transparent conductive film 31a may be interrupted and separated.
  • the transparent substrate 4 may be made of a transparent and insulating material such as glass or a resin substrate including a film. Glass and resin substrates are preferable because they do not require complicated operations because an insulating film does not need to be formed unlike conductive substrates such as metals. Moreover, the strength of the capacitive input device 1 can be increased due to its flexibility.
  • the first transparent conductive film 21a, the second transparent conductive film 31a and the connection portion 31c provided on the transparent substrate 4 are A transparent conductive film is used.
  • ITO Indium Tin Oxide
  • IZO Indium Zinc Oxide
  • AZO Alluminanum Zinc Oxide
  • the thickness of the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c is preferably about 10 to 20 nm.
  • the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c As a method for forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c, chemical film formation methods such as spray pyrolysis and CVD, and physical film formation such as vapor deposition and sputtering. It can be broadly divided into laws. Among these, the sputtering method is preferable because the resistance value and transmittance of the obtained film are less likely to change with the passage of time and the deposition conditions can be easily controlled.
  • the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c are patterned by etching.
  • a transparent insulating material for the insulating films including the insulating films 21b and 31b (only the positions thereof are shown in FIG. 3) and 41a (see FIG. 4), SiO 2 , Al 2 O 3 , polyimide resin
  • An acrylic resin or the like can be used, and the thickness is preferably about 300 to 3000 nm.
  • a method for forming the insulating film an evaporation method, a sputtering method, a dipping method, or a printing method can be used. Among these, the sputtering method is preferable because the resistance value and transmittance of the obtained film are less likely to change with the passage of time and the deposition conditions can be easily controlled.
  • Insulating films 21b, 31b and 41a are patterned by etching in the case of an inorganic film, or by removing uncured portions after curing necessary portions when using a resin.
  • the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed of a single layer of a metal layer (metal thin film) or a conductor film having a multilayer including at least one metal layer.
  • metals such as gold
  • any one selected from silver, copper, a silver alloy, a copper alloy, and MAM (a three-layer structure of Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy) that can be easily patterned by etching may be used. More specifically, it is preferable that the Mo alloy contains Nb and the Al alloy contains Nd.
  • a material containing Al is preferable because it can be manufactured at a relatively low cost and electrical conductivity can be secured.
  • the thickness of the conductive film is about 30 to 500 nm (the total is about 200 to 600 nm when the conductive film is a multilayer), and the width of the conductive member 51a (the length in the y-axis direction in FIG. 3) is 4 to 10 ⁇ m. It is preferable that the length (the length in the x-axis direction in FIG. 3) is about 100 to 300 ⁇ m.
  • the conductive member 51a is formed in a linear shape with a very small width, and more specifically, has a strip-like narrow shape having a very narrow width compared to the pad portion 21. If the width of the conductive member 51a (the length in the y-axis direction in FIG. 3) is smaller than 4 ⁇ m (7 ⁇ m when the conductive film is a multilayer), it becomes difficult to manufacture with good reproducibility by etching. When the conductor film is only a metal layer, it is a single layer, so the width of the conductive member 51a can be controlled to 4 ⁇ m. However, when the conductor film is formed of multiple layers, it is slightly etched.
  • the thickness is 7 ⁇ m or more in order to ensure etching accuracy.
  • the conductive member 51a is slightly visually recognized, and the transparency of the obtained capacitive input device 1 is lowered. Therefore, the visibility of the capacitive input device 1 is lowered, which is not preferable.
  • a conductor film was formed only from the silver alloy, and the conductive member 51a was formed in widths of 4 ⁇ m, 7 ⁇ m, 10 ⁇ m, and 20 ⁇ m, and visual confirmation was performed.
  • visual confirmation by 10 people, when the thickness was 10 ⁇ m or less, a majority of 9 people could not visually recognize the conductive member 51a.
  • the width of the conductive member 51a was 20 ⁇ m, six people were visible. Thereby, it was confirmed that the width of the conductive member 51a should be 10 ⁇ m or less when the conductor film is formed of only a metal layer.
  • an attempt was made to form the conductive member 51a with a width of less than 4 ⁇ m, but the etching accuracy was low, and patterning could not be performed with a required tolerance.
  • a metal layer made of a silver alloy and a metal oxide layer made of IGO were formed in combination, and the conductive member 51a was formed with a width of 4 ⁇ m, 7 ⁇ m, 10 ⁇ m, 20 ⁇ m, 40 ⁇ m, and 50 ⁇ m, and visual confirmation was performed.
  • visual confirmation by 10 people, when the thickness was 40 ⁇ m or less, the majority of 10 people could not visually recognize the conductive member 51a.
  • the width of the conductive member 51a was 50 ⁇ m, six people were visible. Thereby, it was confirmed that the width of the conductive member 51a should be 40 ⁇ m or less when the conductive film is formed of a laminate of a metal layer and a metal oxide layer.
  • the wiring patterns 50 and 60 and the connection terminals 50a and 60a are formed using the same material as that of the conductive member 51a. Thereby, since the formation of the wiring patterns 50 and 60 and the connection terminals 50a and 60a and the formation of the conductive member 51a can be performed simultaneously, the manufacturing process can be shortened.
  • the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are also patterned by etching after forming a conductor film over the entire region by sputtering.
  • the conductor film preferably has a structure in which metal layers made of the above materials and metal oxide layers are alternately stacked.
  • the wiring pattern 50, 60, the connection terminals 50a, 60a, and the conductive layer are formed by forming a layer (that is, the uppermost layer) formed farthest from the transparent substrate 4 with a metal oxide layer. Reflection in the member 51a is suppressed, and it is preferable because it is less visible when viewed from the front side of the transparent substrate 4 (that is, the surface on which the first electrode pattern 20 and the second electrode pattern 30 are formed). .
  • a layer (that is, the lowermost layer) formed at a position closest to the transparent substrate 4 is formed of a metal oxide layer, whereby the wiring patterns 50 and 60, the connection terminals 50a and 60a, and the conductive member are formed.
  • the reflection at 51a is suppressed, and when viewed from the back side of the transparent substrate 4 (that is, the surface on which the first electrode pattern 20 and the second electrode pattern 30 are not formed), it is preferable because the reflection is less visible.
  • indium such as ITO (Indium Tin Oxide), ITO added with Nb, V, Ta, Mo, Ga, Ge, IZO (Indium Zinc Oxide), IGO (Indium Germanium Oxide), etc.
  • ITO Indium Tin Oxide
  • ITO added with Nb, V, Ta, Mo, Ga, Ge
  • IZO Indium Zinc Oxide
  • IGO Indium Germanium Oxide
  • a composite oxide is mentioned.
  • a transparent conductive film having a high resistance value is not used as a material for the wiring patterns 50 and 60, the connection terminals 50a and 60a, and the conductive member 51a, but a single layer or at least one layer of a metal layer (metal thin film).
  • These members are formed of a conductor film having a multilayer including the above metal layers. Therefore, power consumption is suppressed.
  • the width of the conductive member 51a is reduced to 4 to 10 ⁇ m, so that it is difficult to see, so that the capacitive input device 1 having high transparency as a whole can be obtained. It can be provided.
  • the conductor film is formed of a multilayer including at least one or more metal layers, and at least the layer on the side visually recognized by the operator (that is, the side on which the image display device 2 in FIG. 1 is not disposed) is made of metal.
  • the conductive member 51a can be made difficult to be visually recognized.
  • the width of the conductive member 51a is preferably 7 to 40 ⁇ m.
  • the protective film 71 enhances the environmental resistance of each member disposed on the transparent substrate 4 and has the effect of preventing the occurrence of cracks that are a concern when the capacitive input device 1 is deformed by an external force.
  • an insulating film formed of SiO 2 , Al 2 O 3 or the like by vapor deposition, sputtering, dipping, or the like, a polyimide film by screen printing, or the like can be used. It is also possible to use a photosensitive resin that is cured by ultraviolet rays or the like.
  • the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof are simultaneously formed on the transparent substrate 4.
  • a method of forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c will be described below.
  • a transparent conductive film is formed over the entire region using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by spin coater or spraying, and the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c to be formed are disposed at appropriate positions on the transparent substrate 4. Then, exposure is performed using a mask.
  • each side of the first transparent conductive film 21a and the second transparent conductive film 31a formed in a rhombus is 4 to 8 mm, and the first transparent conductive film 21a and the second transparent conductive film 31a. Is designed to be 50 to 200 ⁇ m.
  • the transparent substrate 4 on which the transparent conductive film is laminated is immersed in a developer so that unnecessary portions (that is, portions that do not correspond to the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof). Remove the photoresist. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the transparent conductive film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, thereby forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c.
  • ITO is preferably used as the transparent conductive film material
  • the sputtering conditions are preferably as follows.
  • O 2 / Ar 1 to 2%
  • an ultrahigh pressure mercury lamp X-ray, KrF excimer laser, ArF excimer laser, or the like can be used.
  • a short wavelength one is desirable.
  • a positive resist is used as the photoresist.
  • AZRFP-230K2 manufactured by AZ Electronic Materials Co., Ltd. was used.
  • OFPR-800LB manufactured by Tokyo Ohka may be used.
  • an organic base solution or an inorganic base solution can be used.
  • metal ions may be mixed.
  • TMAH Tetra Methyl Ammonium Hydroxide
  • PMER manufactured by Tokyo Ohka Co., Ltd. was used.
  • an etching solution such as cyan, aqua regia, iodine or oxalic acid can be used as the etching solution.
  • nitric acid, hydrobromic acid, and a ferric chloride solution are used.
  • an alkaline solution is used as a solvent for cleaning the photoresist, and TMAH is preferably used. TMAH was also used in this embodiment.
  • the above-mentioned photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on the material forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c. .
  • a wet etching method capable of mass production that is relatively inexpensive is shown.
  • the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof are patterned by dry etching. May be.
  • an insulating film (not shown) including the insulating films 21b, 31b, and 41a is formed as a transparent film of the capacitive input device 1. A film is formed over the entire region on the substrate 4.
  • an insulating film (not shown) is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like.
  • a photoresist is applied by a spin coater or spraying, and exposure is performed using a mask so that the contact holes 22 to be formed are disposed at appropriate positions on the transparent substrate 4.
  • the transparent substrate 4 on which each film is laminated is immersed in a developing solution, thereby removing unnecessary portions of the photoresist (that is, portions corresponding to the contact holes 22).
  • the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution, thereby removing the portion of the insulating film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, whereby an insulating film (all regions including the insulating films 21b, 31b, and 41a) is formed in a portion other than the contact hole 22.
  • a photosensitive resin can also be used as the insulating film. After application of the resin by printing or dipping, necessary portions are cured by exposure through a mask, and then unnecessary uncured portions are removed. The manufacturing process is further simplified.
  • the sputtering conditions are preferably set as follows.
  • the size of the contact hole 22 is preferably 50 to 200 ⁇ m on one side.
  • the above-described photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on a material for forming an insulating film (not shown) (all regions including the insulating films 21b, 31b, and 41a). .
  • a wet etching method that is relatively inexpensive and capable of mass production is shown.
  • the entire region including the insulating films 21b, 31b, and 41a may be patterned by dry etching.
  • a conductor film is formed over the entire area of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like.
  • a vacuum deposition method a sputtering method, a CVD method, or the like.
  • only a single metal layer may be formed as the conductor film, or a multilayer including the metal layer may be formed.
  • the constituent materials of each layer are appropriately selected by switching the raw materials in the thin film forming apparatus.
  • the metal oxide layer is formed on the operator's viewing side, and the material is switched in the thin film forming apparatus so that the metal layer and the metal oxide layer are alternately stacked.
  • the width of the conductive member 51a to be formed is 4 to 10 ⁇ m (in the case where the conductive film is a multilayer). 7 to 40 ⁇ m), the length (the length in the x-axis direction in FIG. 3) is about 100 to 300 ⁇ m, and the wiring patterns 50 and 60 and the connection terminals 50a and 60a are at appropriate positions on the transparent substrate 4. It exposes using a mask so that it may be arrange
  • the transparent substrate 4 on which each film is laminated is immersed in a developing solution to remove unnecessary portions of the photoresist (that is, portions not corresponding to the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a). Remove. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the conductor film not covered with the photoresist. Then, the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by completely removing the photoresist using a solvent.
  • the sputtering conditions are preferably as follows.
  • the conductor film material and the film formation conditions are not limited to this, and the metal layer material is a metal such as gold, silver, copper, molybdenum (Mo), niobium (Nb), aluminum (Al), etc. Can be used alone, or each alloy can be used, and the film forming conditions are set appropriately.
  • Sputtering conditions DC power: 7 kW, sputtering gas: Ar, gas pressure: 2-4 mTorr, substrate temperature: 100 ° C.
  • a metal such as gold, silver, copper, molybdenum (Mo), niobium (Nb), and aluminum (Al) is used alone or an alloy thereof. Can do.
  • the etching liquid can use the liquid mixture of the acid chosen from any two or more of phosphoric acid, nitric acid, and acetic acid.
  • Photoresist, developer, and the like are the same as in the above-described transparent conductive film forming step.
  • the above-mentioned photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on the material for forming the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a.
  • the wet etching method that is relatively inexpensive and can be mass-produced is shown.
  • the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a may be formed by dry etching. Good.
  • the protective film 71 is formed on the entire surface of the transparent substrate 4 on which the respective films are stacked, thereby A capacitive input device 1 is obtained.
  • an insulating film formed of SiO 2 , Al 2 O 3 or the like by a vapor deposition method, a sputtering method, a dipping method or the like, a polyimide film by a screen printing method, or the like is used as the protective film 71. It is preferable to use a polyimide film having high heat resistance and chemical resistance and high adhesion.
  • a conductive member 51a according to the first embodiment adopting a transparent conductive film (ITO film) as in the conventional case is used as a comparative example, and the resistance value is compared with the first embodiment.
  • the conductive member 51a is a transparent conductive film (ITO film)
  • the other configurations are the same member arrangement and materials as in the first embodiment.
  • the conductive member 51a is an APC (silver, palladium, copper alloy) thin film made of Furuya Metal.
  • Equation (1) is established between the resistivity ⁇ ( ⁇ cm) and the resistance value R ( ⁇ ).
  • R ( ⁇ ⁇ L) / S (1)
  • L represents the length (cm) of the conductor
  • S represents the cross-sectional area (cm 2 ) of the conductor.
  • the resistance value R is about 3.5 ⁇ .
  • the metal used is APC, resistivity ⁇ : 3.5 ⁇ 10 ⁇ 6 ⁇ cm, conductor length L: 200 ⁇ m, conductor cross-sectional area S: 2.0 ⁇ 10 ⁇ 8 cm 2 (conductive member 51a The width is 10 ⁇ m, and the thickness is 200 nm.
  • the resistance value R is about 400 ⁇ .
  • resistivity ⁇ 1.5 ⁇ 10 ⁇ 4 ⁇ cm
  • conductor length L 200 ⁇ m
  • conductor cross-sectional area S 7.5 ⁇ 10 ⁇ 9 cm 2 (width of conductive member 51a 50 ⁇ m, thickness : Cross-sectional area at 15 nm).
  • the resistance values are 400 ⁇ and 3.5 ⁇ , respectively, and the resistance value in the first embodiment is greatly reduced. Therefore, the power consumption of the capacitive input device 1 can be greatly reduced.
  • the capacitance-type input device 1 according to the second embodiment of the present invention is the same as the first embodiment (FIG. 1) except that the stacking order (configuration) and shape of each film in the first embodiment are changed. 3 and FIG. 4), and each film is formed by the same film forming method.
  • FIGS. 5 and 6 differences from the first embodiment will be described in detail with reference to FIGS. 5 and 6.
  • FIG. 5 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device 1 according to the second embodiment
  • FIG. 6 is a schematic sectional view corresponding to the line BB in FIG.
  • the first transparent conductive films 21c forming the pad portions 21 are formed apart from each other, while the adjacent first transparent conductive films 21c are electrically connected by the conductive member 51b. Further, the second transparent conductive film 31d forming the pad portion 31 is formed continuously with the second transparent conductive film 31d formed adjacent to each other through the connection portion 31e. Thereby, the continuous 1st electrode pattern 20 and 2nd electrode pattern 30 are formed, respectively.
  • the conductive member 51b provided in the first electrode pattern 20 and the connection part 31e provided in the second electrode pattern 30 intersect with each other at the intersection 40. At this time, the first transparent conductive film 21c may be connected at the intersection 40, and the second transparent conductive film 31d may be disconnected and separated.
  • a conductive member 51b, wiring patterns 50 and 60, and connection terminals 50a and 60a are formed on a transparent substrate 4.
  • the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by a conductor film including a single metal layer (metal thin film) or a multilayer including at least one metal layer.
  • the thickness of the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a is preferably about 30 to 500 nm in the case of a single layer (the total is about 200 to 600 nm in the case of multiple layers).
  • the width (the length in the y-axis direction in FIG. 5) and the length (the length in the x-axis direction in FIG. 5) are the same as those of the conductive member 51a of the first embodiment.
  • the first transparent conductive film 21c is formed on both ends of the conductive member 51b so that a part thereof overlaps. That is, a part of the first transparent conductive film 21c is laminated on the contact part 52b which is a part on the conductive member 51b, thereby being electrically connected to each other.
  • the shape and size of the first transparent conductive film 21c and the second transparent conductive film 31d and the distance between the first transparent conductive film 21c and the second transparent conductive film 31d are the same as those in the first embodiment.
  • the insulating film 41b On the conductive member 51b, a portion where the first transparent conductive film 21c is not laminated (that is, a portion other than the contact portion 52b) is covered with the insulating film 41b.
  • the insulating film 41 b is disposed at the intersection 40 to electrically insulate the first electrode pattern 20 and the second electrode pattern 30. Therefore, the insulating film 41b does not need to cover all portions of the conductive member 51b where the first transparent conductive film 21c is not laminated, and at least the connection portion 31e in the second electrode pattern 30 and the conductive member 51b are insulated. What is necessary is just to be arrange
  • the size of the insulating film 41b is preferably about 50 to 200 ⁇ m in the x-axis direction and about 50 to 200 ⁇ m in the y-axis direction in FIG. As described above, the size of the insulating film 41b is within a range in which the connection portion 31e and the conductive member 51b are not electrically connected, and can be appropriately designed within the range.
  • connection part 31e for electrically connecting the second transparent conductive films 31d forming the pad part 31 is laminated on the insulating film 41b.
  • the connecting portion 31e is also formed of a transparent conductive film.
  • the width of the connecting portion 31e (the length in the x-axis direction in FIG. 5) is preferably 50 to 200 ⁇ m.
  • the entire surface of the transparent substrate 4 on which the respective films are laminated is covered with the protective film 71 as in the first embodiment.
  • the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed on the transparent substrate 4 as follows.
  • the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed through an etching process as follows.
  • a conductor film is formed over the entire area of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like.
  • the conductor film only the metal layer may be formed as in the first embodiment, or the metal layer and the metal oxide layer may be alternately stacked.
  • the width of the conductive member 51b to be formed (the length in the y-axis direction in FIG. 5) is 4 to 10 ⁇ m (when the conductive film is a multilayer) 7 to 40 ⁇ m), the length (the length in the x-axis direction in FIG. 5) is about 100 to 300 ⁇ m, and the wiring patterns 50 and 60 and the connection terminals 50a and 60a are placed at appropriate positions on the transparent substrate 4. It exposes using a mask so that it may be arrange
  • the transparent substrate 4 on which each film is laminated is immersed in a developing solution so that unnecessary portions (that is, portions not corresponding to the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a) are removed. Remove. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the conductor film not covered with the photoresist. Then, the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by completely removing the photoresist using a solvent.
  • the film forming conditions and the etching conditions are the same as those in forming the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a.
  • the insulating film 41b is formed.
  • the insulating film 41b is formed through an etching process as follows. First, an insulating film (not shown) is formed over the entire region on the transparent substrate 4 of the capacitive input device 1 by using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by a spin coater or spraying, and exposure is performed using a mask so that the insulating film 41b is formed in a range where the connection portion 31e and the conductive member 51b are not electrically connected.
  • the transparent substrate 4 on which each film is laminated is immersed in a developing solution, thereby removing unnecessary portions of the photoresist (that is, portions not corresponding to the insulating film 41b).
  • the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the insulating film not covered with the photoresist.
  • the photoresist is completely removed using a solvent, thereby forming the insulating film 41b.
  • a photosensitive resin can also be used as the insulating film. After application of the resin by printing or dipping, necessary portions are cured by exposure through a mask, and then unnecessary uncured portions are removed. The manufacturing process is further simplified.
  • the film formation conditions and the patterning conditions are the same as those in the above-described film formation of the insulating film (all regions including the insulating films 21b, 31b, and 41a).
  • the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof are formed.
  • the 1st transparent conductive film 21c, the 2nd transparent conductive film 31d, and its connection part 31e are formed through an etching process as follows. First, a transparent conductive film is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like.
  • a transparent conductive film is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by spin coater or spraying, and the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e to be formed are disposed at appropriate positions on the transparent substrate 4. Then, exposure is performed using a mask.
  • the transparent substrate 4 on which the transparent conductive film is laminated is immersed in a developing solution, so that unnecessary portions (that is, portions that do not correspond to the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof).
  • the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the transparent conductive film not covered with the photoresist.
  • the photoresist is completely removed using a solvent, thereby forming the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof.
  • the film formation conditions and the etching conditions are the same as those at the time of forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c.
  • the protective film 71 is formed on the entire surface of the transparent substrate 4 on which the respective films are laminated.
  • the electrostatic capacitance type input device 1 is obtained.
  • the film formation conditions are the same as those for forming the protective film 71 in the first embodiment.
  • the conductor film is composed of a single metal layer or a multilayer including at least one metal layer.
  • Example 1-1 to Example 1-4 and Example 2-1 to Example 2-5 the reflectance of the conductive films having various configurations was simulated.
  • the structure of the conductor film on the transparent substrate 4 in each example is shown in Table 1, and the optical characteristics regarding the conductor film in each example are shown in FIGS.
  • Table 1 shows the configuration (stacking order) of the conductor films in each example formed on the glass substrate as the transparent substrate 4.
  • the arrow in the column of “observation side (viewing side)” indicates the side on which the reflectance is measured, and the reflectance of the surface on which the arrow is described in the glass substrate on which each layer is laminated is illustrated. 7 and FIG. (For example, in Example 1-3, the silver alloy, IGO, silver alloy, and IGO are laminated in this order on the glass substrate, and the reflectance observed from the side on which the IGO is formed is shown in FIG. In Example 1-4, IGO, silver alloy, IGO, and silver alloy are laminated in this order on the glass substrate, and the reflectance observed from the glass substrate side is shown in FIG.
  • the numbers in parentheses for each layer in the table indicate the thickness of each layer.
  • the thickness of these layers should just be the range which can obtain an appropriate resistance value, and can be designed suitably.
  • a silver alloy is preferably about 50 to 500 nm, and a MAM is preferably about 100 to 600 nm.
  • FIG. 7 shows the reflectance of light of each wavelength in Examples 1-1 to 1-4.
  • the material of the metal layer is a silver alloy
  • the material of the metal oxide layer is IGO.
  • Examples 1-1 and 1-2 are cases in which a silver alloy is formed on a glass substrate.
  • the light reflectance is 80 to 98 in a wavelength range of 400 to 700 nm, regardless of which side is viewed. % Is shown. Therefore, when the conductor film is a single metal layer, the reflectivity is high and it is easy to visually recognize. Therefore, when forming the conductive members 51a and 51b, the width is set to 4 to 10 ⁇ m, which is very thin. It can be difficult to visually recognize by forming.
  • Examples 1-3 and 1-4 metal layers and metal oxide layers are alternately stacked, and a metal oxide layer is formed on the viewing side. It is shown that the reflectance is about 15 to 64%, which is lower than those in Example 1-1 and Example 1-2 in the wavelength region of 400 to 700 nm. Therefore, it is difficult to visually recognize the conductor film by forming a metal oxide layer on the viewing side.
  • the metal layer is formed as a multilayer having a metal oxide layer formed on the viewing side than when the metal layer is formed as a single layer. Therefore, when the metal oxide layer is formed on the viewing side, good transparency can be obtained even if the width of the conductive members 51a and 51b is wide. Therefore, the width of the conductive members 51a and 51b is set to 7 to 40 ⁇ m. Is done.
  • FIG. 8 shows the reflectance of light of each wavelength in Examples 2-1 to 2-5.
  • the material of the metal layer is MAM or Mo—Nb alloy, and the material of the metal oxide layer is IGO.
  • Examples 2-1 and 2-2 are cases in which MAM is formed on a glass substrate.
  • the light reflectance is 40 to 53% in the wavelength range of 400 to 700 nm regardless of which side is viewed. It is shown to be a degree. Therefore, the reflectivity is lower than when the conductor film is a single layer of silver alloy, and at the wavelength near 400 nm and near 650 nm, the reflectivity comparable to that obtained when the silver alloy and IGO are laminated can be obtained. it can.
  • Example 2-3 to Example 2-5 when a metal oxide film is combined with MAM (Example 2-3 to Example 2-5), it exhibits a very low reflectance in the wavelength range of 400 to 700 nm.
  • Example 2-4 and Example 2-5 have a reflectance of 10% or less (about 3 to 8%) over the entire wavelength range of 400 to 700 nm, so the visibility is very low. It has been shown to have high transparency.
  • the capacitive input device 1 of the present invention is electrically insulated at the intersection 40 of the first electrode pattern 20 and the second electrode pattern 30.
  • the conductive members 51a and 51b that connect the first transparent conductive films 21a and 21c formed separately from each other, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are conductor films. It consists of Therefore, since the conductive members 51a and 51b can be formed simultaneously with the wiring patterns 50 and 60 and the connection terminals 50a and 60a, the manufacturing process can be simplified.
  • the conductive members 51a and 51b have a smaller resistance value than the case where the conductive members 51a and 51b are formed using a transparent conductive film, and can reduce the power consumption of the capacitive input device 1.
  • the capacitance-type input device 1 of the present invention is used in the field of electronic equipment such as mobile terminals (PDA, Personal Digital Assistant) such as mobile phones and electronic notebooks, game machines, car navigation systems, personal computers, ticket vending machines, and bank terminals. Expected to be useful.
  • PDA Personal Digital Assistant

Abstract

Provided is a capacitance type input device having higher transparency and achieving lower power consumption. The capacitance type input device is provided with an input unit and an output unit on the same surface of a transparent substrate, wherein the output unit comprises a connection terminal for outputting a signal, and a wiring pattern for electrically connecting the input unit and the connection terminal. The input unit comprises a plurality of first electrode patterns composed of a plurality of first transparent conductive films arranged to be adjacent in the first direction, and a conductive member for electrically connecting the first transparent conductive films; and a second electrode pattern composed of a plurality of second transparent conductive films arranged to be adjacent in the second direction which intersects the first direction, and a connection unit arranged at the position intersecting with the conductive member of the first electrode pattern. The conductive member, the connection terminal, and the wiring pattern are formed by the same conductive film, and the conductive film is composed of a single metal layer, or a plurality of layers including at least one metal layer, and the conductive member is formed in the shape of a line.

Description

静電容量型入力装置及びその製造方法Capacitance type input device and manufacturing method thereof
 本発明は、静電容量型入力装置及びその製造方法に係り、特に、高い透明性を備えると共に消費電力を抑えた静電容量型入力装置及びその製造方法に関する。 The present invention relates to a capacitance-type input device and a method for manufacturing the same, and more particularly to a capacitance-type input device that has high transparency and suppresses power consumption and a method for manufacturing the same.
 近年、携帯電話、電子手帳等の携帯端末(PDA、Personal Digital Assistant)、ゲーム機、カーナビゲーション、パーソナルコンピュータ、券売機、銀行の端末等の電子機器分野において、液晶装置などの表面にタブレット型の入力装置(タッチパネル)が導入されており、その需要は飛躍的に伸びている。このような入力装置では、液晶装置の画像表示領域に表示された指示画像を参照しながら、この指示画像が表示されている箇所にスタイラスペンや指などで触れることにより、指示画像に対応する情報の入力を行うことができる。 In recent years, in the field of electronic devices such as portable terminals (PDA, Personal Digital Assistant) such as mobile phones and electronic notebooks, game machines, car navigation systems, personal computers, ticket vending machines, bank terminals, etc., tablets on the surface of liquid crystal devices etc. Input devices (touch panels) have been introduced, and the demand for these devices has increased dramatically. In such an input device, by referring to the instruction image displayed in the image display area of the liquid crystal device, by touching the position where the instruction image is displayed with a stylus pen or a finger, information corresponding to the instruction image Can be entered.
 タッチパネル式入力装置は、スタイラスペンや指で操作エリアに対して入力操作を行ったときに、操作エリア内の入力操作位置を検出し、外部処理装置へ入力操作位置を示す入力信号を出力する。この時の動作原理により、タッチパネル式入力装置は主に、抵抗膜型、静電容量型、電磁誘導型、超音波表面弾性波型、赤外線走査型などがあるが、現在は位置検出がしやすく、比較的コストが抑えられる抵抗膜型の入力装置が主流となっている。 The touch panel type input device detects an input operation position in the operation area when an input operation is performed on the operation area with a stylus pen or a finger, and outputs an input signal indicating the input operation position to the external processing device. Depending on the operating principle at this time, there are mainly touch panel type input devices such as resistance film type, capacitance type, electromagnetic induction type, ultrasonic surface acoustic wave type, infrared scanning type, etc. Resistive film type input devices that are relatively inexpensive are the mainstream.
 しかし、抵抗膜型の入力装置は、フィルムとガラスの2枚構造でフィルムを押下してショートさせる構造のため、動作温度範囲が狭く、経時変化に弱いという問題点がある。さらに、衝撃に弱く、寿命が短いという問題点を有している。また、入力装置の面積の拡大に伴う精度の低下や、金属薄膜を2枚必要とするため透明性に劣るといった問題点もある。 However, the resistance film type input device has a problem that the operating temperature range is narrow and it is vulnerable to changes with time because of the structure in which the film is pressed and short-circuited in a two-layer structure of film and glass. Further, it has a problem that it is vulnerable to impact and has a short life. In addition, there are problems such as a decrease in accuracy associated with an increase in the area of the input device and inferior transparency due to the need for two metal thin films.
 これに対し、静電容量型の入力装置は、入力装置の表面全体に電解を形成し、ユーザーの指が接触又は近接した部分の表面電荷の変化により位置検出を行うため、ほこりや水に強く耐久性があり、さらに高分解能を有する。また、応答速度が高く、さらに指等の導体にしか反応しないため、その他のもの(例えば衣服等)が接触したときの誤作動がないという利点も有している。 On the other hand, the capacitance type input device forms an electrolysis on the entire surface of the input device, and detects the position by changing the surface charge of the portion in contact with or close to the user's finger, so it is resistant to dust and water. It is durable and has high resolution. In addition, since the response speed is high and it reacts only to a conductor such as a finger, there is an advantage that there is no malfunction when another object (such as clothes) contacts.
 このような静電容量型の入力装置として、特許文献1及び2では、1枚の基板上で互いに交差する方向に電極パターンを延在させて、格子状の電極パターンを形成し、ユーザーの指が接触又は近接した際、電極間の静電容量が変化することを検知して入力位置を検出する技術が提案されている。 As such a capacitance-type input device, in Patent Documents 1 and 2, electrode patterns are extended in a direction intersecting each other on a single substrate to form a grid-like electrode pattern, and the user's finger There has been proposed a technique for detecting an input position by detecting that the capacitance between the electrodes changes when the electrode contacts or approaches.
特開2008-310550号公報JP 2008-310550 A 実用新案登録第3134925号公報Utility Model Registration No. 3134925
 一般に、タッチパネル式入力装置は画像表示装置の上に配設され、操作者が画像表示装置に表示された画像を見て、タッチパネル式入力装置に触れることにより操作される。したがって、画像表示装置に表示された画像をタッチパネル式入力装置の操作面側から目視する必要があるため、タッチパネル式入力装置は透明性が高いものが要求される。そのため、タッチパネル式入力装置の基板及び電極パターンの材料として、透明性に優れた材料が用いられてきた。 Generally, a touch panel type input device is disposed on an image display device, and is operated by an operator viewing an image displayed on the image display device and touching the touch panel type input device. Therefore, since it is necessary to visually check the image displayed on the image display device from the operation surface side of the touch panel type input device, the touch panel type input device is required to have high transparency. Therefore, a material having excellent transparency has been used as a material for a substrate and an electrode pattern of a touch panel type input device.
 特許文献1では各電極パターンの交差部を小さくし、さらにその交差部において、透光性の薄膜(透明導電膜)を積層した構造としているため、電極パターンの交差部が目立つことがなく、その結果、透明性の高いタッチパネル式入力装置を提供している。また、特許文献2においても、透明性を有する材料(透明導電膜)により構成された入力装置が開示されている。 In patent document 1, since the crossing part of each electrode pattern is made small, and since it is the structure which laminated the translucent thin film (transparent conductive film) in the crossing part, the crossing part of an electrode pattern does not stand out, As a result, a highly transparent touch panel type input device is provided. Patent Document 2 also discloses an input device that is made of a transparent material (transparent conductive film).
 一方、静電容量型の入力装置は、常時電流を流す必要があるため、その消費電力は、装置全体の抵抗値に大きく依存する。したがって、タッチパネル式入力装置において、透明導電膜をパターニングした場合、透明導電膜は金属と比較して抵抗値が大きいため、入力部を作動させる電圧が高くなり、消費電力が増すという問題点がある。 On the other hand, since the capacitance-type input device needs to constantly flow current, the power consumption greatly depends on the resistance value of the entire device. Therefore, when the transparent conductive film is patterned in the touch panel type input device, the transparent conductive film has a larger resistance value than that of the metal, so that there is a problem that the voltage for operating the input unit is increased and the power consumption is increased. .
 また、静電容量型の入力装置は、上述のように透明導電膜をパターニングした場合、消費電力が増加する。これに対し、わずかでも消費電力の削減を図り、外部装置との接続に用いられる配線パターンとして、抵抗値の低い金属薄膜が用いられていた。したがって、透明性を要するタッチパネル式入力装置においては、電極パターン、及び交差部の導電部材は透明導電膜が用いられる一方で、配線パターンは金属薄膜が用いられており、電極パターン及び交差部の導電部材と、配線パターンとがそれぞれ異なる材料により構成されていた。そのため、配線パターンの成膜工程、及び電極パターン等の成膜工程がそれぞれ別途必要であり、製造工程が煩雑になりやすいという問題点があった。 Also, the capacitance type input device increases the power consumption when the transparent conductive film is patterned as described above. In contrast, a metal thin film having a low resistance value has been used as a wiring pattern used for connection to an external device in order to reduce power consumption even slightly. Therefore, in the touch panel type input device that requires transparency, the electrode pattern and the conductive member of the intersection are made of a transparent conductive film, while the wiring pattern is made of a metal thin film, and the electrode pattern and the conductive part of the intersection are made. The member and the wiring pattern are made of different materials. Therefore, there is a problem that a wiring pattern film forming process and an electrode pattern film forming process are separately required, and the manufacturing process tends to be complicated.
 本発明の目的は、静電容量型入力装置において、透明性が高く、且つ消費電力が小さいタッチパネル式入力装置を提供することにある。また、本発明の他の目的は、静電容量型入力装置を簡単な構成とし、簡略化した製造工程とすることにより安価な静電容量型入力装置を提供することにある。なお本明細書においては、入力装置を通して見る画像に対し、人間の視力による視認性を透明性と表現している。すなわち、微細なため視認できないものによって光が遮られ、光透過量が若干減少した場合でも、画像視認性に影響が無い場合は透明と表現している。 An object of the present invention is to provide a touch panel type input device having high transparency and low power consumption in a capacitance type input device. Another object of the present invention is to provide an inexpensive capacitive input device by making the capacitive input device with a simple configuration and a simplified manufacturing process. In the present specification, the visibility of human vision with respect to an image viewed through an input device is expressed as transparency. That is, even if the light is blocked by what is invisible because it is fine and the amount of light transmission is slightly reduced, it is expressed as transparent when there is no effect on the image visibility.
 前記課題は、本発明に係る静電容量型入力装置によれば、入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置であって、前記出力部は、前記信号を出力する接続端子と、前記入力部と前記接続端子とを電気的に接続する配線パターンと、を有し、前記入力部は、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜と、該第1透明導電膜を電気的に接続する導電部材と、で構成される複数の第1の電極パターンと、前記第1方向と交差する第2方向に隣り合って配設される複数の第2透明導電膜と、該複数の第2透明導電膜と連続して形成されると共に前記導電部材と交差する位置に配設される接続部と、で構成される複数の第2の電極パターンと、前記導電部材と前記接続部との間に配設され、前記導電部材と前記接続部との絶縁を維持する絶縁膜と、を有し、前記導電部材と前記接続端子と前記配線パターンとは同一の導電体膜によって形成され、該導電体膜は、金属層の単層又は少なくとも1層以上の金属層を含む複層からなり、前記導電部材は、線状に形成されていること、により解決される。 According to the capacitance-type input device of the present invention, the subject includes an input unit in which an input operation is performed, and an output unit for outputting a signal from the input unit, and the input unit and The output unit is a capacitance-type input device provided on the same surface of a transparent substrate, and the output unit electrically connects the connection terminal that outputs the signal, the input unit, and the connection terminal. A wiring pattern connected to the plurality of first transparent conductive films disposed adjacent to each other in the first direction on the transparent substrate, and the first transparent conductive film electrically connected to the first transparent conductive film. A plurality of first electrode patterns, a plurality of second transparent conductive films disposed adjacent to each other in a second direction intersecting the first direction, and the plurality of the plurality of first electrode patterns. The contact is formed continuously with the second transparent conductive film and disposed at a position intersecting with the conductive member. A plurality of second electrode patterns, and an insulating film disposed between the conductive member and the connection portion and maintaining insulation between the conductive member and the connection portion. The conductive member, the connection terminal, and the wiring pattern are formed of the same conductor film, and the conductor film is a single layer of a metal layer or a multilayer including at least one metal layer, The conductive member is solved by being formed in a linear shape.
 このように、第1の電極パターンにおいて、第1透明導電膜を電気的に接続する導電部材が、透明導電膜よりも抵抗値の小さい金属層(金属薄膜)を含む導電体膜によって構成されることにより、静電容量型入力装置の消費電力を削減することができる。従来技術では、静電容量型入力装置の操作領域における透明性を確保するため、電極パターンは全て透明導電膜を用いて形成されていた。しかし、透明導電膜はその抵抗値が厚さに依存し、厚さ数十nm程度以上の時であっても、1.5×10-4Ωcm程度の抵抗率をとるが、その抵抗率は金属薄膜の抵抗率(例えば銅の抵抗率1.67×10-6Ωcm)と比較して極端に大きい。したがって、透明導電膜を用いた場合、静電容量型入力装置の消費電力は大きくなるが、本発明のように、金属層を1層、若しくは少なくとも1層以上の金属層を含む複層によって導電体膜を構成することにより、消費電力の削減を図ることができる。 Thus, in the first electrode pattern, the conductive member that electrically connects the first transparent conductive film is constituted by a conductor film including a metal layer (metal thin film) having a resistance value smaller than that of the transparent conductive film. As a result, the power consumption of the capacitive input device can be reduced. In the prior art, all electrode patterns are formed using a transparent conductive film in order to ensure transparency in the operation region of the capacitive input device. However, the resistance value of the transparent conductive film depends on the thickness. Even when the thickness is about several tens of nanometers or more, the transparent conductive film has a resistivity of about 1.5 × 10 −4 Ωcm. It is extremely large compared to the resistivity of the metal thin film (for example, the resistivity of copper 1.67 × 10 −6 Ωcm). Therefore, when a transparent conductive film is used, the power consumption of the capacitive input device increases. However, as in the present invention, the metal layer is conductive by one layer or a multilayer including at least one metal layer. By configuring the body membrane, power consumption can be reduced.
 このとき、請求項2のように、前記導電体膜は前記金属層の単層からなり、前記導電部材の前記第2方向の幅が4~10μmであると好ましい。
 このように、導電体膜を金属層のみで形成した場合、導電部材の幅を4~10μmという非常に細い構成とすると、人間の視力では導電部材を全く視認できない。したがって、導電部材を操作者が視認することがなく、静電容量型入力装置の操作領域の透明性を確保することができる。導電体膜を金属層のみとした場合、導電部材の幅を10μmよりも大きくすると導電部材が僅かではあるが操作者から視認されるようになり、4μmよりも小さくするとエッチング等によるパターニングの精度が低下するため好ましくない。
At this time, it is preferable that the conductor film is a single layer of the metal layer, and the width of the conductive member in the second direction is 4 to 10 μm.
As described above, when the conductor film is formed of only the metal layer, if the width of the conductive member is 4 to 10 μm, the conductive member cannot be visually recognized by human vision. Therefore, the operator does not visually recognize the conductive member, and the transparency of the operation area of the capacitive input device can be ensured. When the conductive film is only a metal layer, if the width of the conductive member is larger than 10 μm, the conductive member is slightly visible to the operator, but if it is smaller than 4 μm, the patterning accuracy by etching or the like is improved. Since it falls, it is not preferable.
 また、請求項3のように、前記導電体膜は金属層と金属酸化物層とが交互に積層された複層からなり、前記導電体膜において、前記金属酸化物層が、視認側に形成されてなると好適である。
 このように、操作者の視認側に金属酸化物層を形成することにより、各層間における光の干渉を利用して、導電体膜の反射率を低下させることができる。
 導電部材のような微細な形状は、透過光では視認されなくとも、反射光の向きによっては視認可能となることがあるが、反射率を低下させることにより、この問題を解消できる。
 そして、金属層と金属酸化物層をそれぞれ複数積層すると、さらに反射率を低下させることができる。その結果、導電体膜によって形成される導電部材、接続端子、配線パターンがより視認しにくくなり、入力部及び出力部において均一に透明性が向上した静電容量型入力装置を提供することができる。
 なお、「視認側」とは、静電容量型入力装置において、操作者が視認する側を指すものである。より詳細には、透明基板上で、入力部と出力部とが形成された側(表面)から操作者が視認する場合は、導電体膜の最上層を指す。一方、入力部と出力部とが形成されていない側(裏面)から操作者が視認する場合は、導電体膜の最下層を指すものである。
According to a third aspect of the present invention, the conductor film is composed of a plurality of layers in which metal layers and metal oxide layers are alternately stacked, and the metal oxide layer is formed on the viewer side in the conductor film. It is suitable if it is made.
Thus, by forming a metal oxide layer on the operator's viewing side, it is possible to reduce the reflectance of the conductor film by utilizing light interference between the respective layers.
A fine shape such as a conductive member may be visible depending on the direction of reflected light even if it is not visually recognized by transmitted light, but this problem can be solved by reducing the reflectance.
Then, when a plurality of metal layers and metal oxide layers are stacked, the reflectance can be further reduced. As a result, it is possible to provide a capacitive input device in which the conductive member, the connection terminal, and the wiring pattern formed by the conductive film are less visible and the transparency is uniformly improved in the input unit and the output unit. .
In addition, the “viewing side” refers to the side that the operator visually recognizes in the capacitive input device. In more detail, when an operator visually recognizes from the side (surface) in which the input part and the output part were formed on the transparent substrate, it refers to the uppermost layer of the conductor film. On the other hand, when an operator visually recognizes from the side (back surface) where the input part and the output part are not formed, it indicates the lowest layer of the conductor film.
 さらにこのとき、請求項4のように、前記導電部材の前記第2方向の幅が7~40μmであると好ましい。
 このように、導電体膜において操作者の視認側に金属酸化物層を形成し、透明性を向上させることによって導電部材を形成する際、導電部材の幅を7~40μmとするとよい。導電部材を金属層のみで構成した場合と異なり、金属酸化物層を視認側に形成した場合、より透明性が向上するため、導電部材の幅を大きくした場合であっても視認されにくくなる。ただし、金属酸化物層を視認側に形成しても、導電部材の幅を40μmよりも大きくした場合、僅かではあるが導電部材が視認されるようになるため好ましくない。また、7μmよりも小さくするとエッチング等によるパターニングの精度が低下するため好ましくない。
Further, at this time, as in claim 4, it is preferable that the width of the conductive member in the second direction is 7 to 40 μm.
In this way, when the conductive member is formed by forming a metal oxide layer on the operator's viewing side in the conductor film and improving the transparency, the width of the conductive member is preferably 7 to 40 μm. Unlike the case where the conductive member is composed only of the metal layer, when the metal oxide layer is formed on the viewing side, the transparency is further improved, so that even when the width of the conductive member is increased, the conductive member is hardly visually recognized. However, even if the metal oxide layer is formed on the viewing side, if the width of the conductive member is larger than 40 μm, the conductive member is slightly visible but is not preferable. On the other hand, if it is smaller than 7 μm, the patterning accuracy by etching or the like is lowered, which is not preferable.
 また、請求項5のように、前記金属層の材料は、銀、銀合金、銅、銅合金、MAM(MoもしくはMo合金/AlもしくはAl合金/MoもしくはMo合金の3層構造化合物)より選択されるいずれかの金属であると好ましい。
 これらの金属材料は抵抗値が小さいため、導電部材と、接続端子と、配線パターンを上記金属の薄膜からなる単層、又は上記金属の薄膜を含む複層とすることにより、消費電力の小さい静電容量型入力装置を得ることができる。また、抵抗値が小さいため、配線ピッチを狭くすることができ、その結果、配線パターンが配設される額縁面積(出力部)を狭くすることができる。さらにまた、配線ピッチが狭小化可能であることから、同設置面積で配線パターンを増やすことが可能となり、高い位置精度で入力信号を検出することができる。
 また、上記金属材料は、エッチングによる加工が容易であるため、本発明の静電容量型入力装置の製造に適している。
Further, as described in claim 5, the material of the metal layer is selected from silver, silver alloy, copper, copper alloy, MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound). Any of the above metals is preferred.
Since these metal materials have small resistance values, static electricity with low power consumption can be obtained by making the conductive member, the connection terminal, and the wiring pattern into a single layer made of the above-mentioned metal thin film or a multiple layer containing the above-mentioned metal thin film. A capacitive input device can be obtained. Further, since the resistance value is small, the wiring pitch can be narrowed, and as a result, the frame area (output portion) where the wiring pattern is disposed can be narrowed. Furthermore, since the wiring pitch can be reduced, the wiring pattern can be increased with the same installation area, and the input signal can be detected with high positional accuracy.
Further, the metal material is suitable for manufacturing the capacitive input device of the present invention because it can be easily processed by etching.
 また、請求項6のように、前記金属層の材料は、銀、銀合金、銅、銅合金、MAM(MoもしくはMo合金/AlもしくはAl合金/MoもしくはMo合金の3層構造化合物)より選択されるいずれかの金属であり、前記金属酸化物層は、インジウム複合酸化物が含有されてなると好適である。
 このように、金属層を上記材料によって形成し、さらに金属酸化物層を上記材料とすることにより、導電体膜をエッチングにより一括で加工することができる。その結果、製造工程が煩雑となることがなく、製造時の費用を削減することができる。
In addition, as described in claim 6, the material of the metal layer is selected from silver, silver alloy, copper, copper alloy, and MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound). Preferably, the metal oxide layer contains an indium composite oxide.
Thus, by forming the metal layer with the above material and further using the metal oxide layer with the above material, the conductor film can be processed at once by etching. As a result, the manufacturing process is not complicated, and the manufacturing cost can be reduced.
 さらにまた、請求項7のように、前記導電部材と前記接続部の交差部において、前記透明基板上に、前記導電部材と、前記絶縁膜と、前記接続部とが、この順に積層されてなると好適である。
 このような構成、すなわち図6のような構成とすると、絶縁膜を第1の電極パターンと第2の電極パターンとの交差部のみに配設するだけでよい。本構成によると、透明基板上に、導電部材が形成されているため、その後、交差部にのみ絶縁膜を形成するだけで、第1の電極パターンと第2の電極パターンの絶縁が保持される。したがって、各部(各部材)を積層させて形成する際、より容易に形成することができる。
 一方、透明基板上に第1及び第2透明導電膜と、第2の電極パターンにおける接続部が先に成膜された構成、すなわち図4のような構成とした場合、導電部材は最後に形成される。この時、導電部材は第1透明電導膜のみを電気的に接続しなくてはならないため、第1透明導電膜と導電部材が接続する部分以外の部分は、全て絶縁膜で覆われている必要がある。
 したがって、本構成によると、絶縁膜を設ける範囲が第1の電極パターンと第2の電極パターンとの交差部のみに限定されるため、第1の電極パターン及び第2の電極パターン上には保護膜のみが成膜される構成となる。その結果、全体の膜厚が薄くなるため、膜厚が厚い時に問題となる干渉色による透明性の低下を防ぐことができる。
 さらに本構成によると、透明基板上に先に透明導電膜が成膜された構成(図4の構成)とは異なり、図6の構成とすると、絶縁膜において導電部材を貫通させるための微小な接触孔を設ける必要がなく、さらに導電部材をその接触孔に貫通させるといった微細なパターニングを施す必要がない。したがって、比較的簡単な構成とすることができ、その結果、静電容量型入力装置の入力部を成膜する際、歩留まりが良くなる。
Furthermore, as in claim 7, when the conductive member, the insulating film, and the connection portion are stacked in this order on the transparent substrate at the intersection of the conductive member and the connection portion. Is preferred.
In such a configuration, that is, a configuration as shown in FIG. 6, the insulating film may be disposed only at the intersection between the first electrode pattern and the second electrode pattern. According to this configuration, since the conductive member is formed on the transparent substrate, the insulation between the first electrode pattern and the second electrode pattern can be maintained only by forming the insulating film only at the intersection thereafter. . Therefore, when each part (each member) is laminated and formed, it can be formed more easily.
On the other hand, when the first and second transparent conductive films and the connection portions in the second electrode pattern are first formed on the transparent substrate, that is, in the structure as shown in FIG. 4, the conductive member is formed last. Is done. At this time, since the conductive member must electrically connect only the first transparent conductive film, all portions other than the portion where the first transparent conductive film and the conductive member are connected must be covered with an insulating film. There is.
Therefore, according to this configuration, since the range in which the insulating film is provided is limited only to the intersection between the first electrode pattern and the second electrode pattern, protection is provided on the first electrode pattern and the second electrode pattern. Only the film is formed. As a result, since the entire film thickness becomes thin, it is possible to prevent a decrease in transparency due to an interference color which becomes a problem when the film thickness is large.
Further, according to the present configuration, unlike the configuration in which the transparent conductive film is first formed on the transparent substrate (configuration in FIG. 4), the configuration in FIG. There is no need to provide a contact hole, and there is no need to perform fine patterning such as passing a conductive member through the contact hole. Therefore, a relatively simple configuration can be obtained, and as a result, the yield is improved when forming the input portion of the capacitive input device.
 また前記課題は、本発明に係る静電容量型入力装置の製造方法によれば、入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置の製造方法であって、前記透明基板上の全面に、透明導電膜を成膜する透明導電膜成膜工程と、前記透明導電膜に対し、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜と、前記第1方向と交差する第2方向に配設される複数の第2透明導電膜と、該複数の第2透明導電膜と連続して形成される接続部と、をエッチングして形成する透明導電膜パターニング工程と、前記透明基板上の全面に、絶縁膜を成膜する絶縁膜成膜工程と、前記絶縁膜をパターニングして、前記第1透明導電膜上において、前記第2透明導電膜と連続して形成される接続部を介在させて両側に接触孔を形成する接触孔形成工程と、前記透明基板上の全面に、金属層の単層又は少なくとも1層以上の金属層を含む複層からなる導電体膜を成膜する導電体膜成膜工程と、前記導電体膜に対し、前記出力部が前記信号を出力するために備えられる接続端子と、該接続端子と前記入力部とを接続する配線パターンと、前記複数の第1透明導電膜を電気的に接続すると共に前記接続部と交差する位置に配設される線状の導電部材と、をエッチングすることにより形成する導電体膜パターニング工程と、を備えること、により解決される。 In addition, according to the method for manufacturing a capacitance-type input device according to the present invention, the subject includes an input unit where an input operation is performed, and an output unit for outputting a signal from the input unit, A method of manufacturing a capacitive input device in which the input unit and the output unit are provided on the same surface of a transparent substrate, wherein a transparent conductive film is formed on the entire surface of the transparent substrate. A plurality of first transparent conductive films disposed adjacent to the transparent conductive film in a first direction on the transparent substrate, and a second direction intersecting the first direction with respect to the transparent conductive film; A transparent conductive film patterning step formed by etching a plurality of second transparent conductive films and a connection portion formed continuously with the plurality of second transparent conductive films; and on the entire surface of the transparent substrate. An insulating film forming step of forming an insulating film, and patterning the insulating film, A contact hole forming step of forming contact holes on both sides with a connection part formed continuously with the second transparent conductive film on one transparent conductive film; and a metal layer on the entire surface of the transparent substrate. A conductor film forming step of forming a conductor film comprising a single layer or a multilayer including at least one metal layer, and the output unit is provided for outputting the signal to the conductor film; A connection terminal, a wiring pattern connecting the connection terminal and the input unit, and a linear pattern electrically connecting the plurality of first transparent conductive films and disposed at a position intersecting the connection unit And a conductive film patterning step formed by etching the conductive member.
 従来技術においては、透明性の確保を目的とし、電極パターンの接続部はすべて透明導電膜で成膜されていたが、接続端子と配線パターンは抵抗値の低い金属薄膜で形成されていた。したがって、本発明のように、導電部材と接続端子と配線パターンとを同一材料からなる導電体膜で形成することにより、その製造工程を簡素化することができる。さらに、複数の第1透明導電膜を電気的に接続する導電部材を、導電体膜によって形成することにより、電極パターンの抵抗値が小さくなるため、消費電力の小さい静電容量型入力装置を提供することができる。 In the prior art, for the purpose of ensuring transparency, all connection portions of the electrode pattern were formed of a transparent conductive film, but the connection terminals and the wiring pattern were formed of a metal thin film having a low resistance value. Therefore, the manufacturing process can be simplified by forming the conductive member, the connection terminal, and the wiring pattern with a conductive film made of the same material as in the present invention. Furthermore, since the conductive member that electrically connects the plurality of first transparent conductive films is formed of a conductive film, the resistance value of the electrode pattern is reduced, so that a capacitive input device with low power consumption is provided. can do.
 さらに前記課題は、本発明に係る静電容量型入力装置の製造方法によれば、入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置の製造方法であって、前記透明基板上の全面に、金属層の単層又は少なくとも1層以上の金属層を含む複層からなる導電体膜を成膜する導電体膜成膜工程と、前記導電体膜に対し、前記出力部が前記信号を出力するために備えられる接続端子と、該接続端子と前記入力部とを接続する配線パターンと、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜を電気的に接続すると共に前記第1方向に沿って形成される線状の導電部材と、をエッチングして形成する導電体膜パターニング工程と、前記透明基板上の全面に、絶縁膜を成膜する絶縁膜成膜工程と、前記絶縁膜において、前記導電部材と、前記第2方向に隣り合って配設される複数の第2透明導電膜と連続して形成されると共に前記導電部材と交差する位置に配設される接続部と、を絶縁する位置以外の部分を除去する絶縁膜パターニング工程と、前記透明基板上の全面に、透明導電膜を成膜する透明導電膜成膜工程と、前記透明導電膜に対し、前記第1透明導電膜と、複数の前記第2透明導電膜と、前記接続部と、をエッチングして形成する透明導電膜パターニング工程と、を備えること、により解決される。 Furthermore, according to the method for manufacturing a capacitance-type input device according to the present invention, the subject includes an input unit where an input operation is performed, and an output unit for outputting a signal from the input unit, A method of manufacturing a capacitance-type input device in which the input unit and the output unit are provided on the same surface of a transparent substrate, wherein a single layer or at least one layer of a metal layer is formed on the entire surface of the transparent substrate. A conductor film forming step of forming a conductor film including a plurality of metal layers, a connection terminal provided for the output unit to output the signal to the conductor film, and the connection A wiring pattern for connecting the terminal and the input unit and a plurality of first transparent conductive films arranged adjacent to each other in the first direction on the transparent substrate are electrically connected and along the first direction. Conductive film formed by etching a linear conductive member to be formed A turning step, an insulating film forming step for forming an insulating film on the entire surface of the transparent substrate, and a plurality of first members disposed adjacent to each other in the second direction in the insulating film. An insulating film patterning step for removing a portion other than a position that insulates the connecting portion formed continuously with the two transparent conductive films and disposed at a position intersecting with the conductive member; and the entire surface on the transparent substrate A transparent conductive film forming step of forming a transparent conductive film, and etching the first transparent conductive film, the plurality of second transparent conductive films, and the connection portion with respect to the transparent conductive film. And the transparent conductive film patterning step to be formed.
 このとき、上述の請求項7の発明の構成の静電容量型入力装置を提供することができるため、干渉色を低減し、透明性を確保した静電容量型入力装置を提供することが可能となる。 At this time, it is possible to provide the capacitance-type input device having the configuration of the invention of claim 7 described above, and therefore it is possible to provide a capacitance-type input device that reduces interference color and ensures transparency. It becomes.
 このとき、請求項10のように、前記導電体膜成膜工程において、前記金属層の単層を成膜し、前記導電体膜パターニング工程において、前記導電部材の前記第2方向の幅が4~10μmとなるように形成すると好適である。
 このように、第1透明導電膜を電気的に接続する導電部材を金属層のみからなる導電体膜によって形成する際、その幅を4~10μmとすることにより、導電部材が視認されにくくなり、入力部において透明性を備えた静電容量型入力装置を提供することができる。
At this time, as in claim 10, in the conductor film forming step, a single layer of the metal layer is formed, and in the conductor film patterning step, the width of the conductive member in the second direction is 4 It is preferable to form so as to be ˜10 μm.
In this way, when the conductive member that electrically connects the first transparent conductive film is formed of a conductor film made of only a metal layer, the conductive member becomes difficult to be visually recognized by setting the width to 4 to 10 μm. It is possible to provide a capacitive input device having transparency in the input unit.
 また、請求項11のように、前記導電体膜成膜工程において、最初又は最後に金属酸化物層を成膜する工程を備えると共に、前記金属層を成膜する工程と、前記金属酸化物層を成膜する工程とを交互に備えると好ましい。
 このように、導電体膜において最上層又は最下層として金属酸化物層を備えることにより、透明性の高い導電体膜とすることができる。このとき、少なくとも視認側に金属酸化物層を備えている必要がある。
 また、導電体膜において金属層と金属酸化物層を交互に積層させることにより、各層間における光の干渉を利用して、より反射率の低い導電体膜とすることができる。その結果、入力部及び出力部の透明性が高い静電容量型入力装置を提供することができる。
In addition, the conductor film forming step includes a step of forming a metal oxide layer first or last in the conductor film forming step, the step of forming the metal layer, and the metal oxide layer. It is preferable to alternately include the step of forming a film.
Thus, by providing a metal oxide layer as the uppermost layer or the lowermost layer in the conductor film, a highly transparent conductor film can be obtained. At this time, it is necessary to provide a metal oxide layer at least on the viewing side.
Further, by alternately laminating metal layers and metal oxide layers in the conductor film, it is possible to obtain a conductor film having a lower reflectivity by utilizing interference of light between the layers. As a result, it is possible to provide a capacitance-type input device with high transparency of the input unit and the output unit.
 さらにこのとき、請求項12のように、前記導電体膜パターニング工程において、前記導電部材の前記第2方向の幅が7~40μmとなるように形成すると好ましい。
 このように、導電体膜において金属酸化物層を最上層または最下層に形成し、導電部材の幅を上記範囲とすることにより、導電部材を視認しにくくすることができるため、より透明性の高い静電容量型入力装置を提供することができる。
Further, at this time, it is preferable that, in the conductor film patterning step, the width of the conductive member in the second direction is 7 to 40 μm.
In this way, by forming the metal oxide layer in the uppermost layer or the lowermost layer in the conductor film and making the width of the conductive member in the above range, the conductive member can be made difficult to visually recognize, so that more transparent A high capacitance type input device can be provided.
 本発明の静電容量型入力装置によれば、少なくとも1層以上の金属層を含む導電体膜によって、第1透明導電膜を電気的に接続する導電部材を形成することにより、導電部材の電気抵抗を小さくし、その結果、消費電力を小さくした静電容量型入力装置を提供することができる。また、導電部材、接続端子、配線パターンを同一の材料とすることにより、製造工程を飛躍的に簡素化させることができる。
 また、導電体膜を金属層のみで形成した場合は、導電部材の幅を4~10μmとすることにより、導電部材の視認性を低下させることができ、透明性の高い静電容量型入力装置とすることができる。
 さらに、金属層と金属酸化物層とを交互に積層させて導電体膜を形成し、さらに金属酸化物層を操作者の視認側に配設することにより、導電体膜の視認性を低下させることができる。そして、このように構成された導電体膜によって形成される導電部材の幅を、7~40μmとすることにより、入力部の透明性を確保することができる。
 また、導電部材、絶縁膜、透明導電膜の順に成膜された構成とすると、絶縁膜は電極パターンの交差部にのみ成膜されるだけでよく、全体の膜厚を薄くすることができる。その結果、干渉色による影響が軽減されるため、透明性の高い静電容量型入力装置を提供することができる。
According to the capacitance-type input device of the present invention, by forming a conductive member that electrically connects the first transparent conductive film with a conductive film including at least one or more metal layers, the electrical conductivity of the conductive member is increased. As a result, it is possible to provide a capacitance-type input device with reduced resistance and, as a result, reduced power consumption. Further, by using the same material for the conductive member, the connection terminal, and the wiring pattern, the manufacturing process can be greatly simplified.
Further, when the conductive film is formed only of the metal layer, the visibility of the conductive member can be lowered by setting the width of the conductive member to 4 to 10 μm, and the capacitance type input device having high transparency. It can be.
Furthermore, by alternately laminating metal layers and metal oxide layers to form a conductor film, and further disposing the metal oxide layer on the operator's viewing side, the visibility of the conductor film is reduced. be able to. Then, by setting the width of the conductive member formed of the conductive film configured as described above to 7 to 40 μm, the transparency of the input section can be ensured.
Further, when the conductive member, the insulating film, and the transparent conductive film are formed in this order, the insulating film only needs to be formed at the intersection of the electrode patterns, and the entire film thickness can be reduced. As a result, since the influence of interference colors is reduced, a highly transparent capacitive input device can be provided.
本発明の実施形態に係る静電容量型入力装置を搭載した入力装置の概略斜視図である。1 is a schematic perspective view of an input device equipped with a capacitive input device according to an embodiment of the present invention. 本発明の実施形態に係る静電容量型入力装置のパターン図である。It is a pattern diagram of the capacitive input device according to the embodiment of the present invention. 本発明の実施形態1に係る静電容量型入力装置のパターン図を一部拡大した説明図である。It is explanatory drawing which expanded partially the pattern figure of the capacitive input device which concerns on Embodiment 1 of this invention. 本発明の実施形態1に係る図3のA-A線に相当する概略断面図である。FIG. 4 is a schematic cross-sectional view corresponding to the line AA of FIG. 3 according to Embodiment 1 of the present invention. 本発明の実施形態2に係る静電容量型入力装置のパターン図を一部拡大した説明図である。It is explanatory drawing which expanded partially the pattern figure of the electrostatic capacitance type input device which concerns on Embodiment 2 of this invention. 本発明の実施形態2に係る図5のB-B線に相当する概略断面図である。FIG. 6 is a schematic cross-sectional view corresponding to line BB in FIG. 5 according to Embodiment 2 of the present invention. 本発明の実施例1-1~実施例1-4に係る光学特性を示すグラフ図である。FIG. 5 is a graph showing optical characteristics according to Example 1-1 to Example 1-4 of the present invention. 本発明の実施例2-1~実施例2-5に係る光学特性を示すグラフ図である。FIG. 7 is a graph showing optical characteristics according to Example 2-1 to Example 2-5 of the present invention.
1 静電容量型入力装置
 1a 入力部
 1b 出力部
2 画像表示装置
3 フレキシブルフラットケーブル
4 透明基板
20 第1の電極パターン(入力部)
21,31 パッド部
 21a,21c 第1透明導電膜
 31a,31d 第2透明導電膜
 21b,31b,41a,41b 絶縁膜
22 接触孔
30 第2の電極パターン(入力部)
31c、31e 接続部
40 交差部
50,60 配線パターン(出力部)
50a,60a 接続端子(出力部)
51a,51b 導電部材
52a,52b 接触部
71 保護膜
100 入力装置
DESCRIPTION OF SYMBOLS 1 Capacitance type input device 1a Input part 1b Output part 2 Image display apparatus 3 Flexible flat cable 4 Transparent substrate 20 1st electrode pattern (input part)
21, 31 Pad part 21a, 21c First transparent conductive film 31a, 31d Second transparent conductive film 21b, 31b, 41a, 41b Insulating film 22 Contact hole 30 Second electrode pattern (input part)
31c, 31e Connection part 40 Intersection part 50, 60 Wiring pattern (output part)
50a, 60a Connection terminal (output part)
51a, 51b Conductive members 52a, 52b Contact portion 71 Protective film 100 Input device
 本発明の実施形態に係る静電容量型入力装置を図面に基づいて説明する。なお、以下に説明する材料、配置、構成等は、本発明を限定するものでなく、本発明の趣旨の範囲内で種々改変することができるものである。 A capacitance-type input device according to an embodiment of the present invention will be described with reference to the drawings. The materials, arrangements, configurations, and the like described below do not limit the present invention and can be variously modified within the scope of the gist of the present invention.
 図1及び図2は本発明の実施形態に係るもので、図1は静電容量型入力装置を搭載した入力装置の概略斜視図、図2は静電容量型入力装置のパターン図であり、図3及び図4は本発明の実施形態1に係るもので、図3は静電容量型入力装置のパターン図を一部拡大した説明図、図4は図3のA-A線に相当する概略断面図であり、図5及び図6は本発明の実施形態2に係るもので、図5は静電容量型入力装置のパターン図を一部拡大した説明図、図6は図5のB-B線に相当する概略断面図、図7は実施例1-1~実施例1-4に係る光学特性を示すグラフ図、図8は実施例2-1~実施例2-5に係る光学特性を示すグラフ図である。 1 and 2 relate to an embodiment of the present invention, FIG. 1 is a schematic perspective view of an input device equipped with a capacitive input device, and FIG. 2 is a pattern diagram of the capacitive input device. 3 and 4 relate to the first embodiment of the present invention. FIG. 3 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device. FIG. 4 corresponds to the AA line in FIG. FIG. 5 and FIG. 6 relate to Embodiment 2 of the present invention, FIG. 5 is a partially enlarged explanatory view of the pattern diagram of the capacitance type input device, and FIG. FIG. 7 is a graph showing optical characteristics according to Examples 1-1 to 1-4, and FIG. 8 is an optical diagram according to Examples 2-1 to 2-5. It is a graph which shows a characteristic.
[実施形態1]
 本発明の実施形態に係る静電容量型入力装置1は、図1に示すように、画像表示装置2と組み合わせて構成されることにより、入力装置100として用いられる。入力装置100は、少なくとも静電容量型入力装置1と、画像表示装置2とフレキシブルフラットケーブル3を備えている。入力装置100において、静電容量型入力装置1は、画像表示装置2の目視側、すなわちユーザーが操作する側に重ねて配設され、静電容量型入力装置1の表面には、操作者が入力操作を行うための入力部1aと、入力部1aからの信号を外部へ出力するための出力部1bが備えられている。
[Embodiment 1]
A capacitive input device 1 according to an embodiment of the present invention is used as an input device 100 by being configured in combination with an image display device 2 as shown in FIG. The input device 100 includes at least a capacitive input device 1, an image display device 2, and a flexible flat cable 3. In the input device 100, the capacitive input device 1 is disposed so as to overlap the viewing side of the image display device 2, that is, the side operated by the user, and the operator inputs the surface of the capacitive input device 1. An input unit 1a for performing an input operation and an output unit 1b for outputting a signal from the input unit 1a to the outside are provided.
 そして、静電容量型入力装置1の出力部1bに対し、入力された信号を出力するためのフレキシブルフラットケーブル3が接続されている。フレキシブルフラットケーブル3は不図示の検出用駆動回路(検出部)に接続される。また、入力装置100の操作時に、操作に影響を及ぼさない領域であれば、駆動用ICがCOG(Chip On Glass)実装されていてもよい。 And the flexible flat cable 3 for outputting the input signal is connected to the output part 1b of the capacitive input device 1. The flexible flat cable 3 is connected to a detection drive circuit (detection unit) (not shown). Further, when the input device 100 is operated, the driving IC may be mounted with COG (Chip On Glass) as long as it does not affect the operation.
 入力装置100に搭載される画像表示装置2は、一般的な液晶パネル、有機ELパネル等を用いることができ、動画や静止画を表示する。
 入力装置100においては、電流量の比率を計測することにより、その位置を判別する静電容量方式を採用している。以下、その操作を説明する。
The image display device 2 mounted on the input device 100 can use a general liquid crystal panel, an organic EL panel, or the like, and displays a moving image or a still image.
The input device 100 employs a capacitance method that determines the position by measuring the ratio of the amount of current. The operation will be described below.
 入力装置100は、静電容量型入力装置1を備え、その操作時、ユーザーは画像表示装置2に表示された画像を、透明な静電容量型入力装置1を介して視認し、対応する入力情報を確認する。そして画像表示装置2に表示された指示用画像に対応する位置を、静電容量型入力装置1上で指等を用いて触れることにより、情報の入力を行う。この時、導電体である指が触れると、静電容量型入力装置1上に配設された検出電極(第1の電極パターン20、第2の電極パターン30)との間で静電容量を持つようになる。その結果として指で触れた位置の静電容量が低下し、その位置を不図示の検出用駆動回路(検出部)により算出することにより行われるものである。 The input device 100 includes the capacitance type input device 1, and during the operation, the user visually recognizes an image displayed on the image display device 2 through the transparent capacitance type input device 1 and performs a corresponding input. Check the information. Information is input by touching a position corresponding to the instruction image displayed on the image display device 2 with a finger or the like on the capacitive input device 1. At this time, when a finger, which is a conductor, touches, the capacitance between the detection electrodes (the first electrode pattern 20 and the second electrode pattern 30) disposed on the capacitive input device 1 is increased. To have. As a result, the capacitance at the position touched by the finger is lowered, and the position is calculated by a detection drive circuit (detection unit) (not shown).
 静電容量型入力装置1は、図2のように、透明基板4上に、x軸方向に延設される第1の電極パターン20、y軸方向に延設される第2の電極パターン30が成膜されることにより、入力部1aが形成される。さらに、各電極パターンに接続される配線パターン50、60及び配線パターン50、60に備えられた接続端子50a、60aが成膜されることにより、出力部1bが形成される。なお、図2は静電容量型入力装置1のパターンの一部を示している。 As shown in FIG. 2, the capacitance type input device 1 includes a first electrode pattern 20 extending in the x-axis direction and a second electrode pattern 30 extending in the y-axis direction on the transparent substrate 4. Is formed, whereby the input portion 1a is formed. Furthermore, the output part 1b is formed by forming the wiring patterns 50 and 60 connected to the electrode patterns and the connection terminals 50a and 60a provided in the wiring patterns 50 and 60, respectively. FIG. 2 shows a part of the pattern of the capacitive input device 1.
 第1の電極パターン20に備えられた第1透明導電膜21a(図3を参照)及び第2の電極パターン30に備えられた第2透明導電膜31aは、それぞれ略菱形に形成されている。第2の電極パターン30において、互いに隣り合う第2透明導電膜31aは、略菱形の頂点同士で接続部31cによって連続して形成され、結果としてy軸方向に連続した第2の電極パターン30を形成する。第1の電極パターン20と第2の電極パターン30とは、互いに交差部40において交差し、両者は電気的に絶縁されている。第1の電極パターン20及び第2の電極パターン30との間は図2のように垂直対応関係でもよいし、その他垂直でない対応角度で透明基板4上に配設されても良い。 The first transparent conductive film 21a (see FIG. 3) provided in the first electrode pattern 20 and the second transparent conductive film 31a provided in the second electrode pattern 30 are each formed in a substantially diamond shape. In the second electrode pattern 30, the second transparent conductive films 31a adjacent to each other are continuously formed by the connection portions 31c at the apexes of the approximately rhombus, and as a result, the second electrode pattern 30 continuous in the y-axis direction is formed. Form. The first electrode pattern 20 and the second electrode pattern 30 intersect each other at the intersection 40, and both are electrically insulated. The first electrode pattern 20 and the second electrode pattern 30 may have a vertical correspondence as shown in FIG. 2 or may be disposed on the transparent substrate 4 at a non-vertical corresponding angle.
 配線パターン50、60は、図2のように、第1の電極パターン20(より詳細には第1透明導電膜21a)及び第2の電極パターン30(より詳細には第2透明導電膜31a)に対し、可能な限り長く接する構成とすると、抵抗を小さくすることができるため好ましい。配線パターン50、60及び接続端子50a、60aは、透明基板4又は絶縁膜上で金属層の単層又は少なくとも1層以上の金属層を含む複層を備えた導電体によって形成される。配線パターン50、60は、それぞれ第1の電極パターン20、第2の電極パターン30と接続端子50a、60aとを電気的に接続しており、この接続端子50a、60aにおいて、フレキシブルフラットケーブル3に接続される。 As shown in FIG. 2, the wiring patterns 50 and 60 include the first electrode pattern 20 (more specifically, the first transparent conductive film 21a) and the second electrode pattern 30 (more specifically, the second transparent conductive film 31a). On the other hand, it is preferable to make the contact as long as possible because the resistance can be reduced. The wiring patterns 50 and 60 and the connection terminals 50a and 60a are formed of a conductor having a single metal layer or a multilayer including at least one metal layer on the transparent substrate 4 or the insulating film. The wiring patterns 50 and 60 electrically connect the first electrode pattern 20 and the second electrode pattern 30 to the connection terminals 50a and 60a, respectively. The connection terminals 50a and 60a are connected to the flexible flat cable 3. Connected.
 この時、接続端子50a、60a上に、異方導電性フィルム(ACF)、フレキシブルフラットケーブル3をこの順に重ねて150℃程度に加熱して熱圧着する。なお、ACFを用いて接続するだけでなく、はんだ接続等の他の接続方法で接続するものであっても良く、フレキシブルフラットケーブル3の代わりに金属導線を用いてもよい。金属導線をフレキシブルフラットケーブル3の代わりに用いる場合は、その接続方法をワイヤボンディング、はんだ、レーザー溶接などとすることができる。 At this time, the anisotropic conductive film (ACF) and the flexible flat cable 3 are superposed in this order on the connection terminals 50a and 60a, and heated to about 150 ° C. for thermocompression bonding. In addition, it may connect not only using ACF but also by other connection methods such as solder connection, and a metal conductor may be used instead of the flexible flat cable 3. When using a metal conductor instead of the flexible flat cable 3, the connection method can be wire bonding, solder, laser welding, or the like.
 次に、実施形態1における第1の電極パターン20及び第2の電極パターン30に関し、図3及び図4を用いて詳細に説明する。 Next, the first electrode pattern 20 and the second electrode pattern 30 in the first embodiment will be described in detail with reference to FIGS.
 図3は、実施形態1に係る静電容量型入力装置1のパターン図を一部拡大した説明図であり、図4は、図3のA-A線に相当する概略断面図である。 FIG. 3 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device 1 according to the first embodiment, and FIG. 4 is a schematic cross-sectional view corresponding to the line AA in FIG.
 図3において、大面積を有するパッド部21及び31(本実施形態では菱形の部分)を形成する第1透明導電膜21a及び第2透明導電膜31a、さらに交差部40を含む透明基板4上の全面に不図示の絶縁膜が形成される。不図示の絶縁膜において、第1透明導電膜21a上にある部分を絶縁膜21bと、第2透明導電膜31a上にある部分を絶縁膜31bと、交差部40の接続部31c上に積層された部分を絶縁膜41aと称する。絶縁膜21bにおいては、絶縁膜を有さない接触孔22が設けられる。透明基板4上の全面にわたって設けられた絶縁膜は、後述の導電部材51a等よりも前に成膜されるため、配線パターン50、60の下層にも設けられる。したがって本実施形態1においては、絶縁膜を成膜した時点で、接触孔22以外の透明基板4上の全ての範囲が絶縁膜によって覆われた構成となる。 In FIG. 3, on the transparent substrate 4 including the first transparent conductive film 21a and the second transparent conductive film 31a forming the pad portions 21 and 31 having a large area (in the present embodiment, diamond-shaped portions) and the intersecting portion 40. An insulating film (not shown) is formed on the entire surface. In the insulating film (not shown), the portion on the first transparent conductive film 21a is laminated on the insulating film 21b, the portion on the second transparent conductive film 31a is laminated on the insulating film 31b, and the connecting portion 31c of the intersection 40. This part is referred to as an insulating film 41a. In the insulating film 21b, a contact hole 22 having no insulating film is provided. Since the insulating film provided over the entire surface of the transparent substrate 4 is formed before the conductive member 51a and the like which will be described later, it is also provided below the wiring patterns 50 and 60. Therefore, in the first embodiment, when the insulating film is formed, the entire range on the transparent substrate 4 other than the contact hole 22 is covered with the insulating film.
 そして、図4に示すように、隣り合って形成された第1透明導電膜21aが絶縁膜41a上において互いに電気的に接続するように、接触孔22を介して導電部材51aが形成される。これにより、電気的に接続された第1の電極パターン20が形成されている。すなわち、離間して隣り合うパッド部21の第1透明導電膜21a同士を、導電部材51aが絶縁膜41a上をブリッジするように配設されることにより、電気的に接続されている。この時、導電部材51aは、接触部52aにおいて、第1透明導電膜21aと接触している。
 さらに静電容量型入力装置1において、各膜を積層させた透明基板4上の全面は保護膜71により覆われている。
Then, as shown in FIG. 4, a conductive member 51a is formed through the contact hole 22 so that the first transparent conductive films 21a formed adjacent to each other are electrically connected to each other on the insulating film 41a. Thereby, the electrically connected first electrode pattern 20 is formed. That is, the first transparent conductive films 21a of the pad portions 21 that are separated and adjacent to each other are electrically connected by being disposed so that the conductive member 51a bridges the insulating film 41a. At this time, the conductive member 51a is in contact with the first transparent conductive film 21a at the contact portion 52a.
Further, in the capacitive input device 1, the entire surface of the transparent substrate 4 on which the respective films are stacked is covered with a protective film 71.
 実施形態1において、静電容量型入力装置1は、透明基板4上に、第1透明導電膜21a及び第2透明導電膜31aを備えたパッド部21、31が操作面側から見て菱形に形成されている。なお、パッド部21、31の形状は、菱形に限定されるものではなく、六角形等、透明基板4上を均一に隙間なく覆うことができる形状を採用することができる。ここで、菱形を採用した場合、その一辺の長さは4~8mmとすると好ましい。 In the first embodiment, the capacitive input device 1 has a rhombus when the pad portions 21 and 31 including the first transparent conductive film 21a and the second transparent conductive film 31a are formed on the transparent substrate 4 as viewed from the operation surface side. Is formed. In addition, the shape of the pad parts 21 and 31 is not limited to a rhombus, and a shape such as a hexagon that can cover the transparent substrate 4 uniformly without a gap can be employed. Here, when a rhombus is employed, the length of one side is preferably 4 to 8 mm.
 パッド部21を形成する第1透明導電膜21aは、互いに隣り合って離間して形成されている一方、パッド部31を形成する第2透明導電膜31aは、交差部40において接続部31cを介し、隣接した第2透明導電膜31aが連続に形成されることにより、それぞれ第1の電極パターン20及び第2の電極パターン30を形成する。そして接続部31cは、その幅(図3のx軸方向の長さ)を50~200μmとすると好ましい。なお、この時、隣接する第1透明導電膜21a同士が交差部40において連続しており、第2透明導電膜31aが途切れて離間した構成としてもよい。 The first transparent conductive film 21a that forms the pad portion 21 is formed adjacent to and spaced from each other, while the second transparent conductive film 31a that forms the pad portion 31 passes through the connection portion 31c at the intersection 40. The adjacent second transparent conductive film 31a is continuously formed to form the first electrode pattern 20 and the second electrode pattern 30, respectively. The connecting portion 31c preferably has a width (length in the x-axis direction in FIG. 3) of 50 to 200 μm. At this time, the first transparent conductive films 21a adjacent to each other may be continuous at the intersection 40, and the second transparent conductive film 31a may be interrupted and separated.
 このとき、透明基板4は、ガラス、フィルムを含む樹脂基板などの透明且つ絶縁性の材料を用いることができる。ガラス、樹脂基板は金属などの導電性のある基板のように、絶縁膜を形成する必要がないため、操作が煩雑になることが無く、好適である。また、フィルムはその可撓性により、静電容量型入力装置1の強度を高めることができる。 At this time, the transparent substrate 4 may be made of a transparent and insulating material such as glass or a resin substrate including a film. Glass and resin substrates are preferable because they do not require complicated operations because an insulating film does not need to be formed unlike conductive substrates such as metals. Moreover, the strength of the capacitive input device 1 can be increased due to its flexibility.
 さらに、第1の電極パターン20、第2の電極パターン30を形成するパッド部21、31において、透明基板4上に設けられる第1透明導電膜21a、第2透明導電膜31a及び接続部31cは透明な導電膜が用いられ、たとえばITO(Indium Tin Oxide)、IZO(Indium Zinc Oxide)、AZO(Aluminium Zinc Oxide)等を用いることができ、好ましくはITOを用いる。これら電極パターンにおいて、第1透明導電膜21a、第2透明導電膜31a及び接続部31cの厚さは10~20nm程度が好ましい。 Further, in the pad portions 21 and 31 for forming the first electrode pattern 20 and the second electrode pattern 30, the first transparent conductive film 21a, the second transparent conductive film 31a and the connection portion 31c provided on the transparent substrate 4 are A transparent conductive film is used. For example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), AZO (Aluminum Zinc Oxide), or the like can be used, and ITO is preferably used. In these electrode patterns, the thickness of the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c is preferably about 10 to 20 nm.
 第1透明導電膜21a、第2透明導電膜31a及び接続部31cの成膜方法としては、スプレー熱分解法、CVD法等の化学的成膜法と蒸着法、スパッタリング法等の物理的成膜法に大別することができる。なかでもスパッタリング法は、得られる膜の抵抗値及び透過率の経時変化が少なく、成膜条件の制御が容易であるため、好ましい。そして第1透明導電膜21a、第2透明導電膜31a及び接続部31cは、エッチングによりパターニングされる。 As a method for forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c, chemical film formation methods such as spray pyrolysis and CVD, and physical film formation such as vapor deposition and sputtering. It can be broadly divided into laws. Among these, the sputtering method is preferable because the resistance value and transmittance of the obtained film are less likely to change with the passage of time and the deposition conditions can be easily controlled. The first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c are patterned by etching.
 絶縁膜21b、31b(図3でその位置のみを示した)及び41a(図4を参照)を含む絶縁膜には透明な絶縁材料を用いるのが好ましく、SiO、Al、ポリイミド樹脂、アクリル樹脂等を用いることができ、その厚さは300~3000nm程度が好ましい。また、絶縁膜の形成方法としては、蒸着法、スパッタリング法、ディッピング法、印刷法を用いることができる。なかでもスパッタリング法は、得られる膜の抵抗値及び透過率の経時変化が少なく、成膜条件の制御が容易であるため、好ましい。そして絶縁膜は、無機系の膜の場合はエッチングにより、樹脂を用いたときは必要部を硬化させた後の未硬化部の除去により、パターニングされて絶縁膜21b、31b及び41aを形成する。 It is preferable to use a transparent insulating material for the insulating films including the insulating films 21b and 31b (only the positions thereof are shown in FIG. 3) and 41a (see FIG. 4), SiO 2 , Al 2 O 3 , polyimide resin An acrylic resin or the like can be used, and the thickness is preferably about 300 to 3000 nm. In addition, as a method for forming the insulating film, an evaporation method, a sputtering method, a dipping method, or a printing method can be used. Among these, the sputtering method is preferable because the resistance value and transmittance of the obtained film are less likely to change with the passage of time and the deposition conditions can be easily controlled. Insulating films 21b, 31b and 41a are patterned by etching in the case of an inorganic film, or by removing uncured portions after curing necessary portions when using a resin.
 導電部材51a及び配線パターン50、60、接続端子50a、60aは金属層(金属薄膜)の単層又は少なくとも1層以上の金属層を含む複層を備えた導電体膜によって形成される。そして、金属層の材料としては金、銀、銅、モリブデン(Mo)、ニオブ(Nb)、アルミ(Al)等の金属を単体、あるいはそれぞれの合金を用いることができる。好ましくはエッチングによりパターニングしやすい銀、銅、銀合金、銅合金、MAM(MoもしくはMo合金/AlもしくはAl合金/MoもしくはMo合金の3層構造)より選択される何れかとするとよい。より詳細には、Mo合金はNbを含有するもの、Al合金はNdを含有するものとすると好ましい。Alを含有した材料を用いることにより、比較的安価に製造することができると共に、導通性を確保できるため好適である。 The conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed of a single layer of a metal layer (metal thin film) or a conductor film having a multilayer including at least one metal layer. And as a material of a metal layer, metals, such as gold | metal | money, silver, copper, molybdenum (Mo), niobium (Nb), aluminum (Al), can use the single substance or each alloy. Preferably, any one selected from silver, copper, a silver alloy, a copper alloy, and MAM (a three-layer structure of Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy) that can be easily patterned by etching may be used. More specifically, it is preferable that the Mo alloy contains Nb and the Al alloy contains Nd. Use of a material containing Al is preferable because it can be manufactured at a relatively low cost and electrical conductivity can be secured.
 導電体膜の厚さは30~500nm程度(導電体膜が複層の場合はその合計が200~600nm程度)、導電部材51aの幅(図3のy軸方向の長さ)は4~10μm(複層の場合は7~40μm)、長さ(図3のx軸方向の長さ)が100~300μm程度であると好ましい。 The thickness of the conductive film is about 30 to 500 nm (the total is about 200 to 600 nm when the conductive film is a multilayer), and the width of the conductive member 51a (the length in the y-axis direction in FIG. 3) is 4 to 10 μm. It is preferable that the length (the length in the x-axis direction in FIG. 3) is about 100 to 300 μm.
 導電部材51aは微小幅の線状に形成されており、より詳細には、パッド部21と比較して幅が非常に狭い短冊形の細幅形状となっている。導電部材51aの幅(図3のy軸方向の長さ)を4μm(導電体膜が複層の場合は7μm)より小さくするとエッチングにより再現性よく製造することが難しくなる。なお、導電体膜を金属層のみとした場合は単層であるため、導電部材51aの幅を4μmの細さまで制御することができるが、導電体膜を複層で形成した場合、僅かにエッチング精度が低下するため、エッチング精度を確保するために、7μm以上とすると好ましい。一方、10μm(複層の場合は40μm)よりも大きくすると導電部材51aが僅かに視認されるようになり、得られる静電容量型入力装置1の透明性が低下する。したがって、静電容量型入力装置1の視認性が低下し、好ましくない。 The conductive member 51a is formed in a linear shape with a very small width, and more specifically, has a strip-like narrow shape having a very narrow width compared to the pad portion 21. If the width of the conductive member 51a (the length in the y-axis direction in FIG. 3) is smaller than 4 μm (7 μm when the conductive film is a multilayer), it becomes difficult to manufacture with good reproducibility by etching. When the conductor film is only a metal layer, it is a single layer, so the width of the conductive member 51a can be controlled to 4 μm. However, when the conductor film is formed of multiple layers, it is slightly etched. Since accuracy decreases, it is preferable that the thickness is 7 μm or more in order to ensure etching accuracy. On the other hand, if it is larger than 10 μm (40 μm in the case of multiple layers), the conductive member 51a is slightly visually recognized, and the transparency of the obtained capacitive input device 1 is lowered. Therefore, the visibility of the capacitive input device 1 is lowered, which is not preferable.
 銀合金のみで導電体膜を形成し、導電部材51aを4μm、7μm、10μm、20μmの幅で形成し、目視による確認を行った。10人で目視による確認を行ったところ、10μm以下の時、過半数の9人が導電部材51aを視認できなかった。また、導電部材51aの幅が20μmのときは、6人が視認可能であった。
 これにより、導電部材51aの幅は、導電体膜を金属層のみで構成した場合、10μm以下とするとよいことが確認された。なお、導電部材51aを4μm未満の幅で形成しようと試みたが、エッチング精度が低く、要求される許容範囲内の精度でパターニングすることができなかった。
A conductor film was formed only from the silver alloy, and the conductive member 51a was formed in widths of 4 μm, 7 μm, 10 μm, and 20 μm, and visual confirmation was performed. As a result of visual confirmation by 10 people, when the thickness was 10 μm or less, a majority of 9 people could not visually recognize the conductive member 51a. In addition, when the width of the conductive member 51a was 20 μm, six people were visible.
Thereby, it was confirmed that the width of the conductive member 51a should be 10 μm or less when the conductor film is formed of only a metal layer. In addition, an attempt was made to form the conductive member 51a with a width of less than 4 μm, but the etching accuracy was low, and patterning could not be performed with a required tolerance.
 さらに、銀合金からなる金属層とIGOからなる金属酸化物層を組み合わせて形成し、導電部材51aを4μm、7μm、10μm、20μm、40μm、50μmの幅で形成し、目視による確認を行った。10人で目視による確認を行ったところ、40μm以下の時、過半数の10人が導電部材51aを視認できなかった。また、導電部材51aの幅が50μmのときは、6人が視認可能であった。
 これにより、導電部材51aの幅は、導電体膜を金属層と金属酸化物層との積層体で構成した場合、40μm以下とするとよいことが確認された。なお、導電部材51aを7μm未満の幅で形成しようと試みたが、エッチング精度が低く、要求される許容範囲内の精度でパターニングすることができなかった。
Further, a metal layer made of a silver alloy and a metal oxide layer made of IGO were formed in combination, and the conductive member 51a was formed with a width of 4 μm, 7 μm, 10 μm, 20 μm, 40 μm, and 50 μm, and visual confirmation was performed. As a result of visual confirmation by 10 people, when the thickness was 40 μm or less, the majority of 10 people could not visually recognize the conductive member 51a. In addition, when the width of the conductive member 51a was 50 μm, six people were visible.
Thereby, it was confirmed that the width of the conductive member 51a should be 40 μm or less when the conductive film is formed of a laminate of a metal layer and a metal oxide layer. In addition, an attempt was made to form the conductive member 51a with a width of less than 7 μm, but the etching accuracy was low, and the patterning could not be performed with a required tolerance.
 配線パターン50、60及び接続端子50a、60aは、上述の導電部材51aと同様の材料を用いて形成される。これにより、配線パターン50、60及び接続端子50a、60aの形成と、導電部材51aの形成を同時に行うことができるため、製造工程を短縮することができる。なお、導電部材51a、配線パターン50、60及び接続端子50a、60aもまた、スパッタリング法により全領域に導電体膜を成膜した後、エッチングによりパターニングされる。 The wiring patterns 50 and 60 and the connection terminals 50a and 60a are formed using the same material as that of the conductive member 51a. Thereby, since the formation of the wiring patterns 50 and 60 and the connection terminals 50a and 60a and the formation of the conductive member 51a can be performed simultaneously, the manufacturing process can be shortened. The conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are also patterned by etching after forming a conductor film over the entire region by sputtering.
 導電体膜は、上記材料からなる金属層と、金属酸化物層が交互に積層された構成とすると好ましい。この時、導電体膜において、透明基板4から最も遠い位置に形成される層(すなわち、最上層)を金属酸化物層によって形成することにより、配線パターン50、60及び接続端子50a、60a及び導電部材51aにおける反射が抑制され、透明基板4の表側(すなわち、第1の電極パターン20及び第2の電極パターン30が形成されている面)から目視した場合、より視認されにくくなるため好適である。 The conductor film preferably has a structure in which metal layers made of the above materials and metal oxide layers are alternately stacked. At this time, in the conductor film, the wiring pattern 50, 60, the connection terminals 50a, 60a, and the conductive layer are formed by forming a layer (that is, the uppermost layer) formed farthest from the transparent substrate 4 with a metal oxide layer. Reflection in the member 51a is suppressed, and it is preferable because it is less visible when viewed from the front side of the transparent substrate 4 (that is, the surface on which the first electrode pattern 20 and the second electrode pattern 30 are formed). .
 さらに、導電体膜において、透明基板4から最も近い位置に形成される層(すなわち、最下層)を金属酸化物層によって形成することにより、配線パターン50、60及び接続端子50a、60a及び導電部材51aにおける反射が抑制され、透明基板4の裏側(すなわち、第1の電極パターン20及び第2の電極パターン30が形成されていない面)から目視した場合、より視認されにくくなるため好適である。 Furthermore, in the conductor film, a layer (that is, the lowermost layer) formed at a position closest to the transparent substrate 4 is formed of a metal oxide layer, whereby the wiring patterns 50 and 60, the connection terminals 50a and 60a, and the conductive member are formed. The reflection at 51a is suppressed, and when viewed from the back side of the transparent substrate 4 (that is, the surface on which the first electrode pattern 20 and the second electrode pattern 30 are not formed), it is preferable because the reflection is less visible.
 金属酸化物層を構成する材料としては、ITO(Indium Tin Oxide)、Nb、V、Ta、Mo、Ga、Geを添加したITO、IZO(Indium Zinc Oxide)、IGO(Indium Germanium Oxide)等のインジウム複合酸化物が挙げられる。 As a material constituting the metal oxide layer, indium such as ITO (Indium Tin Oxide), ITO added with Nb, V, Ta, Mo, Ga, Ge, IZO (Indium Zinc Oxide), IGO (Indium Germanium Oxide), etc. A composite oxide is mentioned.
 このように、本発明では抵抗値の高い透明導電膜を配線パターン50、60及び接続端子50a、60a及び導電部材51aの材料として用いることなく、金属層(金属薄膜)の単層又は少なくとも1層以上の金属層を含む複層を備えた導電体膜によってこれらの部材を形成する。したがって、消費電力が抑制される。 Thus, in the present invention, a transparent conductive film having a high resistance value is not used as a material for the wiring patterns 50 and 60, the connection terminals 50a and 60a, and the conductive member 51a, but a single layer or at least one layer of a metal layer (metal thin film). These members are formed of a conductor film having a multilayer including the above metal layers. Therefore, power consumption is suppressed.
 さらに、導電体膜を金属層の単層によって形成した場合、導電部材51aの幅を4~10μmとすることにより、視認されにくくなるため、全体として透明性の高い静電容量型入力装置1を提供することができるものである。 Further, when the conductor film is formed of a single metal layer, the width of the conductive member 51a is reduced to 4 to 10 μm, so that it is difficult to see, so that the capacitive input device 1 having high transparency as a whole can be obtained. It can be provided.
 また、導電体膜を少なくとも1層以上の金属層を含む複層によって形成し、少なくとも操作者が視認する側(すなわち、図1の画像表示装置2が配設されていない側)の層を金属酸化物層によって形成することにより、導電部材51aを視認されにくくすることができる。このとき、導電部材51aの幅を7~40μmとすると好ましい。 Further, the conductor film is formed of a multilayer including at least one or more metal layers, and at least the layer on the side visually recognized by the operator (that is, the side on which the image display device 2 in FIG. 1 is not disposed) is made of metal. By forming the oxide layer, the conductive member 51a can be made difficult to be visually recognized. At this time, the width of the conductive member 51a is preferably 7 to 40 μm.
 保護膜71は透明基板4上に配設された各部材の耐環境性を高めると共に、静電容量型入力装置1が外力により変形した際に懸念されるクラックの発生を防ぐ効果を有する。保護膜71には、SiO、Alなどを蒸着法、スパッタリング法、ディッピング法等により形成した絶縁膜、スクリーン印刷法によるポリイミドフィルム等を用いることができる。紫外線等で硬化する感光性樹脂を用いることも可能である。 The protective film 71 enhances the environmental resistance of each member disposed on the transparent substrate 4 and has the effect of preventing the occurrence of cracks that are a concern when the capacitive input device 1 is deformed by an external force. As the protective film 71, an insulating film formed of SiO 2 , Al 2 O 3 or the like by vapor deposition, sputtering, dipping, or the like, a polyimide film by screen printing, or the like can be used. It is also possible to use a photosensitive resin that is cured by ultraviolet rays or the like.
 次に、本発明の実施形態1に係る静電容量型入力装置1に関し、その製造方法を具体的に説明する。
 まず、透明基板4上に、第1透明導電膜21a、第2透明導電膜31a及びその接続部31cを各部同時に成膜する。第1透明導電膜21a、第2透明導電膜31a及びその接続部31cの成膜方法を以下に説明する。
Next, a manufacturing method of the capacitive input device 1 according to the first embodiment of the present invention will be specifically described.
First, the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof are simultaneously formed on the transparent substrate 4. A method of forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c will be described below.
(1.透明導電膜成膜工程)
 静電容量型入力装置1の透明基板4上において、全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて透明導電膜を成膜する。その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、成膜される第1透明導電膜21a、第2透明導電膜31a及びその接続部31cが透明基板4上の適切な位置に配設されるようにマスクを用いて露光する。なおこの時、操作面側から見て、菱形に形成された第1透明導電膜21a、第2透明導電膜31aの一辺がそれぞれ4~8mm、第1透明導電膜21aと第2透明導電膜31aの間隔が50~200μmとなるように設計する。
(1. Transparent conductive film formation process)
On the transparent substrate 4 of the capacitive input device 1, a transparent conductive film is formed over the entire region using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by spin coater or spraying, and the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c to be formed are disposed at appropriate positions on the transparent substrate 4. Then, exposure is performed using a mask. At this time, when viewed from the operation surface side, each side of the first transparent conductive film 21a and the second transparent conductive film 31a formed in a rhombus is 4 to 8 mm, and the first transparent conductive film 21a and the second transparent conductive film 31a. Is designed to be 50 to 200 μm.
 露光後、透明導電膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、第1透明導電膜21a、第2透明導電膜31a及びその接続部31cに相当しない部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の透明導電膜を腐食させ、除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、第1透明導電膜21a、第2透明導電膜31a及びその接続部31cを形成する。 After the exposure, the transparent substrate 4 on which the transparent conductive film is laminated is immersed in a developer so that unnecessary portions (that is, portions that do not correspond to the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof). Remove the photoresist. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the transparent conductive film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, thereby forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c.
 第1透明導電膜21a、第2透明導電膜31a及びその接続部31cの成膜時、透明導電膜材料としてITOを用い、スパッタリング条件は以下の条件とすると好ましい。
[スパッタリング条件]
 DCパワー:2KW、スパッタガス:Ar+O、ガス圧:3mTorr、O/Ar:1~2%、基板温度:250℃
When forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c, ITO is preferably used as the transparent conductive film material, and the sputtering conditions are preferably as follows.
[Sputtering conditions]
DC power: 2 KW, sputtering gas: Ar + O 2 , gas pressure: 3 mTorr, O 2 / Ar: 1 to 2%, substrate temperature: 250 ° C.
 また、露光に用いる光源として超高圧水銀灯、X線、KrFエキシマーレーザー、ArFエキシマーレーザー等を用いることができるが、より微細なパターニングを行うには、短波長のものが望ましい。本実施形態では、オーク製作所製ジェットプリンタ:光源CHM-2000(超高圧水銀灯)を用いた。 Further, as a light source used for exposure, an ultrahigh pressure mercury lamp, X-ray, KrF excimer laser, ArF excimer laser, or the like can be used. However, in order to perform finer patterning, a short wavelength one is desirable. In the present embodiment, a jet printer manufactured by Oak Manufacturing Co., Ltd .: a light source CHM-2000 (super high pressure mercury lamp) was used.
 さらにまた、フォトレジストとしてはポジ型レジストが用いられる。本実施形態ではAZエレクトロニックマテリアルズ(株)製AZRFP-230K2を用いた。東京応化製OFPR-800LBを採用しても良い。
 また、現像液としては有機塩基溶液、無機塩基溶液を用いることができるが、無機塩基溶液の使用時は、金属イオンが混入する可能性があるため、有機塩基溶液を用いると好ましい。具体的には、TMAH(Tetra Methyl Ammonium Hydroxyde)水溶液等が挙げられる。本実施形態では東京応化(株)社製PMERを用いた。さらにこの時、エッチング溶液として、シアン系、王水系、ヨウ素系、シュウ酸系等のエッチング溶液を用いることができる。本実施形態では、硝酸、臭化水素酸、塩化第2鉄溶液を用いた。さらに、フォトレジストを洗浄する溶剤としてはアルカリ溶液が用いられ、好ましくはTMAHを用いる。本実施形態においてもTMAHを用いた。
Furthermore, a positive resist is used as the photoresist. In this embodiment, AZRFP-230K2 manufactured by AZ Electronic Materials Co., Ltd. was used. OFPR-800LB manufactured by Tokyo Ohka may be used.
As the developer, an organic base solution or an inorganic base solution can be used. However, when an inorganic base solution is used, it is preferable to use an organic base solution because metal ions may be mixed. Specifically, TMAH (Tetra Methyl Ammonium Hydroxide) aqueous solution and the like can be mentioned. In the present embodiment, PMER manufactured by Tokyo Ohka Co., Ltd. was used. Further, at this time, an etching solution such as cyan, aqua regia, iodine or oxalic acid can be used as the etching solution. In this embodiment, nitric acid, hydrobromic acid, and a ferric chloride solution are used. Further, an alkaline solution is used as a solvent for cleaning the photoresist, and TMAH is preferably used. TMAH was also used in this embodiment.
 上述のフォトレジスト、現像液、エッチング溶液、溶剤はこの限りではなく、第1透明導電膜21a、第2透明導電膜31a及びその接続部31cを形成する材料に依存し、適宜選択することができる。
 なお、本実施形態においては、比較的安価で大量生産が可能なウェットエッチングによる方法を示したが、ドライエッチングにより第1透明導電膜21a、第2透明導電膜31a及びその接続部31cをパターニングしてもよい。
The above-mentioned photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on the material forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c. .
In the present embodiment, a wet etching method capable of mass production that is relatively inexpensive is shown. However, the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c thereof are patterned by dry etching. May be.
(2.絶縁膜成膜工程)
 第1透明導電膜21a、第2透明導電膜31a及びその接続部31cを成膜した後、絶縁膜21b、31b及び41aを含む絶縁膜(不図示)を、静電容量型入力装置1の透明基板4上において全領域にわたって成膜する。
(2. Insulating film formation process)
After the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c are formed, an insulating film (not shown) including the insulating films 21b, 31b, and 41a is formed as a transparent film of the capacitive input device 1. A film is formed over the entire region on the substrate 4.
 まず、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて絶縁膜(不図示)を成膜する。その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、成膜される接触孔22が透明基板4上の適切な位置に配設されるようにマスクを用いて露光する。露光後、各膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、接触孔22に相当する部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の絶縁膜を除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、接触孔22以外の部分に絶縁膜(絶縁膜21b、31b及び41aを含む全領域)が形成される。
 絶縁膜として感光性の樹脂を用いることもできる。印刷あるいはディッピングによる樹脂の塗布の後、マスクを通しての露光により必要な部分を硬化させ、その後、不要な未硬化部分を除去する。製造工程としては、より簡略化される。
First, an insulating film (not shown) is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by a spin coater or spraying, and exposure is performed using a mask so that the contact holes 22 to be formed are disposed at appropriate positions on the transparent substrate 4. After the exposure, the transparent substrate 4 on which each film is laminated is immersed in a developing solution, thereby removing unnecessary portions of the photoresist (that is, portions corresponding to the contact holes 22). After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution, thereby removing the portion of the insulating film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, whereby an insulating film (all regions including the insulating films 21b, 31b, and 41a) is formed in a portion other than the contact hole 22.
A photosensitive resin can also be used as the insulating film. After application of the resin by printing or dipping, necessary portions are cured by exposure through a mask, and then unnecessary uncured portions are removed. The manufacturing process is further simplified.
 不図示の絶縁膜(絶縁膜21b、31b及び41aを含む全領域)の成膜時、絶縁膜材料としてSiOを用いる場合は、スパッタリング条件は以下の条件とすると好ましい。また、接触孔22の大きさはその一辺を50~200μmとすると好ましい。
[スパッタリング条件]
 DCパワー:5KW、スパッタガス:Ar+O、ガス圧:3~5mTorr、O/Ar:20~40%、基板温度:200℃
When SiO 2 is used as the insulating film material when forming an insulating film (not shown) (all regions including the insulating films 21b, 31b and 41a), the sputtering conditions are preferably set as follows. The size of the contact hole 22 is preferably 50 to 200 μm on one side.
[Sputtering conditions]
DC power: 5 KW, sputtering gas: Ar + O 2 , gas pressure: 3-5 mTorr, O 2 / Ar: 20-40%, substrate temperature: 200 ° C.
 上述のフォトレジスト、現像液、エッチング溶液、溶剤はこの限りではなく、不図示の絶縁膜(絶縁膜21b、31b及び41aを含む全領域)を形成する材料に依存し、適宜選択することができる。
 なお、本実施形態においては、比較的安価で大量生産が可能なウェットエッチングによる方法を示したが、ドライエッチングにより絶縁膜21b、31b及び41aを含む全領域をパターニングしてもよい。
The above-described photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on a material for forming an insulating film (not shown) (all regions including the insulating films 21b, 31b, and 41a). .
In the present embodiment, a wet etching method that is relatively inexpensive and capable of mass production is shown. However, the entire region including the insulating films 21b, 31b, and 41a may be patterned by dry etching.
(3.導電体膜成膜工程)
 不図示の絶縁膜(絶縁膜21b、31b及び41aを含む全領域)を成膜、パターニングした後、導電部材51a、配線パターン50、60及び接続端子50a、60aを形成する。導電部材51a、配線パターン50、60及び接続端子50a、60aは、以下のようにエッチング工程を経ることにより形成する。
(3. Conductor film formation process)
After an insulating film (not shown) (all regions including the insulating films 21b, 31b, and 41a) is formed and patterned, the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed. The conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed through an etching process as follows.
 まず、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて導電体膜を成膜する。このとき、導電体膜として金属層の単層のみを成膜しても良いし、また、金属層を含む複層を成膜しても良い。複層を成膜する場合は、薄膜形成装置内で原料の切り替えを行うことによって各層の構成材料を適宜選択する。そして、操作者の視認側に金属酸化物層が成膜されると共に、金属層と金属酸化物層とが交互に積層されるように薄膜形成装置内で材料を切り替える。 First, a conductor film is formed over the entire area of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like. At this time, only a single metal layer may be formed as the conductor film, or a multilayer including the metal layer may be formed. In the case of forming a multilayer, the constituent materials of each layer are appropriately selected by switching the raw materials in the thin film forming apparatus. Then, the metal oxide layer is formed on the operator's viewing side, and the material is switched in the thin film forming apparatus so that the metal layer and the metal oxide layer are alternately stacked.
 その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、成膜される導電部材51aの幅(図3のy軸方向の長さ)が4~10μm(導電体膜を複層とした場合は7~40μm)、長さ(図3のx軸方向の長さ)が100~300μm程度となるように、且つ配線パターン50、60及び接続端子50a、60aが透明基板4上の適切な位置に配設されるようにマスクを用いて露光する。 Thereafter, a photoresist is applied by spin coater or spraying, and the width of the conductive member 51a to be formed (length in the y-axis direction in FIG. 3) is 4 to 10 μm (in the case where the conductive film is a multilayer). 7 to 40 μm), the length (the length in the x-axis direction in FIG. 3) is about 100 to 300 μm, and the wiring patterns 50 and 60 and the connection terminals 50a and 60a are at appropriate positions on the transparent substrate 4. It exposes using a mask so that it may be arrange | positioned.
 露光後、各膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、導電部材51a、配線パターン50、60及び接続端子50a、60aに相当しない部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の導電体膜を腐食させ、除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、導電部材51a、配線パターン50、60及び接続端子50a、60aを形成する。 After the exposure, the transparent substrate 4 on which each film is laminated is immersed in a developing solution to remove unnecessary portions of the photoresist (that is, portions not corresponding to the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a). Remove. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the conductor film not covered with the photoresist. Then, the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by completely removing the photoresist using a solvent.
 導電部材51a、配線パターン50、60及び接続端子50a、60aの成膜時、導電体膜材料として例えば銀合金を用いた場合、スパッタリング条件は以下の条件とすると好ましい。ただし、導電体膜材料及びその成膜条件はこれに限定されるものではなく、金属層の材料としては金、銀、銅、モリブデン(Mo)、ニオブ(Nb)、アルミ(Al)等の金属を単体、あるいはそれぞれの合金を用いることができ、その成膜条件は適宜設定される。
[スパッタリング条件]
 DCパワー:7KW、スパッタガス:Ar、ガス圧:2~4mTorr、基板温度:100℃
When the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed, for example, when a silver alloy is used as the conductive film material, the sputtering conditions are preferably as follows. However, the conductor film material and the film formation conditions are not limited to this, and the metal layer material is a metal such as gold, silver, copper, molybdenum (Mo), niobium (Nb), aluminum (Al), etc. Can be used alone, or each alloy can be used, and the film forming conditions are set appropriately.
[Sputtering conditions]
DC power: 7 kW, sputtering gas: Ar, gas pressure: 2-4 mTorr, substrate temperature: 100 ° C.
 また、導電体膜を複層で構成する際も、金属層として金、銀、銅、モリブデン(Mo)、ニオブ(Nb)、アルミ(Al)等の金属を単体、あるいはそれぞれの合金を用いることができる。また、金属酸化物層としてITO(Indium Tin Oxide)、Nb、V、Ta、Mo、Ga、Geを添加したITO、IZO(Indium Zinc Oxide)、IGO(Indium Germanium Oxide)等を用いて導電体膜を成膜しても良い。なお、導電体膜の構成に関し、後述で詳細に説明する。 Also, when the conductor film is composed of a plurality of layers, a metal such as gold, silver, copper, molybdenum (Mo), niobium (Nb), and aluminum (Al) is used alone or an alloy thereof. Can do. In addition, a conductive film using ITO (Indium Tin Oxide), ITO added with Nb, V, Ta, Mo, Ga, Ge, IZO (Indium Zinc Oxide), IGO (Indium Germanium Oxide), etc. as a metal oxide layer. May be formed. The configuration of the conductor film will be described in detail later.
 なお、エッチング液はリン酸、硝酸、酢酸のいずれか二つ以上から選ばれる酸の混合液を使用することができる。フォトレジスト、現像液等は上述の透明導電膜成膜工程の場合と同様である。 In addition, the etching liquid can use the liquid mixture of the acid chosen from any two or more of phosphoric acid, nitric acid, and acetic acid. Photoresist, developer, and the like are the same as in the above-described transparent conductive film forming step.
 上述のフォトレジスト、現像液、エッチング溶液、溶剤はこの限りではなく、導電部材51a、配線パターン50、60及び接続端子50a、60aを形成する材料に依存し、適宜選択することができる。
 なお、本実施形態においては、比較的安価で大量生産が可能なウェットエッチングによる方法を示したが、ドライエッチングにより導電部材51a、配線パターン50、60及び接続端子50a、60aを成膜してもよい。
The above-mentioned photoresist, developer, etching solution, and solvent are not limited to this, and can be appropriately selected depending on the material for forming the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a.
In the present embodiment, the wet etching method that is relatively inexpensive and can be mass-produced is shown. However, the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a may be formed by dry etching. Good.
(4.保護膜成膜工程)
 上述のように導電部材51a、配線パターン50、60及び接続端子50a、60aを成膜した後、各膜を積層させた透明基板4上の全面に保護膜71を成膜することにより、静電容量型入力装置1を得る。この時、保護膜71として、SiO、Alなどを蒸着法、スパッタリング法、ディッピング法等により形成した絶縁膜、スクリーン印刷法によるポリイミドフィルムなどが用いられる。好ましくは、耐熱性および耐薬品性が高く、接着性の高いポリイミドフィルムを用いるのがよい。
(4. Protection film deposition process)
After forming the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a as described above, the protective film 71 is formed on the entire surface of the transparent substrate 4 on which the respective films are stacked, thereby A capacitive input device 1 is obtained. At this time, as the protective film 71, an insulating film formed of SiO 2 , Al 2 O 3 or the like by a vapor deposition method, a sputtering method, a dipping method or the like, a polyimide film by a screen printing method, or the like is used. It is preferable to use a polyimide film having high heat resistance and chemical resistance and high adhesion.
[比較例]
 実施形態1の導電部材51aに従来と同様に透明導電膜(ITO膜)を採用したものを比較例とし、実施形態1と抵抗値を比較する。なお、比較例において、導電部材51aを透明導電膜(ITO膜)とした以外、その他の構成は実施形態1と同様の部材配置、材料である。また、実施形態1において、導電部材51aはフルヤ金属製のAPC(銀、パラジウム、銅の合金)薄膜とした。
[Comparative example]
A conductive member 51a according to the first embodiment adopting a transparent conductive film (ITO film) as in the conventional case is used as a comparative example, and the resistance value is compared with the first embodiment. In the comparative example, except for the conductive member 51a being a transparent conductive film (ITO film), the other configurations are the same member arrangement and materials as in the first embodiment. In the first embodiment, the conductive member 51a is an APC (silver, palladium, copper alloy) thin film made of Furuya Metal.
 一般に、抵抗率ρ(Ωcm)と抵抗値R(Ω)の間には以下の式(1)が成り立つ。
  R=(ρ×L)/S・・・(1)
ここで、Lはその導体の長さ(cm)、Sは導体の断面積(cm)を示す。
In general, the following equation (1) is established between the resistivity ρ (Ωcm) and the resistance value R (Ω).
R = (ρ × L) / S (1)
Here, L represents the length (cm) of the conductor, and S represents the cross-sectional area (cm 2 ) of the conductor.
 本発明の実施形態1の導電部材51aにおいて上述の式1を適用すると、その抵抗値Rは約3.5Ωとなる。なおこの時、用いる金属をAPCとし、抵抗率ρ:3.5×10-6Ωcm,導体の長さL:200μm,導体の断面積S:2.0×10-8cm(導電部材51aの幅10μm,厚さ:200nmの時の断面積)とした。 When the above formula 1 is applied to the conductive member 51a of the first embodiment of the present invention, the resistance value R is about 3.5Ω. At this time, the metal used is APC, resistivity ρ: 3.5 × 10 −6 Ωcm, conductor length L: 200 μm, conductor cross-sectional area S: 2.0 × 10 −8 cm 2 (conductive member 51a The width is 10 μm, and the thickness is 200 nm.
 一方、導電部材51aを従来の透明導電膜(ITO)とした比較例において、上述の式1を適用すると、その抵抗値Rは約400Ωとなる。なおこの時、抵抗率ρ:1.5×10-4Ωcm,導体の長さL:200μm,導体の断面積S:7.5×10-9cm(導電部材51aの幅50μm,厚さ:15nmの時の断面積)とした。 On the other hand, in the comparative example in which the conductive member 51a is a conventional transparent conductive film (ITO), when the above equation 1 is applied, the resistance value R is about 400Ω. At this time, resistivity ρ: 1.5 × 10 −4 Ωcm, conductor length L: 200 μm, conductor cross-sectional area S: 7.5 × 10 −9 cm 2 (width of conductive member 51a 50 μm, thickness : Cross-sectional area at 15 nm).
 上述のように、第1透明導電膜21aを接続する導体として、透明導電膜(ITO膜)を用いた場合である比較例と、金属薄膜を用いた場合である本発明の実施形態1は、その抵抗値がそれぞれ400Ω、3.5Ωとなり、実施形態1は抵抗値が大きく減少しており、そのため、静電容量型入力装置1の消費電力を大幅に削減することができる。 As described above, as a conductor connecting the first transparent conductive film 21a, a comparative example in which a transparent conductive film (ITO film) is used, and a first embodiment of the present invention in which a metal thin film is used, The resistance values are 400Ω and 3.5Ω, respectively, and the resistance value in the first embodiment is greatly reduced. Therefore, the power consumption of the capacitive input device 1 can be greatly reduced.
[実施形態2]
 本発明の実施形態2に係る静電容量型入力装置1は、上述の実施形態1における各膜の積層順序(構成)及び形状を変更した以外、対応する各膜は上述の実施形態1(図3及び図4)と同様の材料により構成され、さらに各膜は同様の成膜方法により形成される。以下、図5及び図6を参照し、実施形態1と比較して異なる点を詳細に説明する。
[Embodiment 2]
The capacitance-type input device 1 according to the second embodiment of the present invention is the same as the first embodiment (FIG. 1) except that the stacking order (configuration) and shape of each film in the first embodiment are changed. 3 and FIG. 4), and each film is formed by the same film forming method. Hereinafter, differences from the first embodiment will be described in detail with reference to FIGS. 5 and 6.
 図5は、実施形態2に係る静電容量型入力装置1のパターン図を一部拡大した説明図であり、図6は、図5のB-B線に相当する概略断面図である。 FIG. 5 is a partially enlarged explanatory view of the pattern diagram of the capacitive input device 1 according to the second embodiment, and FIG. 6 is a schematic sectional view corresponding to the line BB in FIG.
 図5において、パッド部21を形成する第1透明導電膜21cは、互いに離間して形成されている一方、隣り合う第1透明導電膜21c同士は導電部材51bによって電気的に接続されている。また、パッド部31を形成する第2透明導電膜31dは接続部31eを介して隣り合って形成された第2透明導電膜31dと連続して形成される。これにより、それぞれ連続した第1の電極パターン20及び第2の電極パターン30が形成される。 In FIG. 5, the first transparent conductive films 21c forming the pad portions 21 are formed apart from each other, while the adjacent first transparent conductive films 21c are electrically connected by the conductive member 51b. Further, the second transparent conductive film 31d forming the pad portion 31 is formed continuously with the second transparent conductive film 31d formed adjacent to each other through the connection portion 31e. Thereby, the continuous 1st electrode pattern 20 and 2nd electrode pattern 30 are formed, respectively.
 そして、第1の電極パターン20に備えられた導電部材51bと、第2の電極パターン30に備えられた接続部31eとは、互いに交差部40において交差する。なお、この時、第1透明導電膜21cが交差部40においてつながっており、第2透明導電膜31dが途切れて離間した構成としてもよい。 The conductive member 51b provided in the first electrode pattern 20 and the connection part 31e provided in the second electrode pattern 30 intersect with each other at the intersection 40. At this time, the first transparent conductive film 21c may be connected at the intersection 40, and the second transparent conductive film 31d may be disconnected and separated.
 実施形態2において、静電容量型入力装置1は、透明基板4上に、導電部材51b、配線パターン50、60及び接続端子50a、60aが成膜されている。この導電部材51b、配線パターン50、60及び接続端子50a、60aは単層の金属層(金属薄膜)又は少なくとも1層以上の金属層を含む複層を備えた導電体膜によって形成される。そして、導電部材51b、配線パターン50、60及び接続端子50a、60aの厚さは単層の場合、30~500nm程度(複層の場合、その合計が200~600nm程度)が好ましく、導電部材51bの幅(図5のy軸方向の長さ)及び長さ(図5のx軸方向の長さ)は実施形態1の導電部材51aと同様とする。 In the second embodiment, in the capacitive input device 1, a conductive member 51b, wiring patterns 50 and 60, and connection terminals 50a and 60a are formed on a transparent substrate 4. The conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by a conductor film including a single metal layer (metal thin film) or a multilayer including at least one metal layer. The thickness of the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a is preferably about 30 to 500 nm in the case of a single layer (the total is about 200 to 600 nm in the case of multiple layers). The width (the length in the y-axis direction in FIG. 5) and the length (the length in the x-axis direction in FIG. 5) are the same as those of the conductive member 51a of the first embodiment.
 導電部材51bの両端には、その一部が重なるようにして第1透明導電膜21cが成膜される。すなわち、導電部材51b上の一部である接触部52bに第1透明導電膜21cの一部が積層することにより、互いに電気的に接続される。第1透明導電膜21c、第2透明導電膜31dの形状及び大きさ、第1透明導電膜21cと第2透明導電膜31dの間隔は、上述の実施形態1と同様とする。 The first transparent conductive film 21c is formed on both ends of the conductive member 51b so that a part thereof overlaps. That is, a part of the first transparent conductive film 21c is laminated on the contact part 52b which is a part on the conductive member 51b, thereby being electrically connected to each other. The shape and size of the first transparent conductive film 21c and the second transparent conductive film 31d and the distance between the first transparent conductive film 21c and the second transparent conductive film 31d are the same as those in the first embodiment.
 導電部材51b上において、第1透明導電膜21cが積層していない部分(すなわち、接触部52b以外の部分)は、絶縁膜41bに覆われている。この絶縁膜41bは、交差部40において、第1の電極パターン20および第2の電極パターン30を、電気的に絶縁するために配設される。したがって、絶縁膜41bは、導電部材51b上において、第1透明導電膜21cが積層していない部分を全て覆う必要はなく、少なくとも第2の電極パターン30における接続部31eと、導電部材51bが絶縁されるように配設されていればよい。 On the conductive member 51b, a portion where the first transparent conductive film 21c is not laminated (that is, a portion other than the contact portion 52b) is covered with the insulating film 41b. The insulating film 41 b is disposed at the intersection 40 to electrically insulate the first electrode pattern 20 and the second electrode pattern 30. Therefore, the insulating film 41b does not need to cover all portions of the conductive member 51b where the first transparent conductive film 21c is not laminated, and at least the connection portion 31e in the second electrode pattern 30 and the conductive member 51b are insulated. What is necessary is just to be arrange | positioned.
 また、絶縁膜41bの大きさは、図5のx軸方向の長さが50~200μm、y軸方向の長さが50~200μm程度とすると良い。この絶縁膜41bの大きさは、上述のように、接続部31eと、導電部材51bが電気的に接続されない範囲とし、その範囲で適宜設計することができる。 Further, the size of the insulating film 41b is preferably about 50 to 200 μm in the x-axis direction and about 50 to 200 μm in the y-axis direction in FIG. As described above, the size of the insulating film 41b is within a range in which the connection portion 31e and the conductive member 51b are not electrically connected, and can be appropriately designed within the range.
 絶縁膜41b上には、パッド部31を形成する第2透明導電膜31d同士を電気的に接続する接続部31eが積層される。なお、この接続部31eもまた、透明導電膜で形成されている。このとき、接続部31eの幅(図5のx軸方向の長さ)は50~200μmとするとよい。 On the insulating film 41b, a connection part 31e for electrically connecting the second transparent conductive films 31d forming the pad part 31 is laminated. The connecting portion 31e is also formed of a transparent conductive film. At this time, the width of the connecting portion 31e (the length in the x-axis direction in FIG. 5) is preferably 50 to 200 μm.
 さらに実施形態2の静電容量型入力装置1においても、実施形態1と同様に、各膜を積層させた透明基板4上の全面は保護膜71により覆われている。 Further, also in the capacitive input device 1 of the second embodiment, the entire surface of the transparent substrate 4 on which the respective films are laminated is covered with the protective film 71 as in the first embodiment.
 次に、本発明の実施形態2に係る静電容量型入力装置1に関し、その製造方法を具体的に説明する。 Next, a manufacturing method for the capacitance-type input device 1 according to Embodiment 2 of the present invention will be specifically described.
(1.導電体膜成膜工程)
 まず、透明基板4上に、以下のように導電部材51b、配線パターン50、60及び接続端子50a、60aを成膜する。
 導電部材51b、配線パターン50、60及び接続端子50a、60aは、以下のようにエッチング工程を経ることにより形成される。まず、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて導電体膜を成膜する。この時、導電体膜としては、実施形態1と同様に、金属層のみを成膜しても良いし、金属層及び金属酸化物層を交互に積層させて成膜しても良い。
(1. Conductor film formation process)
First, the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed on the transparent substrate 4 as follows.
The conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed through an etching process as follows. First, a conductor film is formed over the entire area of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like. At this time, as the conductor film, only the metal layer may be formed as in the first embodiment, or the metal layer and the metal oxide layer may be alternately stacked.
 その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、成膜される導電部材51bの幅(図5のy軸方向の長さ)が4~10μm(導電体膜を複層とした場合は7~40μm)、長さ(図5のx軸方向の長さ)が100~300μm程度となるように、且つ配線パターン50、60及び接続端子50a、60aが透明基板4上の適切な位置に配設されるようにマスクを用いて露光する。露光後、各膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、導電部材51b、配線パターン50、60及び接続端子50a、60aに相当しない部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の導電体膜を腐食させ、除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、導電部材51b、配線パターン50、60及び接続端子50a、60aを形成する。 Thereafter, a photoresist is applied by spin coater or spraying, and the width of the conductive member 51b to be formed (the length in the y-axis direction in FIG. 5) is 4 to 10 μm (when the conductive film is a multilayer) 7 to 40 μm), the length (the length in the x-axis direction in FIG. 5) is about 100 to 300 μm, and the wiring patterns 50 and 60 and the connection terminals 50a and 60a are placed at appropriate positions on the transparent substrate 4. It exposes using a mask so that it may be arrange | positioned. After the exposure, the transparent substrate 4 on which each film is laminated is immersed in a developing solution so that unnecessary portions (that is, portions not corresponding to the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a) are removed. Remove. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the conductor film not covered with the photoresist. Then, the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed by completely removing the photoresist using a solvent.
 この時、成膜条件及びエッチング条件は上述の導電部材51a、配線パターン50、60及び接続端子50a、60aの成膜時と同様である。 At this time, the film forming conditions and the etching conditions are the same as those in forming the conductive member 51a, the wiring patterns 50 and 60, and the connection terminals 50a and 60a.
(2.絶縁膜成膜工程)
 導電部材51b、配線パターン50、60及び接続端子50a、60aを成膜した後、絶縁膜41bを成膜する。絶縁膜41bは、以下のようにエッチング工程を経ることにより形成される。まず、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて不図示の絶縁膜を成膜する。その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、絶縁膜41bが、接続部31eと、導電部材51bが電気的に接続されない範囲に形成されるように、マスクを用いて露光する。露光後、各膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、絶縁膜41bに相当しない部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の絶縁膜を腐食させ、除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、絶縁膜41bを形成する。
 絶縁膜として感光性の樹脂を用いることもできる。印刷あるいはディッピングによる樹脂の塗布の後、マスクを通しての露光により必要な部分を硬化させ、その後、不要な未硬化部分を除去する。製造工程としては、より簡略化される。
(2. Insulating film formation process)
After the conductive member 51b, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are formed, the insulating film 41b is formed. The insulating film 41b is formed through an etching process as follows. First, an insulating film (not shown) is formed over the entire region on the transparent substrate 4 of the capacitive input device 1 by using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by a spin coater or spraying, and exposure is performed using a mask so that the insulating film 41b is formed in a range where the connection portion 31e and the conductive member 51b are not electrically connected. After the exposure, the transparent substrate 4 on which each film is laminated is immersed in a developing solution, thereby removing unnecessary portions of the photoresist (that is, portions not corresponding to the insulating film 41b). After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the insulating film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, thereby forming the insulating film 41b.
A photosensitive resin can also be used as the insulating film. After application of the resin by printing or dipping, necessary portions are cured by exposure through a mask, and then unnecessary uncured portions are removed. The manufacturing process is further simplified.
 この時、成膜条件及びパターニング条件は上述の絶縁膜(絶縁膜21b、31b及び41aを含む全領域)の成膜時と同様である。 At this time, the film formation conditions and the patterning conditions are the same as those in the above-described film formation of the insulating film (all regions including the insulating films 21b, 31b, and 41a).
(3.透明導電膜成膜工程)
 絶縁膜41bを成膜した後、第1透明導電膜21c、第2透明導電膜31d及びその接続部31eを成膜する。第1透明導電膜21c、第2透明導電膜31d及びその接続部31eは、以下のようにエッチング工程を経ることにより形成される。まず、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて透明導電膜を成膜する。
(3. Transparent conductive film deposition process)
After forming the insulating film 41b, the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof are formed. The 1st transparent conductive film 21c, the 2nd transparent conductive film 31d, and its connection part 31e are formed through an etching process as follows. First, a transparent conductive film is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like.
 絶縁膜41bを成膜した後、静電容量型入力装置1の透明基板4上の全領域にわたって真空蒸着法、スパッタリング法、CVD法等を用いて透明導電膜を成膜する。その後、スピンコーターや吹きつけにより、フォトレジストを塗布し、成膜される第1透明導電膜21c、第2透明導電膜31d及びその接続部31eが透明基板4上の適切な位置に配設されるようにマスクを用いて露光する。 After forming the insulating film 41b, a transparent conductive film is formed over the entire region of the transparent substrate 4 of the capacitive input device 1 using a vacuum deposition method, a sputtering method, a CVD method, or the like. Thereafter, a photoresist is applied by spin coater or spraying, and the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e to be formed are disposed at appropriate positions on the transparent substrate 4. Then, exposure is performed using a mask.
 露光後、透明導電膜が積層された透明基板4を現像液に浸すことにより、不要な部分(すなわち、第1透明導電膜21c、第2透明導電膜31d及びその接続部31eに相当しない部分)のフォトレジストを除去する。フォトレジストを除去した後、各膜が積層された透明基板4をエッチング溶液に浸すことにより、フォトレジストに覆われていない部分の透明導電膜を腐食させ、除去する。その後、溶剤を用いてフォトレジストを完全に除去することにより、第1透明導電膜21c、第2透明導電膜31d及びその接続部31eを形成する。 After the exposure, the transparent substrate 4 on which the transparent conductive film is laminated is immersed in a developing solution, so that unnecessary portions (that is, portions that do not correspond to the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof). Remove the photoresist. After removing the photoresist, the transparent substrate 4 on which the respective films are laminated is immersed in an etching solution to corrode and remove the portion of the transparent conductive film not covered with the photoresist. Thereafter, the photoresist is completely removed using a solvent, thereby forming the first transparent conductive film 21c, the second transparent conductive film 31d, and the connection portion 31e thereof.
 この時、成膜条件及びエッチング条件は上述の第1透明導電膜21a、第2透明導電膜31a及びその接続部31cの成膜時と同様である。 At this time, the film formation conditions and the etching conditions are the same as those at the time of forming the first transparent conductive film 21a, the second transparent conductive film 31a, and the connection portion 31c.
(4.保護膜成膜工程)
 上述のように第1透明導電膜21c、第2透明導電膜31d及びその接続部31eを成膜した後、各膜を積層させた透明基板4上の全面に保護膜71を成膜することにより、静電容量型入力装置1を得る。この時、成膜条件は上述の実施形態1における保護膜71の成膜時と同様である。
(4. Protection film deposition process)
After forming the first transparent conductive film 21c, the second transparent conductive film 31d, and the connecting portion 31e as described above, the protective film 71 is formed on the entire surface of the transparent substrate 4 on which the respective films are laminated. The electrostatic capacitance type input device 1 is obtained. At this time, the film formation conditions are the same as those for forming the protective film 71 in the first embodiment.
 次に、配線パターン50、60及び接続端子50a、60a及び導電部材51aを構成する導電体膜の構成に関して詳細に説明する。本発明において、導電体膜は、金属層の単層又は少なくとも1層以上の金属層を含む複層によって構成されている。実施例1-1~実施例1-4、実施例2-1~実施例2-5において各種構成の導電体膜に関し、その反射率のシミュレーションを行った。各実施例における透明基板4上の導電体膜の構成を表1に示すと共に、図7及び図8に各実施例の導電体膜に関する光学特性を示す。 Next, the configuration of the conductive film constituting the wiring patterns 50 and 60, the connection terminals 50a and 60a, and the conductive member 51a will be described in detail. In the present invention, the conductor film is composed of a single metal layer or a multilayer including at least one metal layer. In Example 1-1 to Example 1-4 and Example 2-1 to Example 2-5, the reflectance of the conductive films having various configurations was simulated. The structure of the conductor film on the transparent substrate 4 in each example is shown in Table 1, and the optical characteristics regarding the conductor film in each example are shown in FIGS.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
 表1は、透明基板4としてのガラス基板上に成膜された、各実施例における導電体膜の構成(積層順)を示している。なお、表中の「観測側(視認側)」の欄の矢印は、反射率を計測する側を示しており、各層を積層させたガラス基板において矢印を記載した側の面の反射率を図7及び図8に示している。(例えば、実施例1-3ではガラス基板上に銀合金、IGO、銀合金、IGOの順に積層されており、IGOが成膜された側から観測される反射率を図7に示している。また、実施例1-4ではガラス基板上にIGO、銀合金、IGO、銀合金の順に積層されており、ガラス基板側から観測される反射率を図7に示している。) Table 1 shows the configuration (stacking order) of the conductor films in each example formed on the glass substrate as the transparent substrate 4. In the table, the arrow in the column of “observation side (viewing side)” indicates the side on which the reflectance is measured, and the reflectance of the surface on which the arrow is described in the glass substrate on which each layer is laminated is illustrated. 7 and FIG. (For example, in Example 1-3, the silver alloy, IGO, silver alloy, and IGO are laminated in this order on the glass substrate, and the reflectance observed from the side on which the IGO is formed is shown in FIG. In Example 1-4, IGO, silver alloy, IGO, and silver alloy are laminated in this order on the glass substrate, and the reflectance observed from the glass substrate side is shown in FIG.
 また、表中の各層に関する括弧内の数字は各層の厚さを示している。なお、銀合金、MAMに関し、厚さを示していない場合、これらの層の厚さは適当な抵抗値を得られる範囲であればよく、適宜設計することができる。銀合金であれば50~500nm程度、MAMであれば100~600nm程度とすると好ましい。 Also, the numbers in parentheses for each layer in the table indicate the thickness of each layer. In addition, regarding the silver alloy and MAM, when thickness is not shown, the thickness of these layers should just be the range which can obtain an appropriate resistance value, and can be designed suitably. A silver alloy is preferably about 50 to 500 nm, and a MAM is preferably about 100 to 600 nm.
 図7は実施例1-1~実施例1-4における各波長の光の反射率を示したものである。実施例1-1~実施例1-4は、金属層の材料を銀合金、金属酸化物層の材料をIGOとしている。 FIG. 7 shows the reflectance of light of each wavelength in Examples 1-1 to 1-4. In Examples 1-1 to 1-4, the material of the metal layer is a silver alloy, and the material of the metal oxide layer is IGO.
 実施例1-1及び実施例1-2はガラス基板に銀合金を成膜した場合であり、何れの面を目視側としても、波長が400~700nmの領域において光の反射率は80~98%程度であることが示されている。したがって、導電体膜を金属層の単層とした場合、反射率が高くなり、視認されやすいことから、導電部材51a、51bを形成する際、その幅を4~10μmに設定し、非常に細く形成することで視認しづらくすることができる。 Examples 1-1 and 1-2 are cases in which a silver alloy is formed on a glass substrate. The light reflectance is 80 to 98 in a wavelength range of 400 to 700 nm, regardless of which side is viewed. % Is shown. Therefore, when the conductor film is a single metal layer, the reflectivity is high and it is easy to visually recognize. Therefore, when forming the conductive members 51a and 51b, the width is set to 4 to 10 μm, which is very thin. It can be difficult to visually recognize by forming.
 そして、実施例1-3及び実施例1-4は金属層と金属酸化物層を交互に積層し、視認側に金属酸化物層を成膜した場合であり、金属酸化物層側における光の反射率は、波長が400~700nmの領域において実施例1-1及び実施例1-2よりも低く、約15~64%程度であることが示されている。したがって、導電体膜において、視認側に金属酸化物層を形成することにより視認しづらくすることができる。 In Examples 1-3 and 1-4, metal layers and metal oxide layers are alternately stacked, and a metal oxide layer is formed on the viewing side. It is shown that the reflectance is about 15 to 64%, which is lower than those in Example 1-1 and Example 1-2 in the wavelength region of 400 to 700 nm. Therefore, it is difficult to visually recognize the conductor film by forming a metal oxide layer on the viewing side.
 すなわち、金属層を単層で形成する場合よりも金属酸化物層を視認側に成膜した複層で形成した場合の方が、より高い透明性を得ることができる。したがって金属酸化物層を視認側に成膜した場合、導電部材51a、51bの幅を広く形成しても良好な透明性が得られることから、導電部材51a、51bの幅は7~40μmに設定される。 That is, higher transparency can be obtained when the metal layer is formed as a multilayer having a metal oxide layer formed on the viewing side than when the metal layer is formed as a single layer. Therefore, when the metal oxide layer is formed on the viewing side, good transparency can be obtained even if the width of the conductive members 51a and 51b is wide. Therefore, the width of the conductive members 51a and 51b is set to 7 to 40 μm. Is done.
 図8は実施例2-1~実施例2-5における各波長の光の反射率を示したものである。実施例2-1~実施例2-5では、金属層の材料をMAM又はMo-Nb合金、金属酸化物層の材料をIGOとしている。 FIG. 8 shows the reflectance of light of each wavelength in Examples 2-1 to 2-5. In Examples 2-1 to 2-5, the material of the metal layer is MAM or Mo—Nb alloy, and the material of the metal oxide layer is IGO.
 実施例2-1及び実施例2-2はガラス基板にMAMを成膜した場合であり、何れの面を目視側としても、波長が400~700nmの領域において光の反射率は40~53%程度であることが示されている。したがって、導電体膜を銀合金の単層とした場合よりも反射率は低下し、波長が400nm付近及び650nm付近では、銀合金とIGOを積層させた場合と同程度の反射率を得ることができる。 Examples 2-1 and 2-2 are cases in which MAM is formed on a glass substrate. The light reflectance is 40 to 53% in the wavelength range of 400 to 700 nm regardless of which side is viewed. It is shown to be a degree. Therefore, the reflectivity is lower than when the conductor film is a single layer of silver alloy, and at the wavelength near 400 nm and near 650 nm, the reflectivity comparable to that obtained when the silver alloy and IGO are laminated can be obtained. it can.
 さらに、MAMに金属酸化物膜を組み合わせて成膜した場合(実施例2-3~実施例2-5)は、400~700nmの波長範囲において非常に低い反射率を呈する。特に実施例2-4及び実施例2-5は、400~700nmの波長範囲の全域に渡って10%以下(約3~8%程度)の反射率であることから、非常に視認性が低く、高い透明性を備えていることが示されている。 Further, when a metal oxide film is combined with MAM (Example 2-3 to Example 2-5), it exhibits a very low reflectance in the wavelength range of 400 to 700 nm. In particular, Example 2-4 and Example 2-5 have a reflectance of 10% or less (about 3 to 8%) over the entire wavelength range of 400 to 700 nm, so the visibility is very low. It has been shown to have high transparency.
 したがって実施例1-1~実施例1-4、実施例2-1~実施例2-5により、導電体膜において、視認側に金属酸化物層を形成した時、視認側の光の反射率が低下し、その結果、高い透明性を備えた導電体膜とすることが可能であることが示された。 Therefore, according to Examples 1-1 to 1-4 and Examples 2-1 to 2-5, when the metal oxide layer is formed on the viewing side in the conductor film, the light reflectance on the viewing side is determined. As a result, it was shown that a conductive film having high transparency can be obtained.
 上述のように、本発明の静電容量型入力装置1は、第1の電極パターン20及び第2の電極パターン30の交差部40において電気的に絶縁されている。そして、第1の電極パターン20において、離間して成膜された第1透明導電膜21a、21cを接続する導電部材51a、51bと、配線パターン50、60及び接続端子50a、60aが導電体膜で構成されている。したがって、導電部材51a、51bは、配線パターン50、60及び接続端子50a、60aと同時に成膜することが可能であるため、製造工程を簡素化することができる。また導電部材51a、51bは、透明導電膜を用いて形成する場合と比較して、その抵抗値が小さく、静電容量型入力装置1の消費電力を低減することができる。 As described above, the capacitive input device 1 of the present invention is electrically insulated at the intersection 40 of the first electrode pattern 20 and the second electrode pattern 30. In the first electrode pattern 20, the conductive members 51a and 51b that connect the first transparent conductive films 21a and 21c formed separately from each other, the wiring patterns 50 and 60, and the connection terminals 50a and 60a are conductor films. It consists of Therefore, since the conductive members 51a and 51b can be formed simultaneously with the wiring patterns 50 and 60 and the connection terminals 50a and 60a, the manufacturing process can be simplified. In addition, the conductive members 51a and 51b have a smaller resistance value than the case where the conductive members 51a and 51b are formed using a transparent conductive film, and can reduce the power consumption of the capacitive input device 1.
 本発明の静電容量型入力装置1は、携帯電話、電子手帳等の携帯端末(PDA、Personal Digital Assistant)、ゲーム機、カーナビゲーション、パーソナルコンピュータ、券売機、銀行の端末等の電子機器分野において有用であると期待される。 The capacitance-type input device 1 of the present invention is used in the field of electronic equipment such as mobile terminals (PDA, Personal Digital Assistant) such as mobile phones and electronic notebooks, game machines, car navigation systems, personal computers, ticket vending machines, and bank terminals. Expected to be useful.

Claims (12)

  1.  入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置であって、
     前記出力部は、前記信号を出力する接続端子と、前記入力部と前記接続端子とを電気的に接続する配線パターンと、を有し、
     前記入力部は、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜と、該第1透明導電膜を電気的に接続する導電部材と、で構成される複数の第1の電極パターンと、
     前記第1方向と交差する第2方向に隣り合って配設される複数の第2透明導電膜と、
    該複数の第2透明導電膜と連続して形成されると共に前記導電部材と交差する位置に配設される接続部と、で構成される複数の第2の電極パターンと、
     前記導電部材と前記接続部との間に配設され、前記導電部材と前記接続部との絶縁を維持する絶縁膜と、を有し、
     前記導電部材と前記接続端子と前記配線パターンとは同一の導電体膜によって形成され、
     該導電体膜は、金属層の単層又は少なくとも1層以上の金属層を含む複層からなり、
     前記導電部材は、線状に形成されていることを特徴とする静電容量型入力装置。
    An electrostatic capacity including an input unit for performing an input operation and an output unit for outputting a signal from the input unit, wherein the input unit and the output unit are provided on the same surface of the transparent substrate. A mold input device,
    The output unit includes a connection terminal that outputs the signal, and a wiring pattern that electrically connects the input unit and the connection terminal.
    The input unit includes a plurality of first transparent conductive films disposed adjacent to each other in the first direction on the transparent substrate, and a conductive member that electrically connects the first transparent conductive films. A plurality of first electrode patterns;
    A plurality of second transparent conductive films disposed adjacent to each other in a second direction intersecting the first direction;
    A plurality of second electrode patterns comprising a connection portion formed continuously with the plurality of second transparent conductive films and disposed at a position intersecting with the conductive member;
    An insulating film disposed between the conductive member and the connection portion and maintaining insulation between the conductive member and the connection portion;
    The conductive member, the connection terminal and the wiring pattern are formed by the same conductor film,
    The conductor film is composed of a single metal layer or a multilayer including at least one metal layer,
    The capacitive input device, wherein the conductive member is formed in a linear shape.
  2.  前記導電体膜は前記金属層の単層からなり、前記導電部材の前記第2方向の幅が4~10μmであることを特徴とする請求項1に記載の静電容量型入力装置。 2. The capacitance-type input device according to claim 1, wherein the conductor film is made of a single layer of the metal layer, and the width of the conductive member in the second direction is 4 to 10 μm.
  3.  前記導電体膜は金属層と金属酸化物層とが交互に積層された複層からなり、
     前記導電体膜において、前記金属酸化物層が、視認側に形成されてなることを特徴とする請求項1に記載の静電容量型入力装置。
    The conductor film is composed of multiple layers in which metal layers and metal oxide layers are alternately stacked,
    The capacitance-type input device according to claim 1, wherein the metal oxide layer is formed on the viewer side in the conductor film.
  4.  前記導電部材の前記第2方向の幅が7~40μmであることを特徴とする請求項3に記載の静電容量型入力装置。 4. The capacitance-type input device according to claim 3, wherein a width of the conductive member in the second direction is 7 to 40 μm.
  5.  前記金属層の材料は、銀、銀合金、銅、銅合金、MAM(MoもしくはMo合金/AlもしくはAl合金/MoもしくはMo合金の3層構造化合物)より選択されるいずれかの金属であることを特徴とする請求項1乃至4のいずれか一項に記載の静電容量型入力装置。 The material of the metal layer is any metal selected from silver, silver alloy, copper, copper alloy, and MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound). The capacitance-type input device according to any one of claims 1 to 4.
  6.  前記金属層の材料は、銀、銀合金、銅、銅合金、MAM(MoもしくはMo合金/AlもしくはAl合金/MoもしくはMo合金の3層構造化合物)より選択されるいずれかの金属であり、
     前記金属酸化物層は、インジウム複合酸化物が含有されてなることを特徴とする請求項3又は4に記載の静電容量型入力装置。
    The material of the metal layer is any metal selected from silver, silver alloy, copper, copper alloy, MAM (Mo or Mo alloy / Al or Al alloy / Mo or Mo alloy three-layer structure compound),
    5. The capacitive input device according to claim 3, wherein the metal oxide layer contains an indium composite oxide.
  7.  前記導電部材と前記接続部の交差部において、
     前記透明基板上に、前記導電部材と、前記絶縁膜と、前記接続部とが、この順に積層されてなることを特徴とする請求項1乃至6のいずれか一項に記載の静電容量型入力装置。
    At the intersection of the conductive member and the connection part,
    The capacitance type according to any one of claims 1 to 6, wherein the conductive member, the insulating film, and the connection portion are laminated in this order on the transparent substrate. Input device.
  8.  入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置の製造方法であって、
     前記透明基板上の全面に、透明導電膜を成膜する透明導電膜成膜工程と、
     前記透明導電膜に対し、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜と、前記第1方向と交差する第2方向に配設される複数の第2透明導電膜と、該複数の第2透明導電膜と連続して形成される接続部と、をエッチングして形成する透明導電膜パターニング工程と、
     前記透明基板上の全面に、絶縁膜を成膜する絶縁膜成膜工程と、
     前記絶縁膜をパターニングして、前記第1透明導電膜上において、前記第2透明導電膜と連続して形成される接続部を介在させて両側に接触孔を形成する接触孔形成工程と、
     前記透明基板上の全面に、金属層の単層又は少なくとも1層以上の金属層を含む複層からなる導電体膜を成膜する導電体膜成膜工程と、
     前記導電体膜に対し、前記出力部が前記信号を出力するために備えられる接続端子と、該接続端子と前記入力部とを接続する配線パターンと、前記複数の第1透明導電膜を電気的に接続すると共に前記接続部と交差する位置に配設される線状の導電部材と、をエッチングすることにより形成する導電体膜パターニング工程と、
     を備えることを特徴とする、静電容量型入力装置の製造方法。
    An electrostatic capacity including an input unit for performing an input operation and an output unit for outputting a signal from the input unit, wherein the input unit and the output unit are provided on the same surface of the transparent substrate. A method of manufacturing a mold input device,
    A transparent conductive film forming step of forming a transparent conductive film on the entire surface of the transparent substrate;
    A plurality of first transparent conductive films disposed adjacent to the transparent conductive film in a first direction on the transparent substrate, and a plurality of first transparent films disposed in a second direction intersecting the first direction. A transparent conductive film patterning step formed by etching two transparent conductive films and a connection portion formed continuously with the plurality of second transparent conductive films;
    An insulating film forming step of forming an insulating film on the entire surface of the transparent substrate;
    A contact hole forming step of patterning the insulating film and forming contact holes on both sides of the first transparent conductive film with a connection portion formed continuously with the second transparent conductive film;
    A conductor film forming step of forming a conductor film composed of a single metal layer or a multilayer including at least one metal layer on the entire surface of the transparent substrate;
    Electrically connecting a connection terminal provided for the output unit to output the signal to the conductor film, a wiring pattern connecting the connection terminal and the input unit, and the plurality of first transparent conductive films. A conductive film patterning step that is formed by etching a linear conductive member that is connected to the connecting portion and disposed at a position intersecting with the connecting portion;
    A method for manufacturing a capacitance-type input device.
  9.  入力操作が行われる入力部と、該入力部からの信号を出力するための出力部と、を有し、前記入力部及び前記出力部が、透明基板の同一面上に備えられた静電容量型入力装置の製造方法であって、
     前記透明基板上の全面に、金属層の単層又は少なくとも1層以上の金属層を含む複層からなる導電体膜を成膜する導電体膜成膜工程と、
     前記導電体膜に対し、前記出力部が前記信号を出力するために備えられる接続端子と、該接続端子と前記入力部とを接続する配線パターンと、前記透明基板上の第1方向に隣り合って配設される複数の第1透明導電膜を電気的に接続すると共に前記第1方向に沿って形成される線状の導電部材と、をエッチングして形成する導電体膜パターニング工程と、
     前記透明基板上の全面に、絶縁膜を成膜する絶縁膜成膜工程と、
     前記絶縁膜において、前記導電部材と、前記第2方向に隣り合って配設される複数の第2透明導電膜と連続して形成されると共に前記導電部材と交差する位置に配設される接続部と、を絶縁する位置以外の部分を除去する絶縁膜パターニング工程と、
     前記透明基板上の全面に、透明導電膜を成膜する透明導電膜成膜工程と、
     前記透明導電膜に対し、前記第1透明導電膜と、複数の前記第2透明導電膜と、前記接続部と、をエッチングして形成する透明導電膜パターニング工程と、
     を備えることを特徴とする、静電容量型入力装置の製造方法。
    An electrostatic capacity including an input unit for performing an input operation and an output unit for outputting a signal from the input unit, wherein the input unit and the output unit are provided on the same surface of the transparent substrate. A method of manufacturing a mold input device,
    A conductor film forming step of forming a conductor film composed of a single metal layer or a multilayer including at least one metal layer on the entire surface of the transparent substrate;
    Adjacent to the conductor film in the first direction on the transparent substrate, a connection terminal provided for the output unit to output the signal, a wiring pattern for connecting the connection terminal and the input unit, A conductive film patterning step for electrically connecting a plurality of first transparent conductive films disposed in a line and etching a linear conductive member formed along the first direction;
    An insulating film forming step of forming an insulating film on the entire surface of the transparent substrate;
    In the insulating film, the conductive member and a plurality of second transparent conductive films disposed adjacent to each other in the second direction are formed continuously and are disposed at positions intersecting with the conductive member. An insulating film patterning step for removing a portion other than the position for insulating the portion;
    A transparent conductive film forming step of forming a transparent conductive film on the entire surface of the transparent substrate;
    A transparent conductive film patterning step of etching the first transparent conductive film, the plurality of second transparent conductive films, and the connection portion with respect to the transparent conductive film;
    A method for manufacturing a capacitance-type input device.
  10.  前記導電体膜成膜工程において、前記金属層の単層を成膜し、
     前記導電体膜パターニング工程において、前記導電部材の前記第2方向の幅が4~10μmとなるように形成することを特徴とする請求項8又は9に記載の静電容量型入力装置の製造方法。
    In the conductor film forming step, forming a single layer of the metal layer,
    10. The method of manufacturing a capacitive input device according to claim 8, wherein, in the conductor film patterning step, the conductive member is formed to have a width in the second direction of 4 to 10 μm. .
  11.  前記導電体膜成膜工程において、最初又は最後に金属酸化物層を成膜する工程を備えると共に、
     前記金属層を成膜する工程と、前記金属酸化物層を成膜する工程とを交互に備えることを特徴とする請求項8又は9に記載の静電容量型入力装置の製造方法。
    In the conductor film forming step, including a step of forming a metal oxide layer first or last,
    10. The method of manufacturing a capacitive input device according to claim 8, comprising alternately forming the metal layer and forming the metal oxide layer. 11.
  12.  前記導電体膜パターニング工程において、前記導電部材の前記第2方向の幅が7~40μmとなるように形成することを特徴とする請求項11に記載の静電容量型入力装置の製造方法。 12. The method of manufacturing a capacitive input device according to claim 11, wherein, in the conductor film patterning step, the conductive member is formed to have a width in the second direction of 7 to 40 μm.
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