WO2010111834A1 - Diode électroluminescente quasi-verticale - Google Patents

Diode électroluminescente quasi-verticale Download PDF

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Publication number
WO2010111834A1
WO2010111834A1 PCT/CN2009/071129 CN2009071129W WO2010111834A1 WO 2010111834 A1 WO2010111834 A1 WO 2010111834A1 CN 2009071129 W CN2009071129 W CN 2009071129W WO 2010111834 A1 WO2010111834 A1 WO 2010111834A1
Authority
WO
WIPO (PCT)
Prior art keywords
metal
electrode
light emitting
quasi
electrode contact
Prior art date
Application number
PCT/CN2009/071129
Other languages
English (en)
Inventor
Limin Lin
Hung-Shen Chu
Ka Wah Chan
Original Assignee
Hong Kong Applied Science and Technology Research Institute Co. Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hong Kong Applied Science and Technology Research Institute Co. Ltd filed Critical Hong Kong Applied Science and Technology Research Institute Co. Ltd
Priority to CN200980000034.8A priority Critical patent/CN101681877B/zh
Priority to PCT/CN2009/071129 priority patent/WO2010111834A1/fr
Publication of WO2010111834A1 publication Critical patent/WO2010111834A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0016—Processes relating to electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Definitions

  • the present invention relates to semiconductor devices, and more particularly, to a light emitting diode and method of making a light emitting diode.
  • LEDs Light emitting diodes
  • N nitrogen
  • LEDs are currently one of the most innovative and fastest growing technologies in the semiconductor industry. While LEDs have been in use for decades as indicators and for signaling purposes, technology developments and improvements have allowed for a broader use of LEDs in illumination applications.
  • Semiconductors that contain nitrogen (N) as the Group V element have proven to be useful for short-wavelength light emitting devices. Among these, extensive research has been conducted on gallium-nitride based semiconductors for use as light emitting diodes, such as In x GaI - X N and Al x Ga y ln z N, and such light emitting diodes (LEDs) have already been put to practical use.
  • LLO laser lift off
  • the sapphire also can be removed by mechanical methods, including grinding, lapping and mechanical chemical polishing (CMP), but the difficulty in planar mounting and uniform polishing within several microns make it difficult to use of this mechanical method and achieve reliable device performance and high yield.
  • method of making quasi-vertical light emitting devices includes providing a growth substrate; growing a plurality of semiconductor layers on the growth substrate; etching the plurality of semiconductor layers to produce device isolation trenches forming a plurality of separable semiconductor devices and a plurality of holes; drilling a plurality of blind holes in the sapphire substrate at the location of each of the plurality of holes in the plurality of semiconductor layer, the plurality of blind holes drilled to a predetermined depth, wherein the drilling defines blind hole walls and a blind hole end in each of the plurality of blind holes; depositing n-semiconductor metal in each of the plurality of blind holes; forming an n-electrode contact in each of the plurality of blind holes by plating each of the plurality of blind holes with an n-electrode metal, the n-electrode metal connected to the n-semiconductor metal; thinning the sapphire substrate to expose the
  • method of making quasi-vertical light emitting devices includes providing a sapphire substrate; growing a plurality of semiconductor layers on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer, and a p-GaN layer; etching the plurality of semiconductor layers to produce device isolation trenches forming a plurality of separable semiconductor devices; etching the plurality of semiconductor layers to provide at least one hole in the plurality of semiconductor layers, the at least one hole etched to the sapphire substrate; etching an n-mesa in the active layer and the p-GaN layer; drilling at least one blind hole in the sapphire substrate at the location of the at least one hole in the plurality of semiconductor layer, the at least one sapphire hole drilled to a predetermined depth, wherein the drilling defines blind hole walls in each of the at least one blind hole; depositing a p-metal on the p-GaN layer
  • a quasi-vertical light emitting device includes a sapphire substrate; a plurality of semiconductor layers grown on the sapphire substrate, the plurality of semiconductor layers including an n-GaN layer, an active layer, and a p-GaN layer; a plurality of holes etched in the plurality of semiconductor layers, each of the plurality of holes etched to the sapphire substrate, and a plurality of sapphire holes in the sapphire substrate, each of the plurality of holes aligned with one of the plurality of sapphire holes to form hole walls, the hole walls plated with an n-metal and each of the plurality of holes filled with an n-metal to form an n-electrode contact; an n-mesa in the active layer and the p-GaN layer, the n-mesa plated with an n-metal and a passivation layer grown over the n-metals;
  • FIG. 1 is a partial plan view of a semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 2 is side cross sectional view of the semiconductor structure shown in FIG. 1 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 3 is side cross sectional view of the semiconductor structure shown in FIG. 1 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 4 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 5 is side cross sectional view of the semiconductor structure shown in FIG. 4 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 6 is side cross sectional view of the semiconductor structure shown in FIG. 4 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 7 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 8 is side cross sectional view of the semiconductor structure shown in
  • FIG. 7 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 9 is side cross sectional view of the semiconductor structure shown in
  • FIG. 7 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 10 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 11 is side cross sectional view of the semiconductor structure shown in
  • FIG. 10 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 12 is side cross sectional view of the semiconductor structure shown in
  • FIG. 10 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 13 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 14 is side cross sectional view of the semiconductor structure shown in
  • FIG. 13 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 15 is side cross sectional view of the semiconductor structure shown in
  • FIG. 13 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 16 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 17 is side cross sectional view of the semiconductor structure shown in
  • FIG. 16 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 18 is side cross sectional view of the semiconductor structure shown in
  • FIG. 16 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 19 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 20 is side cross sectional view of the semiconductor structure shown in
  • FIG. 19 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 21 is side cross sectional view of the semiconductor structure shown in FIG. 19 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 22 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 23 is side cross sectional view of the semiconductor structure shown in FIG. 22 taken at line A, in accordance with an embodiment of the present invention.
  • FIG. 24 is side cross sectional view of the semiconductor structure shown in FIG. 22 taken at line B, in accordance with an embodiment of the present invention.
  • FIG. 25 is a partial plan view of the semiconductor structure, in accordance with an embodiment of the present invention.
  • FIG. 26 is side cross sectional view of the semiconductor structure shown in FIG. 25 taken at line A, in accordance with an embodiment of the present invention.
  • embodiments of the present invention are directed to a quasi-vertical light emitting diode (quasi-VLED).
  • quasi-VLED quasi-vertical light emitting diode
  • blind holes are drilled into the growth substrate for the forming of an n-electrode contact. Therefore, complete removal of the growth substrate is not required to expose the n-electrode contact.
  • FIGS. 1 to 26 illustrate an example process for fabricating a semiconductor structure for use as a quasi-vertical light emitting diode.
  • the method includes providing a growth substrate; growing a plurality of semiconductor layers on the growth substrate; etching the plurality of semiconductor layers to produce device isolation trenches forming a plurality of separable semiconductor devices and a plurality of holes; drilling, by laser or dry etching, a plurality of blind holes in the sapphire substrate from semiconductor layer side, having the plurality of semiconductor layers, the plurality of holes drilled to a predetermined depth, wherein the drilling defines blind hole walls in each of the plurality of blind holes; and depositing metals by, for example, E-beam or sputtering to form ohmic contacts to the n-type semiconductor.
  • FIG. 1 is a partial plan view of a semiconductor structure, in accordance with an embodiment of the present invention.
  • the semiconductor structure is any suitable semiconductor wafer or substrate.
  • FIG. 2 is side cross sectional view of the semiconductor structure shown in FIG.
  • FIG. 3 is side cross sectional view of the semiconductor structure shown in FIG. 1 taken at line A, and FIG. 3 is side cross sectional view of the semiconductor structure shown in FIG. 1 taken at line B, in accordance with an embodiment of the present invention.
  • the semiconductor structure shown includes a sapphire substrate 110, an undoped and doped n-GaN layer 112 grown on the sapphire substrate 110, an active layer 114 having multiple quantum wells grown on the n-GaN layer 112, and a p-GaN layer 116 is grown on the active layer 114.
  • Mesa isolation is used to separate the semiconductor into separate dies 118. While four separate dies 118, are shown, FIG. 1 is only a partial view of the semiconductor structure and any suitable number of dies may be formed using embodiments of the present invention.
  • Etching is also performed to define a plurality of holes 120 in the n-GaN layer 112, the active layer 114, and the p-GaN layer 116.
  • Two holes 120 are formed in each die 118 as an n-electrode bonding area.
  • the holes are shown as having a square shape but may have any suitable shape and location as needed by the specific device requirements.
  • FIGS. 4 to 6 FIG. 4 is a partial plan view of the semiconductor structure, FIG. 5 is side cross sectional view of the semiconductor structure shown in FIG. 4 taken at line A, and FIG. 6 is side cross sectional view of the semiconductor structure shown in FIG. 4 taken at line B, in accordance with an embodiment of the present invention.
  • An n-mesa 400 is etched into the active layer 114 and the p-GaN layer 118.
  • the n-mesa 400 may be etched by ICP (inductively coupled plasma) etching or any other suitable etching method.
  • FIGS. 7 to 26 illustrate a single die of the four shown in the semiconductor structure illustrated in FIGS. 1 to 6. However, any number of components may be similarly fabricated during the illustrated and described process.
  • FIGS. 7 to 9 FIG. 7 is a partial plan view of the semiconductor structure
  • FIG. 8 is side cross sectional view of the semiconductor structure shown in FIG. 7 taken at line A, in accordance with an embodiment of the present invention
  • FIG. 9 is side cross sectional view of the semiconductor structure shown in FIG. 7 taken at line B, in accordance with an embodiment of the present invention.
  • a plurality of sapphire holes 700 are formed in to the sapphire layer 110.
  • sapphire drilling is performed by laser, dry etching, wet etching, or any other suitable method, to a predetermined depth at each of the locations where one of the holes 120 was etched.
  • a suitable depth is greater than 5 um.
  • a suitable depth is greater than 10 um.
  • one suitable depth is 30 um.
  • these are example depths, and other depths may be used depending on the specific requirements of the device.
  • FIG. 10 is a partial plan view of the semiconductor structure
  • FIG. 11 is side cross sectional view of the semiconductor structure shown in FIG. 10 taken at line A
  • FIG. 12 is side cross sectional view of the semiconductor structure shown in FIG. 10 taken at line B, in accordance with an embodiment of the present invention.
  • a p-metal 1000 is deposited on the p-GaN layer, for example, by E-beam and lift-off.
  • One example p-metal is Ni/Au.
  • other suitable metals may be used.
  • FIG. 13 is a partial plan view of the semiconductor structure
  • FIG. 14 is side cross sectional view of the semiconductor structure shown in FIG. 13 taken at line A
  • FIG. 15 is side cross sectional view of the semiconductor structure shown in FIG. 13 taken at line B, in accordance with an embodiment of the present invention.
  • An n-metal 1300 is deposited in the n-mesa 400 shown and described with reference to FIGS. 4 to 6.
  • the n-metal 1300 is also deposited along walls and an end of the plurality of sapphire holes 700.
  • the n-metal 1300 is deposited, for example, by E-beam and lift-off.
  • One example n-metal is Ti/AI/Ti/Au.
  • FIG. 16 is a partial plan view of the semiconductor structure
  • FIG. 17 is side cross sectional view of the semiconductor structure shown in FIG. 16 taken at line A
  • FIG. 18 is side cross sectional view of the semiconductor structure shown in FIG. 16 taken at line B, in accordance with an embodiment of the present invention.
  • Via/hole plating is performed to form an electrode contact 1600.
  • the via/hole plating is performed by electroless plating or electro-plating, or any other suitable method to fill metal inside of the holes.
  • One suitable metal is, for example, Ni or Cu.
  • FIG. 19 is a partial plan view of the semiconductor structure
  • FIG. 20 is side cross sectional view of the semiconductor structure shown in FIG. 19 taken at line A
  • FIG. 21 is side cross sectional view of the semiconductor structure shown in FIG. 19 taken at line B, in accordance with an embodiment of the present invention.
  • a passivation layer 1900 is grown to cover all n metals so that now only the p metal is exposed.
  • the passivation layer is a SiO 2 passivation layer.
  • FIG. 22 is a partial plan view of the semiconductor structure
  • FIG. 23 is side cross sectional view of the semiconductor structure shown in FIG. 22 taken at line A
  • FIG. 24 is side cross sectional view of the semiconductor structure shown in FIG. 22 taken at line B, in accordance with an embodiment of the present invention.
  • a p-electrode 2200 is applied to the p-metal 1000 as a host substrate before sapphire substrate 110 is thinned.
  • Cu is plated to the p-metal 1000.
  • Si is bonded to the p-metal 1000.
  • other conductive materials may be applied using any suitable method.
  • FIG. 25 is a partial plan view of the sapphire side of the semiconductor structure
  • FIG. 26 is side cross sectional view of the semiconductor structure shown in FIG. 25 taken at line A, in accordance with an embodiment of the present invention.
  • the sapphire substrate 110 is thinned using a grinding, lapping, chemical mechanical polishing (CMP) or other suitable thinning method to expose the electrode contact 1600.
  • CMP chemical mechanical polishing
  • the electrode contact 1600 is then exposed for contact with an n-electrode.
  • the other side of the semiconductor structure has the p-electrode 2200.
  • the semiconductor structure may then be diced into separate light emitting diodes.
  • the quasi-vertical light emitting diodes made according to embodiments of the present invention may use vertical LED packaging, and avoid the need for any new, complex packaging process.
  • mirrors can be added to reflect the light to the sapphire side of the device. Light extraction can also be improved by texturing the light emitting surface of the device.
  • Embodiments of the present invention provide a number of advantages over the prior art. For example, according to one embodiment, because the contact area between the p-electrode layer 2200, which is a good thermal and electrical conductor, and the active layer 114 is large, the heat dissipation and current spreading of p-GaN will be good, especially when compared to a flip-chip LED, which has gaps and can have less heat dissipation. Also, the Ohmic contact for the n-GaN layer may connect with conductive metals, such as Cu or Ni, along the side walls of the sapphire holes 700.
  • the ohmic contact metal (n-metal 1300) for the n-GaN layer 112 is connected to the n-GaN layer 112 on the same side of the n-GaN layer 112 as the electrode metals (p-metal 1000) for the p-GaN layer 116. Therefore, the complete removal of the sapphire substrate 110 is not necessary.
  • the uniformity tolerance for mechanical thinning is decided by the depth of the hole drilled or etched into sapphire, and the tolerance is therefore greater than that required for the complete removal of sapphire. According to one embodiment, the mechanical thinning is stopped before reaching the active layer or before getting close to the active layer, so the performance of device will not be degraded by the mechanical damage and the yield can be improved.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

L'invention porte sur un dispositif électroluminescent quasi-vertical. La diode électroluminescente quasi-verticale comprend un substrat en saphir (110) ; une pluralité de couches semi-conductrices développées sur le substrat en saphir (110), la pluralité de couches semi-conductrices comprenant une couche n-GaN (112), une couche active (114) et une couche p-GaN (116) ; une pluralité de trous gravés dans la pluralité de couches semi-conductrices, chacun de la pluralité de trous (120) étant gravé jusqu'au substrat en saphir (110), et une pluralité de trous de saphir (700) dans le substrat en saphir, chacun de la pluralité de trous (120) étant aligné avec l'un de la pluralité de trous de saphir (700) afin de former des parois de trou, les parois et le fond du trou recevant un dépôt de métal n (1300) et chacun de la pluralité de trous (120) étant rempli d'un autre métal afin de former un contact d'électrode n ; une structure mesa-n dans la couche active (114) et la couche p-GaN (116), la structure mesa-n étant recevant un dépôt de métal n (1300) et une couche de passivation (1900) développée au-dessus du métal n (1300) ; et une couche de métal p (1000) déposée sur la couche p-GaN (116), et une électrode p (2200) liée au métal p (1000).
PCT/CN2009/071129 2009-04-01 2009-04-01 Diode électroluminescente quasi-verticale WO2010111834A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200980000034.8A CN101681877B (zh) 2009-04-01 2009-04-01 准垂直结构发光二极管
PCT/CN2009/071129 WO2010111834A1 (fr) 2009-04-01 2009-04-01 Diode électroluminescente quasi-verticale

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2009/071129 WO2010111834A1 (fr) 2009-04-01 2009-04-01 Diode électroluminescente quasi-verticale

Publications (1)

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WO2010111834A1 true WO2010111834A1 (fr) 2010-10-07

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2012091008A1 (ja) * 2010-12-28 2014-06-05 日亜化学工業株式会社 半導体発光装置

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201340396A (zh) * 2012-03-23 2013-10-01 Chi Mei Lighting Tech Corp 發光二極體元件及其製造方法
CN111653653B (zh) * 2020-06-17 2021-10-22 京东方科技集团股份有限公司 一种发光器件及其制作方法、显示面板

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527409A (zh) * 2003-03-05 2004-09-08 中国科学院半导体研究所 小尺寸氮化镓基蓝、绿色发光二极管管芯的制作方法
JP2006100475A (ja) * 2004-09-29 2006-04-13 Toyoda Gosei Co Ltd 半導体発光素子
US7285431B2 (en) * 2004-09-30 2007-10-23 Institute Of Semiconductors, Chinese Academy Of Sciences Method for manufacturing a GaN based LED of a black hole structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1527409A (zh) * 2003-03-05 2004-09-08 中国科学院半导体研究所 小尺寸氮化镓基蓝、绿色发光二极管管芯的制作方法
JP2006100475A (ja) * 2004-09-29 2006-04-13 Toyoda Gosei Co Ltd 半導体発光素子
US7285431B2 (en) * 2004-09-30 2007-10-23 Institute Of Semiconductors, Chinese Academy Of Sciences Method for manufacturing a GaN based LED of a black hole structure

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2012091008A1 (ja) * 2010-12-28 2014-06-05 日亜化学工業株式会社 半導体発光装置
JP5786868B2 (ja) * 2010-12-28 2015-09-30 日亜化学工業株式会社 半導体発光装置

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CN101681877A (zh) 2010-03-24
CN101681877B (zh) 2011-09-28

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