WO2011073886A1 - Substrat pour un dispositif électroluminescent semi-conducteur - Google Patents

Substrat pour un dispositif électroluminescent semi-conducteur Download PDF

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Publication number
WO2011073886A1
WO2011073886A1 PCT/IB2010/055783 IB2010055783W WO2011073886A1 WO 2011073886 A1 WO2011073886 A1 WO 2011073886A1 IB 2010055783 W IB2010055783 W IB 2010055783W WO 2011073886 A1 WO2011073886 A1 WO 2011073886A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
semiconductor structure
light emitting
holes
attaching
Prior art date
Application number
PCT/IB2010/055783
Other languages
English (en)
Inventor
Fabrice Jerome Letertre
Original Assignee
Koninklijke Philips Electronics N.V.
Philips Lumileds Lighting Company, Llc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V., Philips Lumileds Lighting Company, Llc filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2011073886A1 publication Critical patent/WO2011073886A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
    • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
    • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Definitions

  • the present invention is directed to methods of attaching a light emitting device to a substrate then processing the substrate.
  • LEDs light emitting diodes
  • RCLEDs resonant cavity light emitting diodes
  • VCSELs vertical cavity laser diodes
  • edge emitting lasers are among the most efficient light sources currently available.
  • Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as Ill-nitride materials.
  • Ill-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, Ill-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p-type regions.
  • a package typically includes a thermally conductive plate with electrical conductors running from the die attach region to the package terminals.
  • the p and n layers of the LED are electrically connected to the package conductors.
  • the support substrate is metal bonded to the package, providing a current path to the n or p-type LED layers adjacent to the support substrate, and the opposite conductivity type layers are connected via a wire (e.g., a wire ribbon) to a package contact pad.
  • both n and p-connections are formed by die attaching to multiple contact pads patterned to mate to the n and p-contact metallizations on the die. No wires are required.
  • a semiconductor structure comprising a light emitting layer disposed between an n-type region and a p-type region is grown on a first substrate.
  • the semiconductor structure is attached to a top surface of a second substrate.
  • the second substrate includes a body with a plurality of holes filled with a conductive material. After attaching the semiconductor structure to the second substrate, the body is thinned from the bottom surface of the second substrate, such that a bottom surface of the holes is exposed.
  • attaching the semiconductor structure to a substrate with conductive vias permits wafer- level processing of the semiconductor structure and the substrate. Heat may be conducted away from the semiconductor structure by the conductive vias.
  • Fig. 1 illustrates LEDs grown on a growth substrate.
  • Fig. 2 illustrates the LEDs of Fig. 1 attached to a substrate with conductive vias.
  • Fig. 3 illustrates removing the growth substrate from the structure of Fig. 2.
  • Fig. 4 illustrates thinning the substrate of Fig. 3 to expose the bottom of the conductive vias.
  • Fig. 5 illustrates an LED and substrate attached to a mount.
  • Fig. 6 illustrates an LED, substrate with through vias, and substrate with integrated circuitry attached to a mount.
  • a semiconductor light emitting device is bonded to a substrate with conductive through-vias.
  • the substrate supports the semiconductor light emitting device to prevent breakage during wafer-level processing.
  • the through-vias may conduct heat away from the light emitting device during operation.
  • Fig. 1 illustrates a Ill-nitride device 12 and portions of two other devices grown on a growth substrate 10. Only a portion of the growth substrate 10 is shown. Multiple LEDs are grown on a single growth substrate. A growth substrate may be, for example, on the order of centimeters in diameter. Each LED may be, for example, about 1 mm long. Growth substrate 10 may be, for example, a sapphire, SiC, Si, composite, or any other suitable substrate. Composite substrates are described in more detail in US 2007/0072324, which is incorporated herein by reference.
  • the semiconductor structure of the device includes an n-type region 42, a light emitting or active region 44, and a p-type region 46.
  • An n-type region 42 is grown first on substrate 10.
  • the n-type region may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, which may be n-type or not intentionally doped, release layers designed to facilitate later release of the growth substrate or thinning of the semiconductor structure after substrate removal, and n- or even p-type device layers designed for particular optical or electrical properties desirable for the light emitting region to efficiently emit light.
  • a light emitting or active region 44 is grown over the n-type region 42.
  • suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick quantum well light emitting layers separated by barrier layers.
  • a p-type region 46 is grown over the light emitting region 44.
  • the p-type region may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers.
  • a metal p-contact 50 is formed on the p-type region.
  • P-contact 50 may include one or more metal layers such as, for example, a reflective layer, such as silver, an ohmic contact layer, and a guard layer. Portions of the p-contact 50, the p-type region 46, and the light emitting region 44 of the semiconductor structure are etched away to expose portions of the n-type region.
  • N-contacts 52 are formed on the exposed portions of the n-type region. The n- and p-contacts 52 and 50 may be separated by a gap 54, which may be filled with an insulating material such as a suitable dielectric.
  • a single large p-contact may be formed on the top surface of the semiconductor structure in the orientation illustrated in Fig. 1.
  • a contact to the n-type region is formed on a surface of the n-type region exposed after removing the growth substrate, as described below in reference to Fig. 3.
  • Trenches 48 may be formed between individual devices 12.
  • Metal bond pads, not shown in Fig. 1 may be formed over n- and p-contacts 52 and 50.
  • one or both of p-contacts 50 and n-contacts 52 are reflective, and light is extracted from the device through the surface of the semiconductor opposite the contacts, the bottom surface of the semiconductor structure illustrated in Fig. 1.
  • Substrate 24 may include vias or holes 22 filled with a conductive material such as metal formed in a non-metallic body 20.
  • the material of body 20 may be selected for ease of forming vias and ease of thinning, as described below. Examples of suitable materials include silicon and ceramics such as A1N.
  • Vias 22 in a silicon substrate 20 may be formed by
  • Vias 22 may be, for example, between 10 and 100 microns deep in some embodiments, between 30 and 70 microns deep in some embodiments, and 50 microns deep in some embodiments. Vias 22 may be filled with any suitable conductive material formed by any suitable technique. In some embodiments, copper is electroplated into the vias.
  • LEDs 12 are attached to substrate 24 by, for example, a metallic bond or any other suitable bonding technique.
  • copper bond pads may be formed on LEDs 12 and substrate 24 then directly bonded pad to pad. Dielectric regions which insulate the n- and p-type pads may be formed between the copper bonds pads. In some embodiments, there is no air gap between the bonded pads.
  • LEDs 12 are attached to substrate 24 by solder or other metal interconnects, which may include multiple layers of materials.
  • interconnects between LEDs 12 and substrate 24 include at least one gold layer and the bond between the LEDs 12 and the substrate 24 is formed by ultrasonic bonding, or molecular bonding between mating surfaces. LEDs 12 are aligned on substrate 24 such that vias 22 are electrically connected to n- and p-contacts 52 and 50, shown in Fig. 1.
  • all or part of the growth substrate 10 may be removed by a technique appropriate to the growth substrate, as illustrated in Fig. 3.
  • a sapphire growth substrate may be removed by laser lift off, which may permit reuse of the growth substrate.
  • a silicon substrate may be removed by grinding, etching, polishing or a combination of these techniques.
  • a transparent substrate may remain part of the device.
  • additional LED processing may be performed, such as surface etching, cleaning, or deposition of dielectric layers, for example.
  • the semiconductor structure remaining after removing the host substrate is thinned, for example by photoelectrochemical etching.
  • the semiconductor surface may be roughened or patterned, for example with a photonic crystal structure. Since the entire wafer of LEDs 12 is connected to substrate 24, conventional wafer-scale tools may be used for processing after the growth substrate is removed.
  • the top surface of the wafer of LEDs 12 may be attached to handling tape 28, as is known in the art of semiconductor processing.
  • the substrate 24 may be thinned by conventional techniques such as etching, grinding, or polishing, which remove material from the bottom surface of the substrate.
  • Substrate 24 is thinned to a thickness suitable for mechanical handling, and at least until the bottoms 22a of vias 22 are exposed.
  • substrate 24 permits wafer-level processing on both the front side (for example, removing the LED growth substrate and thinning the LED semiconductor structure) and back side (for example, thinning the substrate 24 to expose the vias) of the structure.
  • the substrate 24 may be diced at locations 30 between individual LEDs 12.
  • Mount 34 may be, for example, a silicon, ceramic, or AIN mount, a silicon mount with through vias as described above, a printed circuit board, or any other structure on which LED 12 and substrate 24 may be mounted.
  • Conductive vias 22 in substrate 24 may align with vias 32 in mount 34.
  • Vias 32 in mount 34 may be formed in, for example, a silicon structure 30.
  • integrated circuits such as those required for, for example, efficient driving, feedback control, and electrostatic discharge protection, are formed in a substrate with conductive through-vias, as illustrated in Fig. 6.
  • integrated circuitry 40 may be formed in a silicon body before or after vias 38 are formed.
  • a wavelength converting material which absorbs light emitted by the light emitting region and emits light of one or more different peak wavelengths, may be disposed over the LED 12 illustrated in Figs. 5 and 6.
  • polarizers, dichroic filters or other optics known in the art are formed over the LED or over the wavelength converting material.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Devices (AREA)

Abstract

La présente invention concerne une structure semi-conductrice comprenant une couche électroluminescente disposée entre une région de type n et une région de type p, ladite structure étant mise à croître sur un premier substrat. La structure semi-conductrice est fixée à une surface supérieure d'un second substrat. Le second substrat comprend un corps doté d'une pluralité de trous remplis d'un matériau conducteur. Une fois que la structure semi-conductrice est fixée au second substrat, le corps est aminci depuis la surface inférieure du second substrat, de sorte qu'une surface inférieure des trous soit exposée.
PCT/IB2010/055783 2009-12-18 2010-12-13 Substrat pour un dispositif électroluminescent semi-conducteur WO2011073886A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP09306264 2009-12-18
EP09306264.4 2009-12-18

Publications (1)

Publication Number Publication Date
WO2011073886A1 true WO2011073886A1 (fr) 2011-06-23

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Family Applications (1)

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PCT/IB2010/055783 WO2011073886A1 (fr) 2009-12-18 2010-12-13 Substrat pour un dispositif électroluminescent semi-conducteur

Country Status (2)

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TW (1) TW201143170A (fr)
WO (1) WO2011073886A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013021305A1 (fr) * 2011-08-10 2013-02-14 Koninklijke Philips Electronics N.V. Traitement d'un niveau tranche de del divisant une tranche de support
WO2013057668A1 (fr) * 2011-10-19 2013-04-25 Koninklijke Philips Electronics N.V. Tranche à del collée à une tranche porteuse pour un traitement sur tranche
US9172213B2 (en) 2012-03-14 2015-10-27 Koninklijke Philips N.V. VCSEL module and manufacture thereof

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201324705A (zh) * 2011-12-08 2013-06-16 Genesis Photonics Inc 電子元件

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501893A (en) 1992-12-05 1996-03-26 Robert Bosch Gmbh Method of anisotropically etching silicon
WO2005091388A1 (fr) * 2004-03-18 2005-09-29 Matsushita Electric Industrial Co., Ltd. Base de nitrure conduit avec une injection de type p
US20070072324A1 (en) 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc Substrate for growing a III-V light emitting device
DE102006043843A1 (de) * 2005-09-23 2007-04-19 Samsung Electro-Mechanics Co., Ltd., Suwon Verfahren zur Herstellung einer Leuchtdiode mit vertikaler Struktur
US7256483B2 (en) 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
US20080029761A1 (en) * 2006-08-01 2008-02-07 Peng Jing Through-hole vertical semiconductor devices or chips
US20080296627A1 (en) * 2007-05-30 2008-12-04 Nichia Corporation Nitride semiconductor device and method of manufacturing the same
WO2010111821A1 (fr) * 2009-03-30 2010-10-07 Hong Kong Applied Science And Technology Research Institute Co., Ltd Substrat hôte pour dispositifs électroluminescents à base de nitrure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5501893A (en) 1992-12-05 1996-03-26 Robert Bosch Gmbh Method of anisotropically etching silicon
WO2005091388A1 (fr) * 2004-03-18 2005-09-29 Matsushita Electric Industrial Co., Ltd. Base de nitrure conduit avec une injection de type p
US7256483B2 (en) 2004-10-28 2007-08-14 Philips Lumileds Lighting Company, Llc Package-integrated thin film LED
DE102006043843A1 (de) * 2005-09-23 2007-04-19 Samsung Electro-Mechanics Co., Ltd., Suwon Verfahren zur Herstellung einer Leuchtdiode mit vertikaler Struktur
US20070072324A1 (en) 2005-09-27 2007-03-29 Lumileds Lighting U.S., Llc Substrate for growing a III-V light emitting device
US20080029761A1 (en) * 2006-08-01 2008-02-07 Peng Jing Through-hole vertical semiconductor devices or chips
US20080296627A1 (en) * 2007-05-30 2008-12-04 Nichia Corporation Nitride semiconductor device and method of manufacturing the same
WO2010111821A1 (fr) * 2009-03-30 2010-10-07 Hong Kong Applied Science And Technology Research Institute Co., Ltd Substrat hôte pour dispositifs électroluminescents à base de nitrure

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013021305A1 (fr) * 2011-08-10 2013-02-14 Koninklijke Philips Electronics N.V. Traitement d'un niveau tranche de del divisant une tranche de support
WO2013057668A1 (fr) * 2011-10-19 2013-04-25 Koninklijke Philips Electronics N.V. Tranche à del collée à une tranche porteuse pour un traitement sur tranche
US9172213B2 (en) 2012-03-14 2015-10-27 Koninklijke Philips N.V. VCSEL module and manufacture thereof

Also Published As

Publication number Publication date
TW201143170A (en) 2011-12-01

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