WO2013021305A1 - Traitement d'un niveau tranche de del divisant une tranche de support - Google Patents

Traitement d'un niveau tranche de del divisant une tranche de support Download PDF

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Publication number
WO2013021305A1
WO2013021305A1 PCT/IB2012/053848 IB2012053848W WO2013021305A1 WO 2013021305 A1 WO2013021305 A1 WO 2013021305A1 IB 2012053848 W IB2012053848 W IB 2012053848W WO 2013021305 A1 WO2013021305 A1 WO 2013021305A1
Authority
WO
WIPO (PCT)
Prior art keywords
led
wafer
layer
vias
carrier
Prior art date
Application number
PCT/IB2012/053848
Other languages
English (en)
Inventor
Marc Andre De Samber
Eric Cornelis Egbertus Van Grunsven
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2013021305A1 publication Critical patent/WO2013021305A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/483—Containers
    • H01L33/486—Containers adapted for surface mounting

Definitions

  • This invention relates to light emitting diodes (LEDs) and, in particular, to a method of employing a carrier wafer for wafer level processing of LEDs.
  • LEDs light emitting diodes
  • a wafer containing many semiconductor LEDs is diced, and the individual LED dies are mounted on a submount wafer. Electrodes on the LEDs are bonded to metal pads on the top surface of the submount wafer. The metal pads on the top surface typically lead to robust metal pads on the bottom surface of the submount wafer for eventual bonding to a circuit board. Prior to the LEDs being mounted on the submount wafer, the submount wafer is fully processed to incorporate its various electrical interconnections.
  • the LED dies on the submount wafer are then further processed using wafer level processing.
  • wafer level processing typically includes removing the growth substrate (e.g., sapphire for GaN LEDs), roughening the exposed semiconductor layer for increasing light extraction, and forming encapsulating lenses over the LEDs.
  • the submount wafer is then diced to separate out the individual LEDs/submounts.
  • the LEDs are flip-chips, having both electrodes on the bottom surface of the LED.
  • the invention also applies to other types of LEDs.
  • a carrier wafer that contains holes (vias) formed through or partially through the wafer.
  • the wafer is silicon.
  • a dielectric layer e.g., silicone dioxide or silicon nitride
  • the wafer is thinned so that the holes are through-holes.
  • the LED wafer prior to dicing, is then aligned with and affixed to the carrier wafer using a polymer or other adhesive material.
  • the metal electrodes on the bottom surface of the LEDs are aligned with the holes in the carrier wafer.
  • the polymer exposed through the holes is etched away to expose the LEDs' metal electrodes.
  • a seed layer, such as copper, is then formed in the holes and over the bottom surface of the carrier wafer.
  • the seed layer is then electroplated with copper.
  • the plated copper at least partially fills the holes so as to make electrical contact with the LED electrodes and also forms a copper layer on the bottom surface of the carrier wafer.
  • the plated copper and copper seed layer may be patterned (to isolate the p and n metal electrodes) by etching the copper after the plating process.
  • photoresist is patterned on the seed layer to define areas that are not to be plated and, after the plating process, the photoresist is removed and the underlying seed layer is etched away.
  • Solder mask material is then patterned over the bottom surface of the carrier to define areas of the copper layer that will resist solder.
  • Metal pads such as formed of Ni and Au, are then formed over the exposed copper layer to protect the copper from oxidation and enable good wetting by solder when the surface mount LEDs are eventually soldered to a printed circuit board.
  • the top surface of the LED wafer may be subject to wafer level processing. Such wafer level processing includes removing the growth substrate (e.g., sapphire for GaN LEDs), roughening the exposed semiconductor layer for increasing light extraction, and forming encapsulating lenses over the LEDs.
  • the carrier wafer and LED wafer are then diced to form individual LEDs. Very little carrier wafer material is wasted, since the carrier dice are the same size as the LED dice.
  • the resulting LEDs may be surface mounted onto a thermally conductive printed circuit board (PCB). There is a direct metal thermal path between the semiconductor layers, the LED electrodes, the plated copper layer on the carrier, and the PCB.
  • the carrier wafer can be made very thin to provide a very short thermal path.
  • the carrier wafer may be formed to contain integrated electronics for each LED, such as ESD protection devices, controllers, sensors, or other circuitry.
  • Fig. 1 is a simplified top down view of a carrier wafer with a plurality of holes (vias) formed in it.
  • the vias may be blind vias or through-hole vias.
  • Fig. 2 is a simplified top down view of an LED wafer with a plurality of LEDs formed in it. Bottom electrodes of the LEDs align with the vias in the carrier wafer.
  • Fig. 3 is a cross-sectional view of a portion of the carrier wafer along line 3-3 in Fig. 1, illustrating two vias for a single LED.
  • Fig. 4 is a cross-sectional view of a portion of the carrier wafer along line 3-3 (Fig. 1) and a portion of the LED wafer along line 4-4 (Fig. 2) being aligned before wafer bonding.
  • Fig. 5 illustrates the two wafers bonded together using a thin polymer layer or other suitable adhesive.
  • Fig. 6 illustrates the polymer layer exposed though the vias being etched away to expose the metal electrodes of the LEDs.
  • Fig. 7 illustrates a seed layer deposited over the LED electrodes, the sidewalls of the vias, and the bottom surface of the carrier wafer.
  • Fig. 8 illustrates the seed layer being plated with copper and then patterned to isolate the p electrode from the n electrode.
  • the copper layer may be patterned in various other ways.
  • Fig. 9 illustrates a solder mask material patterned to expose portions of the copper layer for locating bonding pads and illustrates the bonding pads electrically contacting the copper layer.
  • Fig. 10 illustrates a single LED, after the carrier wafer and LED wafer have been diced, being soldered to metal pads on a printed circuit board.
  • Fig. 1 is a simplified top down view of a carrier wafer 10.
  • the carrier wafer 10 may be silicon, a ceramic, or any other suitable material. Silicon is preferred since it can be made very thin and will be used in the example.
  • Vias 12 are etched into the surface of the wafer 10 using conventional photolithographic techniques. In one embodiment, the wafer 10 has a diameter of 6 inches and is approximately 650 microns thick. The vias 12 are etched as blind vias with a depth of greater than 200 microns. The wafer 10 is then thinned to about 200 microns, such as by chemical-mechanical polishing (CMP), to cause the blind vias 12 to extend completely through the wafer 10.
  • CMP chemical-mechanical polishing
  • the Si carrier wafer 10 is then oxidized using conventional techniques, or a nitride layer may be formed over its exposed surfaces. This forms a thin dielectric layer over the surfaces of the wafer 10, including over the sidewalls of the vias 12. If the carrier wafer material is a dielectric, no dielectric layer needs to be formed.
  • the carrier wafer 12 is silicon and has formed in it integrated electronics for each LED, such as ESD protection devices, controllers, sensors, or other circuitry.
  • the circuitry may be formed surrounding the vias 12 and may be formed using conventional IC fabrication processes.
  • Fig. 2 is a simplified top down view of an LED wafer 16.
  • the LED wafer 16 will typically be the same size as the carrier wafer 10. Areas 18 on the wafer 16 correspond to individual LEDs that align with sets of the vias 12 in Fig. 1.
  • the LEDs are GaN-based LEDs, such as an AlInGaN or InGaN LEDs, for producing blue light.
  • a relatively thick n-type GaN layer is grown on a sapphire growth substrate using conventional techniques.
  • the relatively thick GaN layer typically includes a low temperature nucleation layer and one or more additional layers so as to provide a low-defect lattice structure for the n-type cladding layer and active layer.
  • One or more n-type cladding layers are then formed over the thick n-type layer, followed by an active layer, one or more p-type cladding layers, and a p-type contact layer (for
  • portions of the p-layers and active layer are etched away to expose the n-layer for metallization. In this way, the p contact and n contact are on the same side of the chip. Current from the n-metal contact initially flows laterally through the n-layer.
  • the LED bottom electrodes are typically formed of a reflective metal.
  • Fig. 3 is a cross-sectional view of a portion of the carrier wafer 10 along line 3-3 in Fig. 1 , illustrating two vias 12 for a single LED.
  • the surface of the silicon 20, as well as the surface internal to the vias 12, is shown covered with a dielectric layer 22, such as oxide or nitride.
  • Fig. 4 is a cross-sectional view of a portion of the carrier wafer 10 along line 3-3 in Fig. 1 and a portion of the LED wafer 16 along line 4-4 in Fig. 2 being aligned before wafer bonding.
  • the growth substrate 24 may be sapphire, SiC, GaN, or other material used to grow epitaxial layers for forming a GaN-based LED. Also shown are the LED's n-layer 26, active layer 28, p-layer 30, p-contact layer 32, dielectric layers 34 for electrical insulation and mechanical support, and metal electrodes 36 and 38 electrically contacting the p-layer 30 and n-layer 26, respectively.
  • LEDs n-layer 26 active layer 28, p-layer 30, p-contact layer 32, dielectric layers 34 for electrical insulation and mechanical support, and metal electrodes 36 and 38 electrically contacting the p-layer 30 and n-layer 26, respectively.
  • Various techniques for forming the LED wafer 16 in Fig. 4 are well known.
  • a thin polymer bond layer 50 is applied to either the bottom surface of the LED wafer 16 or the top surface of the carrier wafer 10.
  • the polymer bond layer 50 may be spun on.
  • the wafers 10 and 16 are then aligned.
  • the wafers 10 and 16 are then pressed together at an elevated temperature to cure the bond layer 50.
  • the resulting bond layer 50 may have a thickness of about 10 microns.
  • the CTE and other characteristics of the bond layer 50 material should be selected so that there is no delamination at the typically high operating temperatures of the LED.
  • the bond layer 50 is a BCB (bisbenzocyclobutene) resin or may be another suitable adhesive.
  • BCB uses a cure temperature above 200°C.
  • Other suitable adhesives include 2K silicones or 2K epoxy materials, only needing low temperatures to cure. By using low temperature-curing adhesives, warpage effects in the stack can be reduced.
  • the vias 12 are used as masks, and the bonding layer 50 exposed through the vias 12 is etched away using conventional techniques. In one embodiment, dry etching is used. The openings in the bonding layer 50 will thus be the same size as the vias 12. The bottom surface of the carrier wafer 10 is then cleaned.
  • a very thin seed layer 54 is then deposited over the carrier wafer 10 to cover the exposed electrodes 36/38 of the LED wafer 16, the sidewalls of the vias 12, and the surface of the carrier 10.
  • the seed layer 54 may be deposited by sputtering, evaporation, or other technique.
  • the seed layer 54 may comprise a first layer of TiW or TiN for improved adhesion and to act as a barrier layer to Cu atom migration, (and a second layer of copper.) ??
  • Fig. 8 illustrates the seed layer 54 being electroplated with copper to form a relatively thick copper layer 56.
  • the copper layer 56 and underlying seed layer 54 are then patterned, using conventional photolithographic and etching processes, as shown in Fig. 8, to isolate the p electrode 57 from the n electrode 58.
  • Plating a seed layer with copper is a well known process.
  • the thickness of the copper layer 56 is selected to carry the required LED current with negligible voltage drop. In one embodiment, the copper layer 56 is thicker than 10 microns.
  • the copper layer 56 may be patterned in various other ways. In one such alternative way, a patterned photoresist layer may be formed over the seed layer 54. Only the exposed portions of the seed layer 54 will then be plated with the copper layer 56. The photoresist layer is then stripped away, and the exposed seed layer 54 is then etched away to electrically isolate the portions of the copper layer 56, shown in Fig. 8.
  • Fig. 9 illustrates a solder mask material 60 patterned to expose portions of the copper layer 56.
  • the solder mask material 60 resists solder and is well known. If the vias 12 are not filled during the plating process, the solder mask material 60 may fill the vias 12.
  • a metal protection layer forming bonding pads 64 and 66 is then formed over the exposed copper layer 56 for protecting the copper from oxidation and to enable good wetting by solder when the surface mount LEDs are eventually soldered to a printed circuit board.
  • the bonding pads 64/66 may instead be formed prior to the solder mask being formed.
  • the bonding pads 64/66 may be formed by a Ni layer followed by an Au layer.
  • An electroless process, a sputtering process, or other deposition process may be used to form the bonding pads 64/66. Any other metal interconnection pattern may be formed if desired, such as for interconnecting LEDs.
  • the LED wafer 16 may be wafer processed, as shown in Fig. 9.
  • Some suitable wafer processes include removing the sapphire growth substrate by CMP or laser lift-off, roughening of the exposed n-layer 26 for improving light extraction, molding a phosphor and/or encapsulating lenses over the LEDs, etc.
  • the carrier wafer 10 provides mechanical support for the thin LED wafer 16 during the wafer level processing.
  • the carrier wafer 10 and LED wafer 16 are diced, such as by sawing, to form individual surface mount packages.
  • Fig. 10 illustrates a single LED, after the carrier wafer 10 and LED wafer 16 have been diced, being soldered to metal pads 74 and 76 on a printed circuit board (PCB) 78.
  • the board 78 is a metal core board for conducting heat away from the LED.
  • the soldering may be performed by refiow, or using a solder paste, or another technique. In another embodiment, ultrasonic bonding is used.
  • the heat generated by the LED is efficiently transferred from the semiconductor layers to the board 78 via the bonding pads 64 and 66, the LED metal electrodes 36/38, and the copper layer 56.
  • the copper layer 56 is self-aligned to the LED electrodes 36/38 for maximum heat transference.
  • the carrier wafer 10 may be made thin so there is only a short metal thermal path directly from the semiconductor layers to the PCB 78.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

Une tranche de DEL (16) comprend des couches semi-conductrices et des électrodes de DEL (34) sur une surface inférieure de la tranche de DEL. Une tranche de support (10), telle que du silicium, possède des trous d'interconnexion (12) formés dans celle-ci avant sa liaison à la tranche de DEL. La tranche de DEL est ensuite liée à la tranche de support à l'aide d'une couche de liaison polymère (50), les trous d'interconnexion étant alignés avec les électrodes de DEL. La couche de liaison exposée par les trous d'interconnexion est ensuite éliminée par gravure. Une couche d'ensemencement (54) est ensuite déposée sur la tranche de support, qui entre électriquement en contact avec les électrodes de DEL par l'intermédiaire des trous d'interconnexion. La couche d'ensemencement est ensuite recouverte de cuivre, et des motifs sont formés sur le cuivre pour former n et p électrodes (56, 58). Un masque de soudure (60) est ensuite formé sur la couche métallique, et des plages de soudure (64, 66) sont formées sur la couche métallique exposée pour une liaison par montage en surface à une carte de circuit thermoconductrice.
PCT/IB2012/053848 2011-08-10 2012-07-27 Traitement d'un niveau tranche de del divisant une tranche de support WO2013021305A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161521783P 2011-08-10 2011-08-10
US61/521,783 2011-08-10

Publications (1)

Publication Number Publication Date
WO2013021305A1 true WO2013021305A1 (fr) 2013-02-14

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013110853A1 (de) * 2013-10-01 2015-04-02 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterchip und Verfahren zur Herstellung von strahlungsemittierenden Halbleiterchips

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029599A2 (fr) * 2003-09-24 2005-03-31 Matsushita Electric Works, Ltd. Dispositif photoluminescent et son procede de fabrication
US20050285130A1 (en) * 2004-06-24 2005-12-29 Min-Hsun Hsieh Light emitting diode having an adhesive layer and manufacturing method thereof
US20060006404A1 (en) * 2004-06-30 2006-01-12 James Ibbetson Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
US20060278885A1 (en) * 2005-06-14 2006-12-14 Industrial Technology Research Institute LED wafer-level chip scale packaging
US20070148911A1 (en) * 2005-12-28 2007-06-28 Industrial Technology Research Institute Wafer bonding method
US20070202623A1 (en) * 2005-10-28 2007-08-30 Gelcore Llc Wafer level package for very small footprint and low profile white LED devices
US20070284602A1 (en) * 2004-06-30 2007-12-13 Ashay Chitnis Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US20080035935A1 (en) * 2006-08-11 2008-02-14 Shum Frank T Surface mountable chip
DE102009053064A1 (de) * 2009-11-13 2011-05-19 Osram Opto Semiconductors Gmbh Dünnfilm-Halbleiterbauelement mit Schutzdiodenstruktur und Verfahren zur Herstellung eines Dünnfilm-Halbleiterbauelements
WO2011073886A1 (fr) * 2009-12-18 2011-06-23 Koninklijke Philips Electronics N.V. Substrat pour un dispositif électroluminescent semi-conducteur

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005029599A2 (fr) * 2003-09-24 2005-03-31 Matsushita Electric Works, Ltd. Dispositif photoluminescent et son procede de fabrication
US20050285130A1 (en) * 2004-06-24 2005-12-29 Min-Hsun Hsieh Light emitting diode having an adhesive layer and manufacturing method thereof
US20060006404A1 (en) * 2004-06-30 2006-01-12 James Ibbetson Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
US20070284602A1 (en) * 2004-06-30 2007-12-13 Ashay Chitnis Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US20060278885A1 (en) * 2005-06-14 2006-12-14 Industrial Technology Research Institute LED wafer-level chip scale packaging
US20070202623A1 (en) * 2005-10-28 2007-08-30 Gelcore Llc Wafer level package for very small footprint and low profile white LED devices
US20070148911A1 (en) * 2005-12-28 2007-06-28 Industrial Technology Research Institute Wafer bonding method
US20080035935A1 (en) * 2006-08-11 2008-02-14 Shum Frank T Surface mountable chip
DE102009053064A1 (de) * 2009-11-13 2011-05-19 Osram Opto Semiconductors Gmbh Dünnfilm-Halbleiterbauelement mit Schutzdiodenstruktur und Verfahren zur Herstellung eines Dünnfilm-Halbleiterbauelements
WO2011073886A1 (fr) * 2009-12-18 2011-06-23 Koninklijke Philips Electronics N.V. Substrat pour un dispositif électroluminescent semi-conducteur

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013110853A1 (de) * 2013-10-01 2015-04-02 Osram Opto Semiconductors Gmbh Strahlungsemittierender Halbleiterchip und Verfahren zur Herstellung von strahlungsemittierenden Halbleiterchips
US9721940B2 (en) 2013-10-01 2017-08-01 Osram Opto Semiconductors Gmbh Radiation-emitting semiconductor chip and method of producing radiation-emitting semiconductor chips
DE102013110853B4 (de) * 2013-10-01 2020-12-24 OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung Strahlungsemittierender Halbleiterchip und Verfahren zur Herstellung von strahlungsemittierenden Halbleiterchips

Also Published As

Publication number Publication date
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