WO2013050898A1 - Liant électro-isolant pour le montage d'un dispositif électroluminescent - Google Patents

Liant électro-isolant pour le montage d'un dispositif électroluminescent Download PDF

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Publication number
WO2013050898A1
WO2013050898A1 PCT/IB2012/055008 IB2012055008W WO2013050898A1 WO 2013050898 A1 WO2013050898 A1 WO 2013050898A1 IB 2012055008 W IB2012055008 W IB 2012055008W WO 2013050898 A1 WO2013050898 A1 WO 2013050898A1
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WO
WIPO (PCT)
Prior art keywords
light emitting
wafer
mount
electrically insulating
type region
Prior art date
Application number
PCT/IB2012/055008
Other languages
English (en)
Inventor
Marc Andre De Samber
Eric Cornelis Egbertus Van Grunsven
Original Assignee
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics N.V. filed Critical Koninklijke Philips Electronics N.V.
Publication of WO2013050898A1 publication Critical patent/WO2013050898A1/fr

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
    • H01L2933/0008—Processes
    • H01L2933/0033—Processes relating to semiconductor body packages
    • H01L2933/0066—Processes relating to semiconductor body packages relating to arrangements for conducting electric current to or from the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate

Definitions

  • the present invention relates to an electrically insulating bond for attaching a semiconductor light emitting device to a mount.
  • Semiconductor light emitting devices may be attached to a mount with a wafer scale process.
  • LEDs light emitting diodes
  • RCLEDs resonant cavity light emitting diodes
  • VCSELs surface- emitting lasers
  • edge emitting lasers are among the most efficient light sources currently available.
  • Materials systems currently of interest in the manufacture of high-brightness light emitting devices capable of operation across the visible spectrum include Group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as Ill-nitride materials.
  • Ill-nitride light emitting devices are fabricated by epitaxially growing a stack of semiconductor layers of different compositions and dopant concentrations on a sapphire, silicon carbide, Ill-nitride, or other suitable substrate by metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or other epitaxial techniques.
  • MOCVD metal-organic chemical vapor deposition
  • MBE molecular beam epitaxy
  • the stack often includes one or more n-type layers doped with, for example, Si, formed over the substrate, one or more light emitting layers in an active region formed over the n-type layer or layers, and one or more p-type layers doped with, for example, Mg, formed over the active region. Electrical contacts are formed on the n- and p- type regions.
  • LEDs are typically mounted on a carrier and packaged to protect the LED from environmental harm and mechanical damage.
  • LED chips are mounted on carriers one at a time. That is, each LED is individually mounted onto a printed circuit board or a reflector cup for example.
  • wirebond connections are conventionally made to each LED chip.
  • US 2008/0142817 describes a "chip scale” method for packaging LEDs.
  • Chip scale refers to bonding an LED wafer to a carrier substrate on a wafer scale.
  • a device formed by the method of US 2008/0142817 is shown in Fig. 1 1.
  • a substrate on which a plurality of diodes 160 are formed is wafer bonded to a carrier substrate 200 on which a plurality of bond pads 240 are formed.
  • a plurality of vias 22A and 22B may be formed in the carrier substrate which are then plated or filled with metal or other conducting material that is electrically connected to bond pads 28 A, 28B on the back side of substrate 200 (i.e. opposite diode 160).
  • a passivation layer 320 may be formed on the upper surface of the substrate 200 adjacent the diode 160 and patterned to reveal at least a portion of an electrode on a surface of diode 160 and at least a portion of the via 22B (which is then covered with metal interconnect 330, as described below).
  • the vias 22A and 22B are electrically isolated from each other (and likewise bond pads 28A and 28B are isolated from each other).
  • a metal interconnect 330 may be formed using conventional techniques (such as evaporation) to connect the conductive via 22B with the exposed electrode of diode 160. The completed devices may then be separated to provide individual packaged devices.
  • Embodiments of the invention include a wafer and a mount.
  • the wafer includes a plurality of light emitting devices, each light emitting device comprising a light emitting region disposed between an n-type region and a p-type region.
  • a first conductive pad is electrically connected to the n-type region.
  • a second conductive pad is electrically connected to the p-type region.
  • An electrically insulating bonding layer is disposed between the wafer and the mount. Openings aligned with the first and second conductive pads are formed in the electrically insulating bonding layer.
  • a method according to embodiments of the invention includes forming an electrically insulating bonding layer on one of a wafer and a mount.
  • the wafer includes a plurality of light emitting devices, each light emitting device comprising a light emitting region disposed between an n-type region and a p-type region.
  • a first conductive pad is electrically connected to the n- type region.
  • a second conductive pad is electrically connected to the p-type region.
  • the method further includes attaching the wafer to the mount with the electrically insulating bonding layer. After attaching the wafer to the mount, at least one opening in the electrically insulating bonding layer is formed to expose at least one of the first conductive pad and the second conductive pad. A conductive material is formed in the opening.
  • Fig. 1 illustrates a portion of a wafer including three semiconductor light emitting devices.
  • Fig. 2 illustrates a portion of mount.
  • Fig. 3 is a top view of a portion of the mount illustrated in Fig. 2.
  • FIG. 4 illustrates the structure of Fig. 1 attached to the structure illustrated in Fig. 2.
  • Fig. 5 illustrates the structure of Fig. 4 after forming openings in the bonding material and thinning the mount.
  • Fig. 6 illustrates one of the devices shown in Fig. 5 after forming a seed layer and a cap.
  • Fig. 7 illustrates the structure of Fig. 6 after disposing a metal layer in the openings.
  • Fig. 8 illustrates the structure of Fig. 7 after removing the cap and seed layers and forming pads.
  • Fig. 9 illustrates the structure of Fig. 8 after removing the growth substrate and forming optional additional layers over the semiconductor light emitting devices.
  • Fig. 10 illustrates a semiconductor light emitting device attached to a mount including integrated circuitry.
  • Fig. 1 1 illustrates a prior art semiconductor light emitting device attached to a mount. DETAILED DESCRIPTION
  • the wafer of diodes is attached to the carrier substrate by metal bonds that also establish electrical connection between the diodes and the carrier substrate.
  • a wafer of semiconductor light emitting devices is attached to a mount by an electrically insulating material such as a dielectric bond.
  • the mount may be a partially processed silicon wafer, for example. Openings are formed in the bonding material to expose electrical pads on the light emitting devices, then conductive material is disposed in the openings.
  • the dielectric bond may be formed at near room temperature, which may reduce the stress built-in to the bond due to the difference in coefficient of thermal expansion between the wafer of semiconductor light emitting devices and the mount.
  • Fig. 1 illustrates a portion of a wafer of semiconductor light emitting devices.
  • Three light emitting devices 1 1A, 1 IB, and 11C are illustrated in Fig. 1.
  • a full wafer of semiconductor light emitting devices will typically include many more light emitting devices.
  • the semiconductor light emitting devices are Ill-nitride LEDs that emit blue or UV light, semiconductor light emitting devices besides LEDs such as laser diodes and semiconductor light emitting devices made from other materials systems such as other III-V materials, Ill-phosphide, Ill-arsenide, II- VI materials, ZnO, or Si-based materials may be used.
  • a semiconductor structure 12 is grown on a growth substrate 10.
  • the growth substrate 10 may be any suitable substrate such as, for example, sapphire, SiC, Si, GaN, or composite substrates.
  • the semiconductor structure 12 includes a light emitting or active region sandwiched between n- and p-type regions.
  • An n-type region may be grown first and may include multiple layers of different compositions and dopant concentration including, for example, preparation layers such as buffer layers or nucleation layers, and/or layers designed to facilitate removal of the growth substrate, which may be n-type or not intentionally doped, and n- or even p-type device layers designed for particular optical, material, or electrical properties desirable for the light emitting region to efficiently emit light.
  • a light emitting or active region is grown over the n-type region.
  • suitable light emitting regions include a single thick or thin light emitting layer, or a multiple quantum well light emitting region including multiple thin or thick light emitting layers separated by barrier layers.
  • a p-type region may then be grown over the light emitting region.
  • the p-type region may include multiple layers of different composition, thickness, and dopant concentration, including layers that are not intentionally doped, or n-type layers.
  • the total thickness of all the semiconductor material in the device is less than 10 ⁇ in some embodiments and less than 6 ⁇ in some embodiments.
  • a metal p-contact is formed on the p-type region. If a majority of light is directed out of the semiconductor structure through a surface opposite the p-contact, such as in a flip chip device, the p-contact may be reflective.
  • a flip chip device may be formed by patterning the semiconductor structure by standard photolithographic operations and etching the semiconductor structure to remove a portion of the entire thickness of the p-type region and a portion of the entire thickness of the light emitting region, to form a mesa which reveals a surface of the n-type region on which a metal n-contact is formed.
  • the mesa and p- and n-contacts may be formed in any suitable manner.
  • the semiconductor structure 12 is etched down to an insulating layer, which may be an insulating semiconductor layer that is part of the semiconductor structure 12, or substrate 10.
  • the p- and n-contacts may be redistributed by a stack of insulating layers and metals as is known in the art, to form large electrical pads 14A and 14B.
  • One of electrical pads 14A and 14B is electrically connected to the p-type region of the semiconductor structure 12 and the other of electrical pads 14A and 14B is electrically connected to the n-type region of the
  • Electrical pads may be any suitable conductive material including, for example, copper, gold, and alloys.
  • the p- and n-contacts, the stack to redistribute the contacts, and electrical pads 14A and 14B are formed to support semiconductor structure 12 during later removal of growth substrate 10, for example to prevent or reduce cracking in semiconductor structure 12.
  • Electrical pads 14A and 14B are electrically isolated from each other by a gap 16 as illustrated in Fig. 1.
  • Gap 16 may be filled with an insulating material such as a dielectric, air, or any other suitable gas.
  • Fig. 2 is a cross sectional view of a portion of a mount 18 to which the structure of Fig. 1 may be attached.
  • Fig. 3 is a plan view of a portion of mount 18.
  • mount 18 is a silicon wafer.
  • Vias 22 may be formed through the entire thickness of the silicon 20. Vias 22 are sized and arranged to correspond with electrical pads 14A and 14B on the structure of Fig. 1. Vias 22 may have substantially vertical sidewalls, as illustrated, or angled sidewalls.
  • a silicon mount 18 may be made electrically inert by coating silicon 20 with a coating 24, which may be, for example, an oxide of silicon formed by any suitable process including plasma enhanced chemical vapor deposition or thermal oxidation.
  • Bonding layer 26 may be an electrically insulating material such as a dielectric
  • Mount 18 may touch the wafer of devices 11 or may be spaced apart from the wafer of devices 11 by the bonding layer 26, as illustrated in Fig. 4.
  • bonding material is disposed on the wafer of devices 1 1, on mount 18, or both, then the wafer of devices 11 and mount 18 are aligned, pressed together, and the bonding layer 26 is cured.
  • Alignment, pressing together, and curing may be performed as sequential or simultaneous process steps. Some or all of the steps may be performed at elevated temperature.
  • the openings 22 in mount 18 are roughly aligned with electrical pads 14A and 14B on devices 11 , for example by visual alignment.
  • bonding layer 26 may completely cover electrical pads 14A and 14B. Accordingly, bonding layer 26 forms a mechanical connection only - no electrical connection between the wafer of devices 11 and the mount 18 is established by attaching the wafer of devices to the mount.
  • Bonding layer 26 may also be formed such that it fills in any gaps or indentations on the surface of the wafer of devices 11 , for example to prevent contaminants from reaching devices 11 or to support devices 11 during layer removal of growth substrate 10. [0027] In Fig.
  • mount 18 may be optionally thinned, for example by etching away a portion of the thickness of silicon wafer 20.
  • a typical thickness for a 6 inch diameter silicon wafer is 650 ⁇ .
  • Silicon layer 20 of mount 18 may be thinned to, for example, 200 ⁇ or thinner in some embodiments, 150 ⁇ or thinner in some embodiments, and 100 ⁇ or thinner in some embodiments.
  • Mount 18 may be thinned to reduce the thickness of openings 22 which are filled with metal, as described below in reference to Fig. 7. In some embodiments, mount 18 is thinned such that mount 18 is not thick enough to mechanically support devices 1 1. In such embodiments, at the stage of processing illustrated in Figs. 5 and 6, devices 11 are supported by growth substrate 10.
  • openings 28 are formed in electrically insulating bonding layer 26, to expose electrical pads 14A and 14B. Openings 28 may be formed by conventional masking, patterning, and etching by any suitable technique, including, for example, plasma etching. In some embodiments, mount wafer 20 with its pre-formed openings 22 is sufficient for use as a hard mask, serving as shielding layer to define the patterning of the openings 28. An anisotropic etching chemistry (such as reactive ion etching or inductively coupled plasma etching) is used to form openings 22 such that further processing of the filling metal is feasible.
  • An anisotropic etching chemistry such as reactive ion etching or inductively coupled plasma etching
  • FIGs. 6, 7, 8, 9, and 10 only a single device 1 1 is illustrated, for clarity. It is to be understood that the structures illustrated in these figures may be formed on a wafer of devices 1 1. Accordingly, the structures illustrated in these figures may be repeated many times across a wafer of devices 11.
  • an electrically conductive seed layer 30 is formed on the bottom surface (in the orientation illustrated in Fig. 6) of the structure. Seed layer 30 is also formed on the sidewall of openings 22 and on the exposed surface of silicon layer 20. Seed layer 30 may be, for example, a single metal, an alloy, or a stack of metals. Examples of suitable materials include Cu, Au, Ti, and TiW. In one example, seed layer 30 includes a TiW barrier/adhesion layer and a Cu layer. Examples of suitable thicknesses include 50-100 nm TiW and 0.5 to 1 ⁇ Cu. Seed layer 30 may be formed by any suitable process including, for example, sputtering, evaporation, or a deposition process such as CVD. Seed layer 30 is in direct electrical contact with electrical pads 14A and 14B. Seed layer 30 forms the base layer for the via-filling process illustrated in Fig. 7.
  • a cap layer 32 is formed over the portion of seed layer 30 which is on the bottom surface (in the orientation illustrated) of silicon layer 20.
  • Cap layer 32 may be, for example, an electrically insulating material such as a dielectric, an organic layer, polyimide, BCB or epoxy.
  • Cap layer 32 may be formed by any suitable process including, for example, roller coating. Cap layer prevents the conductive material formed in the vias in Fig. 7 from forming on silicon layer 20.
  • a conductive material 34 is formed in the openings 22 in mount 18.
  • Conductive material 34 may be a metal such as Cu formed by any suitable process including plating. During plating, metal adheres only to conductive surfaces, such as the exposed surface of seed layer 30. No metal adheres to cap layer 32 because cap layer 32 is electrically insulating; accordingly, no metal is plated on silicon layer 20. Conductive material 34 may completely fill openings 22, as illustrated in Fig. 7, or conductive material 34 may conformally coat the seed layer 30 in contact with electrical pads 14A and 14B and on the sidewalls of openings 22, such that openings 22 are only partially filled. In the configuration illustrated in Fig. 7, conductive metal 34 is disposed directly beneath the openings formed in bonding material 26 to expose electrical pads 14A and 14B. In some embodiments, conductive material 34 may be formed in an alternative configuration by forming a conformal cap layer 32 on the bottom surface of the structure, then patteming cap layer 32 to expose seed layer 30 in areas where conductive material 34 is required.
  • insulating material 36 such as solder resist, photo-imageable solder resist (PI), or BCB is applied to the bottom surface of the structure, then patterned to form openings aligned with conductive material 34. Insulating material layer 36 electrically isolates the semiconducting silicon layer 20, defines the location of pads 38, and may create stress relief between pads 38 and silicon layer 20.
  • Pads 38 are then formed in the openings in insulating material 36.
  • Pads 38 may be, for example, an electrically conductive material such as an inert, solderable, or solder layer, suitable for attachment to other substrates such as printed circuit boards.
  • growth substrate 10 is optionally removed (as illustrated in Fig. 9) or thinned. In other embodiments, growth substrate 10 may remain part of the final device. Growth substrate 10 is removed or thinned by any process that is suitable to the particular growth substrate material, such as laser lift-off for a sapphire substrate, etching, or a mechanical technique such as grinding. After the growth substrate is removed, the top surface of
  • semiconductor structure 12 and bonding layer 26 in the area 13 between devices is exposed.
  • the top surface of semiconductor structure 12 may be optionally roughened or patterned, for example to improve light extraction.
  • One or more optional additional layers 40 such as wavelength converting layers, filter layers, dichroic layers, lenses or other optics may be formed over the growth substrate if there or semiconductor structure 12 if the growth substrate is removed.
  • the optional additional layers may be in contact with the structure as illustrated in Fig. 9, or spaced apart from the top surface of the structure.
  • Individual devices on the finished structure may then be optionally tested.
  • the structure may then be diced by any suitable technique into individual devices 1 1 or groups of devices 1 1.
  • Fig. 10 illustrates an alternative embodiment of the invention, where integrated electrical functionality is formed in the silicon wafer 20 of mount 18.
  • silicon wafer may be processed to form integrated circuitry 42 in addition to vias 22.
  • Integrated circuitry 42 may be, for example, an electrostatic protection diode such as a Zener diode.
  • Other circuitry such as, for example, switches for selecting parts of a single device or an array of devices to be driven, or drivers, may be included in some embodiments. Forming such a device in a silicon wafer is well known to a person of skill in the art.
  • Integrated circuitry may be formed in the area of silicon wafer 20 that is disposed between electrical pads 14A and 14B, as illustrated in Fig. 10. Since wafer 20 may be thinned in Fig. 5, circuitry 42 may be formed in the top portion of silicon layer 20.
  • Direct electrical contacts 44 to circuitry 42 may be formed on mount 18 before bonding. Electrical contacts 44 may be formed over vias 22 in silicon wafer 20. Seed layer 30 is then deposited in vias 22 as described in Fig. 6. Seed layer 30 makes electrical contact to electrical contacts 44. Additional vias 22 may be formed to make electrical contact to circuitry 42.
  • circuitry 42 is connected in series between electrical pads 14A and 14B. The first side of circuitry 42 is connected to electrical pad 14A through conductive material 34B and 34A. The second side of circuitry 42 is connected to electrical pad 14B through conductive material 34C and 34D.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Led Device Packages (AREA)
  • Led Devices (AREA)

Abstract

Dans des modes de réalisation, l'invention concerne une plaquette et un support (18). Ladite plaquette comporte plusieurs dispositifs électroluminescents (12), chacun comprenant une région électroluminescente disposée entre une région de type n et une région de type p. Un premier tampon conducteur (14A) est relié électriquement à la région de type n. Un second tampon conducteur (14B) est électriquement relié à la région de type p. Une couche de liaison électro-isolante (26) est disposée entre la plaquette et le support (18). Des ouvertures alignées avec les premier et second tampons conducteurs sont formées dans la couche de liaison électro-isolante (26).
PCT/IB2012/055008 2011-10-07 2012-09-21 Liant électro-isolant pour le montage d'un dispositif électroluminescent WO2013050898A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201161544417P 2011-10-07 2011-10-07
US61/544,417 2011-10-07

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Publication Number Publication Date
WO2013050898A1 true WO2013050898A1 (fr) 2013-04-11

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014142448A1 (fr) * 2013-03-12 2014-09-18 Jin Sung Park Encapsulation de diode électroluminescente à l'échelle de puce de niveau de tranche
WO2015055346A1 (fr) * 2013-10-18 2015-04-23 Osram Opto Semiconductors Gmbh Composant semi-conducteur optoélectronique et procédé de production dudit composant
JP2016526797A (ja) * 2013-07-03 2016-09-05 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． メタライゼーション層の下に応力緩和層を有するｌｅｄ
CN112542481A (zh) * 2020-12-28 2021-03-23 无锡新仕嘉半导体科技有限公司 一种集成多晶硅二极管的led结构

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661029B1 (en) * 2000-03-31 2003-12-09 General Electric Company Color tunable organic electroluminescent light source
WO2005029599A2 (fr) * 2003-09-24 2005-03-31 Matsushita Electric Works, Ltd. Dispositif photoluminescent et son procede de fabrication
US20050221602A1 (en) * 2002-11-23 2005-10-06 Infineon Technologies Ag Electrodepositing a metal in integrated circuit applications
US20070284602A1 (en) * 2004-06-30 2007-12-13 Ashay Chitnis Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US20080029761A1 (en) * 2006-08-01 2008-02-07 Peng Jing Through-hole vertical semiconductor devices or chips
US20080142817A1 (en) 2005-06-30 2008-06-19 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6661029B1 (en) * 2000-03-31 2003-12-09 General Electric Company Color tunable organic electroluminescent light source
US20050221602A1 (en) * 2002-11-23 2005-10-06 Infineon Technologies Ag Electrodepositing a metal in integrated circuit applications
WO2005029599A2 (fr) * 2003-09-24 2005-03-31 Matsushita Electric Works, Ltd. Dispositif photoluminescent et son procede de fabrication
US20070284602A1 (en) * 2004-06-30 2007-12-13 Ashay Chitnis Dielectric wafer level bonding with conductive feed-throughs for electrical connection and thermal management
US20080142817A1 (en) 2005-06-30 2008-06-19 Cree, Inc. Chip-scale methods for packaging light emitting devices and chip-scale packaged light emitting devices
US20080029761A1 (en) * 2006-08-01 2008-02-07 Peng Jing Through-hole vertical semiconductor devices or chips

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2014142448A1 (fr) * 2013-03-12 2014-09-18 Jin Sung Park Encapsulation de diode électroluminescente à l'échelle de puce de niveau de tranche
JP2016526797A (ja) * 2013-07-03 2016-09-05 コーニンクレッカ フィリップス エヌ ヴェＫｏｎｉｎｋｌｉｊｋｅ Ｐｈｉｌｉｐｓ Ｎ．Ｖ． メタライゼーション層の下に応力緩和層を有するｌｅｄ
WO2015055346A1 (fr) * 2013-10-18 2015-04-23 Osram Opto Semiconductors Gmbh Composant semi-conducteur optoélectronique et procédé de production dudit composant
JP2016533044A (ja) * 2013-10-18 2016-10-20 オスラム オプト セミコンダクターズ ゲゼルシャフト ミット ベシュレンクテル ハフツングＯｓｒａｍ Ｏｐｔｏ Ｓｅｍｉｃｏｎｄｕｃｔｏｒｓ ＧｍｂＨ オプトエレクトロニクス半導体デバイスを製造する方法および半導体デバイス
US9780078B2 (en) 2013-10-18 2017-10-03 Osram Opto Semiconductor Gmbh Method for producing optoelectronic semiconductor devices and optoelectronic semiconductor device
CN112542481A (zh) * 2020-12-28 2021-03-23 无锡新仕嘉半导体科技有限公司 一种集成多晶硅二极管的led结构

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