WO2010052066A1 - Circuiterie pour l'amplification d'un signal numérique et circuit émetteur-récepteur pour un système de bus - Google Patents

Circuiterie pour l'amplification d'un signal numérique et circuit émetteur-récepteur pour un système de bus Download PDF

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Publication number
WO2010052066A1
WO2010052066A1 PCT/EP2009/062429 EP2009062429W WO2010052066A1 WO 2010052066 A1 WO2010052066 A1 WO 2010052066A1 EP 2009062429 W EP2009062429 W EP 2009062429W WO 2010052066 A1 WO2010052066 A1 WO 2010052066A1
Authority
WO
WIPO (PCT)
Prior art keywords
circuit
branch
current
output
output circuit
Prior art date
Application number
PCT/EP2009/062429
Other languages
German (de)
English (en)
Inventor
Marco Neuscheler
Ricardo Erckert
Axel Wenzler
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to CN200980144420.4A priority Critical patent/CN102210100B/zh
Priority to JP2011535060A priority patent/JP2012508492A/ja
Publication of WO2010052066A1 publication Critical patent/WO2010052066A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017509—Interface arrangements
    • H03K19/017518—Interface arrangements using a combination of bipolar and field effect transistors [BIFET]
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/30—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor
    • H03F3/3069—Single-ended push-pull [SEPP] amplifiers; Phase-splitters therefor the emitters of complementary power transistors being connected to the output
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
    • H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/08—Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
    • H04L25/085—Arrangements for reducing interference in line transmission systems, e.g. by differential transmission
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F2200/00—Indexing scheme relating to amplifiers
    • H03F2200/297—Indexing scheme relating to amplifiers the loading circuit of an amplifying stage comprising a capacitor

Definitions

  • the invention relates to an output circuit having the features of the preamble of claim 1 and a transceiver circuit for a bus system having the features of the preamble of claim 6.
  • Control devices, sensors and actuators, in particular of a motor vehicle or commercial vehicle, are often connected to one another with the aid of a communication system, such as the bus system known by the name "FlexRay".
  • a communication system such as the bus system known by the name "FlexRay”.
  • FlexRay is a fast, deterministic and fault-tolerant bus system, especially for use in motor vehicles.
  • the FlexRay protocol operates on the principle of Time Division Multiple Access (TDMA), whereby the subscribers or the messages to be transmitted are assigned fixed time slots in which they have exclusive access to the communication connection. The time slots are repeated in a fixed cycle, so that the time at which a message is transmitted over the bus, can be accurately predicted and the bus access is deterministic.
  • TDMA Time Division Multiple Access
  • FlexRay divides the cycle into a static and a dynamic part.
  • the fixed time slots are located in the static part at the beginning of a bus cycle.
  • the dynamic part the time slots are specified dynamically.
  • the exclusive bus access only for a short time, for the duration of at least one so-called minislot enabled. Only if a bus access occurs within a minislot, the time slot is extended by the required time. Thus, bandwidth is only consumed when it is actually needed.
  • FlexRay communicates via one or two physically separate lines with a maximum data rate of 10 Mbit / sec. FlexRay can also operate at lower data rates. Channels realized by the lines correspond to the physical layer, in particular the so-called OSI (Open System Architecture) layer model. The use of two channels is mainly used for the redundant and thus fault-tolerant transmission of
  • the messages are transmitted by means of a differential signal, that is, the signal transmitted via the connecting lines results from the difference between the individual signals transmitted via the two lines.
  • the layer layer above the physical layer layer is designed such that an electrical or an optical transmission of the signal or signals via the line (s) or a transmission in other ways is possible.
  • pulses are distorted because falling (high-to-low) and rising (low-to-high) edges are delayed in different ways on the transmission path.
  • the delay between the rising and falling edges of a signal is also referred to as pulse distortion or asymmetric delay.
  • Asymmetric delays can have both systematic and stochastic causes. Particularly in the case of the comparatively high bit rate of 10 MHz provided in FlexRay systems, such an asymmetrical transmission behavior with respect to the rising and falling edges can have a disruptive effect on the quality of the data transmissions. Consequently, this asymmetric transmission behavior on the physical layer must be avoided as far as possible.
  • Figure 5 shows a well-known circuit arrangement in the form of a driver, which is formed as an inverter with complementarily arranged and formed insulating layer field effect transistors (MOSFETs).
  • MOSFETs insulating layer field effect transistors
  • this driver In the manufacture of this driver is trying to be complementary to each other paired PMOS and NMOS transistors as well as possible. However, since PMOS and NMOS transistors are not produced in the same manufacturing step, this pairing is inadequate. This has the consequence that a duration t1 of a rising edge of an output signal generated by the driver differs from a duration t2 of a falling edge.
  • FIG. 6 shows the output signal generated by the known driver as a function of a rectangular input signal of the driver.
  • Transceiver circuits for flexray applications require the same runtime for the rising edge and the falling edge. The differences in the
  • Slope steepnesses for example, of a 5V port (eg Pin RXD) contribute significantly to the runtime errors in the system.
  • the object of the invention is to provide an output circuit in which the
  • Duration of a rising edge of an output signal and the duration of a falling edge of the output signal also differ as slightly as possible, when used in the output circuit field effect transistors complementary branches of the output circuit with respect to their electrical properties are not exactly complementary to each other.
  • the edge steepness of a through the output circuit according to the invention output signal generated by the insertion of the current sources irrespective of in particular for technological reasons inadequate pairing of NMOS and PMOS T ransistoren.
  • the circuit concept on which the invention is based is suitable for all applications which require the same delay for the rising edge and for the falling edge of a signal.
  • the output circuit according to the invention can be designed as a driver for a connection RxD and / or for bus connections BP and BM of a flexray transceiver circuit.
  • FIG. 1 shows a bus system with nodes, each having a transceiver circuit
  • Figure 2 is a schematic representation of an output circuit according to a first preferred embodiment
  • FIG. 3 is a detailed illustration of the output circuit of Figure 2;
  • FIG. 4 shows a representation of an output circuit according to a second preferred embodiment, which has a low-impedance output follower
  • Figure 5 is an illustration of a known circuit arrangement
  • FIG. 6 shows slope variations in a diagram in the known circuit arrangement from FIG. 5 and their effect on signal propagation times.
  • FIG. 1 shows a bus system 1 1, to which a plurality of nodes 13 are connected.
  • the bus system 1 1 may be a FlexRay communication system, and thus the bus system 1 1 may be constructed according to the specifications of the FlexRay consortium.
  • the individual nodes 13 are connected via bus lines 15 either directly or indirectly via a star coupler 17.
  • Each bus line 15 is formed as a cable with at least one wire pair consisting of two wires 19, each forming an electrical conductor.
  • the bus system 1 1 thus has a channel for transmitting data through the wires 19 of the
  • the bus system 11 may comprise a plurality of channels, preferably two channels, which are implemented by two separate pairs of wires (not shown). By using two channels, the payload rate of data transfers between nodes 13 can be increased by transmitting different data over the two channels. Since the bus system can continue to work on a defect on one of the two pairs of wires, results in a higher reliability of the bus system 1 1.
  • Each node 13 has a transceiver circuit 21, which is preferably designed as an integrated circuit.
  • a first bus connection BP and a second bus connection BM of the transceiver circuit 21 are each connected to one of the wires 19 of one of the bus lines 15.
  • the transceiver circuit 21 has a receiver circuit 23 for receiving data via the bus line 15 and a transmitter circuit 25 for transmitting data via the bus line 15 to which the node 13 is connected. Both the receiver circuit 23 and the transmitter circuit 25 are connected within the transceiver circuit 21 to the two bus terminals BP and BM. Both the receiver circuit 23 and the
  • Transmitter circuit 25 are arranged to transmit a differential digital signal via the pair of wires of the bus line 15 connected to the corresponding transceiver circuit 21.
  • the transceiver circuit 21 also has a logic unit 27 which is coupled to the receiver circuit 23 and to the transmitter circuit 25.
  • the logic unit 27 has terminals for connecting the transceiver circuit 21 to a control circuit formed, for example, by a microcontroller 31 or a microcomputer. These connections or lines connected thereto form an interface 29 between the transceiver circuit 21 and the control circuit or the microcontroller 31.
  • the microcontroller 31 has a communication controller 33 for controlling communications between the nodes 13 via the bus line 15.
  • the communication controller 33 is configured to control the communication operations in accordance with the protocols of the bus system 11, in particular for carrying out media access methods of the bus system 11.
  • the communication controller 33 may also be configured to calculate checksums of data frames to be transmitted over the bus 15, for example according to the CRC method and / or to check the checksums of the received data frames.
  • a line RxD for transmitting data received from the transceiver circuit 21 via the bus line 15 from the transceiver circuit 21 to the communication controller 33 and a line TxD for transmitting data that the transceiver circuit 21 should send via the bus line 15 are provided , provided from the communication controller 33 to the transceiver circuit 21.
  • the interface 29 also includes further lines 34, which serve, for example, for the exchange of control information between the communication controller 33 and the transceiver circuit 21.
  • the microcontroller 31 has a calculation core 35, memory 37 (main memory and / or read-only memory) and input and output devices 39.
  • the microcontroller 31 may be configured to execute further protocol software and / or application programs.
  • the communication controller 33 is integrated in the microcontroller 31. Notwithstanding this, in an embodiment not shown, the communication controller 33 is a separate circuit from the microcontroller 31, preferably as an integrated circuit
  • FIG. 2 shows an output circuit 61 of the transceiver circuit 21 for outputting a digital signal OUT.
  • the digital signal OUT may be the digital signal RxD generated by the logic unit 27 or the two complementary bus signals BP... Generated by the transmitter circuit 25 and BM act.
  • the logic unit 27 and the transmitter circuit 25 comprise one or more output circuits 61.
  • the logic unit 27 may also have a further output circuit 61 for generating an output signal OUT, which is transmitted via at least one of the further lines 34 from the logic unit 27 to the microcontroller 31.
  • the output circuit 61 may be integrated into other circuits or components than into the transceiver circuit 21.
  • the output circuit may be integrated in the microcontroller 31 or in any other integrated circuit.
  • the output circuit 61 has a transistor stage 63 which comprises a first branch 65 which is arranged between a supply voltage line 67 of the output circuit 61 and an output 69 of the output circuit 61.
  • the first branch 65 has a series connection of a first current source 71 and a drain-source path of a p-channel MOSFET M1.
  • a second branch 75 is arranged, which is complementary to the first branch 65 is formed.
  • the second branch 75 comprises an n-channel MOSFET M2 whose drain-source path is connected in series with a second current source 77.
  • a load capacitance 79 is arranged between the output 69 of the output circuit and the ground line 73. Gate terminals of the two transistors M1 and M2 are connected together and form an input 78 of the output circuit 61st
  • the two current sources 71, 77 are designed as a current mirror.
  • the current mirror has a transistor M7.
  • a reference current source 81 for providing a reference current IREF, which may be connected to a drain terminal of the transistor M7.
  • the current mirror is formed, in addition to the transistor M7, by further transistors M3, M4 and M6, which are assigned to the first branch 65.
  • a transistor M5 of the current mirror and the transistor M7 are associated with the second branch 75.
  • the reference current source 81 is not provided.
  • the transistor stage 63 is followed by an output follower designed as a current amplifier 83.
  • the current amplifier 83 is similar to the transistor stage 63 realized symmetrically with two mutually complementary branches.
  • An upper branch 85 is between the
  • An input 87 of the current amplifier 83 is connected to an emitter follower of the current amplifier 83 comprising a resistor R1 and a PNP transistor Q1.
  • the emitter follower R1, Q1 is followed by an output transistor Q2 of the upper branch 85 designed as an NPN transistor.
  • a lower branch 89 of the current amplifier 83 is connected, which is arranged between the output 69 and the ground line 73.
  • the lower branch 89 has an emitter follower connected to the input 87, which is formed by an NPN transistor Q3 and a resistor Q2, and an output transistor Q4 arranged downstream of this as a PNP transistor.
  • the emitter terminals of the two output transistors Q2 and Q4 are connected together and terminated at the output 69 of the output circuit 61.
  • the load capacitance 79 is arranged between the output 69 and the ground line 73.
  • an at least substantially constant capacitance C1 is arranged.
  • the constant capacitance C1 can be arranged in a semiconductor chip of an integrated circuit in which the output circuit 16 is integrated. A value of constant
  • Capacitance C1 is predetermined by its structure or by the structure of the semiconductor chip.
  • a digital input signal IN is applied to the input of the output circuit.
  • the output circuit 61 thus allows the implementation of a port, for example, a 5V digital output, with symmetrical edges, that is with the same slope for the rising edge and the falling edge.
  • the same transit time is produced by the output circuit 61 both for the rising edge and for the falling edge of a digital signal IN applied to the input 78. It is assumed that the following receiver (usually the input of a microcontroller) has its switching threshold at 0.5 * VDD.
  • the load capacitance 79 together with the current sources 71, 77 for generating currents 11 and 12 through the two branches 65, 75, produces a defined edge steepness of
  • the output circuit 61 is as a current controlled port with the transistors
  • the current through transistor M3 is a copy of the current through transistor M5. This copy is generated by M6 and the current mirrors M4, M3.
  • the edge steepness depends on the load capacitance 79.
  • the constant and predetermined capacitance C1 can be provided at the output 91 of the transistor stage 63.
  • the unknown load capacitance 79 which is generally dependent on connecting lines or bus lines 15, is subsequently amplified by the low-resistance amplifier 83 at least essentially driven 1.
  • the edge steepness becomes independent of the load capacitance 79.
  • transistors Q1 through Q4 may be replaced by MOS transistors having a very large W / L ratio between a channel width and a channel length (output impedance
  • 1 / (2 * gm)).

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)

Abstract

L'invention concerne un circuit de sortie (61) pour un circuit émetteur-récepteur (21) pour un système de bus (11), servant à l'amplification d'un signal d'entrée numérique (IN) appliqué à une borne d'entrée (78) du circuit de sortie. Le circuit de sortie (61) selon l'invention présente un étage à transistor (63) en montage complémentaire qui comprend deux branches en série (65, 75) complémentaires entre elles, chaque branche (65, 75) présentant un transistor à effet de champ (M1, M2). L'invention vise à fournir un circuit de sortie (61) dans lequel la durée (t1) d'un front montant d'un signal de sortie et la durée (t2) d'un front descendant d'un signal de sortie (OUT) diffèrent le moins possible. A cet effet, chaque branche (65, 75) présente respectivement une source de courant (71, 77) qui est montée en série avec une section drain-source du transistor à effet de champ (M1, M2) de cette branche (65, 75). Chaque source de courant (71, 77) sert à produire un courant s'écoulant dans la branche (65, 75) lorsque la section drain-source du transistor à effet de champ (M1, M2) de la même branche (65, 75) est au moins partiellement conductrice. Le courant (I1, I2) pouvant être produit par la source de courant (71, 77) d'une branche (65, 75) correspond au moins pratiquement au courant (I2, I1) pouvant être produit par la source de courant (77, 71) de l'autre branche (75, 65).
PCT/EP2009/062429 2008-11-10 2009-09-25 Circuiterie pour l'amplification d'un signal numérique et circuit émetteur-récepteur pour un système de bus WO2010052066A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN200980144420.4A CN102210100B (zh) 2008-11-10 2009-09-25 用于放大数字信号的电路装置和用于总线系统的收发器电路
JP2011535060A JP2012508492A (ja) 2008-11-10 2009-09-25 デジタル信号を増幅させるための回路構成、及びバスシステムのためのトランシーバ回路

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102008057619.0 2008-11-10
DE102008057619.0A DE102008057619B4 (de) 2008-11-10 2008-11-10 Schaltungsanordnung zum Verstärken eines Digitalsignals und Transceiverschaltung für ein Bussystem

Publications (1)

Publication Number Publication Date
WO2010052066A1 true WO2010052066A1 (fr) 2010-05-14

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PCT/EP2009/062429 WO2010052066A1 (fr) 2008-11-10 2009-09-25 Circuiterie pour l'amplification d'un signal numérique et circuit émetteur-récepteur pour un système de bus

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JP (1) JP2012508492A (fr)
CN (1) CN102210100B (fr)
DE (1) DE102008057619B4 (fr)
WO (1) WO2010052066A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102013222786A1 (de) * 2013-11-08 2015-05-13 Robert Bosch Gmbh Teilnehmerstation für ein Bussystem und Verfahren zur Reduzierung von leitungsgebundenen Emissionen in einem Bussystem
DE102018203708A1 (de) * 2018-03-12 2019-09-12 Robert Bosch Gmbh Sende-/Empfangseinrichtung für ein Bussystem und Betriebsverfahren hierfür

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0236525A1 (fr) * 1986-03-12 1987-09-16 Deutsche ITT Industries GmbH Ligne à retard intégrée pour signaux numériques utilisant des transistors à effet de champ
US5550501A (en) * 1994-02-23 1996-08-27 Nec Corporation Current buffer circuit with enhanced response speed to input signal
DE102006011059A1 (de) * 2006-03-08 2007-09-13 Robert Bosch Gmbh Verfahren und System zum Übertragen von in einem Signal codierten Daten

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150811U (ja) * 1984-03-19 1985-10-07 三洋電機株式会社 バツフア−回路
JPH01161913A (ja) * 1987-12-18 1989-06-26 Toshiba Corp クロックドライバー回路
JP2583294B2 (ja) * 1988-10-28 1997-02-19 日産自動車株式会社 パルス伝送用出力バッファ回路
JPH03228425A (ja) * 1990-02-01 1991-10-09 Fujitsu Ltd 半導体集積回路装置
JP2800380B2 (ja) * 1990-07-13 1998-09-21 日産自動車株式会社 出力バツフア回路
US5581197A (en) * 1995-05-31 1996-12-03 Hewlett-Packard Co. Method of programming a desired source resistance for a driver stage
JP3050289B2 (ja) * 1997-02-26 2000-06-12 日本電気株式会社 出力バッファ回路の出力インピーダンス調整回路
JP3334548B2 (ja) * 1997-03-21 2002-10-15 ヤマハ株式会社 定電流駆動回路

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0236525A1 (fr) * 1986-03-12 1987-09-16 Deutsche ITT Industries GmbH Ligne à retard intégrée pour signaux numériques utilisant des transistors à effet de champ
US5550501A (en) * 1994-02-23 1996-08-27 Nec Corporation Current buffer circuit with enhanced response speed to input signal
DE102006011059A1 (de) * 2006-03-08 2007-09-13 Robert Bosch Gmbh Verfahren und System zum Übertragen von in einem Signal codierten Daten

Also Published As

Publication number Publication date
JP2012508492A (ja) 2012-04-05
CN102210100B (zh) 2015-01-14
DE102008057619B4 (de) 2021-08-26
CN102210100A (zh) 2011-10-05
DE102008057619A1 (de) 2010-05-12

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