WO2023280488A1 - Module de transmission et procédé de transmission de signaux différentiels dans un système de bus série - Google Patents

Module de transmission et procédé de transmission de signaux différentiels dans un système de bus série Download PDF

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Publication number
WO2023280488A1
WO2023280488A1 PCT/EP2022/065079 EP2022065079W WO2023280488A1 WO 2023280488 A1 WO2023280488 A1 WO 2023280488A1 EP 2022065079 W EP2022065079 W EP 2022065079W WO 2023280488 A1 WO2023280488 A1 WO 2023280488A1
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WO
WIPO (PCT)
Prior art keywords
transmission
current
stage
stages
bus
Prior art date
Application number
PCT/EP2022/065079
Other languages
German (de)
English (en)
Inventor
Steffen Walker
Felix Lang
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Priority to CN202280060784.XA priority Critical patent/CN117917050A/zh
Publication of WO2023280488A1 publication Critical patent/WO2023280488A1/fr

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L12/40006—Architecture of a communication node
    • H04L12/40032—Details regarding a bus interface enhancer
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40208—Bus networks characterized by the use of a particular bus standard
    • H04L2012/40215—Controller Area Network CAN
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40—Bus networks
    • H04L2012/40267—Bus for use in transportation systems
    • H04L2012/40273—Bus for use in transportation systems the transportation system being a vehicle

Definitions

  • the present invention relates to a transmission module and a method for transmitting differential signals in a serial bus system, which can be used in particular for CAN XL.
  • Serial bus systems are used for message or data transmission in technical systems.
  • a serial bus system can enable communication between sensors and control devices in a vehicle or a technical production facility, etc.
  • CAN FD In a CAN bus system, messages are transmitted using the CAN and/or CAN FD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD.
  • CAN FD With CAN FD, during transmission on the bus, there is a switch back and forth between a slow operating mode in a first communication phase (arbitration phase) and a fast operating mode in a second communication phase (data phase).
  • data phase With a CAN FD bus system, a data transmission rate of more than 1 MBit per second (1Mbps) is possible in the second communication phase.
  • CAN FD becomes used by most manufacturers in the first step with 500kbit/s arbitration bit rate and 2Mbit/s data bit rate in the vehicle.
  • CAN FD In order to enable even higher data rates in the second communication phase, there are successor bus systems for CAN FD, such as CANSIC and CAN XL.
  • CANSIC according to the CiA601-4 standard, a data rate of around 5 to 8 Mbit/s can be achieved in the second communication phase.
  • CAN XL a data rate of > 10 Mbit/s is required in the second communication phase, whereby the standard (CiA610-3) for this is currently being defined by the CAN in Automation (CiA) organization.
  • a bus signal CAN_H and ideally a bus signal CAN_L are driven onto a bus separately for a transmission signal TxD.
  • a bus state is actively driven in the bus signals CAN_H, CAN_L.
  • the other bus state is not driven and is set due to a terminating resistor for bus lines or bus cores of the bus.
  • the signal forms of the bus signals CAN_H, CAN_L can deviate from the ideal signal form in a real bus system.
  • transceivers which are also referred to as CAN transceivers or CAN FD transceivers, etc., are usually used in a CAN bus system for the individual communication participants.
  • the CAN transceivers or CAN FD transceivers must not be allowed to transmit or
  • Tranceivers for CAN XL must comply with even more stringent limit values that are specified in the IEC62228-3 standard. This is the only way to operate the bus system at the specified higher bit rates than with CAN FD and CAN SIC. Depending on the semiconductor technology available, compliance with these strict limits poses a major challenge.
  • transceivers for CAN SIC or transceivers for CAN XL must have a third state in the arbitration phase, which is also called SIC mode or SIC operating mode, in addition to the states recessive (rec) and dominant (dom). , the state sic, are generated.
  • a common mode voltage of the bus lines for the CAN_H, CAN_L signals must be kept within narrow limits in three transmission states, namely recessive, dominant, sic.
  • the common-mode voltage is generated across a common-mode choke, which is used in particular in a certification measurement to check compliance with the IEC62228-3 standard.
  • the common mode choke is also called common mode choke (CMC).
  • CMC common mode choke
  • DM differential mode
  • CM common mode
  • the common-mode choke generates a differential signal with an undesired common-mode signal superimposed on it at the output from a differential signal without a common-mode component at the input. This is unfavorable since this is fed directly into the CAN bus on the bus side and is visible to other CAN modules.
  • the object of the present invention to provide a transmission module and a method for transmitting differential signals in a serial bus system which solve the aforementioned problems.
  • the transmission module and the method for sending differential signals in a serial bus system are intended to allow compensation for disturbance variables that affect the emission behavior of the transmission module.
  • the object is achieved by a transmission module for sending differential signals in a serial bus system having the features of claim 1.
  • the transmission module has a first transmission stage for generating transmission currents for a first signal that is to be sent to a bus of the bus system, a second transmission stage for generating transmission currents for a second signal that is applied to the bus as a signal that is different from the first signal is to transmit, a third transmission stage for generating transmission currents for the first signal, a fourth transmission stage for generating transmission currents for the second signal, and current mirrors for the first to fourth transmission stages, the first to fourth transmission stages being connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series, each current mirror being connected to at least one reference current source, and each transmission stage being configured to measure the value of the electrical current output by the transmission stage during operation of the transmission module set at one of the current mirrors.
  • the transmission module described enables the required limit values for the emission of a transmission/reception device for CAN XL to be achieved.
  • the transmission module satisfies in particular the IEC62228-3 standard, which stipulates limit values to be observed for the bus states dom, sic and rec on the bus 40, which were generated on the basis of transmission states dom, sic and rec of the transmission module.
  • the transmission module can adapt the impedance between the bus lines for the signals CAN_H and CAN_L very well to the characteristic characteristic impedance or impedance of the bus line used.
  • the transmitter module prevents reflections and thus allows operation in the bus system at higher bit rates.
  • the transmission module described permits a chronologically staggered and controlled switching process. Switching on according to the Gaussian error function can be implemented here. This enables a soft behavior to be set during the switch-on process. In addition, the possible variation of time stages when switching on prevents the occurrence of a narrow-band frequency line in the emission frequency spectrum.
  • the transmission module described can reduce effects due to asymmetrical behavior of the transmission stages, which can occur in the transmission states dom, sic, rec and worsen the emission.
  • the transmit module prevents unequal behavior of components in transmit stages A, B (effect 1) of a full bridge, so that in the dom state a change in the common-mode voltage is minimized or prevented compared to the rec state.
  • the transmit module can prevent unequal behavior of components in transmit stages A/D and C/B of the full bridge (Effect 2), so that in the sic state, a change in the common-mode voltage is minimized or prevented compared to the rec state will.
  • the transmission stage can be designed to set the value of the electrical current output by the transmission stage during operation of the transmission module at the input of the current mirror.
  • each of the first to fourth transmission stages can have a current mirror for connection to the at least one reference current source, the value of the current of the reference current source of a transmission stage being adjustable during operation of the transmission module.
  • the current mirror of each transmission stage can have two CMOS transistors, the CMOS transistors of the current mirror of the first transmission stage being PMOS transistors, the CMOS transistors of the current mirror of the second transmission stage being NMOS transistors, the CMOS transistors of the current mirror of the third Transmission stage are PMOS transistors, and wherein the CMOS transistors of the current mirror of the fourth transmission stage are NMOS transistors.
  • the reference current source has at least two current stages that are connected in parallel to one another.
  • At least one of the at least two current stages can be or have a current sink.
  • a number n of the at least two current stages for each of the first to fourth transmission stages may be the same, where n is a natural number greater than 1.
  • the transmission stage can be designed to set the value of the electrical current output by the transmission stage during operation of the transmission module at the input of the current mirror.
  • a current mirror can be connected to the first and third transmission stage and a current mirror to the second and fourth transmission stage, each transmission stage having at least two switches which are connected in parallel and are provided for switching on or off current stages of the transmission stage, and each the at least two switches of a transmission stage are connected to a decoupling transistor of the associated current mirror.
  • each current mirror comprises two CMOS transistors, the CMOS transistors of the current mirror connected to the first and third transmission stages being PMOS transistors and the CMOS transistors of the current mirror connected to the second and fourth transmission stages being PMOS transistors is, are NMOS transistors.
  • the output connections of the full bridge can be provided for connection to a terminating resistor of the bus.
  • the transmission module may also have a resistor one end of which is connected to the current mirror of the first transmission stage and the other end of which is connected to the current mirror of the third transmission stage, and a resistor one end of which is connected to the current mirror of the second transmission stage. and whose other end is connected to the current mirror of the fourth transmission stage.
  • each of the first through fourth transmit stages may also include a reverse polarity diode to protect against positive feedback in a bus voltage supply terminal and negative feedback from a ground terminal, and at least one cascode to protect the CMOS transistors.
  • At least two cascodes are connected in parallel, a number y of the cascodes being the same for each of the first to fourth transmission stages, y being a natural number greater than 1, and the on-resistance of the at least two cascodes being different.
  • the transmission module can also have a control circuit for controlling switchable components of the first to fourth transmission stages as a function of a digital transmission signal and of an operating mode set for the transmission module.
  • the drive circuit may be designed for the time-staggered and controlled switching of the resistance values of the at least two current stages.
  • the transmission module described above can be part of a transmission/reception device for a subscriber station for a serial bus system, which also has a reception module for receiving signals from the bus.
  • the transmitting/receiving device can be part of a subscriber station for a serial bus system, which also has a communication control device for controlling communication in the bus system and for generating a digital transmission signal for driving the first to fourth transmission stages.
  • the subscriber station may be designed for communication in a bus system in which exclusive, collision-free access by a subscriber station to the bus of the bus system is guaranteed at least temporarily.
  • the aforementioned object is also achieved by a method for sending differential signals in a serial bus system having the features of claim 20.
  • the method is carried out using a transmission module which has current mirrors for a first to fourth transmission stage, each current mirror being connected to at least one reference current source, and the method having the steps of generating, with a first transmission stage, transmission currents for a first signal, which is to be sent to a bus of the bus system, generating, with a second transmission stage, transmission streams for a second signal, which is to be sent to the bus as a signal which is different from the first signal, generating, with a third transmission stage, transmission streams for the first signal, and generating, with a fourth transmission stage, transmission currents for the second signal, the first to fourth transmission stages being connected in a full bridge in which the first and fourth transmission stages are connected in series and the third and second transmission stages are connected in series are, and each transmission stage the value of the output during operation of the transmission module from the transmission stage e electrical current at one of the current mirrors.
  • the method offers the same advantages as those mentioned above with regard to the transmission module.
  • FIG. 1 shows a simplified block diagram of a bus system according to a first exemplary embodiment
  • FIG. 2 shows a diagram to illustrate the structure of a message that can be sent by a subscriber station of the bus system according to the first exemplary embodiment
  • FIG. 3 shows an example of the ideal time profile of bus signals CAN_H, CAN_L in the bus system of FIG. 1;
  • FIG. 4 shows the time profile of a differential voltage VDIFF which forms on the bus of the bus system as a result of the bus signals from FIG. 4;
  • FIG. 5 shows an example of a time profile of a digital transmission signal which is to be converted into bus signals CAN_H, CAN_L for a bus of the bus system of FIG. 1 in the arbitration phase (SIC operating mode);
  • FIG. 6 shows the time profile of the bus signals CAN_H, CAN_L when changing from a recessive bus state to a dominant bus state and back to the recessive bus state, which are sent to the bus in the arbitration phase (SIC operating mode) on the basis of the transmission signal from FIG. 5;
  • FIG. 7 shows an example of a time profile of a digital transmission signal which is to be converted in the data phase into bus signals CAN_H, CAN_L for the bus of the bus system from FIG. 1;
  • FIG. 8 shows the time course of the bus signals CAN_H, CAN_L, which are sent to the bus in the data phase on the basis of the transmission signal from FIG. 6;
  • FIG. 9 shows a block diagram with a common mode choke in the bus system of FIG.
  • FIG. 10 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to the first exemplary embodiment
  • FIG. 11 is a timing diagram showing the turn-on of various power stages of a transmit stage for a first specific example of the transmit module of FIG. 10;
  • Figure 12 shows a detail of a transmission stage for a second specific example of the transmission module of Figure 10.
  • FIG. 13 shows a circuit diagram of a transmission module for a subscriber station of the bus system according to a second exemplary embodiment.
  • bus system 1 which, for example, can be a CAN bus system, a CAN FD bus system, etc., at least in sections.
  • the bus system 1 can be used in a vehicle, in particular a motor vehicle, an airplane, etc., or in a hospital, etc.
  • the bus system 1 has a large number of subscriber stations 10, 20, 30, which are each connected to a bus 40 or bus line with a first bus wire 41 and a second bus wire 42.
  • the bus cores 41, 42 can also be called CAN_H and CAN_L for the signals on the bus 40.
  • About the bus 40 messages 45, 46, 47 in the form of signals between the individual subscriber stations 10, 20, 30 are transmitted.
  • the subscriber stations 10, 20, 30 can be, for example, control devices or display devices of a motor vehicle.
  • the subscriber stations 10, 30 each have a communication control device 11 and a transceiver 12.
  • the transceiver 12 has a transmit module 121 and a receive module 122.
  • Subscriber station 20 has a communication control device 21 and a transceiver 22.
  • Transceiver 22 has a transmit module 221 and a receive module 222.
  • the transmitting/receiving devices 12 of the subscriber stations 10, 30 and the transmitting/receiving device 22 of the subscriber station 20 are each connected directly to the bus 40, even if this is not shown in FIG.
  • the communication control devices 11, 21 are each used to control communication between the respective subscriber station 10, 20, 30 via the bus 40 and at least one other subscriber station of the subscriber stations 10, 20, 30 that are connected to the bus 40.
  • the communication control devices 11 create and read first messages 45, 47, which are modified CAN messages 45, 47, for example.
  • the modified CAN messages 45, 47 are constructed, for example, on the basis of the CAN SIC format or the CAN XL format.
  • the transceiver 12 serves to send and receive the messages 45, 47 from the bus.
  • the transmission module 121 receives a digital transmission signal TxD created by the communication control device 11 for one of the messages 45, 47 and converts this into signals on the bus 40.
  • the reception module 121 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them.
  • the reception module 122 sends the reception signal RxD to the communication control device 11.
  • the communication control device 21 can be designed like a conventional CAN controller according to ISO 11898-1:2015, ie like a CAN FD tolerant classic CAN controller or a CAN FD controller.
  • the communication control device 21 creates and reads second messages 46, for example CAN FD messages 46.
  • the transceiver 22 is used to send and receive the messages 46 from the bus 40.
  • the transmission module 221 receives a digital transmission signal TxD and created by the communication control device 21 converts this into signals for a message 46 on the bus 40.
  • the reception module 221 receives signals sent on the bus 40 in accordance with the messages 45 to 47 and generates a digital reception signal RxD from them.
  • the transceiver 22 can be designed like a conventional CAN transceiver.
  • the two subscriber stations 10, 30 can be used to form and then transmit messages 45 with different CAN formats, in particular the CAN FD format or the CAN SIC format or the CAN XL format, and to receive such messages 45, as described in more detail below.
  • the frame 450 for the message 45 which is in particular a CAN XL frame, as is provided by the communication control device 11 for the transceiver 12 for transmission onto the bus 40.
  • the communication control device 11 creates the frame 450 as compatible with CAN FD.
  • the frame 450 is compatible with CAN SIC.
  • the frame 450 for the CAN communication on the bus 40 is divided into different communication phases 451, 452, namely an arbitration phase 451 (first communication phase) and a data phase 452 (second communication phase).
  • the frame 450 has, after a start bit SOF, an arbitration field 453, a control field 454, a data field 455, a checksum field 456 and a frame termination field 457.
  • an identifier with, for example, bits ID28 to ID18 in the arbitration field 453 is used to negotiate bit by bit between the subscriber stations 10, 20, 30 as to which subscriber station 10, 20, 30 is sending the message 45, 46 with the highest priority wants and therefore gets exclusive access to the bus 40 of the bus system 1 for the next time for sending in the subsequent data phase 452.
  • a physical layer is used as in CAN and CAN-FD.
  • the physical layer corresponds to the physical layer or layer 1 of the well-known OSI model (Open Systems Interconnection model).
  • phase 451 An important point during phase 451 is that the known CSMA/CR method is used, which allows subscriber stations 10, 20, 30 to access the bus 40 simultaneously without the higher-priority message 45, 46 being destroyed. As a result, further bus subscriber stations 10, 20, 30 can be added to the bus system 1 relatively easily, which is very advantageous.
  • the CS M A/CR method has the consequence that there must be so-called recessive states on the bus 40, which other subscriber stations 10, 20,
  • the individual subscriber stations 10, 20, 30 can be overwritten with dominant levels or dominant states on the bus 40.
  • the individual subscriber stations 10, 20, 30 In the recessive state, the individual subscriber stations 10, 20, 30 have high-impedance conditions, which, in combination with the parasites of the bus wiring, results in longer time constants. This leads to a limitation of the maximum bit rate of today's CAN FD physical layer to around 2 megabits per second in real vehicle use.
  • the data phase 452 in addition to part of the control field 454, the user data of the CAN-XL frame 450 or the message 45 from the data field 455 and the checksum field 456 are sent.
  • a checksum over the data of the data phase 452 including the stuff bits can be contained in the checksum field 456, which the sender of the message 45 inserts as an inverse bit after a predetermined number of identical bits, in particular 10 identical bits.
  • the arbitration phase 451 is switched back to.
  • At least one acknowledge bit may be included in an end field in the frame completion phase 457 . There may also be a sequence of 11 same bits indicating the end of the CAN XL frame 450. The at least one acknowledge bit can be used to communicate whether a receiver has discovered an error in the received CAN XL frame 450 or the message 45 or not.
  • a sender of the message 45 does not start sending bits of the data phase 452 to the bus 40 until the subscriber station 10 as the sender has won the arbitration and the subscriber station 10 as the sender thus has exclusive access to the bus 40 of the bus system 1 for sending .
  • the subscriber stations 10, 30 partially use a format known from CAN/CAN-FD in accordance with ISO11898-1:2015 as the first communication phase, in particular up to the FDF bit (inclusive).
  • the net data transmission rate can be increased, in particular to more than 10 megabits per second.
  • the transmission module 121 then generates the states L0 or LI for the signals CAN_H,
  • CAN_L on the bus 40.
  • the frequency of the signals CAN_H, CAN_L may be increased in the data phase 452 as shown on the right side in FIG.
  • the net data transfer rate in the data phase 452 is increased compared to the arbitration phase 451.
  • the transceiver 12 of the subscriber station 30 switches its physical layer at the end of the arbitration phase 451 from the first mode (SLOW) to a third mode (FAST_RX), since the subscriber station 30 in the data phase 452 only receives, i.e. no transmitter, of the frame is 450.
  • all transmitting/receiving devices 12 of the subscriber stations 10, 30 switch their operating mode to the first operating mode (SLOW).
  • all transceivers 12 also switch their physical layer.
  • the receiving module 122 can distinguish between the states 401, 402 and L0, LI with the receiving thresholds that are in the ranges TH_T1, TH_T2, TH_T3.
  • the reception module 122 uses at least the reception threshold TI of, for example, 0.7 V in the arbitration phase 451.
  • the reception module 122 uses the reception threshold T2 of, for example, -0.35 V, for example in the arbitration phase 451, but possibly also in the data phase 452.
  • the reception threshold T3 of, for example, 0.0V is used in the data phase 452.
  • the transmission module 121 receives from the communication control device 11 in the arbitration phase 451 and generates the signals CAN_H, CAN_L for the bus 40 therefrom.
  • the transmission module 121 for the transmission signal TxD from FIG. 5 generates the signals CAN_H, CAN_L for the bus cores 41, 42 in such a way that a state 403 (sic) is also present.
  • State 403 (sic) can have different lengths, as shown with state 403_0 (sic) when transitioning from state 402 (rec) to state 401 (dom) and state 403_1 (sic) when transitioning from state 401 ( dom) to state 402 (rec). State 403_0 (sic) is shorter in time than state 403_1 (sic).
  • the transmission module 121 is switched to a SIC operating mode (SIC mode).
  • SIC mode SIC operating mode
  • the term 403 (sic) or sic state 403 is always used below.
  • the transmission module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL.
  • the transmit module status sic can not only be generated for CAN-SIC or CAN-XL (xl_sic).
  • the transmission module status sic can also be generated with CAN FD. In CAN-FD, however, the time for the transmit module status sic can be shorter than in CAN-SIC or CAN-XL.
  • the transmission module 121 receives from the communication control device 11 in the data phase 452 and generates the signals CAN_H, CAN_L for the bus 40 therefrom.
  • a common-mode choke CMC can be connected between the transmitting/receiving devices 12, 22 on the bus 40.
  • the abbreviation "CMC" stands for the English term Common Mode Choke.
  • the common mode choke CMC has the two inductances Lh and LI.
  • the inductance Lh is connected to the bus core 41 for the signal CAN_H.
  • the inductance Lh is connected to the bus core 42 for the signal CAN_L.
  • a coupling factor k is effective between the inductances Lh and LI.
  • FIG. 9 shows the situation in which a differential signal CANH_TC, CAN_L_TC, which the transceiver 12 sent to the bus 40, arrives at the input of the common-mode choke CMC.
  • a differential signal CANH_B, CAN_L_B for the bus 40 is output at the output of the common-mode choke CMC, which signal is sent to the transceiver 22, among other things, as shown in FIG.
  • the differential signals CANH_TC, CAN_LB are the same and the differential signals CANH_TC, CAN_LB are the same.
  • the common-mode choke CMC Due to the physical component structure of the common mode choke CMC, its two inductances Lh and LI are usually not the same. For example, there is a offset of 0.1%. The consequence of this is that the common-mode choke CMC superimposes an undesired common-mode signal CMC_H, CMC_L on the differential signal CANH_TC, CAN_L_TC at its input, which has no common-mode component, and outputs it at its output.
  • the differential signal CANH_B, CAN_L_B contains a common mode signal CMC_H, CMC_L in addition to the differential signal CANH_TC, CAN_L_TC. This is unfavorable since the common mode signal CMC_H, CMC_L is fed directly into the bus 40 on the bus side, as shown in FIG. This increases the emission of the bus system 1 or in particular a subscriber station 10, 20, 30.
  • the transmission module 121 described below can reduce the previously described effect of the common mode choke CMC.
  • Fig. 10 shows the basic structure of the transmission module 121 for one of the subscriber stations 10, 30.
  • the transmission module 121 can signals CAN_H, CAN_L according to FIG. 5 with the states 401, 402, 403 and signals CAN_H, CAN_L according to FIG. 8 with the states Generate LO, LI.
  • the transmission module 121 has four transmission stages, namely a first transmission stage 121A, a second transmission stage 121B, a third transmission stage 121C and a fourth transmission stage 121D. As shown in FIG. 10, the transmission stages 121A to 121D are connected as a full bridge. The components of the transmission stages 121A to 121D, which are described in more detail below, are controlled via at least one control device 124. At least one control device 124 sends at least one signal to control terminals 125 to which the components of the transmission stages 121A to 121D are connected. For the sake of clarity, not all of the line connections for this are shown in FIG.
  • the transmission module 121 is connected to the bus 40, more precisely its first bus core 41 for CAN_H or CAN-XL_H and its second bus core 42 for CAN_L or CAN-XL_L.
  • Each of the transmission stages 121A to 121D is connected to the bus 40.
  • the connection to ground or CAN_GND is implemented via a connection 44.
  • the first and second bus wires 41, 42 are terminated with a terminating resistor 49.
  • the terminating resistor 49 is connected to the full bridge as an external load resistor.
  • the resistor 49 is connected in the bridge branch between the connections for the bus wires 41, 42.
  • the first transmission stage 121A of FIG. 10 has a reverse polarity diode D_A, at least first through y-th transistors HVP_A1 through HVP_Ay connected in parallel with one another, and a stage circuit 121A1.
  • y is a natural number > 1.
  • the stepping circuit 121A1 has a current mirror with a reference current of a current source IrefA1..n, which is a first to n-th current source IrefAl to IrefAn corresponding to the current sources IrefDl to IrefDn according to FIG. 11, where n is a natural number>1.
  • the current source IrefAl..n forms a first to nth current stage S1 to Sn, which supply the electric currents II to In, as described in more detail with reference to FIG.
  • a control circuit T_A is also present.
  • the current mirror has a reference transistor P_Aref, which is connected to the current source IrefAl..n, and a decoupling transistor P_Ao.
  • the transistors HVP_A1 to HVP_Ay can each be a CMOS transistor, in particular a PMOS transistor.
  • the transistors P_Aref and P_Ao of the current mirror can be CMOS transistors, in particular PMOS transistors.
  • CMOS denotes a semiconductor device that uses both p-channel and n-channel MOSFETs on a common substrate.
  • CMOS stands for the English term “Complementary metal-oxide-semiconductor”, which means “complementary / complementary metal-oxide-semiconductor”.
  • MOSFET stands for metal oxide field effect transistor.
  • the control circuit T_A controls the current sources lref_Al to lref_An of the first to the nth current stage according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121 .
  • the second transmission stage 121B of FIG. 10 has a reverse polarity diode D_B, at least first through y-th transistors HVN_B1 through HVN_By connected in parallel with each other, and a stage circuit 121B1.
  • y is the natural number >1.
  • the stage circuit 121 Bl has a current mirror with a reference current of a current source IrefBl..n, which has a first to nth current source IrefBl to IrefBn corresponding to the current sources IrefDl to IrefDn according to FIG. 11, where n is a natural number > 1.
  • the current source IrefBl..n forms a first to nth current stage S1 to Sn, which supply the electric currents II to In, as described in more detail with reference to FIG.
  • a control circuit T_B is also present.
  • the current mirror has a reference transistor N_Bref, which is connected to the first to nth current sources IrefBl to IrefBn, and a decoupling transistor N_Bo.
  • the transistors HVN_B1 to HVN_By can each be a CMOS transistor, in particular an NMOS transistor.
  • the transistors N_Bref and N_Bo of the current mirror can be CMOS transistors, in particular NMOS transistors.
  • the control circuit T_B controls the current sources lref_Bl to lref_Bn of the first to the nth current stage according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.
  • the third transmission stage 121C of FIG. 10 has a reverse polarity diode D_C, at least first through y-th transistors HVP_C1 through HVP_Cy connected in parallel with each other, and a stage circuit 121C1.
  • y is the natural number > 1.
  • the stepping circuit 121C1 has a current mirror with reference current of a current source IrefCl..n, which has a first to n-th current sources IrefCl to IrefCn corresponding to the current sources IrefDl to IrefDn in FIG natural number > 1.
  • the current source IrefDl..n forms a first to nth current stage S1 to Sn, which supply the electric currents II to In, as described in more detail with reference to FIG.
  • a control circuit T_C is also present.
  • the current mirror has a reference transistor P_Cref, which is connected to the first to nth current sources IrefCl to IrefCn, and an output transistor P_Co.
  • the transistors HVP_C1 to HVP_Cy can each be a CMOS transistor, in particular a PMOS transistor.
  • the transistors P_Cref and P_Co of the current mirror can be CMOS transistors, in particular PMOS transistors.
  • the control circuit T_C controls the current sources lref_Cl to lref_Cn of the first to n-th current levels according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.
  • the fourth transmission stage 121D of FIG. 10 has a polarity reversal diode D_D, at least one first to yth transistor HVN_D1 to HVN_Dy, which are connected in parallel, and a stage circuit 121Dl Current mirror with reference current of a current source IrefDl..n, which has a first to n-th current source IrefDl to IrefDn according to FIG. 11, where n is a natural number >1.
  • the current source IrefDl..n forms a first to nth current stage S1 to Sn, which supply the electric currents II to In, as shown and described in more detail with reference to FIG.
  • a control circuit T_D is also present.
  • the current mirror has a reference transistor N_Dref, which is connected to the first to nth current sources IrefDl to IrefDn, and a decoupling transistor N_Do.
  • the transistors HVN_D1 to HVN_Dy can each be a CMOS transistor, in particular an NMOS transistor.
  • the transistors N_Dref and N_Do of the current mirror can be CMOS transistors, in particular NMOS transistors.
  • the control circuit T_D controls the current sources lref_Dl to lref_Dn of the first to n-th current stages according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 121.
  • the number y can be chosen arbitrarily.
  • the number y and thus the number of high-voltage transistors HVN_D1 to HVN_Dy in a transmission stage 121A, 121B, 121C, 121D can be selected between 1 and 4.
  • a number greater than 4 can be selected for y.
  • the number n can be chosen arbitrarily. In particular, the number n and thus the number of stages or number of current stages can be selected between 1 and 60. Alternatively, however, a number greater than 60 can be selected for n.
  • a resistor R_SIC_H is connected between the transmission stages 121A, 121C.
  • One end of resistor R_SIC_H is connected to the anode of reverse polarity diode D_A and the drain of transistor P_Ao.
  • the other end of resistor R_SIC_H is connected to the anode of reverse polarity diode D_C and the drain of transistor P_Co.
  • a resistor R_SIC_L is connected between the transmission stages 121D, 121B.
  • One end of the resistor R_SIC_L is connected to the source of the transistors HVN_D1 to HVN_Dy and to the drain of the transistor N_Ao.
  • the other end of the resistor R_SIC_L is connected to the source of the transistors HVN_B1 to HVN_By and to the drain of the transistor N_Bo.
  • Each of the polarity reversal diodes D_A, D_B, D_C, D_D protects the associated transmission stage against positive feedback on connection 44 (CAN-Supply) and negative feedback on connection 43 (CAN_GND).
  • Each of the polarity reversal diodes D_A, D_B, D_C, D_D can also be referred to as a blocking diode.
  • Each of the stage circuits 121A1, 121B1, 121C1, 121D1, more precisely the associated control circuit T_A, T_B, T_C, T_D, provides a transmission current value for the associated transmission stage 121A, 121B, 121C, 121D depending on the operating mode for arbitration or data phase of the transmission module 121 and the transmission signal TxD. Explanations are also included in Table 1.
  • the transmission current value of the individual transmission stages 121A, 121B, 121C, 121D can thus be adjusted depending on the operating mode, such as arbitration (SLOW or SIC) or data phase (FAST_TX or FAST_RX) of the transmission module 121 and the transmission signal TxD.
  • Each transmission stage 121A to 121D is thus configured to set the value of the electric current IA1 to IAn etc. output by the transmission stage 121A to 121D during operation of the transmission module 121 at the input of the current mirror that is present in the respective transmission stages 121A to 121D.
  • the electrical currents IA1 to IAn etc. can also be referred to as II to In for the tapped circuits 121A1, 121B1, 121C1, 121D1.
  • the setting of the transmission current values is described in more detail below with reference to FIG. 11 and FIG.
  • Each of the transistors HVP_A1 to HVP_Ay, HVN_B to HVN_By, HVP_C to HVP_Cy, HVN_D to HVN_Dy is an HV cascode and may also be referred to as an HV standoff device.
  • the transistors HVP_A1 to HVP_Ay protect the CMOS transistors P_Ao, P_Aref of the current mirror by the transistors HVP_A1 to HVP_Ay absorbing high voltage drops.
  • Each of the transistors HVN_B to HVN_By, HVP_C to HVP_Cy, HVN_D to HVN_Dy has the same function for the CMOS transistors of the respectively associated stage circuits 121B1, 121C1, 121D1.
  • the transmission stage 121A is connected between the connection 43 for the voltage supply and the connection 41 (CANH) for the signal CAN_H.
  • the transmission stage 121C is connected between the connection 43 for the voltage supply and the connection 42 (CANL) and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 121D is connected between the connection 41 (CANH) for the CAN_H signal and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 121B is connected between the connection 42 (CANL) for the signal CAN_L and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 121A is in the CANH path switched.
  • the transmission stage 121D is connected to the CANH path.
  • the transmission stage 121C is switched into the CANL path.
  • the transmission stage 121B is switched to the CANL path.
  • the transmission module 121 has parallel circuits of a specific number of current stages in the stage circuits 121A1, 121B1, 121C1, 121D1.
  • the current of the current stages is determined by the current sources lrefAl..n, lrefBl..n, lrefCl..n, lrefDl..n.
  • the first current stage S1 has the current source IrefDl.
  • the second current stage S2 has the current source IrefD2.
  • the nth current stage Sn has the current source IrefDn.
  • at least one of the current sources IrefDl to IrefDn is a current sink.
  • the current sources IrefAl..n, current sources IrefBl..n, current sources IrefCl..n of the step circuits 121A1, 121B1, 121C1 are constructed in the same way.
  • the parallel connection of all current stages is connected in series in the CANH path and in the CANL path with at least one HV cascode HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy and a polarity reversal diode D_A, D_B, D_C, D_D, as previously described.
  • HV cascodes HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVN_Dy allow compliance with limit values (maximum rating parameters), such as voltage at CANH and CANL -27V to +40V.
  • the driver current of the transmission stages is 121A/121B and the transmission stages 121C/121D.
  • the driving current of the transmission stages 121A/121B and the transmission stages 121C/121D is supplied from the current stages of the associated stage circuits 121A1/121B1 and 121C1/121D1.
  • the transmission module 121 or the respective transmission stage 121A, 121B, 121C, 121D is switched off or not switched to be conductive.
  • the resistors R_SIC_H and R_SIC_L are used to set the differential resistance between the connections CANH, CANL during the transmission module state (SIC state).
  • the resistors R_SIC_H, R_SIC_L each have a value of 240 ohms, for example.
  • the aim is to set an impedance of 120 ohms according to the characteristic impedance Zw of the bus cores 41, 42.
  • the impedance of the current mirrors of all four transmission stages 121A, 121B, 121C, 121D can be selected to be significantly greater than 240 ohms. In simplified terms, this leads to a parallel connection of the two 240 ohm resistors and thus to an adjusted impedance of 120 ohms.
  • a differential resistance between the connections CANH, CANL can be set with the transmission stage 121 even in the state 401 (dom), which matches the characteristic impedance of the bus cores 41, 42 of typically 120 ohms each. This avoids reflections in state 401 (dom).
  • An additional advantage of the configuration of the transmission stage 121 described is that the current which flows in the two paths of the transmission stages 121 A/D and 121 B/C during the state 403 (sic) can be set arbitrarily or “freely”, as indicated in Table 1.
  • each stage circuit 121A1, 121B1, 121C1, 121D1 of Fig. 10 into n parts or the n current stages allows a time-staggered and controlled switching process between the bus states 401, 402, 403 in the arbitration phase (SIC mode) 451 or the Bus states L0, LI of the data phase 452.
  • the current values of the n current stages are set for this, as illustrated in a special example with FIG.
  • 12 shows an example of the current level per switching stage or current stage S1 to S12.
  • the value of the current I (vertical axis in FIG. 12) or II, 12, 16, 112 etc. is set by selecting the value of the electric current of the respective current stage S1 to S12.
  • the individual current stages S1 to S12 (horizontal axis in FIG. 12) thus have current sources IrefD1, IrefD2 to IrefDn, which supply an electric current with different current values.
  • the individual current stages Sl to S12 are activated using the drive circuits T_A, T_B, T_C, T_D of the stage circuits 121A1, 121B1, 121C1 , 121D1 switched on or off at different times.
  • a corresponding electric current I flows in the CANH path or CANL path into which the higher-order transmission stage 121A, 121B, 121C, 121D is connected.
  • the transmission module 121 (transmitter) of FIG. 10 with FIG. 11 specifies the current which, due to the DCMR effect of the common mode choke CMC of FIG.
  • CM interference causes the CM interference described with reference to FIG.
  • the CM interference is attenuated by the common mode choke CMC of FIG.
  • the transmission module 121 (transmitter) of Fig. 10 with Fig. 11 is therefore more advantageous in connection with a common-mode choke CMC than a transmission stage in which the transmission module (transmitter) specifies the voltage (differential voltage) which is then transferred from the common-mode choke CMC to the bus 40 is transmitted as previously described for FIG.
  • the current in the CANH path and in the CANL path for generating a dominant level on the bus 40 is gradually increased by switching on the current stages of the stage circuits 121A1, 121B1, 121C1, 121D1 with a time offset.
  • the transition from a state 401 (dominant) to a state 402 (recessive), which corresponds to a falling edge of the differential voltage VDIFF of FIG Current in the CANH and CANL path is gradually reduced.
  • the entire current which is given by the sum of the currents II to I12 or II to In of all current stages S1 to Sn, flows during state 401 (dominant).
  • the bus signals CAN_H, CAN_L By setting the time and by selecting the current levels of the individual current stages S1 to S12, it is possible to use the bus signals CAN_H, CAN_L to adapt to one another during the transition between the states 401, 402, so that the symmetrical course of CAN_H and CAN_L according to FIG. 6 is realized.
  • the structure of the transmission module 121 enables the individual current stages of the stage circuits 121A1, 121B1, 121C1, 121D1 to be switched on at different times. This time control makes it possible to align the signal form of CAN_H and CAN_L as required according to FIG. Targeted shaping of the signal curves for CAN_H and CAN_L is possible.
  • the bus states 401, 402, 403 in the arbitration phase 451 or the bus states L0, LI in the data phase 452 can be formed depending on the specifications.
  • the currents of the individual current stages S1 to Sn of the stage circuits 121A1, 121B1, 121C1, 121D1 and thus their respective proportion of the total current can be selected in different ways in order to achieve the lowest possible emission, in particular a low emission of the transmission module 121.
  • Advantageous for a low emission is to add or remove little current at the beginning and at the end of a switching process between bus states 401, 402 and to add or remove a large amount of current in the middle of the switching process. Therefore, the setting of the currents II, I2 to In of the current stages S1 to S12 shown in FIG. 12 is very advantageous.
  • the configuration according to FIGS. 10 to 12 avoids a current increase during turn-off, the transition from the state 401 (dominant) to the State 402 (Recessive).
  • the granularity of the time grading (staggering) for switching the individual current stages S1 to S12 on or off is in a range of around 2 ns. Such small steps or time staggering steps cause little common mode interference and have little negative impact on the emission.
  • the current steps, which are set via the current stages S1, S2 to S6 to S12, are kept fixed and the grading over time varies, so that the behavior is as soft as possible during the switch-on process (according to the Gaussian error function).
  • the variation the time steps or time stages also prevents the occurrence of a narrow-band frequency line in the emission frequency spectrum.
  • the staggering steps can be carried out using fixed time steps and varied current steps.
  • the structure of the transmission module 121 shown enables symmetrical switching of the bus signals CAN_H and CAN_L (Fig. 6) with steep switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, LI of the data phase 452 allows.
  • the switching edges between the bus states 401, 402, 403 in the arbitration phase (SIC operating mode) 451 or the bus states L0, LI of the data phase 452 realized.
  • the symmetry of the time profile of the bus signals CAN_H and CAN_L which is necessary to comply with the emission limit values, is achieved during the switching processes.
  • a comparison (matching) of the characteristic curves is achieved by the selection or use of the current sources of the step circuits 121A1, 121B1, 121C1, 121D1.
  • the adjustment (matching) of the characteristic curves is therefore less dependent on parameters of the transistors used in the stage circuits 121A1, 121B1, 121C1, 121D1.
  • Dominant state 401 (dom) is determined by matching tap circuit 121A1 with tap circuit 121B1.
  • the term “adjustment” means an active trimming step according to one possibility.
  • “adjustment” means that the values of the current sources of the step circuits 121A1, 121Bl match as well as possible, which by default takes place without an adjustment step or trimming step.
  • the Sic state (sic) is determined by matching tap circuit 121A1 with tap circuit 121C1 and matching tap circuit 121D1 with tap circuit 121B1.
  • the LO state is determined by matching tap circuit 121A1 with tap circuit 121B1.
  • State LI is determined by matching stage circuit 121C1 with stage circuit 121D1.
  • the transmission stage of FIG. 10 is operated without staggering steps.
  • the control circuits T_A, T_B, T_C, T_D are designed, the electrical currents IA1..h, IA1..h, IAl...n, IAl...n, which are used to generate the corresponding states dom, sic, rec, LI, L2 with the transmission stages 121A, 121B, 121C, 121D are required to be set directly via the current sources lrefAl..n, lrefBl..n, lrefCl..n, lrefDl...n of the stage circuits 121A1, 121B1, 121C1, 121D1 .
  • control circuits T_A, T_B, T_C, T_D are designed to transmit the electrical currents IAl..n, IAl..n, IAl..n, IAl..n, which are used to generate the corresponding states dom, sic, rec, LI, L2 with the transmission stages 121A, 121B, 121C, 121D are required, via the current level and/or time offset and/or edge steepness (slew rate) of the electrical currents IAl..n, IAl..n, IAl..n, IAl. .n to set.
  • the transmission module 121 has the following functions in addition to the functions according to the first or second embodiment.
  • the drive circuits T_A, T_B, T_C, T_D are designed to produce Effect 1 and Effect 2 described below independently of one another by different current levels of the stage circuits 121A1, 121B1, 121C1, 121D1, which are set depending on the state of the transmission module 121 compensate.
  • the transmission module 121 in the present exemplary embodiment can have an unequal Prevent behavior of components in transmission stages 121A/121D and 121C/ 121B of the full bridge (Effect 2), so that in the sic state a change in the common mode voltage compared to the rec state 402 is minimized or prevented.
  • the transmission module 121 is able, due to its design, to reduce effects due to asymmetrical behavior of the transmission stages, which can occur in the transmission states dom (401), sic (403), rec (402) and increase the overshoot and therefore deteriorate the emission.
  • the effect 1 can be damped by the cascodes of the transmission stages 121A, 121B.
  • the resistance Ron (switch-on resistance) of the cascodes in the transmission stages 121A, 121B can be changed, in particular by activation with the respectively associated activation circuit T_A, T_B. This is done by changing the up to y parallel-connected transistors HVP_A1 to HVP_Ay and/or the up to y parallel-connected transistors HVN_B1 to HVN_By.
  • the cascodes from the transmission stages 121D In order not to change the symmetry of the two series circuits of the transmission stages 121A, 121D and the transmission stages 121C, 121B in the sic state 403, the cascodes from the transmission stages 121D,
  • each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVP_Dy is connected to a connection 125 at its control connection (gate connection). Each of these transistors can thus be controlled by the at least one control device 124 .
  • the intervention for correcting the common mode level in the dom state 401 takes place via an equal or the same change from HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy or via an equal or the same change from HVP_D1 to HVN_Dy and HVP_B1 to HVN_By.
  • the configuration of the transmission module 121 can prevent substrate current losses in particular in the polarity reversal diodes D_A and D_B from causing the common-mode level in the dom state 401 to no longer be correct.
  • the polarity reversal diodes D_A and D_B are energized to a lesser extent and all polarity reversal diodes D_A, D_B, D_C, D_D of the four transmission stages 121A, 121B, 121C, 121D are also active.
  • the transmit module 1210 can prevent different common mode levels from being present in the dom state and in the sic state. In addition, it can be prevented that effects of the same quality are produced by unequal behavior in the cascodes.
  • the transmission module 121 can positively influence the effects on the emission values of the transmission/reception device 12, which are decisively influenced by the transmission module 121.
  • Fig. 13 shows the basic structure of a transmission module 1210 according to a fourth exemplary embodiment for one of the subscriber stations 10, 30.
  • the transmission module 1210 can send signals CAN_H, CAN_L according to FIG. 5 with the states 401, 402, 403 and signals CAN_H, CAN_L according to FIG. 8 with the states L0, LI.
  • the transmission module 1210 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC and CAN-XL.
  • the states for the bus 40 can be generated as indicated in Table 1 above.
  • the transmission module 1210 has four transmission stages, namely a first transmission stage 1210A, a second transmission stage 1210B, a third transmission stage 1210C and a fourth transmission stage 1210D. As shown in FIG. 13, the transmission stages 1210A to 1210D are connected as a full bridge. The control of components of the transmission stages 1210A to 1210D described in more detail below takes place via at least one control device 124. At least one control device 124 sends at least one signal to control connections 125 to which the components of the transmission stages 1210A to 1210D are connected. For the sake of clarity, not all of the line connections for this are shown in FIG.
  • the transmission module 1210 has a first supply circuit 1211 and a second supply circuit 1212.
  • the first supply circuit 1211 can be connected to a connection module 1210A0 with the first transmission stage 1210A.
  • the first supply circuit 1211 with a Connection module 1210C0 connected to the third transmission stage 1210C.
  • the second supply circuit 1212 can be connected to the second transmission stage 1210B with a connection module 1210B0.
  • the second supply circuit 1212 can be connected to the fourth transmission stage 1210D with a connection module 1210D0.
  • Each connection module 1210A0, 1210C0 carries a multiplicity of electrical lines between the first supply circuit 1211 and the associated transmission stage 1210A, 1210C, as described in more detail below.
  • connection module 1210B0, 1210D0 carries a multiplicity of electrical lines between the second supply circuit 1212 and the associated transmission stage 1210B, 1210D, as described in more detail below.
  • the connection modules 1210A0, 1210B0, 1210C0, 1210D0 can, in particular, pass through at least one of the lines between the second supply circuit 1212 and the associated transmission stage 1210A, 1210C, 1210B, 1210D without interruption.
  • the connection modules 1210A0, 1210B0, 1210C0, 1210D0 are optional.
  • the transmission module 1210 is connected to the bus 40, more precisely its first bus core 41 for CAN_H or CAN-XL_H and its second bus core 42 for CAN_L or CAN-XL_L. Connected to the bus 40 are each of the transmit stages 1210A-1210D.
  • the transmission stages 1210A, 1210C are connected between the first supply circuit 1211 and the bus 40.
  • FIG. The transmitter stages 1210D, 1210B are connected between the second supply circuit 1212 and the bus 40.
  • the first and second bus wires 41, 42 are terminated with the terminating resistor 49.
  • the terminating resistor 49 is connected to the full bridge as an external load resistor.
  • the resistor 49 is connected in the bridge branch between the connections for the bus wires 41, 42.
  • the at least one connection 43 is connected to the first supply circuit 1211 .
  • at least one connection 43 is connected to the second supply circuit 1212 .
  • the first supply circuit 1211 has a current mirror with a reference current of at least one current source IrefAC.
  • the current mirror of the first supply circuit 1211 has a reference transistor P_ACref, which is connected to the at least one current source IrefAC.
  • the at least one current source IrefAC is connected to the source connection of the reference transistor P_ACref.
  • the at least one current source IrefAC is connected to ground or CAN_GND via at least one connection 44 .
  • the current mirror has a number of z decoupling transistors, namely a decoupling transistor P_ACo_l to P_ACo_z.
  • z is a natural number >1.
  • the gate connection of each decoupling transistor P_ACo_l to P_ACo_z is connected to the gate connection and the source connection of the reference transistor P_ACref.
  • the transistor P_ACref and the transistors P_ACo_l to P_ACo_z of the current mirror can be CMOS transistors, in particular PMOS transistors.
  • Each of the 1 to z decoupling transistors P_ACo_l to P_ACo_z is connected with a separate line to one of the current stages of the transmission stage 1210A and/or to one of the current stages of the transmission stage 1210C. This is illustrated in FIG. 13 with the identification l..z and the associated connection module 1210A0, 1210C0.
  • the at least one current source IrefAC supplies an electric current I0_AC for a first to a-th current stage S1 to Sa of the first transmission stage 1210A.
  • a is a natural number >1.
  • the first to a-th current stages S1 to Sa supply the electrical currents I_A1 to I_Aa of the transmission stage 1210A analogously to the description of FIG. 11 .
  • the at least one current source IrefAC forms the power supply for the first to c-th current stages S1 to Sc of the third transmission stage 1210C.
  • c is a natural number > 1.
  • the first to c-th current stages S1 to Sc supply the electric currents I CI to I Cc of the transmission stage 1210C analogously to the description of FIG. 11 .
  • the stage circuit 1210A1 has first through a-th transistors P_Ao_l through P_Ao_a, which form the first through a-th current stages S1 through Sa and which supply electric currents I_A1 through I_Aa, as mentioned above.
  • a control circuit T_A is also present.
  • Each of the transistors HVP_A1 to HVP_Ay can be a CMOS transistor, in particular a PMOS transistor.
  • the transistors P_Ao_l to P_Ao_a can be CMOS transistors, in particular PMOS transistors.
  • the drain terminals of the transistors P_Ao_l to P_Ao_a are connected to one another.
  • the junction of the drain terminals of the transistors P_Ao_l to P_Ao_a is connected to one end of the resistor R_SIC_H and to the anode of the reverse polarity diode D_A.
  • the control circuit T_A controls the transistors P_Ao_l to P_Ao_a of the first to a-th current stages S1 to Sa according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 1210, as previously described with reference to FIG. 11 in particular.
  • the third transmission stage 1210C of FIG. 13 has a reverse polarity diode D_C, at least first through y-th transistors HVP_C1 through HVP_Cy connected in parallel with one another, and a stage circuit 1210C1.
  • y is the natural number > 1.
  • the stage circuit 1210C1 has first to c-th transistors P_Co_l to P_Co_c, which form the first to c-th current stages S1 to Sc and which supply the electric currents I_C1 to l_Cc, as mentioned before.
  • a control circuit T_C is also present.
  • Each of the transistors HVP_C1 to HVP_Cy can be a CMOS transistor, in particular a PMOS transistor.
  • the transistors P_Co_l to P_Co_c can be CMOS transistors, in particular PMOS transistors.
  • the drain terminals of the transistors P_Co_l to P_Co_c are connected to one another.
  • the junction of the drain terminals of the transistors P_Co_l to P_Co_c is connected to one end of the resistor R_SIC_H and to the anode of the reverse polarity diode D_C.
  • the control circuit T_C controls the transistors P_Co_l to P_Co_c of the first to c-th current stages S1 to Sc according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 1210, as previously described with reference to FIG. 11 in particular.
  • the second supply circuit 1212 has a current mirror with a reference current of at least one current source IrefDB.
  • the current mirror of the second supply circuit 1212 has a reference transistor N_DBref, which is connected to the at least one current source IrefDB.
  • the at least one current source IrefDB is connected to the source connection of the reference transistor N_DBref.
  • the at least one current source IrefDB is connected to the at least one connection 43 at its other end.
  • the current mirror of the second supply circuit 1212 has a number of z decoupling transistors, namely a decoupling transistor N_DBo_l to N_DBCo_z.
  • z is the natural number >1.
  • the gate connection of each decoupling transistor N_DBo_l to N_DBo_z is connected to the gate connection and the source connection of the reference transistor P_ACref.
  • the transistor N_DBref and the transistors N_DBo_l to N_DBo_z of the current mirror can be CMOS transistors, in particular NMOS transistors.
  • Each of the 1 to z decoupling transistors N_DBo_l to N_DBo_z is connected to one of the current stages of the transmission stage 1210D and/or to one of the current stages of the transmission stage 1210B with a separate line. This is illustrated in FIG. 13 with the identification l..z and the associated connection module 1210D0, 1210B0.
  • the at least one current source IrefDB supplies an electric current I0_DB for a first to bth current stage S1 to Sb of the second transmission stage 1210B.
  • b is a natural number > 1.
  • the first to b-th current stages S1 to Sb supply the electrical currents I_B1 to I_Bb of the transmission stage 1210B analogously to the description of FIG. 11 .
  • the at least one current source IrefDB forms the power supply for the first to dth current stages S1 to Sd of the fourth transmission stage 1210D.
  • d is a natural number >1.
  • the first to ri te current stages S1 to Sd supply the electrical currents I D1 to I Dd of the transmission stage 1210D analogously to the description of FIG. 11 .
  • the second transmission stage 1210B of FIG. 13 has a reverse polarity diode D_B, at least first through y-th transistors HVN_B1 through HVN_By connected in parallel with one another, and a stage circuit 1210B1.
  • y is the natural number > 1.
  • the stage circuit 1210B1 has first to b-th transistors N_Bo_l to N_Bo_b, which form the first to b-th current stages S1 to Sb and which supply the electric currents I_B1 to l_Bb as mentioned before.
  • a control circuit T_B is also present.
  • Each of the transistors HVN_B1 to HVN_By can be a CMOS transistor, in particular an NMOS transistor.
  • the transistors N_Bo_l to N_Bo_b can be CMOS transistors, in particular NMOS transistors.
  • the drain terminals of the transistors N_Bo_l to N_Bo_b are connected to one another.
  • the junction of the drains of the transistors N_Bo_l to N_Bo_b is connected to one end of the resistor R_SIC_L and to the sources of the first to yth transistors HVN_B1 to HVN_By.
  • the control circuit T_B controls the transistors N_Bo_l to N_Bo_b of the first to b-th current stages S1 to Sb according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 1210, as previously described with reference to FIG. 11 in particular.
  • the fourth transmission stage 1210D of FIG. 13 has a reverse polarity diode D_D, at least first through y-th transistors HVN_D1 through HVN_Dy connected in parallel with one another, and a stage circuit 1210D1.
  • y is the natural number > 1.
  • the stage circuit 1210D1 has first to d-th transistors N_Do_l to N_Do_d, which form the first to d-th current stages S1 to Sd and which supply the electric currents I_D1 to l_Dd, as mentioned before.
  • a control circuit T_D is also present.
  • Each of the transistors HVN_D1 to HVN_Dy can be a CMOS transistor, in particular an NMOS transistor.
  • the transistors N_Do_l to N_Do_d can be CMOS transistors, in particular NMOS transistors.
  • the drain terminals of the transistors N_Do_l to N_Do_d are connected to one another.
  • the junction of the drains of the transistors N_Do_l to N_Do_d is connected to one end of the resistor R_SIC_L and to the sources of the first to yth transistors HVN_D1 to HVN_Dy.
  • the control circuit T_D controls the transistors N_Do_l to N_Do_d of the first to dth current stages S1 to Sd according to the transmission signal TxD and the set operating mode SIC, FAST_TX of the transmission module 1210, as previously described with reference to FIG. 11 in particular.
  • the number y can be chosen arbitrarily.
  • the number y and thus the number of high-voltage transistors HVN_D1 to HVN_Dy in a transmission stage 121A, 121B, 121C, 121D can be selected between 1 and 4.
  • a number greater than 4 can be chosen for y.
  • the numbers a, b, c, d can be chosen as desired, as specified in more detail using Table 3 below.
  • each of the numbers a, b, c, d and thus the number of stages or number of current stages between 1 and 60 can be selected.
  • a number greater than 60 can be selected for the numbers a, b, c, d.
  • the resistor R_SIC_H is connected between the transmission stages 1210A, 1210C.
  • One end of the resistor R_SIC_H is connected to the anode of the reverse polarity diode D_A and the drain terminals of the a transistors P_Ao_l to P_Ao_a.
  • the other end of the resistor R_SIC_H is connected to the anode of the reverse polarity diode D_C and the drain terminals of the a transistors P_Co_l to P_Co_a.
  • the resistor R_SIC_L is connected between the transmission stages 1210D, 1210B.
  • One end of the resistor R_SIC_L is connected to the source of the transistors HVN_D1 to HVN_Dy and to the drain of the d transistors N_Do_l to N_Do_d.
  • the other end of the resistor R_SIC_L is connected to the source of the transistors HVN_B1 to HVN_By and to the drain of the b transistors N_Bo_l to N_Bo_b.
  • Each of the polarity reversal diodes D_A, D_B, D_C, D_D protects the associated transmission stage against positive feedback on connection 44 (CAN-Supply) and negative feedback on connection 43 (CAN_GND).
  • Each of the polarity reversal diodes D_A, D_B, D_C, D_D can also be referred to as a blocking diode.
  • Each of the stage circuits 1210A1, 1210B1, 1210C1, 1210D1, more precisely the associated control circuit T_A, T_B, T_C, T_D provides a transmission current value for the associated transmission stage 1210A, 1210B, 1210C, 1210D depending on the operating mode for arbitration or data phase of the transmission module 1210 and of the transmit signal TxD. Explanations on this are also contained in Table 2 above. The values given in Table 2 for the impedances of the transmission module 121 and for the driver current for the transmission stages 121A/121B are the same as the values for the impedances of the transmission module 1210 and for the driver current for the transmission stages 1210A/1210B.
  • driver current for the transmission stages 121C/121D is equal to the values for the impedances of the transmission module 1210 and for the driver current for the transmission stages 1210C/1210D.
  • decoupling stages in particular decoupling transistors P_ACo_l...z, of the power supply circuit 1211 and of decoupling stages, in particular decoupling transistors N_DBo_l...z, of
  • Power supply circuit 1212 is basically freely selectable. The relationships between z and a, b, c, d, on the other hand, are fixed.
  • Table 3 shows an example of the values a, b, c, d, z that can be chosen for the transmit module 1212 of FIG. Table 3 thus shows an example of how many parallel-connected switching transistors of each transmission stage 1210A, 1210B, 1210C, 1210D are each conductive in order to set the corresponding states of the transmission module 1210 (transmitter states).
  • Table 3 Required number of switching transistors connected in parallel for the transmitter stages 1210A, 1210B, 1210C, 1210D depending on the status of the transmitter module
  • step by step in particular about 2ns per step, switched in a staggered manner.
  • the number z results from the number of current stages that are required to establish a dominant state dom.
  • P_ACo_l to P_ACo_z are used by the two transmission stages 1210A, 1210C.
  • P_ACo_z is only used by transmit stage 1210A.
  • only some of the z decoupling transistors N_DBo_l to N_DBo_z are used by the two transmission stages 1210B, 1210D.
  • the other part of the z decoupling transistors N_DBo_l to N_DBo_z is only used by the transmission stage 1210B.
  • the transmission current value of the individual transmission stage 1210A, 1210B, 1210C, 1210D can thus be set depending on the operating mode (SLOW or SIC, FAST_TX) of the transmission module 1210 and the transmission signal TxD.
  • Each transmission stage 121A to 121D is designed to set the value of the electric current I_A1 to l_Aa etc.
  • the electrical currents I_A1 to I_Aa etc. can also be referred to briefly as II to In for the tap changers 1210A1, 1210B1, 1210C1, 1210D1, as also explained above with FIGS. 11 and 12 and as explained below.
  • Each of the transistors HVP_A1 to HVP_Ay, HVN_B to HVN_By, HVP_C to HVP_Cy, HVN_D to HVN_Dy is an HV cascode and can also be referred to as an HV standoff device.
  • the transistors HVP_A1 to HVP_Ay protect the CMOS transistors P_Ao_l to P_Ao_a of the transmission stage 1210A1 by the transistors HVP_A1 to HVP_Ay absorbing high voltage drops.
  • Each of the transistors HVN_B through HVN_By, HVP_C through HVP_Cy, HVN_D through HVN_Dy has the same function for the CMOS transistors of the respective associated stage circuits 1210B1, 1210C1, 1210D1.
  • the transmission stage 1210A is connected between the connection 43 for the voltage supply and the connection 41 (CANH) for the signal CAN_H.
  • the transmission stage 1210C is connected between the connection 43 for the voltage supply and the connection 42 (CANL) and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 1210D is connected between the connection 41 (CANH) for the CAN_H signal and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 1210B is connected between the connection 42 (CANL) for the signal CAN_L and the connection 43 for ground or the connection 44 (CAN_GND).
  • the transmission stage 1210A is switched into the CANH path.
  • the transmission stage 1210D is switched to the CANH path.
  • the transmission stage 1210C is connected to the CANL path.
  • the transmission stage 1210B is switched to the CANL path.
  • the transmission module 121 has parallel circuits of a specific number of current stages in the stage circuits 1210A1, 1210B1, 1210C1, 1210D1.
  • the current of the current stages is determined by the current sources IrefAC, IrefDB and the switches of the transmission stages 1210A, 1210B, 1210C, 1210D, which are designed as transistors.
  • the transmission module 1210 of FIG. 13 thus has the four parts or transmission stages 1210A, 1210B, 1210C, 1210D and the resistors R_SIC_H, R_SIC_L and is connected to the external bus load resistor RL.
  • the current reference with the current sources IrefAC and IrefBD is permanently set in the transmission module 1210 from FIG.
  • the two current mirrors of the circuits 1211, 1212 each have z parallel-connected decoupling transistors decoupling transistors P_ACo_l..z and N_DBo_l...z.
  • the current reference sources IrefDB or IrefAC are not switched in a time-staggered manner, as in the previous exemplary embodiments, but the switching transistors of the transmitter stages 1210A, 1210B, 1210C, 1210D are switched as previously described.
  • the configuration of the transmission module 1210 according to FIG. 13 enables the current stages of the transmission stages 1210A, 1210B, 1210C, 1210D to be switched on step by step, staggered over time.
  • This configuration of the transmission module 1210 results in switching processes that are significantly more interference-free than in the switching of the transmission module 121 of the preceding exemplary embodiments.
  • the clearly interference-free switching operations of the transmitter module 1210 lead to significantly lower interference emissions and thus significantly lower emissions.
  • the reason for this is that the transmission module 1210 does not work on the sensitive reference of the current mirror gate line with high dynamics, like the transmission module 121 of the previous exemplary embodiments.
  • An additional advantage of the transmitter module 1210 of FIG. 13 is that the silicon area for the reference current generation, namely in the circuits 1211, 1212, is halved to quartered compared to that of the transmitter module 121 of the previous exemplary embodiments.
  • transmit module 1210 of Figure 13 Yet another advantage of the transmit module 1210 of Figure 13 is that the current reference is shared in circuits 1211, 1212 for transmit stages A/C and B/D. This leads to better matching of the L0/L1 levels for the bus 40.
  • the reference current sources IrefAC and IrefBD can be made dependent on one another. In this case only one reference current can be used.
  • the transmission module 1210 of Fig. 13 uses an adjustment or configuration method for the adjustment (matching) of the SIC/Dom states, which compares the currents I0_AC, I0_DB of the two reference current sources IrefAC and IrefBD to a specific extent adjusted in order to achieve the lowest possible common-mode interference on the bus wires 41, 42. This can reduce emissions.
  • the control device 124 is designed to adjust the values of the currents I0_AC, I0_DB of the reference current sources IrefAC, Iref_DB in order to compensate for effect 2 described above.
  • the transmission module 1210 in the present exemplary embodiment can prevent an unequal behavior of components in the transmission stages 1210A/1210D and 1210C/1210B of the full bridge (effect 2).
  • effect 2 the transmission stages 1210A/1210D and 1210C/1210B of the full bridge
  • the transmission module 1210 is able, due to its design, to reduce effects due to asymmetrical behavior of the transmission stages, which can occur in the transmission states dom (401), sic (403), rec (402) and the overshoot increase and therefore worsen the emission.
  • the previously described effect 1 can be damped by the cascodes of the transmission stages 1210A, 1210B.
  • the resistance Ron (switch-on resistance) of the cascodes in the transmission stages 1210A, 1210B can be changed, in particular by driving with the respectively associated control circuit T_A, T_B. This is done by changing the up to y parallel-connected transistors HVP_A1 to HVP_Ay and/or the up to y parallel-connected transistors HVN_B1 to HVN_By.
  • each of the transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, HVN_D1 to HVP_Dy is connected to a connection 125 at its control connection (gate connection).
  • Each of these transistors can thus be controlled by the at least one control device 124 .
  • the intervention for correcting the common-mode level in the dom state 401 takes place via an equal or the same change from HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy or via an equal or the same change from HVP_D1 to HVN_Dy and HVP_B1 to HVN_By.
  • the configuration of the transmission module 1210 can prevent substrate current losses in particular in the polarity reversal diodes D_A and D_B from causing the common mode level in the dom state 401 to no longer be correct.
  • the polarity reversal diodes D_A and D_B are energized to a lesser extent and, furthermore, all polarity reversal diodes D_A, D_B, D_C, D_D of the four transmission stages 1210A, 1210B, 1210C, 1210D are active.
  • the transmit module 1210 can prevent different common mode levels in the dom state and in the sic state available. In addition, it can be prevented that effects of the same quality are produced by unequal behavior in the cascodes.
  • the transmission module 1210 can positively influence the effects on the emission values of the transmission/reception device 12, which are decisively influenced by the transmission module 1210.
  • the previously described bus system 1 according to the first and second exemplary embodiment is described using a bus system based on the CAN protocol.
  • the bus system 1 according to the first and/or second exemplary embodiment can alternatively be another type of communication network in which the signals are transmitted as differential signals. It is advantageous, but not an essential requirement, that in the bus system 1 exclusive, collision-free access by a subscriber station 10, 20, 30 to the bus 40 is guaranteed at least for certain periods of time.
  • the bus system 1 is in particular a CAN bus system or a CAN HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.
  • the bus system 1 can be another communication network in which the signals are transmitted as differential signals and serially over the bus.
  • the functionality of the exemplary embodiments described above can be used, for example, in transmitting/receiving devices 12, 22 which are in a CAN bus system or a CAN HS bus system or a CAN FD Bus system or a CAN SIC bus system or a CAN XL bus system can be operated.
  • the two bus states 401, 402 at least temporarily, no dominant and recessive bus state is used, but instead a first bus state and a second bus state are used, both of which are driven.
  • An example of such a bus system is a CAN XL bus system.
  • subscriber stations 10, 30 can be present, of which at least one subscriber station uses a transmission module 121 according to FIG. 10 and at least one subscriber station uses a transmission module 1210 according to FIG. The number and arrangement of the subscriber stations 10, 20, 30 in the
  • Bus system 1 according to the first and second exemplary embodiment and modifications thereof is arbitrary. In particular, only subscriber stations 10 or only subscriber stations 30 are present in the bus systems 1 of the first or second exemplary embodiment.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Dc Digital Transmission (AREA)

Abstract

L'invention concerne un module de transmission (121; 1210A) et un procédé de transmission de signaux différentiels dans un système de bus série (1). Le module de transmission (121) présente un premier étage de transmission (121A ; 1210A) pour générer des courants de transmission (I1 à In) pour un premier signal (CAN _H) qui doit être transmis sur un bus (40) du système de bus (1), un deuxième étage de transmission (121B ; 1210B) pour générer des courants de transmission (I1 à In) pour un deuxième signal (CAN _L) qui doit être transmis sous la forme d'un signal différentiel par rapport au premier signal (CAN _H) sur le bus (40), un troisième étage de transmission (121C ; 1210C) pour générer des courants de transmission (I1 à In) pour le premier signal (CAN _H), un quatrième étage de transmission (121D ; 1210D) pour générer des courants de transmission (I1 à In) pour le deuxième signal (CAN _L), et des miroirs de courant pour les premier à quatrième étages de transmission (121A à 121D ; 1210A à 1210D), les premier à quatrième étages de transmission (121A à 121D ; 1210A à 1210D) sont reliés dans un pont complet, dans lequel les premier et quatrième étages de transmission (121A, 121D; 1210A, 1210D) sont connectés en série et les troisième et deuxième étages de transmission sont connectés en série, chaque miroir de courant étant connecté à au moins une source de courant de référence (IrefA1.n ; IrefB1.n ; IrefC1.n ; IrefD1.n ; IrefAC ; IrefDB), et chaque étage de transmission (121A à 121D ; 1210A à 1210D) étant conçu pour régler la valeur du courant électrique (I1 à In ; I_A1 à I_Aa) sortie par l'étage de transmission (121A à 121D6 ; 1210A à 1210D) pendant le fonctionnement du module de transmission (121) au niveau de l'un des miroirs de courant.
PCT/EP2022/065079 2021-07-08 2022-06-02 Module de transmission et procédé de transmission de signaux différentiels dans un système de bus série WO2023280488A1 (fr)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111431A (en) * 1998-05-14 2000-08-29 National Semiconductor Corporation LVDS driver for backplane applications
US20030193350A1 (en) * 2002-04-12 2003-10-16 Stmicroelectronics, Inc. Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
DE102013222782A1 (de) * 2013-11-08 2015-05-13 Robert Bosch Gmbh Teilnehmerstation für ein Bussystem und Verfahren zur Reduzierung von leitungsgebundenen Emissionen in einem Bussystem

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6111431A (en) * 1998-05-14 2000-08-29 National Semiconductor Corporation LVDS driver for backplane applications
US20030193350A1 (en) * 2002-04-12 2003-10-16 Stmicroelectronics, Inc. Versatile RSDS-LVDS-miniLVDS-BLVDS differential signal interface circuit
DE102013222782A1 (de) * 2013-11-08 2015-05-13 Robert Bosch Gmbh Teilnehmerstation für ein Bussystem und Verfahren zur Reduzierung von leitungsgebundenen Emissionen in einem Bussystem

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