WO2010001536A1 - Dispositif de circuit intégré à semi-conducteurs - Google Patents

Dispositif de circuit intégré à semi-conducteurs Download PDF

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Publication number
WO2010001536A1
WO2010001536A1 PCT/JP2009/002739 JP2009002739W WO2010001536A1 WO 2010001536 A1 WO2010001536 A1 WO 2010001536A1 JP 2009002739 W JP2009002739 W JP 2009002739W WO 2010001536 A1 WO2010001536 A1 WO 2010001536A1
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Prior art keywords
power supply
voltage
time
supply voltage
aging
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PCT/JP2009/002739
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English (en)
Japanese (ja)
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拓也 有村
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パナソニック株式会社
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Publication of WO2010001536A1 publication Critical patent/WO2010001536A1/fr

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly, to an improvement in a low power consumption LSI and a technique for reducing the power consumption of an LSI.
  • the power consumption in the system LSI can be broadly divided into dynamic power and leakage power caused by transistor switching.
  • the dynamic power Pd in the CMOS circuit is expressed by the following formula (1).
  • Examples of techniques for reducing dynamic power include clock gating that stops clocks at places where switching is not required, multi-power supplies that use a plurality of power supply voltages inside an LSI, and DVFS (dynamically changing voltage and frequency according to processing load) Dynamic Voltage and Frequency Scaling) is used.
  • clock gating that stops clocks at places where switching is not required
  • multi-power supplies that use a plurality of power supply voltages inside an LSI
  • DVFS dynamically changing voltage and frequency according to processing load Dynamic Voltage and Frequency Scaling
  • leakage current is classified into subthreshold leakage current, gate leakage current, junction leakage current, and the like.
  • it is necessary to reduce the gate oxide film thickness and reduce the threshold voltage Vth.
  • subthreshold leakage current and gate leakage current have increased due to miniaturization.
  • leakage power when viewed as an LSI has increased dramatically in recent years due to the influence of the adoption of a low Vt cell due to high speed, the increase in the number of elements due to high integration, and self-heating due to the increase in power density.
  • the leak current is so large that it is said to occupy the same proportion as the dynamic power in the process generation of 65 nm or less.
  • Technologies to reduce leakage power include high-k insulating film, multi-Vth that uses multiple types of Vth transistors, power shut-off that divides the LSI into multiple power domains and shuts off unnecessary domain power, board power Substrate bias control for applying a bias to Vth to control Vth is used.
  • Vth is reduced as the process is miniaturized, even if the absolute value of the variation amount of Vth is the same as the conventional one, the ratio of the absolute value to Vth increases. Yes.
  • Patent Document 1 discloses a semiconductor integrated circuit device in which a performance measurement circuit is provided inside an LSI, and the operation speed and power consumption of the circuit function module are measured and stored at the time of LSI inspection.
  • the device described in Patent Document 1 considers manufacturing variations for each chip, and selects a frequency, power supply voltage, and substrate bias that can achieve the lowest power consumption with the same performance.
  • the variation in Vth includes variations due to aging as well as manufacturing variations.
  • one example is that hot carriers generated in the channel of the MOSFET are injected and captured in the gate insulating film to cause fluctuations in Vth (speed deterioration). Therefore, in order to guarantee the operation of the LSI for a specified period, it is necessary to design and inspect such semiconductor devices over time. For this reason, in general, a design in which a speed deterioration due to secular change is added as a design margin in advance is performed. Further, in the inspection, a technique such as guaranteeing the operation during a specified period by subtracting the design margin from the inspection voltage in advance is employed.
  • the device since the design is performed assuming that the operation speed becomes slow due to aging deterioration, there is an unnecessary speed margin at the initial stage of use where aging deterioration does not occur. That is, at the initial stage of use, the device operates at a voltage value higher than the device capability.
  • Patent Document 1 takes into account manufacturing variations, but cannot provide a solution for these problems due to aging.
  • An object of the present invention is to provide a low power consumption LSI and a semiconductor integrated circuit device that achieves low power consumption of the LSI without degrading other performance.
  • a semiconductor integrated circuit device is a semiconductor integrated circuit device in which transistors operating with a power supply voltage are integrated, and includes an actual use time measuring means for measuring the application time of the power supply voltage as an actual use time, and a measured actual use Storage means for storing time, an aging deterioration coefficient table for storing in advance the relationship between the power supply voltage application time and the operation voltage for guaranteeing the operation speed of the transistor, and the actual use time stored in the storage means An optimum operating voltage value is obtained from the value of the aging degradation coefficient table, and a power supply voltage control means for changing the power supply voltage based on the operating voltage value is adopted.
  • the low power consumption LSI and the low power consumption of the LSI can be achieved without degrading other performances by operating at a voltage that is lower by the aging deterioration margin at the initial stage of operation with little aging deterioration. be able to.
  • the figure which shows the transistor deterioration amount with respect to the actual use time of this invention The figure which shows the transistor operation minimum voltage with respect to the actual use time of this invention 1 is a block diagram showing a configuration of a semiconductor integrated circuit device according to a first embodiment of the present invention.
  • Block diagram showing a configuration of a semiconductor integrated circuit device according to a fourth embodiment of the present invention Block diagram showing a configuration of a semiconductor integrated circuit device according to a fifth embodiment of the present invention.
  • FIG. 1 is a diagram showing the amount of transistor deterioration with respect to the actual usage time, where the horizontal axis represents the actual usage time and the vertical axis represents the transistor deterioration amount [%].
  • the amount of deterioration increases with time from the initial deterioration amount Y (0) at the start of use, and finally deteriorates to the time point Y (X) of the product warranty period X (see FIG. 1a). Indicates progress. From the initial deterioration amount Y (0) at the start of use to the time point Y (X) of the product warranty period X is the transistor deterioration amount due to the use of X years (see FIG. 1b).
  • the reason why the deterioration amount at the start of use is Y (0) instead of 0 is as follows. That is, in a normal LSI inspection, a burn-in test for screening initial defects is performed. For this reason, a certain degree of deterioration occurs even at the start of use. Therefore, the amount of deterioration that occurs due to the actual usage time of the product warranty period X is Y (X) -Y (0). In other words, from the viewpoint of design, the LSI needs to be designed with a margin so that it can operate even if Y (X) speed degradation occurs. Y (0) before shipment is also Y (0). This means that an inspection considering the deterioration of X) is necessary.
  • FIG. 2 is a diagram showing the transistor operation lower limit voltage with respect to the actual use time.
  • FIG. 2 is obtained by replacing the vertical axis of the graph of FIG. 1 with the operating voltage of the transistor.
  • the curve in FIG. 2 is an operation lower limit voltage (V.limit), and indicates that it is necessary to supply a voltage equal to or higher than V.limit in order to operate the LSI normally.
  • V.limit operation lower limit voltage
  • the operation lower limit voltage (V.limit) increases, and it is finally necessary to supply V (X). For this reason, conventionally, it has been necessary to apply the reference operating voltage V.Ref so that the voltage does not become lower than the operation lower limit voltage V (X) in the product warranty period X.
  • V.Ref the reference operating voltage
  • V.limit the operating lower limit voltage
  • the inventor pays attention to this point and updates the set voltage in a certain period as V.New.
  • the voltage is set to a value as close as possible to V (0) and operated at a low voltage.
  • the voltage value is periodically updated so that it does not become lower than V.limit.
  • the voltage is set so as to approach V.Ref. Figure 2b. The shaded portion shown in FIG.
  • FIG. 3 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention based on the above basic concept.
  • the present embodiment is an example applied to a low power consumption LSI in which MOSFETs are integrated.
  • the low power consumption LSI 101 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, an aging degradation coefficient table 104, a nonvolatile storage device 105, and a power supply 106.
  • FIG. 3 shows the minimum necessary functional blocks, and an actual LSI has a plurality of functional blocks in addition to the functional blocks.
  • the low power consumption LSI 101 is supplied with a system power source 110 and a power-on reset 109 from an external power source 107.
  • the low-power consumption LSI 101 is supplied with a low-speed clock 111 from the RTC (Real Time Clock) 108 to the actual use time measuring unit 103.
  • RTC Real Time Clock
  • the power supply voltage control unit 102 is optimized according to the power supply voltage application time of the low power consumption LSI 101 based on the values of the power-on reset 109 from the external power supply 107 and the actual usage time measurement unit 103 and the aging degradation coefficient table 104. An operating voltage value is obtained, and the power supply voltage is changed based on the operating voltage value. Specifically, the power supply voltage control unit 102 instructs the optimum operating voltage corresponding to the usage time to the power supply 106 using information in the actual usage time measurement unit 103 and the aging degradation coefficient table 104.
  • the power supply voltage control unit 102 converts the speed deterioration due to aging deterioration into voltage, and performs power supply voltage control that lowers the operating power supply voltage and increases the voltage according to aging deterioration at the initial stage of use.
  • the power supply voltage control unit 102 periodically updates the aging deterioration time stored in the nonvolatile storage device 105 to the latest value.
  • the actual use time measuring unit 103 measures the power-on reset 109 from the external power supply 107 and the power supply voltage application time of the low power consumption LSI 101 as the actual use time. In particular, the actual use time measuring unit 103 measures the power supply voltage application time supplied to the LSI from the outside.
  • the aging degradation coefficient table 104 stores a relationship between the power supply voltage application time and the operating voltage for guaranteeing the operating speed of the transistor as a table value in advance. That is, in the aging deterioration coefficient table 104, the operation voltage value obtained by subtracting a voltage corresponding to the aging deterioration margin from the reference voltage is mainly stored at the initial stage of operation with little aging deterioration. In order to guarantee the performance, the operation voltage value that approaches the reference voltage step by step is stored.
  • the non-volatile storage device 105 stores the actual usage time measured by the actual usage time measurement unit 103. Specifically, since the nonvolatile storage device 105 periodically stores and updates the measured aging deterioration time, it stores the total aging deterioration time even when the external power source 107 is shut off.
  • the nonvolatile storage device 105 is configured by a nonvolatile memory such as an EEPROM, for example.
  • the power source 106 is supplied with a system power source 110 from an external power source 107, and variably supplies an operating power source voltage to the inside of the low power consumption LSI 101 supplied based on the system power source 110.
  • the power supply 106 can change the power supply voltage based on the operating voltage value notified by the power supply voltage control unit 102.
  • the system power supply 110 is turned on from the external power supply 107, and the operating power supply voltage of the low power consumption LSI 101 is boosted. After the power supply is stabilized, the power-on reset 109 is canceled, and the power supply voltage control unit 102 and the actual usage time measurement unit 103 start operating.
  • the actual usage time measurement unit 103 counts time using the low-speed clock 111 supplied from the RTC 108.
  • a low-speed clock supplied from the RTC 108 is used as a time measuring means for convenience, but any device capable of measuring time may be used.
  • the actual usage time measurement unit 103 supplies an interrupt signal 112 to the power supply voltage control unit 102 when measuring a certain period of time.
  • the power supply voltage control unit 102 detects the interrupt signal 112, it reads the actual use time stored from the nonvolatile storage device 105 and adds the value measured by the actual use time measurement unit 103 to calculate the current use time. To do.
  • the power supply voltage control unit 102 refers to the aging degradation coefficient table 104 and finds an optimum operating voltage corresponding to the calculated usage time. Thereafter, the power supply voltage control unit 102 notifies the power supply 106 of the power supply voltage control signal 113.
  • the calculated actual use time is written in the nonvolatile storage device 105.
  • the power supply 106 changes the power supply voltage 114 according to the instruction of the power supply voltage control signal 113. This cycle is periodically repeated to control the operating voltage to change according to the aging time.
  • the low power consumption LSI 101 mainly uses an operation voltage value obtained by subtracting a voltage corresponding to an aging deterioration margin from a reference voltage in an initial operation stage with little aging deterioration.
  • the aging deterioration coefficient table 104 stores the operation voltage value that gradually approaches the reference voltage in order to guarantee the same performance as the aging deterioration proceeds.
  • the optimum operating voltage value is obtained from the actual usage time stored in the device 105 and the value of the aging deterioration coefficient table 104, and the power supply voltage is changed based on this operating voltage value.
  • the power consumption of the power-powered LSI 101 can be reduced.
  • the circuit itself can be designed to have a smaller area / low power consumption at the time of design.
  • the speed margin due to aging deterioration is converted into voltage and subtracted from the operating power supply voltage to achieve low power consumption of the device at the initial stage of use without degrading performance.
  • the operating power supply voltage can be set low at the beginning of use, the degree of aging deterioration with respect to the usage time can be alleviated, and the life of the device can be extended.
  • the speed margin required at the time of design can be reduced by taking this mitigation into consideration, so the designed circuit itself can be designed to have a smaller area and lower power consumption. Is possible.
  • the interrupt signal 112 is supplied from the actual usage time measurement unit 103.
  • the power supply voltage control unit 102 uses another signal as a trigger to read the value of the actual usage time measurement unit 103. May be.
  • FIG. 4 is a block diagram showing a configuration of the semiconductor integrated circuit device according to the second embodiment of the present invention.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description of overlapping portions is omitted.
  • the low power consumption LSI 201 includes a power supply voltage control unit 202, a baseband signal processing unit 213, an aging degradation coefficient table 104, a nonvolatile storage device 205, and a power supply 106.
  • FIG. 4 shows the minimum necessary functional blocks, and an actual LSI has a plurality of functional blocks in addition to the functional blocks.
  • the low power consumption LSI 201 is supplied with a system power supply 110 and a power-on reset 109 from an external power supply 107.
  • the RF receiving unit 212 and the antenna 211 are connected to the baseband signal processing unit 213 of the low power consumption LSI 201.
  • the RF receiving unit 212 receives the RF signal 214 via the antenna 211 from a wireless network (not shown).
  • the RF receiving unit 212 outputs the received baseband signal 215 including the time information to the baseband signal processing unit 213.
  • the baseband signal processing unit 213 receives time information from the wireless network received by the RF receiving unit 212.
  • the nonvolatile storage device 205 stores the shipping time in advance at the time of LSI inspection in addition to the function of the nonvolatile storage device 105 of FIG.
  • the power supply voltage control unit 202 measures the real time from the difference between the time information received by the RF reception unit 212 and the shipping time stored in the nonvolatile storage device 205. I do.
  • the actual use time can be calculated by subtracting the LSI shipping time from the current time information acquired by the RF receiver 212, and the same effects as in the first embodiment, It is possible to achieve low power consumption of the low power consumption LSI 101 without lowering other performance.
  • the circuit can be simplified and the cost can be reduced.
  • the baseband signal processing unit of these communication devices can be used.
  • time information is received from a wireless network
  • a wired network may be used.
  • FIG. 5 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the third embodiment of the present invention.
  • the same components as those in FIG. 3 are denoted by the same reference numerals, and description of overlapping portions is omitted.
  • the low power consumption LSI 301 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, an aging degradation coefficient table 104, and a nonvolatile storage device 105.
  • the low power consumption LSI 301 is supplied with a system power supply 110 and a power-on reset 109 from an external power supply 307. Further, the power supply voltage control unit 102 outputs a power supply voltage control signal 313 to the external power supply 307.
  • the low power consumption LSI 301 is supplied with the internal power supply voltage from the external power supply 307, and the power supply 106 shown in FIG.
  • FIG. 6 is a block diagram showing a configuration of a semiconductor integrated circuit device according to Embodiment 4 of the present invention.
  • the same components as those in FIG. 5 are denoted by the same reference numerals, and description of overlapping portions is omitted.
  • the low power consumption LSI 401 includes a power supply voltage control unit 102, an actual usage time measurement unit 103, and an aging degradation coefficient table 104.
  • the low power consumption LSI 401 uses a nonvolatile storage device 405 as an external device.
  • the non-volatile storage device 405 stores the actual use time measured by the actual use time measuring unit 103, similarly to the non-volatile storage device 105 of FIG.
  • the nonvolatile storage device 405 stores the total aging time even when the external power supply 307 is shut off.
  • the nonvolatile storage device 405 may be configured by an external device instead of the low power consumption LSI 401.
  • FIG. 7 is a block diagram showing a configuration of a semiconductor integrated circuit device according to the fifth embodiment of the present invention.
  • the same components as those in FIG. 5 are denoted by the same reference numerals, and description of overlapping portions is omitted.
  • the low power consumption LSI 501 includes a power supply voltage control unit 502, an actual usage time measurement unit 103, an aging degradation coefficient table 504, a nonvolatile storage device 105, and a substrate voltage output power supply 506.
  • the aging degradation coefficient table 504 stores in advance the relationship between the power supply voltage application time and the substrate voltage for guaranteeing the operation speed of the transistor.
  • the substrate voltage output power supply 506 supplies the substrate voltage inside the low power consumption LSI 501.
  • the substrate voltage output power supply 506 supplies the internal power supply voltage 514 to the power supply voltage control unit 502, the actual usage time measurement unit 103, the aging degradation coefficient table 504, and the nonvolatile memory device 105.
  • the power supply voltage control unit 502 outputs a power supply voltage control signal 513 to the substrate voltage output power supply 506.
  • the power supply voltage control unit 502 supplies an optimum substrate voltage value corresponding to the power supply voltage application time of the low power consumption LSI 501 to the substrate voltage output power supply 506. Inform.
  • the substrate voltage output power source 506 changes the substrate voltage based on the notified substrate voltage value.
  • the power supply voltage control unit 502 controls the substrate bias instead of controlling the operating power supply voltage as in the above embodiments. That is, at the initial stage of use, reverse bias is applied to the substrate to reduce the leakage current, and the substrate voltage is increased by an amount that cancels out the speed deterioration due to aging according to the usage time. It is suitable for application to substrate bias control in which a substrate power supply is biased to control Vth. Accordingly, as in the case of each of the above embodiments, the operating power supply voltage can be set low at the beginning of use, and accordingly, the degree of aging deterioration with respect to the use time can be reduced, and the life of the device can be extended. it can. On the other hand, if the guaranteed operation period is determined, the speed margin required at the time of design can be reduced by taking this mitigation into consideration, so the designed circuit itself can be designed to have a smaller area and lower power consumption. Is possible.
  • each of the above embodiments is applied to a semiconductor integrated circuit device in which MOSFETs are integrated, but the same effect can be obtained also in the case of a CMOS circuit and a low power consumption LSI using the same. .
  • semiconductor integrated circuit device In each of the above embodiments, the name “semiconductor integrated circuit device” is used. However, this is for convenience of description, and may be a low power consumption LSI, a semiconductor integrated circuit, a method for reducing power consumption of an LSI, or the like. Of course.
  • the type, number, connection method, and the like of each circuit unit constituting the semiconductor integrated circuit device are not limited to the above-described embodiment.
  • the semiconductor integrated circuit device according to the present invention is not only useful for products in the mobile field where a longer operating time is required, but is also widely applied to servers and home products where low power consumption is required. To get.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
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Abstract

L’invention concerne un dispositif de circuit intégré à semi-conducteurs qui réalise une LSI (intégration à grande échelle) à basse consommation d’énergie et une réduction de la consommation d’énergie de la LSI sans nuire à d’autres performances. Une LSI à basse consommation d’énergie (101) est munie d’une table de facteurs de détérioration par vieillissement (104) pour stocker principalement la valeur de tension de fonctionnement obtenue en soustrayant une tension, correspondant à une marge de détérioration par vieillissement, d’une tension de référence dans le premier stade d’un fonctionnement durant lequel une détérioration par vieillissement se produit rarement, et, avec l’évolution de la détérioration par vieillissement, mémoriser la valeur de tension de fonctionnement qui approche de manière progressive la tension de référence afin de garantir la même performance. Une unité de régulation de tension d’alimentation (102) acquiert la valeur de tension de fonctionnement optimale à partir du temps réel d’utilisation mémorisé dans le dispositif de mémoire non-volatile (105) et de la valeur de la table de facteurs de détérioration par vieillissement (104) et change la tension d’alimentation en fonction de la valeur de tension de fonctionnement acquise.
PCT/JP2009/002739 2008-07-03 2009-06-16 Dispositif de circuit intégré à semi-conducteurs WO2010001536A1 (fr)

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JP2008175013A JP2010016653A (ja) 2008-07-03 2008-07-03 半導体集積回路装置
JP2008-175013 2008-07-03

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JP5451405B2 (ja) * 2010-01-06 2014-03-26 エヌイーシーコンピュータテクノ株式会社 半導体集積回路
JP5435663B2 (ja) * 2011-09-06 2014-03-05 エヌイーシーコンピュータテクノ株式会社 電子機器の保守装置、方法、及びプログラム

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197411A (ja) * 2004-01-06 2005-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
WO2007091361A1 (fr) * 2006-02-10 2007-08-16 Sony Computer Entertainment Inc. Procédé, programme et processeur arithmétique pour régler la tension d'alimentation d'un microprocesseur
JP2008147274A (ja) * 2006-12-07 2008-06-26 Internatl Business Mach Corp <Ibm> 半導体集積回路装置及びそれを備える内部電源制御システム
JP2009038128A (ja) * 2007-07-31 2009-02-19 Oki Electric Ind Co Ltd 半導体集積回路装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197411A (ja) * 2004-01-06 2005-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
WO2007091361A1 (fr) * 2006-02-10 2007-08-16 Sony Computer Entertainment Inc. Procédé, programme et processeur arithmétique pour régler la tension d'alimentation d'un microprocesseur
JP2008147274A (ja) * 2006-12-07 2008-06-26 Internatl Business Mach Corp <Ibm> 半導体集積回路装置及びそれを備える内部電源制御システム
JP2009038128A (ja) * 2007-07-31 2009-02-19 Oki Electric Ind Co Ltd 半導体集積回路装置

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