WO2009150600A1 - Structure à aire de surface améliorée - Google Patents

Structure à aire de surface améliorée Download PDF

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Publication number
WO2009150600A1
WO2009150600A1 PCT/IB2009/052419 IB2009052419W WO2009150600A1 WO 2009150600 A1 WO2009150600 A1 WO 2009150600A1 IB 2009052419 W IB2009052419 W IB 2009052419W WO 2009150600 A1 WO2009150600 A1 WO 2009150600A1
Authority
WO
WIPO (PCT)
Prior art keywords
pillars
dielectric
wall
depositing
layer
Prior art date
Application number
PCT/IB2009/052419
Other languages
English (en)
Inventor
Jinesh Balakrishna Pillai Kochupurackal
Freddy Roozeboom
Johan Hendrik Klootwijk
Wouter Dekkers
Original Assignee
Nxp B.V.
Koninklijke Philips Electronics N.V.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp B.V., Koninklijke Philips Electronics N.V. filed Critical Nxp B.V.
Publication of WO2009150600A1 publication Critical patent/WO2009150600A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors having potential barriers
    • H01L29/94—Metal-insulator-semiconductors, e.g. MOS
    • H01L29/945—Trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84—Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains

Definitions

  • the invention relates to a structure with a higher effective surface area than the substrate area occupied by the structure, and methods for its manufacture.
  • One example of a type of device in which such an enhanced surface area structure is of use is for a capacitor.
  • Another example is a battery.
  • Both examples have relevant properties determined by the effective surface area of the structure, and there is a general need for higher surface areas. The trend of increasing miniaturisation runs counter to this general need, resulting in the design of structures that have a higher effective surface area than the area occupied by the structure. Indeed, in some examples the size of passive and filtering MOS capacitors is a major limit on the reduction of the total size of system- in-package
  • a particular example of such a device structure is presented in Roozeboom et al, "ALD options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs", ECS transactions, volume 3 number 15, pages 173 to 181 (2007).
  • a plurality of pillars are etched in an array.
  • the pillars have a relatively high aspect ratio (of order 20) and are formed in a structure with a horizontal cross section having three extensions, approximately a trefoil.
  • the pillar thus has three legs and the structure may be referred to as a tripod structure.
  • a capacitor is formed by atomic layer deposition of a number of layers over the surface of the pillar.
  • Such a structure has a much higher effective surface area, i.e. the area of the pillars, than the surface area of the substrate occupied by the pillars. This allows the structures to deliver a good capacitance per unit area, usually expressed in nF/mm 2 .
  • the inventors have realised however that the hollow structure has enhanced structural stability.
  • the structures are more resistant to shear than for solid structures. This in turn significantly enhances structural stability and reduces the chances of the structures sticking together and or breaking, especially during manufacturing.
  • the present invention considers also any combination of elements and features mentioned in the present disclosure with one or more other elements of features mentioned there. Thus any combination is considered as part of the present invention.
  • Fig. 1 is a schematic top view of a pillar of an embodiment of the invention
  • Fig. 2 is a schematic section along AA of the pillar of Fig. 1;
  • Fig. 3 is a schematic side section of an array of pillars of the embodiment of Fig. 1;
  • Fig. 4 is a schematic view of the layers on the walls of the pillars of the embodiment of Fig. 1;
  • Fig. 5 is a schematic view of the layers on the walls of the pillars of another embodiment;
  • Fig. 6 is a schematic view of the layers on the walls of the pillars of another embodiment.
  • Fig. 1 illustrates a top view of a pillar structure used in a device according to a first embodiment
  • Fig. 2 illustrates a section of the pillar through A-A of Fig. 1.
  • the structure includes a hollow pillar 2 having a wall 4 enclosing a opening 6.
  • the horizontal cross section is of substantially trefoil shape, with three extensions 7, resulting in a pillar having three legs.
  • the pillar may thus be referred to as a tripod structure.
  • Such a tripod structure gives an improved area enhancement compared with other possible structures.
  • an array of such hollow pillars 2 is formed on a highly conductive doped silicon substrate 8.
  • the pillars extend vertically substantially perpendicularly to the first major surface 10 of the substrate, and the array extends laterally.
  • the size and shape of the pillars needs to be selected depending on both the etching process used to make the pillars and the application for which the pillars are to be used.
  • the pillars are to be used for a capacitor with additional layers deposited as shown in Figure 4, which relates to a metal oxide semiconductor (MOS) capacitor design.
  • MOS metal oxide semiconductor
  • the shape of the opening 6 in the pillars matches the shape of the pillar itself, i.e. the wall 4 has a substantially constant thickness around the circumference of the pillar.
  • Such a structure has maximum stability.
  • an oxide nitride oxide (ONO) dielectric 16 is provided on both the inner and outer surfaces of the wall 4 and an electrode 20 of conductive polysilicon fills the structure.
  • the ONO dielectric 16 is formed of an oxide layer 22, a nitride layer 24 and an oxide layer 26.
  • a mask step is followed by a high-aspect ratio etch to form the pillars 2 complete with walls 4 and openings 6 in a single etch process in the first major surface 10 of silicon substrate 8.
  • the etch process will etch the inside of the wall at a slower rate than the outside of the wall, in view of the greater accessibility of the etch site outside the wall to etch species than the etch site within the wall, forming the opening 6. For this reason, as illustrated in Fig. 2, the etch depth of the opening 6 can be lower than the etch depth of the outside of the pillar 2.
  • the tripods are arranged so close together that this does not occur to maximise surface area and in such a case the etch depth of the opening 6 will match or even be the greater than the etch depth outside the pillar 2.
  • the dielectric 16 is then formed on both the inside and the outside of wall 4. Thermal oxidation is used to grow oxide layer 22. Silicon nitride is then deposited by low pressure chemical vapour deposition (LPCVD) to form nitride layer 24 and then oxide layer 26 is formed by a tetraethylorthosilicate (TEOS) oxide deposition.
  • LPCVD low pressure chemical vapour deposition
  • TEOS tetraethylorthosilicate
  • LPCVD is then used to form the electrode layer 20 by depositing insitu phosphorous doped poly crystalline silicon filling the spaces between pillars 2.
  • the size of the structure formed will depend on the exact process used.
  • a comparative example would be a non-hollow structure with an exterior height of 30 ⁇ m and a typical cross section of 3.2 ⁇ m. Such a structure could be made using the same etch process. Calculations show that the effective area enhancement of the prior art pillar of the comparative example is 9, i.e. the effective surface area of the pillar is 9 times the surface area of substrate occupied.
  • the embodiment delivers an effective area enhancement of 8.
  • the embodiment is not beneficial.
  • shear modulus of a solid cylindrical structure is proportional to R 4 where R is the radius and the shear modulus of a hollow cylinder is (R 0 Ut 4 - Rm 4 ) where R 1n is the inner radius and R 0 Ut is the outer radius.
  • the ratio of shear modulii is given by (R ou t 4 - R m 4 )/R 4 .
  • the structures proposed are not cylinders, their strength is given by similar formulae.
  • a rough estimate of the shear modulus ratio in the present case is thus given by the shear modulus formula (R 0 Ut 4 - R in 4 )/R 4 which for the values mentioned is 2.4.
  • the structure according to the embodiment has a stiffness of 2 to 3 times that of the comparative example.
  • a further benefit of the embodiment relates to the processing of the polysilicon electrode 20.
  • the processing of this electrode requires an annealing step to activate the polysilicon. This annealing step causes stress along individual pillars in the comparative example causing damage to those structures. This is reduced in the embodiment.
  • a metal insulator metal in a second embodiment, illustrated in Figure 5, a metal insulator metal
  • (MIM) capacitor stack 12 with metal layer 14, dielectric 16 and metal layer 18 is provided on both the inside and outside of the wall.
  • a polysilicon electrode 20 is used as in the first embodiment.
  • the metal insulator metal stack 12 is deposited on both sides of the wall 4, i.e. on the inside as well as the outside.
  • the metal insulator metal stack 12 is deposited including a first metallization 14, an insulator 16, and a second metallization 18.
  • the insulator is a high-k oxide, i.e. an oxide having a higher dielectric constant than silicon dioxide. Suitable high-k oxides include HfO 2 and HfSiO x . In principle, any CVD or ALD compatible dielectric may be used in this technique.
  • the metallizations 14, 18 may be of any suitable layer of pure metal, metal alloy, or other material with metallic properties, such as Nitrides, Suicides, or even Silicon compounds.
  • a thin layer of TiN of thickness 50nm to lOOnm is provided as both metallizations 14,18.
  • metal used conventionally in the term metal insulator metal (MIM) does not require that the metallizations are of pure metal - instead it requires that the properties of the "metal" layers are metallic.
  • a metal insulator metal stack 12 is deposited including a first metallization 14, an insulator 16, and a second metallization 18.
  • the insulator is a high-k oxide, i.e. an oxide having a higher dielectric constant than silicon dioxide. Suitable high-k oxides include HfO 2 and HfSiO x .
  • the metallizations 14, 18 may be of any suitable layer of pure metal, metal alloy, or other material with metallic properties, such as Nitrides, Suicides, or even Silicon compounds. In the embodiment illustrated, a thin layer of TiN of thickness 50nm to lOOnm is provided as both metallizations 14,18.
  • hollow pillars are formed as explained in the first embodiment.
  • a three layer metal insulator metal stack 12 is then deposited on both the inside and outside.
  • atomic layer deposition is used, a deposition process in which single atomic layers are deposited separately one after the other. Typically, this is achieved by alternating growth reagents, each layer requiring both reagents. Suitable materials are discussed in the paper by Roozeboom et al already mentioned.
  • the process used to form the TiN layers 14,18 is the ALD process described in the paper by Roozeboom et al referred to above using TiCU vapor dosing in combination with an H 2 -N 2 plasma exposure.
  • the dielectric 16 is high-k HfO 2 deposited by ALD using tetrakis (ethylmethylamino) hafnium (TEMAHf) with an O 3 plasma at 400 0 C.
  • the polysilicon electrode 20 is then deposited with in-situ phosphorous doping by LPCVD and activated by annealing to make it conductive.
  • a multiple MIM stack 30 is formed thereby further increasing the capacitance density as illustrated in Fig. 6.
  • a second dielectric 32 is deposited followed by a third metal layer 34.
  • An alternative embodiment provides a multiple MOS capacitor with a first ONO layer deposited on a wall, followed by a first metal followed by a second ONO layer and then the polysilicon electrode 40.
  • the above embodiments are provided purely by way of example.
  • the capacitors may be MOS capacitors, MIM capacitors, or any suitable type of capacitor with any appropriate metallization and dielectric.
  • the approach need not just be applied to the manufacture of capacitors, but also to any other type of application where area enhancement is useful.
  • the invention may have application in the field of integrated batteries for power supply back up.
  • Other applications include solar cells and Peltier cooling devices.
  • the invention is not just limited to ALD but other deposition processes such as for example low pressure chemical vapour deposition (LPCVD) are possible. Chemical deposition techniques such as sol- gel vacuum impregnation may also be used on suitable layers.
  • LPCVD low pressure chemical vapour deposition
  • a less-conductive substrate may be used in combination with a subsequent doping step.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

Une structure avec une aire de surface supérieure à l'aire occupée par la structure comporte un certain nombre de piliers (2), les piliers étant creux et comportant une ouverture (6) s'étendant dans le pilier. Une couche intermédiaire est prévue sur la surface du pilier et une électrode remplit les espaces entre les piliers (2). La structure a une stabilité structurelle améliorée réduisant un dommage potentiel en particulier pendant la fabrication. La structure peut être utilisée pour des condensateurs ou des batteries, par exemple.
PCT/IB2009/052419 2008-06-09 2009-06-08 Structure à aire de surface améliorée WO2009150600A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP08157896.5 2008-06-09
EP08157896 2008-06-09

Publications (1)

Publication Number Publication Date
WO2009150600A1 true WO2009150600A1 (fr) 2009-12-17

Family

ID=40973176

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB2009/052419 WO2009150600A1 (fr) 2008-06-09 2009-06-08 Structure à aire de surface améliorée

Country Status (1)

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WO (1) WO2009150600A1 (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809982B2 (en) 2008-09-30 2014-08-19 Nxp B.V. Robust high aspect ratio semiconductor device
EP3588560A1 (fr) * 2018-06-21 2020-01-01 Murata Manufacturing Co., Ltd. Structure semi-conductrice améliorée pour des applications haute tension
CN112313797A (zh) * 2018-06-21 2021-02-02 株式会社村田制作所 针对高电压应用而增强的半导体结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369432B1 (en) * 1998-02-23 2002-04-09 Micron Technology, Inc. Enhanced capacitor shape
US20030162361A1 (en) * 2002-02-27 2003-08-28 Coursey Belford T. Selective hemispherical silicon grain (hsg) conversion inhibitor for use during the manufacture of a semiconductor device
US20050161720A1 (en) * 2004-01-26 2005-07-28 Park Je-Min Semiconductor device and method of manufacturing the semiconductor device
WO2007125510A2 (fr) * 2006-05-02 2007-11-08 Nxp B.V. Dispositif electrique comprenant une electrode amelioree

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6369432B1 (en) * 1998-02-23 2002-04-09 Micron Technology, Inc. Enhanced capacitor shape
US20030162361A1 (en) * 2002-02-27 2003-08-28 Coursey Belford T. Selective hemispherical silicon grain (hsg) conversion inhibitor for use during the manufacture of a semiconductor device
US20050161720A1 (en) * 2004-01-26 2005-07-28 Park Je-Min Semiconductor device and method of manufacturing the semiconductor device
WO2007125510A2 (fr) * 2006-05-02 2007-11-08 Nxp B.V. Dispositif electrique comprenant une electrode amelioree

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
ROOZEBOOM F ET AL: "ALD options for Si-integrated Ultrahigh-density Decoupling Capacitors in Pore and Trench Designs", E C S TRANSACTIONS, ELECTROCHEMICAL SOCIETY, US, vol. 3, no. 15, 1 January 2007 (2007-01-01), pages 173 - 181, XP008110701, ISSN: 1938-5862 *

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8809982B2 (en) 2008-09-30 2014-08-19 Nxp B.V. Robust high aspect ratio semiconductor device
EP3588560A1 (fr) * 2018-06-21 2020-01-01 Murata Manufacturing Co., Ltd. Structure semi-conductrice améliorée pour des applications haute tension
WO2019243882A3 (fr) * 2018-06-21 2020-02-13 Murata Manufacturing Co., Ltd. Structure semi-conductrice améliorée pour des applications haute tension
CN112313797A (zh) * 2018-06-21 2021-02-02 株式会社村田制作所 针对高电压应用而增强的半导体结构
TWI828707B (zh) * 2018-06-21 2024-01-11 日商村田製作所股份有限公司 用於高電壓應用的增強型半導體結構

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